[PATCH] dma: define compile-time ARCH_DMA_MINALIGN constant for all archs

[Ahmad Fatoum <a.fatoum@pengutronix.de>]

DMA_ALIGNMENT is not a compile-time constant on MIPS. This didn't bother
us so far, but will when we need to use it as argument to __aligned().

Let's additionally define ARCH_DMA_MINALIGN like Linux does and require
that all architectures define it to a compile-time constant if
DMA_ALIGNMENT isn't one.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/mips/include/asm/dma.h       |  2 ++
 arch/openrisc/include/asm/cache.h | 14 ++------------
 arch/openrisc/include/asm/dma.h   |  6 +++++-
 include/dma.h                     |  4 ++++
 4 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/arch/mips/include/asm/dma.h b/arch/mips/include/asm/dma.h
index 2ae75f047bd7..e5c8abd0bf1e 100644
--- a/arch/mips/include/asm/dma.h
+++ b/arch/mips/include/asm/dma.h
@@ -19,6 +19,8 @@
 #define DMA_ALIGNMENT	\
 	max(current_cpu_data.dcache.linesz, current_cpu_data.scache.linesz)
 
+#define ARCH_DMA_MINALIGN	128
+
 struct device;
 
 #define dma_alloc_coherent dma_alloc_coherent
diff --git a/arch/openrisc/include/asm/cache.h b/arch/openrisc/include/asm/cache.h
index 5dee26b190e1..4bba6923b1e8 100644
--- a/arch/openrisc/include/asm/cache.h
+++ b/arch/openrisc/include/asm/cache.h
@@ -16,6 +16,8 @@
 #ifndef __ASM_OPENRISC_CACHE_H_
 #define __ASM_OPENRISC_CACHE_H_
 
+#include <asm/dma.h>
+
 void flush_dcache_range(unsigned long addr, unsigned long stop);
 void invalidate_dcache_range(unsigned long addr, unsigned long stop);
 void flush_cache(unsigned long addr, unsigned long size);
@@ -28,16 +30,4 @@ void dcache_disable(void);
 void icache_enable(void);
 void icache_disable(void);
 
-/*
- * Valid L1 data cache line sizes for the OpenRISC architecture are
- * 16 and 32 bytes.
- * If the board configuration has not specified one we default to the
- * largest of these values for alignment of DMA buffers.
- */
-#ifdef CONFIG_SYS_CACHELINE_SIZE
-#define ARCH_DMA_MINALIGN       CONFIG_SYS_CACHELINE_SIZE
-#else
-#define ARCH_DMA_MINALIGN       32
-#endif
-
 #endif /* __ASM_OPENRISC_CACHE_H_ */
diff --git a/arch/openrisc/include/asm/dma.h b/arch/openrisc/include/asm/dma.h
index 27d269f49182..090e01cb7e44 100644
--- a/arch/openrisc/include/asm/dma.h
+++ b/arch/openrisc/include/asm/dma.h
@@ -8,6 +8,10 @@
 #ifndef __ASM_DMA_H
 #define __ASM_DMA_H
 
-/* empty */
+/*
+ * Valid L1 data cache line sizes for the OpenRISC architecture are
+ * 16 and 32 bytes.
+ */
+#define DMA_ALIGNMENT       32
 
 #endif /* __ASM_DMA_H */
diff --git a/include/dma.h b/include/dma.h
index 53cb50b707f4..1f650aecb950 100644
--- a/include/dma.h
+++ b/include/dma.h
@@ -22,6 +22,10 @@
 #define DMA_ALIGNMENT	32
 #endif
 
+#ifndef ARCH_DMA_MINALIGN
+#define ARCH_DMA_MINALIGN	DMA_ALIGNMENT
+#endif
+
 #ifdef CONFIG_HAS_DMA
 void *dma_alloc(size_t size);
 void *dma_zalloc(size_t size);
-- 
2.39.5