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Wed, 11 Dec 2024 07:00:14 -0800 (PST) Received: from localhost.localdomain ([95.161.223.172]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3878248f8e1sm1471461f8f.18.2024.12.11.07.00.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 07:00:13 -0800 (PST) From: Alexander Shiyan To: barebox@lists.infradead.org Cc: Alexander Shiyan Date: Wed, 11 Dec 2024 18:00:02 +0300 Message-Id: <20241211150002.2993689-1-eagle.alexander923@gmail.com> X-Mailer: git-send-email 2.38.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241211_070016_621185_F360D783 X-CRM114-Status: GOOD ( 10.77 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.whiteo.stw.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-5.0 required=4.0 tests=AWL,BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: [PATCH] ARM: rockchip: dmc fix LPDDR5 bank info for sys_reg version 3 X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.whiteo.stw.pengutronix.de) This patch add support for additional bank info used by LPDDR5. Taken from U-boot code, commit 875bc40 by YouMin Chen Signed-off-by: Alexander Shiyan --- arch/arm/mach-rockchip/dmc.c | 7 ++++++- include/mach/rockchip/dmc.h | 11 +++++++---- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-rockchip/dmc.c b/arch/arm/mach-rockchip/dmc.c index 81c7e2649e..86e61f3116 100644 --- a/arch/arm/mach-rockchip/dmc.c +++ b/arch/arm/mach-rockchip/dmc.c @@ -58,7 +58,12 @@ static resource_size_t rockchip_sdram_size(u32 sys_reg2, u32 sys_reg3) cs0_col = 9 + (sys_reg2 >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); cs1_col = cs0_col; - bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); + if (dram_type == LPDDR5) + /* LPDDR5: 0:8bank(bk=3), 1:16bank(bk=4) */ + bk = 3 + ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); + else + /* Other: 0:8bank(bk=3), 1:4bank(bk=2) */ + bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); cs0_row = sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & SYS_REG_CS0_ROW_MASK; cs1_row = sys_reg2 >> SYS_REG_CS1_ROW_SHIFT(ch) & SYS_REG_CS1_ROW_MASK; diff --git a/include/mach/rockchip/dmc.h b/include/mach/rockchip/dmc.h index ed256f6daf..3df9aa5e9c 100644 --- a/include/mach/rockchip/dmc.h +++ b/include/mach/rockchip/dmc.h @@ -12,10 +12,13 @@ enum { DDR4 = 0, - DDR3 = 0x3, - LPDDR2 = 0x5, - LPDDR3 = 0x6, - LPDDR4 = 0x7, + DDR3 = 3, + LPDDR2 = 5, + LPDDR3 = 6, + LPDDR4 = 7, + LPDDR4X = 8, + LPDDR5 = 9, + DDR5 = 10, UNUSED = 0xFF }; -- 2.38.2