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Mon, 06 Jan 2025 14:47:01 +0100 Received: from localhost ([::1] helo=dude02.red.stw.pengutronix.de) by dude02.red.stw.pengutronix.de with esmtp (Exim 4.96) (envelope-from ) id 1tUnRd-00CsVv-1l; Mon, 06 Jan 2025 14:47:01 +0100 From: Sascha Hauer Date: Mon, 06 Jan 2025 14:47:02 +0100 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250106-k3-r5-v2-5-9de6270089ef@pengutronix.de> References: <20250106-k3-r5-v2-0-9de6270089ef@pengutronix.de> In-Reply-To: <20250106-k3-r5-v2-0-9de6270089ef@pengutronix.de> To: "open list:BAREBOX" X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1736171221; l=1278; i=s.hauer@pengutronix.de; s=20230412; h=from:subject:message-id; bh=I6AffcjyjYkKWZa3YxC9m6UC+aI8am6CNeW0ALNPMjk=; b=aFD2LIwpQUcTOqEBU7WGA8MNGZwm37Mu/ADawjFqU/aeFsNLefn+f1UYpM/RiEo1RPFhIe/Gj w8UNmMKOg0PCpG7uY8PU9Lpq3jBeTdtEvB0je5r+rjuJAP+pJ5kZT7i X-Developer-Key: i=s.hauer@pengutronix.de; a=ed25519; pk=4kuc9ocmECiBJKWxYgqyhtZOHj5AWi7+d0n/UjhkwTg= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250106_134706_936189_2FF282D6 X-CRM114-Status: GOOD ( 12.68 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.whiteo.stw.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-5.3 required=4.0 tests=AWL,BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: [PATCH v2 05/22] nommu_v7_vectors_init: disable for r5 X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.whiteo.stw.pengutronix.de) Some ARMv7 cores like the Cortex-R5 do not have a VBAR register for setting up the vector table. This patch disables the vector table setup specifically for the Cortex-R5. Signed-off-by: Sascha Hauer --- arch/arm/cpu/no-mmu.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/cpu/no-mmu.c b/arch/arm/cpu/no-mmu.c index be3cfaf12b..c4ef5d1f9d 100644 --- a/arch/arm/cpu/no-mmu.c +++ b/arch/arm/cpu/no-mmu.c @@ -19,9 +19,26 @@ #include #include #include +#include #define __exceptions_size (__exceptions_stop - __exceptions_start) +static bool has_vbar(void) +{ + u32 mainid; + + __asm__ __volatile__( + "mrc p15, 0, %0, c0, c0, 0 @ read control reg\n" + : "=r" (mainid) + : + : "memory"); + + if ((mainid & 0xfff0) == ARM_CPU_PART_CORTEX_R5) + return false; + + return true; +} + static int nommu_v7_vectors_init(void) { void *vectors; @@ -30,6 +47,9 @@ static int nommu_v7_vectors_init(void) if (cpu_architecture() < CPU_ARCH_ARMv7) return 0; + if (!has_vbar()) + return 0; + /* * High vectors cannot be re-mapped, so we have to use normal * vectors -- 2.39.5