* [PATCH v3 00/23] ARM: K3: Add R5 boot support
@ 2025-01-13 11:26 Sascha Hauer
2025-01-13 11:26 ` [PATCH v3 01/23] ARM: add ARMv7R MPU support Sascha Hauer
` (22 more replies)
0 siblings, 23 replies; 26+ messages in thread
From: Sascha Hauer @ 2025-01-13 11:26 UTC (permalink / raw)
To: open list:BAREBOX
So far we only supported the TI K3 SoCs booting 2nd stage after U-Boot.
This series adds full boot support for K3 SoCs, or more specifically,
the AM625 SoC.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
Changes in v3:
- add patch to add AM625(sip)-SK board support
- add patch to detect DRAM size on AM625
- add tool to generate config files from yaml files instead of adding
binary files from U-Boot
- pass only used regions to MPU init instead of all
- implement cache maintenance functions and coherent mem in MPU support
- drop patch to use PIO for small MMC transfers (no longer needed due to
proper cache maintenance with MPU support)
- Document origin of keys
- Link to v2: https://lore.kernel.org/r/20250106-k3-r5-v2-0-9de6270089ef@pengutronix.de
Changes in v2:
- remove unused enable_caches() function
- add patch to disable secondary watchdogs in barebox
- add patch to fix SCR read on Cortex-R5 cores
- handle inner cert in K3 image tool
- Link to v1: https://lore.kernel.org/r/20241129-k3-r5-v1-0-67c4bb42a5c7@pengutronix.de
---
Sascha Hauer (23):
ARM: add ARMv7R MPU support
lib/rationale: compile for pbl
DDR: Add k3 DDR driver
ARM: move ARM_CPU_PART_* defines to header
nommu_v7_vectors_init: disable for r5
clocksource: timer-ti-dm: add support for K3 SoCs
ARM: K3: mount /boot even with env handling disabled
clk: add K3 clk driver
pmdomain: add K3 driver
rproc: add K3 arm64 rproc driver
ARM: k3: add k3_debug_ll_init()
ARM: K3: use debug_ll code for regular PBL console
elf: use iomem regions as fallback when loading to non-sdram memory
rproc: add K3 system_controller
firmware: ti_sci: add function to get global handle
ARM: k3: Add initial r5 support
scripts: k3: add script to generate cfg files from yaml
ARM: k3: Add k3img tool
ARM: beagleplay: add Cortex-R5 boot support
Documentation: add build documentation for TI K3 SoCs
ARM: am625: disable secondary watchdogs
ARM: k3: Add DRAM size detection
ARM: k3: am625-sk board support
Documentation/boards/ti-k3.rst | 79 +
arch/arm/Kconfig | 2 -
arch/arm/boards/Makefile | 1 +
arch/arm/boards/am625-sk/Makefile | 3 +
arch/arm/boards/am625-sk/am625-sk-ddr.c | 2223 +++++++
arch/arm/boards/am625-sk/am625sip-sk-ddr.c | 2229 +++++++
arch/arm/boards/am625-sk/ddr.h | 7 +
arch/arm/boards/am625-sk/entry-r5.S | 29 +
arch/arm/boards/am625-sk/entry.S | 29 +
arch/arm/boards/am625-sk/lowlevel.c | 119 +
arch/arm/boards/beagleplay/Makefile | 4 +-
arch/arm/boards/beagleplay/ddr.c | 586 ++
arch/arm/boards/beagleplay/ddr.h | 6 +
arch/arm/boards/beagleplay/entry-r5.S | 18 +
arch/arm/boards/beagleplay/lowlevel.c | 38 +
arch/arm/cpu/Kconfig | 8 +
arch/arm/cpu/Makefile | 3 +-
arch/arm/cpu/armv7r-mpu.c | 254 +
arch/arm/cpu/cpu.c | 3 +
arch/arm/cpu/cpuinfo.c | 11 +-
arch/arm/cpu/no-mmu.c | 20 +
arch/arm/cpu/start.c | 7 +
arch/arm/cpu/uncompress.c | 2 +
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/k3-am625-r5-beagleplay.dts | 4 +
arch/arm/dts/k3-am625-r5-sk.dts | 4 +
arch/arm/dts/k3-am625-r5.dtsi | 103 +
arch/arm/dts/k3-am625-sk.dts | 9 +
arch/arm/dts/k3-am625.dtsi | 15 +
arch/arm/dts/k3-am625sip-r5-sk.dts | 4 +
arch/arm/include/asm/armv7r-mpu.h | 135 +
arch/arm/include/asm/cputype.h | 11 +
arch/arm/include/asm/dma.h | 3 +-
arch/arm/mach-k3/Kconfig | 27 +
arch/arm/mach-k3/Makefile | 18 +
arch/arm/mach-k3/board-cfg-am625.yaml | 36 +
arch/arm/mach-k3/common.c | 16 +-
arch/arm/mach-k3/custMpk.pem | 51 +
arch/arm/mach-k3/ddrss.c | 76 +
arch/arm/mach-k3/pm-cfg-am625.yaml | 12 +
arch/arm/mach-k3/r5.c | 280 +
arch/arm/mach-k3/rm-cfg-am625.yaml | 981 +++
arch/arm/mach-k3/schema.yaml | 436 ++
arch/arm/mach-k3/sec-cfg-am625.yaml | 379 ++
arch/arm/mach-k3/ti-degenerate-key.pem | 10 +
common/elf.c | 14 +-
drivers/clk/Makefile | 1 +
drivers/clk/k3/Makefile | 2 +
drivers/clk/k3/am625.c | 475 ++
drivers/clk/k3/pll.c | 375 ++
drivers/clk/k3/ti-k3-clk.h | 8 +
drivers/clocksource/timer-ti-dm.c | 53 +-
drivers/ddr/Kconfig | 1 +
drivers/ddr/Makefile | 1 +
drivers/ddr/k3/Kconfig | 2 +
drivers/ddr/k3/Makefile | 1 +
.../ddr/k3/am64/lpddr4_address_slice_0_macros.h | 624 ++
.../ddr/k3/am64/lpddr4_address_slice_1_macros.h | 624 ++
.../ddr/k3/am64/lpddr4_address_slice_2_macros.h | 624 ++
.../ddr/k3/am64/lpddr4_am64_ctl_regs_rw_masks.h | 21 +
drivers/ddr/k3/am64/lpddr4_am64_if.h | 103 +
drivers/ddr/k3/am64/lpddr4_am64_obj_if.h | 14 +
drivers/ddr/k3/am64/lpddr4_am64_structs_if.h | 15 +
drivers/ddr/k3/am64/lpddr4_ctl_regs.h | 1306 ++++
drivers/ddr/k3/am64/lpddr4_data_slice_0_macros.h | 2036 +++++++
drivers/ddr/k3/am64/lpddr4_data_slice_1_macros.h | 2036 +++++++
drivers/ddr/k3/am64/lpddr4_ddr_controller_macros.h | 6436 ++++++++++++++++++++
drivers/ddr/k3/am64/lpddr4_phy_core_macros.h | 1838 ++++++
drivers/ddr/k3/am64/lpddr4_pi_macros.h | 5784 ++++++++++++++++++
drivers/ddr/k3/cps_drv_lpddr4.h | 102 +
drivers/ddr/k3/k3-ddrss.c | 488 ++
drivers/ddr/k3/lpddr4.c | 1071 ++++
drivers/ddr/k3/lpddr4.h | 69 +
drivers/ddr/k3/lpddr4_am64_ctl_regs_rw_masks.c | 1309 ++++
drivers/ddr/k3/lpddr4_am6x.c | 398 ++
drivers/ddr/k3/lpddr4_am6x.h | 41 +
drivers/ddr/k3/lpddr4_am6x_sanity.h | 253 +
drivers/ddr/k3/lpddr4_if.h | 142 +
drivers/ddr/k3/lpddr4_obj_if.c | 52 +
drivers/ddr/k3/lpddr4_obj_if.h | 88 +
drivers/ddr/k3/lpddr4_sanity.h | 439 ++
drivers/ddr/k3/lpddr4_structs_if.h | 52 +
drivers/firmware/ti_sci.c | 59 +-
drivers/pmdomain/ti/Kconfig | 4 +
drivers/pmdomain/ti/Makefile | 1 +
drivers/pmdomain/ti/ti-k3.c | 479 ++
drivers/remoteproc/Kconfig | 6 +
drivers/remoteproc/Makefile | 2 +
drivers/remoteproc/ti_k3_arm64_rproc.c | 226 +
drivers/remoteproc/ti_k3_system_controller.c | 214 +
drivers/remoteproc/ti_sci_proc.h | 149 +
images/.gitignore | 1 +
images/Makefile.k3 | 65 +
include/mach/k3/common.h | 4 +
include/mach/k3/debug_ll.h | 32 +-
include/mach/k3/r5.h | 9 +
include/soc/k3/clk.h | 7 +
include/soc/k3/ddr.h | 26 +
include/soc/ti/ti_sci_protocol.h | 7 -
lib/math/Makefile | 2 +-
scripts/Makefile.lib | 3 +
scripts/k3img | 187 +
scripts/ti-board-config.py | 170 +
103 files changed, 36756 insertions(+), 89 deletions(-)
---
base-commit: 67606e84177c322b92e28d5b5ba3b06c2b1723c3
change-id: 20241129-k3-r5-0da3e97beaf9
Best regards,
--
Sascha Hauer <s.hauer@pengutronix.de>
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v3 01/23] ARM: add ARMv7R MPU support
2025-01-13 11:26 [PATCH v3 00/23] ARM: K3: Add R5 boot support Sascha Hauer
@ 2025-01-13 11:26 ` Sascha Hauer
2025-01-13 11:26 ` [PATCH v3 02/23] lib/rationale: compile for pbl Sascha Hauer
` (21 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Sascha Hauer @ 2025-01-13 11:26 UTC (permalink / raw)
To: open list:BAREBOX
This adds MPU (memory protection unit) support for ARMv7R cores.
Code is based on U-Boot-2025.01-rc1.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/cpu/Kconfig | 8 ++
arch/arm/cpu/Makefile | 3 +-
arch/arm/cpu/armv7r-mpu.c | 254 ++++++++++++++++++++++++++++++++++++++
arch/arm/cpu/cpu.c | 3 +
arch/arm/cpu/start.c | 7 ++
arch/arm/cpu/uncompress.c | 2 +
arch/arm/include/asm/armv7r-mpu.h | 135 ++++++++++++++++++++
arch/arm/include/asm/dma.h | 3 +-
8 files changed, 413 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/Kconfig b/arch/arm/cpu/Kconfig
index 6563394a7a..84fe770b6d 100644
--- a/arch/arm/cpu/Kconfig
+++ b/arch/arm/cpu/Kconfig
@@ -156,3 +156,11 @@ config CACHE_L2X0
bool "Enable L2x0 PrimeCell"
depends on MMU && ARCH_HAS_L2X0
+config ARMV7R_MPU
+ bool
+ depends on CPU_V7
+ select MALLOC_TLSF
+ help
+ Some ARM systems without an MMU have instead a Memory Protection
+ Unit (MPU) that defines the type and permissions for regions of
+ memory.
diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
index 999cc375da..1769249645 100644
--- a/arch/arm/cpu/Makefile
+++ b/arch/arm/cpu/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
-obj-y += cpu.o
+obj-pbl-y += cpu.o
obj-$(CONFIG_ARM_EXCEPTIONS) += exceptions_$(S64_32).o interrupts_$(S64_32).o
obj-$(CONFIG_MMU) += mmu-common.o
@@ -62,3 +62,4 @@ pbl-$(CONFIG_ARM_ATF) += atf.o
obj-pbl-y += common.o sections.o
KASAN_SANITIZE_common.o := n
+obj-pbl-$(CONFIG_ARMV7R_MPU) += armv7r-mpu.o
diff --git a/arch/arm/cpu/armv7r-mpu.c b/arch/arm/cpu/armv7r-mpu.c
new file mode 100644
index 0000000000..e2108ef723
--- /dev/null
+++ b/arch/arm/cpu/armv7r-mpu.c
@@ -0,0 +1,254 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Cortex-R Memory Protection Unit specific code
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ */
+#define pr_fmt(fmt) "armv7r-mpu: " fmt
+
+#include <memory.h>
+#include <string.h>
+#include <cache.h>
+#include <errno.h>
+#include <tlsf.h>
+#include <dma.h>
+#include <linux/bitfield.h>
+#include <asm/armv7r-mpu.h>
+#include <asm/system.h>
+#include <asm/cache.h>
+#include <asm/dma.h>
+#include <asm/mmu.h>
+#include <linux/printk.h>
+
+#define MPUIR_DREGION GENMASK(15, 8)
+
+/**
+ * Note:
+ * The Memory Protection Unit(MPU) allows to partition memory into regions
+ * and set individual protection attributes for each region. In absence
+ * of MPU a default map[1] will take effect. make sure to run this code
+ * from a region which has execution permissions by default.
+ * [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460d/I1002400.html
+ */
+
+void armv7r_mpu_disable(void)
+{
+ u32 reg;
+
+ reg = get_cr();
+ reg &= ~CR_M;
+ dsb();
+ set_cr(reg);
+ isb();
+}
+
+void armv7r_mpu_enable(void)
+{
+ u32 reg;
+
+ reg = get_cr();
+ reg |= CR_M;
+ dsb();
+ set_cr(reg);
+ isb();
+}
+
+int armv7r_mpu_enabled(void)
+{
+ return get_cr() & CR_M;
+}
+
+static __maybe_unused void armv7_mpu_print_config(void)
+{
+ int i;
+
+ for (i = 0; i < 16; i++) {
+ u32 addr, size, attr;
+
+ asm volatile ("mcr p15, 0, %0, c6, c2, 0" : : "r" (i));
+
+ asm volatile ("mrc p15, 0, %0, c6, c1, 0" : "=r" (addr));
+ asm volatile ("mrc p15, 0, %0, c6, c1, 2" : "=r" (size));
+ asm volatile ("mrc p15, 0, %0, c6, c1, 4" : "=r" (attr));
+
+ pr_debug("%s: %d 0x%08x 0x%08x 0x%08x\n", __func__, i, addr, size, attr);
+ }
+}
+
+void armv7r_mpu_config(struct mpu_region_config *rgn)
+{
+ u32 attr, val;
+
+ pr_debug("%s: no: %d start: 0x%08x size: 0x%08x\n", __func__,
+ rgn->region_no, rgn->start_addr, rgn->reg_size);
+
+ attr = get_attr_encoding(rgn->mr_attr);
+
+ /* MPU Region Number Register */
+ asm volatile ("mcr p15, 0, %0, c6, c2, 0" : : "r" (rgn->region_no));
+
+ /* MPU Region Base Address Register */
+ asm volatile ("mcr p15, 0, %0, c6, c1, 0" : : "r" (rgn->start_addr));
+
+ /* MPU Region Size and Enable Register */
+ if (rgn->reg_size)
+ val = (rgn->reg_size << REGION_SIZE_SHIFT) | ENABLE_REGION;
+ else
+ val = DISABLE_REGION;
+ asm volatile ("mcr p15, 0, %0, c6, c1, 2" : : "r" (val));
+
+ /* MPU Region Access Control Register */
+ val = rgn->xn << XN_SHIFT | rgn->ap << AP_SHIFT | attr;
+ asm volatile ("mcr p15, 0, %0, c6, c1, 4" : : "r" (val));
+}
+
+static int armv7r_mpu_supported_regions(void)
+{
+ u32 num;
+
+ asm volatile ("mrc p15, 0, %0, c0, c0, 4" : "=r" (num));
+
+ return FIELD_GET(MPUIR_DREGION, num);
+}
+
+static int armv7r_get_unused_region(void)
+{
+ int i;
+
+ for (i = 0; i < armv7r_mpu_supported_regions(); i++) {
+ u32 mpu_rasr;
+
+ /* MPU Region Number Register */
+ asm volatile ("mcr p15, 0, %0, c6, c2, 0" : : "r" (i));
+
+ asm volatile ("mrc p15, 0, %0, c6, c1, 2" : "=r" (mpu_rasr));
+
+ if (!(mpu_rasr & ENABLE_REGION))
+ return i;
+ }
+
+ return -ENOSPC;
+}
+
+int armv7r_mpu_setup_regions(struct mpu_region_config *rgns, u32 num_rgns)
+{
+ u32 i, supported_regions;
+
+ supported_regions = armv7r_mpu_supported_regions();
+
+ /* Regions to be configured cannot be greater than available regions */
+ if (num_rgns > supported_regions)
+ return -EINVAL;
+
+ /**
+ * Assuming dcache might not be enabled at this point, disabling
+ * and invalidating only icache.
+ */
+ icache_disable();
+ icache_invalidate();
+
+ armv7r_mpu_disable();
+
+ for (i = 0; i < supported_regions; i++) {
+ if (i < num_rgns) {
+ armv7r_mpu_config(&rgns[i]);
+ } else {
+ struct mpu_region_config rgn = {
+ .region_no = i,
+ };
+
+ armv7r_mpu_config(&rgn);
+ }
+ }
+
+ armv7r_mpu_enable();
+
+ icache_enable();
+
+ return 0;
+}
+
+static tlsf_t dma_coherent_pool;
+static unsigned long dma_coherent_start;
+static unsigned long dma_coherent_size;
+
+int armv7r_mpu_init_coherent(unsigned long start, enum size reg_size)
+{
+ int region_no;
+ unsigned long size;
+ struct mpu_region_config rgn = {
+ .start_addr = start,
+ .xn = XN_EN,
+ .ap = PRIV_RW_USR_RW,
+ .mr_attr = STRONG_ORDER,
+ .reg_size = reg_size,
+ };
+
+ region_no = armv7r_get_unused_region();
+ if (region_no < 0)
+ return region_no;
+
+ rgn.region_no = region_no;
+
+ armv7r_mpu_config(&rgn);
+
+ size = 1 << (reg_size + 1);
+
+ dma_coherent_pool = tlsf_create_with_pool((void *)start, size);
+
+ dma_coherent_start = start;
+ dma_coherent_size = size;
+
+ return 0;
+}
+
+static int armv7r_request_pool(void)
+{
+ if (dma_coherent_start && dma_coherent_size)
+ request_sdram_region("DMA coherent pool", dma_coherent_start,
+ dma_coherent_size);
+ return 0;
+}
+postmem_initcall(armv7r_request_pool);
+
+void *dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle)
+{
+ void *ret = tlsf_memalign(dma_coherent_pool, DMA_ALIGNMENT, size);
+
+ if (!ret)
+ return NULL;
+
+ if (dma_handle)
+ *dma_handle = (dma_addr_t)ret;
+
+ memset(ret, 0, size);
+
+ return ret;
+}
+
+void dma_free_coherent(struct device *dev,
+ void *mem, dma_addr_t dma_handle, size_t size)
+{
+ free(mem);
+}
+
+void arch_sync_dma_for_cpu(void *vaddr, size_t size, enum dma_data_direction dir)
+{
+ unsigned long start = (unsigned long)vaddr;
+ unsigned long end = start + size;
+
+ if (dir != DMA_TO_DEVICE)
+ __dma_inv_range(start, end);
+}
+
+void arch_sync_dma_for_device(void *vaddr, size_t size, enum dma_data_direction dir)
+{
+ unsigned long start = (unsigned long)vaddr;
+ unsigned long end = start + size;
+
+ if (dir == DMA_FROM_DEVICE)
+ __dma_inv_range(start, end);
+ else
+ __dma_clean_range(start, end);
+}
diff --git a/arch/arm/cpu/cpu.c b/arch/arm/cpu/cpu.c
index b00e9e51e5..800d6b3cab 100644
--- a/arch/arm/cpu/cpu.c
+++ b/arch/arm/cpu/cpu.c
@@ -52,6 +52,8 @@ int icache_status(void)
return (get_cr () & CR_I) != 0;
}
+#ifndef __PBL__
+
/*
* SoC like the ux500 have the l2x0 always enable
* with or without MMU enable
@@ -108,3 +110,4 @@ static int arm_request_stack(void)
return 0;
}
coredevice_initcall(arm_request_stack);
+#endif
diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c
index ece9512a79..0022ea768b 100644
--- a/arch/arm/cpu/start.c
+++ b/arch/arm/cpu/start.c
@@ -25,6 +25,7 @@
#include <uncompress.h>
#include <compressed-dtb.h>
#include <malloc.h>
+#include <asm/armv7r-mpu.h>
#include <debug_ll.h>
@@ -153,6 +154,12 @@ __noreturn __prereloc void barebox_non_pbl_start(unsigned long membase,
arm_barebox_size = barebox_image_size + MAX_BSS_SIZE;
malloc_end = barebox_base;
+ if (IS_ENABLED(CONFIG_ARMV7R_MPU)) {
+ malloc_end = ALIGN_DOWN(malloc_end - SZ_8M, SZ_8M);
+
+ armv7r_mpu_init_coherent(malloc_end, REGION_8MB);
+ }
+
/*
* Maximum malloc space is the Kconfig value if given
* or 1GB.
diff --git a/arch/arm/cpu/uncompress.c b/arch/arm/cpu/uncompress.c
index ac1462b7b1..4657a4828e 100644
--- a/arch/arm/cpu/uncompress.c
+++ b/arch/arm/cpu/uncompress.c
@@ -65,6 +65,8 @@ void __noreturn barebox_pbl_start(unsigned long membase, unsigned long memsize,
if (IS_ENABLED(CONFIG_MMU))
mmu_early_enable(membase, memsize);
+ else if (IS_ENABLED(CONFIG_ARMV7R_MPU))
+ set_cr(get_cr() | CR_C);
/* Add handoff data now, so arm_mem_barebox_image takes it into account */
if (boarddata)
diff --git a/arch/arm/include/asm/armv7r-mpu.h b/arch/arm/include/asm/armv7r-mpu.h
new file mode 100644
index 0000000000..8d737d6d14
--- /dev/null
+++ b/arch/arm/include/asm/armv7r-mpu.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
+ */
+
+#ifndef _ASM_ARMV7_MPU_H
+#define _ASM_ARMV7_MPU_H
+
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#endif
+
+#ifdef CONFIG_CPU_V7M
+#define AP_SHIFT 24
+#define XN_SHIFT 28
+#define TEX_SHIFT 19
+#define S_SHIFT 18
+#define C_SHIFT 17
+#define B_SHIFT 16
+#else /* CONFIG_CPU_V7R */
+#define XN_SHIFT 12
+#define AP_SHIFT 8
+#define TEX_SHIFT 3
+#define S_SHIFT 2
+#define C_SHIFT 1
+#define B_SHIFT 0
+#endif /* CONFIG_CPU_V7R */
+
+#define CACHEABLE BIT(C_SHIFT)
+#define BUFFERABLE BIT(B_SHIFT)
+#define SHAREABLE BIT(S_SHIFT)
+#define REGION_SIZE_SHIFT 1
+#define ENABLE_REGION BIT(0)
+#define DISABLE_REGION 0
+
+enum region_number {
+ REGION_0 = 0,
+ REGION_1,
+ REGION_2,
+ REGION_3,
+ REGION_4,
+ REGION_5,
+ REGION_6,
+ REGION_7,
+};
+
+enum ap {
+ NO_ACCESS = 0,
+ PRIV_RW_USR_NO,
+ PRIV_RW_USR_RO,
+ PRIV_RW_USR_RW,
+ UNPREDICTABLE,
+ PRIV_RO_USR_NO,
+ PRIV_RO_USR_RO,
+};
+
+enum mr_attr {
+ STRONG_ORDER = 0,
+ SHARED_WRITE_BUFFERED,
+ O_I_WT_NO_WR_ALLOC,
+ O_I_WB_NO_WR_ALLOC,
+ O_I_NON_CACHEABLE,
+ O_I_WB_RD_WR_ALLOC,
+ DEVICE_NON_SHARED,
+};
+enum size {
+ REGION_8MB = 22,
+ REGION_16MB,
+ REGION_32MB,
+ REGION_64MB,
+ REGION_128MB,
+ REGION_256MB,
+ REGION_512MB,
+ REGION_1GB,
+ REGION_2GB,
+ REGION_4GB,
+};
+
+enum xn {
+ XN_DIS = 0,
+ XN_EN,
+};
+
+struct mpu_region_config {
+ uint32_t start_addr;
+ enum region_number region_no;
+ enum xn xn;
+ enum ap ap;
+ enum mr_attr mr_attr;
+ enum size reg_size;
+};
+
+void armv7r_mpu_disable(void);
+void armv7r_mpu_enable(void);
+int armv7r_mpu_enabled(void);
+void armv7r_mpu_config(struct mpu_region_config *rgn);
+int armv7r_mpu_setup_regions(struct mpu_region_config *rgns, u32 num_rgns);
+int armv7r_mpu_init_coherent(unsigned long start, enum size size);
+
+static inline u32 get_attr_encoding(u32 mr_attr)
+{
+ u32 attr;
+
+ switch (mr_attr) {
+ case STRONG_ORDER:
+ attr = SHAREABLE;
+ break;
+ case SHARED_WRITE_BUFFERED:
+ attr = BUFFERABLE;
+ break;
+ case O_I_WT_NO_WR_ALLOC:
+ attr = CACHEABLE;
+ break;
+ case O_I_WB_NO_WR_ALLOC:
+ attr = CACHEABLE | BUFFERABLE;
+ break;
+ case O_I_NON_CACHEABLE:
+ attr = 1 << TEX_SHIFT;
+ break;
+ case O_I_WB_RD_WR_ALLOC:
+ attr = (1 << TEX_SHIFT) | CACHEABLE | BUFFERABLE;
+ break;
+ case DEVICE_NON_SHARED:
+ attr = (2 << TEX_SHIFT) | BUFFERABLE;
+ break;
+ default:
+ attr = 0; /* strongly ordered */
+ break;
+ };
+
+ return attr;
+}
+
+#endif /* _ASM_ARMV7_MPU_H */
diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h
index 8739607e51..2232ebac8b 100644
--- a/arch/arm/include/asm/dma.h
+++ b/arch/arm/include/asm/dma.h
@@ -10,7 +10,8 @@
struct device;
-#ifndef CONFIG_MMU
+#if !defined(CONFIG_MMU) && !defined(CONFIG_ARMV7R_MPU)
+
#define dma_alloc_coherent dma_alloc_coherent
static inline void *dma_alloc_coherent(struct device *dev,
size_t size, dma_addr_t *dma_handle)
--
2.39.5
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v3 02/23] lib/rationale: compile for pbl
2025-01-13 11:26 [PATCH v3 00/23] ARM: K3: Add R5 boot support Sascha Hauer
2025-01-13 11:26 ` [PATCH v3 01/23] ARM: add ARMv7R MPU support Sascha Hauer
@ 2025-01-13 11:26 ` Sascha Hauer
2025-01-13 11:26 ` [PATCH v3 04/23] ARM: move ARM_CPU_PART_* defines to header Sascha Hauer
` (20 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Sascha Hauer @ 2025-01-13 11:26 UTC (permalink / raw)
To: open list:BAREBOX
Upcoming K3 PLL support needs rational_best_approximation() in PBL, so
enable it for PBL.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
lib/math/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/math/Makefile b/lib/math/Makefile
index 197f92a097..3a31567c58 100644
--- a/lib/math/Makefile
+++ b/lib/math/Makefile
@@ -2,6 +2,6 @@
obj-y += div64.o
pbl-y += div64.o
-obj-y += rational.o
+obj-pbl-y += rational.o
obj-y += int_pow.o
obj-y += int_sqrt.o
--
2.39.5
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v3 04/23] ARM: move ARM_CPU_PART_* defines to header
2025-01-13 11:26 [PATCH v3 00/23] ARM: K3: Add R5 boot support Sascha Hauer
2025-01-13 11:26 ` [PATCH v3 01/23] ARM: add ARMv7R MPU support Sascha Hauer
2025-01-13 11:26 ` [PATCH v3 02/23] lib/rationale: compile for pbl Sascha Hauer
@ 2025-01-13 11:26 ` Sascha Hauer
2025-01-13 11:26 ` [PATCH v3 05/23] nommu_v7_vectors_init: disable for r5 Sascha Hauer
` (19 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Sascha Hauer @ 2025-01-13 11:26 UTC (permalink / raw)
To: open list:BAREBOX
Move the ARM_CPU_PART_* defines to arch/arm/include/asm/cputype.h where
they are located in Linux as well so they become reusable by other code.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/cpu/cpuinfo.c | 11 +----------
arch/arm/include/asm/cputype.h | 11 +++++++++++
2 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/arch/arm/cpu/cpuinfo.c b/arch/arm/cpu/cpuinfo.c
index 7dca57248b..3137b9924f 100644
--- a/arch/arm/cpu/cpuinfo.c
+++ b/arch/arm/cpu/cpuinfo.c
@@ -10,6 +10,7 @@
#include <memory.h>
#include <asm/system.h>
#include <asm/barebox-arm.h>
+#include <asm/cputype.h>
#define CPU_ARCH_UNKNOWN 0
#define CPU_ARCH_ARMv3 1
@@ -23,16 +24,6 @@
#define CPU_ARCH_ARMv7 9
#define CPU_ARCH_ARMv8 10
-#define ARM_CPU_PART_CORTEX_A5 0xC050
-#define ARM_CPU_PART_CORTEX_A7 0xC070
-#define ARM_CPU_PART_CORTEX_A8 0xC080
-#define ARM_CPU_PART_CORTEX_A9 0xC090
-#define ARM_CPU_PART_CORTEX_A15 0xC0F0
-#define ARM_CPU_PART_CORTEX_A53 0xD030
-#define ARM_CPU_PART_CORTEX_A55 0xD050
-#define ARM_CPU_PART_CORTEX_A57 0xD070
-#define ARM_CPU_PART_CORTEX_A72 0xD080
-
static void decode_cache(unsigned long size)
{
int linelen = 1 << ((size & 0x3) + 3);
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index c3fc057650..38012fb1ec 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -117,4 +117,15 @@ static inline int cpu_is_xsc3(void)
#define cpu_is_xscale() 1
#endif
+#define ARM_CPU_PART_CORTEX_A5 0xC050
+#define ARM_CPU_PART_CORTEX_A7 0xC070
+#define ARM_CPU_PART_CORTEX_A8 0xC080
+#define ARM_CPU_PART_CORTEX_A9 0xC090
+#define ARM_CPU_PART_CORTEX_A15 0xC0F0
+#define ARM_CPU_PART_CORTEX_A53 0xD030
+#define ARM_CPU_PART_CORTEX_A55 0xD050
+#define ARM_CPU_PART_CORTEX_A57 0xD070
+#define ARM_CPU_PART_CORTEX_A72 0xD080
+#define ARM_CPU_PART_CORTEX_R5 0xc150
+
#endif
--
2.39.5
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v3 05/23] nommu_v7_vectors_init: disable for r5
2025-01-13 11:26 [PATCH v3 00/23] ARM: K3: Add R5 boot support Sascha Hauer
` (2 preceding siblings ...)
2025-01-13 11:26 ` [PATCH v3 04/23] ARM: move ARM_CPU_PART_* defines to header Sascha Hauer
@ 2025-01-13 11:26 ` Sascha Hauer
2025-01-13 11:26 ` [PATCH v3 06/23] clocksource: timer-ti-dm: add support for K3 SoCs Sascha Hauer
` (18 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Sascha Hauer @ 2025-01-13 11:26 UTC (permalink / raw)
To: open list:BAREBOX
Some ARMv7 cores like the Cortex-R5 do not have a VBAR register for
setting up the vector table. This patch disables the vector table
setup specifically for the Cortex-R5.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/cpu/no-mmu.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm/cpu/no-mmu.c b/arch/arm/cpu/no-mmu.c
index be3cfaf12b..c4ef5d1f9d 100644
--- a/arch/arm/cpu/no-mmu.c
+++ b/arch/arm/cpu/no-mmu.c
@@ -19,9 +19,26 @@
#include <asm/system_info.h>
#include <debug_ll.h>
#include <asm/sections.h>
+#include <asm/cputype.h>
#define __exceptions_size (__exceptions_stop - __exceptions_start)
+static bool has_vbar(void)
+{
+ u32 mainid;
+
+ __asm__ __volatile__(
+ "mrc p15, 0, %0, c0, c0, 0 @ read control reg\n"
+ : "=r" (mainid)
+ :
+ : "memory");
+
+ if ((mainid & 0xfff0) == ARM_CPU_PART_CORTEX_R5)
+ return false;
+
+ return true;
+}
+
static int nommu_v7_vectors_init(void)
{
void *vectors;
@@ -30,6 +47,9 @@ static int nommu_v7_vectors_init(void)
if (cpu_architecture() < CPU_ARCH_ARMv7)
return 0;
+ if (!has_vbar())
+ return 0;
+
/*
* High vectors cannot be re-mapped, so we have to use normal
* vectors
--
2.39.5
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v3 06/23] clocksource: timer-ti-dm: add support for K3 SoCs
2025-01-13 11:26 [PATCH v3 00/23] ARM: K3: Add R5 boot support Sascha Hauer
` (3 preceding siblings ...)
2025-01-13 11:26 ` [PATCH v3 05/23] nommu_v7_vectors_init: disable for r5 Sascha Hauer
@ 2025-01-13 11:26 ` Sascha Hauer
2025-01-13 11:26 ` [PATCH v3 07/23] ARM: K3: mount /boot even with env handling disabled Sascha Hauer
` (17 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Sascha Hauer @ 2025-01-13 11:26 UTC (permalink / raw)
To: open list:BAREBOX
K3 SoCs have a timer compatible to the ones found on the AM335x SoCs.
This patch adds support for these SoCs to the driver. The main
difference is that on AM335x we do not have clk support and get the
timer frequency from a SoC specific call, thus we have to play some
ifdeffery to add clk support for K3 and still keep the SoC specific
call to the AM335x code.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/clocksource/timer-ti-dm.c | 53 +++++++++++++++++++++++++++++++++++----
1 file changed, 48 insertions(+), 5 deletions(-)
diff --git a/drivers/clocksource/timer-ti-dm.c b/drivers/clocksource/timer-ti-dm.c
index 8473cf733d..eb658402f5 100644
--- a/drivers/clocksource/timer-ti-dm.c
+++ b/drivers/clocksource/timer-ti-dm.c
@@ -21,8 +21,8 @@
#include <clock.h>
#include <init.h>
#include <io.h>
-#include <mach/omap/am33xx-silicon.h>
#include <mach/omap/am33xx-clock.h>
+#include <linux/clk.h>
#include <stdio.h>
@@ -65,10 +65,15 @@ static struct clocksource dmtimer_cs = {
.priority = 70,
};
+struct omap_dmtimer_data {
+ int (*get_clock)(struct device *dev);
+};
+
static int omap_dmtimer_probe(struct device *dev)
{
struct resource *iores;
- u64 clk_speed;
+ int clk_speed;
+ const struct omap_dmtimer_data *data;
/* one timer is enough */
if (base)
@@ -79,8 +84,12 @@ static int omap_dmtimer_probe(struct device *dev)
return PTR_ERR(iores);
base = IOMEM(iores->start);
- clk_speed = am33xx_get_osc_clock();
- clk_speed *= 1000;
+ data = device_get_match_data(dev);
+
+ clk_speed = data->get_clock(dev);
+ if (clk_speed < 0)
+ return clk_speed;
+
dmtimer_cs.mult = clocksource_hz2mult(clk_speed, dmtimer_cs.shift);
/* Enable counter */
@@ -89,10 +98,44 @@ static int omap_dmtimer_probe(struct device *dev)
return init_clock(&dmtimer_cs);
}
+static int am335x_get_clock(struct device *dev)
+{
+ return am33xx_get_osc_clock() * 1000;
+}
+
+static __maybe_unused struct omap_dmtimer_data am335x_data = {
+ .get_clock = am335x_get_clock,
+};
+
+static int k3_get_clock(struct device *dev)
+{
+ struct clk *clk;
+
+ clk = clk_get(dev, NULL);
+ if (IS_ERR(clk))
+ return dev_err_probe(dev, PTR_ERR(clk), "Cannot get clock\n");
+
+ return clk_get_rate(clk);
+}
+
+static __maybe_unused struct omap_dmtimer_data k3_data = {
+ .get_clock = k3_get_clock,
+};
+
static __maybe_unused struct of_device_id omap_dmtimer_dt_ids[] = {
+#ifdef CONFIG_ARCH_OMAP
{
.compatible = "ti,am335x-timer",
- }, {
+ .data = &am335x_data,
+ },
+#endif
+#ifdef CONFIG_ARCH_K3
+ {
+ .compatible = "ti,am654-timer",
+ .data = &k3_data,
+ },
+#endif
+ {
/* sentinel */
}
};
--
2.39.5
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v3 07/23] ARM: K3: mount /boot even with env handling disabled
2025-01-13 11:26 [PATCH v3 00/23] ARM: K3: Add R5 boot support Sascha Hauer
` (4 preceding siblings ...)
2025-01-13 11:26 ` [PATCH v3 06/23] clocksource: timer-ti-dm: add support for K3 SoCs Sascha Hauer
@ 2025-01-13 11:26 ` Sascha Hauer
2025-01-13 11:26 ` [PATCH v3 08/23] clk: add K3 clk driver Sascha Hauer
` (16 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Sascha Hauer @ 2025-01-13 11:26 UTC (permalink / raw)
To: open list:BAREBOX
barebox for the Cortex-R5 boot processor doesn't have environment
enabled, but still needs the bootsource mounted to /boot. Both steps
are behind a #ifdef CONFIG_ENV_HANDLING. Move the mounting of /boot
outside the ifdef.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-k3/common.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 1b623d22f6..d7b44f31e8 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -178,7 +178,6 @@ static int am625_init(void)
}
postcore_initcall(am625_init);
-#if defined(CONFIG_ENV_HANDLING)
static int omap_env_init(void)
{
char *partname, *cdevname, *envpath;
@@ -217,14 +216,17 @@ static int omap_env_init(void)
symlink(rootpath, "/boot");
- envpath = xasprintf("%s/barebox.env", rootpath);
+ if (IS_ENABLED(CONFIG_ENV_HANDLING)) {
+ envpath = xasprintf("%s/barebox.env", rootpath);
- pr_debug("Loading default env from %s on device %s\n",
- envpath, partname);
+ pr_debug("Loading default env from %s on device %s\n",
+ envpath, partname);
- default_environment_path_set(envpath);
+ default_environment_path_set(envpath);
+
+ free(envpath);
+ }
- free(envpath);
out:
free(partname);
free(cdevname);
@@ -232,4 +234,3 @@ static int omap_env_init(void)
return 0;
}
late_initcall(omap_env_init);
-#endif
--
2.39.5
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v3 08/23] clk: add K3 clk driver
2025-01-13 11:26 [PATCH v3 00/23] ARM: K3: Add R5 boot support Sascha Hauer
` (5 preceding siblings ...)
2025-01-13 11:26 ` [PATCH v3 07/23] ARM: K3: mount /boot even with env handling disabled Sascha Hauer
@ 2025-01-13 11:26 ` Sascha Hauer
2025-01-13 11:26 ` [PATCH v3 09/23] pmdomain: add K3 driver Sascha Hauer
` (15 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Sascha Hauer @ 2025-01-13 11:26 UTC (permalink / raw)
To: open list:BAREBOX
The clk support for K3 SoCs is implemented on the Cortex-R5 boot
processor by the ti-dm firmware binary. The A53 cores access the clks
via mailboxes. However, during early boot we are running barebox on the
Cortex-R5 processor and the ti-dm firmware is not yet running, so we
must implement our own clk driver. Code is based on U-Boot-2025.01-rc1.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/clk/Makefile | 1 +
drivers/clk/k3/Makefile | 2 +
drivers/clk/k3/am625.c | 475 +++++++++++++++++++++++++++++++++++++++++++++
drivers/clk/k3/pll.c | 375 +++++++++++++++++++++++++++++++++++
drivers/clk/k3/ti-k3-clk.h | 8 +
include/soc/k3/clk.h | 7 +
6 files changed, 868 insertions(+)
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 764539e91e..8c3544c750 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -31,3 +31,4 @@ obj-y += bcm/
obj-$(CONFIG_COMMON_CLK_SCMI) += clk-scmi.o
obj-$(CONFIG_COMMON_CLK_GPIO) += clk-gpio.o
obj-$(CONFIG_TI_SCI_CLK) += ti-sci-clk.o
+obj-$(CONFIG_ARCH_K3) += k3/
diff --git a/drivers/clk/k3/Makefile b/drivers/clk/k3/Makefile
new file mode 100644
index 0000000000..8d96373ab6
--- /dev/null
+++ b/drivers/clk/k3/Makefile
@@ -0,0 +1,2 @@
+obj-y += am625.o
+obj-pbl-y += pll.o
diff --git a/drivers/clk/k3/am625.c b/drivers/clk/k3/am625.c
new file mode 100644
index 0000000000..c7e28658d1
--- /dev/null
+++ b/drivers/clk/k3/am625.c
@@ -0,0 +1,475 @@
+#define pr_fmt(fmt) "ti-k3-clk: " fmt
+
+#include <linux/clk.h>
+#include <of.h>
+#include <driver.h>
+#include "ti-k3-clk.h"
+
+static const char * const gluelogic_hfosc0_clkout_parents[] = {
+ NULL,
+ NULL,
+ "osc_24_mhz",
+ "osc_25_mhz",
+ "osc_26_mhz",
+ NULL,
+};
+
+static const char * const main_emmcsd0_io_clklb_sel_out0_parents[] = {
+ "board_0_mmc0_clklb_out",
+ "board_0_mmc0_clk_out",
+};
+
+static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = {
+ "board_0_mmc1_clklb_out",
+ "board_0_mmc1_clk_out",
+};
+
+static const char * const main_ospi_loopback_clk_sel_out0_parents[] = {
+ "board_0_ospi0_dqs_out",
+ "board_0_ospi0_lbclko_out",
+};
+
+static const char * const main_usb0_refclk_sel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "postdiv4_16ff_main_0_hsdivout8_clk",
+};
+
+static const char * const main_usb1_refclk_sel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "postdiv4_16ff_main_0_hsdivout8_clk",
+};
+
+static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "hsdiv4_16fft_main_0_hsdivout0_clk",
+};
+
+static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "hsdiv4_16fft_mcu_0_hsdivout0_clk",
+};
+
+static const char * const clkout0_ctrl_out0_parents[] = {
+ "hsdiv4_16fft_main_2_hsdivout1_clk",
+ "hsdiv4_16fft_main_2_hsdivout1_clk10",
+};
+
+static const char * const clk_32k_rc_sel_out0_parents[] = {
+ "gluelogic_rcosc_clk_1p0v_97p65k",
+ "hsdiv0_16fft_mcu_32khz_gen_0_hsdivout0_clk",
+ "clk_32k_rc_sel_div_clkout",
+ "gluelogic_lfosc0_clkout",
+};
+
+static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = {
+ "postdiv4_16ff_main_2_hsdivout5_clk",
+ "postdiv4_16ff_main_0_hsdivout6_clk",
+ "board_0_cp_gemac_cpts0_rft_clk_out",
+ NULL,
+ "board_0_mcu_ext_refclk0_out",
+ "board_0_ext_refclk1_out",
+ "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
+ "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+};
+
+static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
+ "postdiv4_16ff_main_0_hsdivout5_clk",
+ "hsdiv4_16fft_main_2_hsdivout2_clk",
+};
+
+static const char * const main_emmcsd1_refclk_sel_out0_parents[] = {
+ "postdiv4_16ff_main_0_hsdivout5_clk",
+ "hsdiv4_16fft_main_2_hsdivout2_clk",
+};
+
+static const char * const main_gtcclk_sel_out0_parents[] = {
+ "postdiv4_16ff_main_2_hsdivout5_clk",
+ "postdiv4_16ff_main_0_hsdivout6_clk",
+ "board_0_cp_gemac_cpts0_rft_clk_out",
+ NULL,
+ "board_0_mcu_ext_refclk0_out",
+ "board_0_ext_refclk1_out",
+ "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
+ "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+};
+
+static const char * const main_ospi_ref_clk_sel_out0_parents[] = {
+ "hsdiv4_16fft_main_0_hsdivout1_clk",
+ "postdiv1_16fft_main_1_hsdivout5_clk",
+};
+
+static const char * const wkup_clkout_sel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "gluelogic_lfosc0_clkout",
+ "hsdiv4_16fft_main_0_hsdivout2_clk",
+ "hsdiv4_16fft_main_1_hsdivout2_clk",
+ "postdiv4_16ff_main_2_hsdivout9_clk",
+ "clk_32k_rc_sel_out0",
+ "gluelogic_rcosc_clkout",
+ "gluelogic_hfosc0_clkout",
+};
+
+static const char * const wkup_clksel_out0_parents[] = {
+ "hsdiv1_16fft_main_15_hsdivout0_clk",
+ "hsdiv4_16fft_mcu_0_hsdivout0_clk",
+};
+
+static const char * const main_usart0_fclk_sel_out0_parents[] = {
+ "usart_programmable_clock_divider_out0",
+ "hsdiv4_16fft_main_1_hsdivout1_clk",
+};
+
+static inline struct clk *k3_clk_divider(const char *name, const char *parent,
+ void __iomem *reg, u8 shift, u8 width, u32 flags, u32 div_flags)
+{
+ return clk_divider(name, parent, CLK_SET_RATE_PARENT, reg, shift, width, 0);
+}
+
+static inline struct clk *k3_clk_pll(const char *name, const char *parent,
+ void __iomem *reg, u32 flags)
+{
+ return clk_register_ti_k3_pll(name, parent, reg);
+}
+
+static inline struct clk *k3_clk_mux(const char *name, const char * const *parents,
+ int num_parents, void __iomem *reg, u8 shift,
+ u8 width, u32 flags)
+{
+ return clk_mux(name, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT | flags, reg,
+ shift, width, parents, num_parents, 0);
+}
+
+static inline struct clk *k3_clk_div_devfreq(const char *name, const char *parent,
+ void __iomem *reg, u8 shift, u8 width, u32 flags, u32 div_flags, u32 freq)
+{
+ return NULL;
+}
+
+static inline struct clk *k3_clk_mux_pllctrl(const char *name, const char * const *parents,
+ int num_parents, void __iomem *reg, u32 freq)
+{
+ return NULL;
+}
+
+struct clk_lookup_data {
+ unsigned int dev_id;
+ unsigned int clk_id;
+ const char *clk_name;
+};
+
+#define DEV_CLK(_dev_id, _clk_id, _clk_name) { .dev_id = _dev_id, \
+ .clk_id = _clk_id, .clk_name = _clk_name, }
+
+static struct clk_lookup_data am625_lookup[] = {
+ DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"),
+ DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"),
+ DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"),
+ DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"),
+ DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"),
+ DEV_CLK(13, 9, "board_0_ext_refclk1_out"),
+ DEV_CLK(13, 10, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
+ DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 19, "board_0_rgmii1_rxc_out"),
+ DEV_CLK(13, 20, "board_0_rgmii1_txc_out"),
+ DEV_CLK(13, 22, "board_0_rgmii2_rxc_out"),
+ DEV_CLK(13, 23, "board_0_rgmii2_txc_out"),
+ DEV_CLK(13, 25, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 26, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 27, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 28, "board_0_rmii1_ref_clk_out"),
+ DEV_CLK(13, 29, "board_0_rmii2_ref_clk_out"),
+ DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"),
+ DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
+ DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
+ DEV_CLK(16, 3, "hsdiv4_16fft_main_0_hsdivout4_clk"),
+ DEV_CLK(16, 4, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(16, 5, "board_0_ext_refclk1_out"),
+ DEV_CLK(16, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(16, 7, "postdiv4_16ff_main_2_hsdivout8_clk"),
+ DEV_CLK(16, 8, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(16, 9, "board_0_ext_refclk1_out"),
+ DEV_CLK(16, 10, "gluelogic_rcosc_clkout"),
+ DEV_CLK(16, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(16, 12, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(57, 0, "main_emmcsd0_io_clklb_sel_out0"),
+ DEV_CLK(57, 1, "board_0_mmc0_clklb_out"),
+ DEV_CLK(57, 2, "board_0_mmc0_clk_out"),
+ DEV_CLK(57, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(57, 6, "main_emmcsd0_refclk_sel_out0"),
+ DEV_CLK(57, 7, "postdiv4_16ff_main_0_hsdivout5_clk"),
+ DEV_CLK(57, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"),
+ DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"),
+ DEV_CLK(58, 1, "board_0_mmc1_clklb_out"),
+ DEV_CLK(58, 2, "board_0_mmc1_clk_out"),
+ DEV_CLK(58, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(58, 6, "main_emmcsd1_refclk_sel_out0"),
+ DEV_CLK(58, 7, "postdiv4_16ff_main_0_hsdivout5_clk"),
+ DEV_CLK(58, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"),
+ DEV_CLK(61, 0, "main_gtcclk_sel_out0"),
+ DEV_CLK(61, 1, "postdiv4_16ff_main_2_hsdivout5_clk"),
+ DEV_CLK(61, 2, "postdiv4_16ff_main_0_hsdivout6_clk"),
+ DEV_CLK(61, 3, "board_0_cp_gemac_cpts0_rft_clk_out"),
+ DEV_CLK(61, 5, "board_0_mcu_ext_refclk0_out"),
+ DEV_CLK(61, 6, "board_0_ext_refclk1_out"),
+ DEV_CLK(61, 7, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
+ DEV_CLK(61, 8, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(61, 9, "wkup_clksel_out0"),
+ DEV_CLK(61, 10, "hsdiv1_16fft_main_15_hsdivout0_clk"),
+ DEV_CLK(61, 11, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
+ DEV_CLK(75, 0, "board_0_ospi0_dqs_out"),
+ DEV_CLK(75, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(75, 2, "main_ospi_loopback_clk_sel_out0"),
+ DEV_CLK(75, 3, "board_0_ospi0_dqs_out"),
+ DEV_CLK(75, 4, "board_0_ospi0_lbclko_out"),
+ DEV_CLK(75, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(75, 7, "main_ospi_ref_clk_sel_out0"),
+ DEV_CLK(75, 8, "hsdiv4_16fft_main_0_hsdivout1_clk"),
+ DEV_CLK(75, 9, "postdiv1_16fft_main_1_hsdivout5_clk"),
+ DEV_CLK(77, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(95, 0, "gluelogic_rcosc_clkout"),
+ DEV_CLK(95, 1, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(95, 2, "wkup_clksel_out0"),
+ DEV_CLK(95, 3, "hsdiv1_16fft_main_15_hsdivout0_clk"),
+ DEV_CLK(95, 4, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
+ DEV_CLK(102, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(102, 1, "board_0_i2c0_scl_out"),
+ DEV_CLK(102, 2, "hsdiv4_16fft_main_1_hsdivout0_clk"),
+ DEV_CLK(107, 0, "wkup_clksel_out0"),
+ DEV_CLK(107, 1, "hsdiv1_16fft_main_15_hsdivout0_clk"),
+ DEV_CLK(107, 2, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
+ DEV_CLK(107, 3, "mshsi2c_wkup_0_porscl"),
+ DEV_CLK(107, 4, "hsdiv4_16fft_mcu_0_hsdivout1_clk"),
+ DEV_CLK(135, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+ DEV_CLK(136, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+ DEV_CLK(140, 0, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
+ DEV_CLK(140, 1, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
+ DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"),
+ DEV_CLK(146, 1, "usart_programmable_clock_divider_out0"),
+ DEV_CLK(146, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"),
+ DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(157, 20, "clkout0_ctrl_out0"),
+ DEV_CLK(157, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk10"),
+ DEV_CLK(157, 24, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(157, 25, "board_0_ddr0_ck0_out"),
+ DEV_CLK(157, 40, "mshsi2c_main_0_porscl"),
+ DEV_CLK(157, 77, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"),
+ DEV_CLK(157, 82, "cpsw_3guss_main_0_mdio_mdclk_o"),
+ DEV_CLK(157, 83, "emmcsd8ss_main_0_emmcsdss_io_clk_o"),
+ DEV_CLK(157, 87, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
+ DEV_CLK(157, 89, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
+ DEV_CLK(157, 129, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
+ DEV_CLK(157, 132, "cpsw_3guss_main_0_rgmii1_txc_o"),
+ DEV_CLK(157, 135, "cpsw_3guss_main_0_rgmii2_txc_o"),
+ DEV_CLK(157, 145, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"),
+ DEV_CLK(157, 158, "wkup_clkout_sel_out0"),
+ DEV_CLK(157, 159, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(157, 160, "gluelogic_lfosc0_clkout"),
+ DEV_CLK(157, 161, "hsdiv4_16fft_main_0_hsdivout2_clk"),
+ DEV_CLK(157, 162, "hsdiv4_16fft_main_1_hsdivout2_clk"),
+ DEV_CLK(157, 163, "postdiv4_16ff_main_2_hsdivout9_clk"),
+ DEV_CLK(157, 164, "clk_32k_rc_sel_out0"),
+ DEV_CLK(157, 165, "gluelogic_rcosc_clkout"),
+ DEV_CLK(157, 166, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(161, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(161, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(161, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(161, 3, "main_usb0_refclk_sel_out0"),
+ DEV_CLK(161, 4, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(161, 5, "postdiv4_16ff_main_0_hsdivout8_clk"),
+ DEV_CLK(161, 10, "board_0_tck_out"),
+ DEV_CLK(162, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(162, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(162, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(162, 3, "main_usb1_refclk_sel_out0"),
+ DEV_CLK(162, 4, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(162, 5, "postdiv4_16ff_main_0_hsdivout8_clk"),
+ DEV_CLK(162, 10, "board_0_tck_out"),
+ DEV_CLK(166, 3, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+ DEV_CLK(166, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(169, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(169, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(170, 0, "hsdiv0_16fft_main_12_hsdivout0_clk"),
+ DEV_CLK(170, 1, "board_0_tck_out"),
+ DEV_CLK(170, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+
+ /*
+ * Timer clocks. There is a mux between the timer and the clock core
+ * which we haven't modeled here. The values reflect the reset default
+ * of the mux
+ */
+ DEV_CLK(35, 2, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(36, 2, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(37, 2, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(38, 2, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(39, 2, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(40, 2, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(41, 2, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(42, 2, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(43, 2, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(48, 2, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(49, 2, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(50, 2, "gluelogic_hfosc0_clkout"),
+
+ DEV_CLK(0, 0, NULL),
+};
+
+static struct clk *of_clk_ti_k3_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct clk_lookup_data *clk_data = data;
+ struct clk *clk;
+ unsigned int dev_id = clkspec->args[0];
+ unsigned int clk_id = clkspec->args[1];
+
+ while (1) {
+ if (!clk_data->clk_name) {
+ pr_err("clk %d/%d not found\n", dev_id, clk_id);
+ return ERR_PTR(-ENOENT);
+ }
+
+ if (clk_data->dev_id == dev_id && clk_data->clk_id == clk_id)
+ goto found;
+
+ clk_data++;
+ }
+found:
+ clk = clk_lookup(clk_data->clk_name);
+ if (IS_ERR(clk))
+ pr_err("clk %s not found\n", clk_data->clk_name);
+
+ return clk;
+}
+
+static int am625_clk_init(struct device *dev)
+{
+ int ret;
+
+ clk_fixed("osc_26_mhz", 26000000);
+ clk_fixed("osc_25_mhz", 25000000);
+ clk_fixed("osc_24_mhz", 24000000);
+ k3_clk_mux("gluelogic_hfosc0_clkout",
+ gluelogic_hfosc0_clkout_parents, 6, (void *)0x43000030, 0, 3, 0),
+ clk_fixed("gluelogic_rcosc_clkout", 12500000);
+ clk_fixed("gluelogic_rcosc_clk_1p0v_97p65k", 97656);
+ clk_fixed("board_0_cp_gemac_cpts0_rft_clk_out", 0);
+ clk_fixed("board_0_ddr0_ck0_out", 0);
+ clk_fixed("board_0_ext_refclk1_out", 0);
+ clk_fixed("board_0_i2c0_scl_out", 0);
+ clk_fixed("board_0_mcu_ext_refclk0_out", 0);
+ clk_fixed("board_0_mmc0_clklb_out", 0);
+ clk_fixed("board_0_mmc0_clk_out", 0);
+ clk_fixed("board_0_mmc1_clklb_out", 0);
+ clk_fixed("board_0_mmc1_clk_out", 0);
+ clk_fixed("board_0_ospi0_dqs_out", 0);
+ clk_fixed("board_0_ospi0_lbclko_out", 0);
+ clk_fixed("board_0_rgmii1_rxc_out", 0);
+ clk_fixed("board_0_rgmii1_txc_out", 0);
+ clk_fixed("board_0_rgmii2_rxc_out", 0);
+ clk_fixed("board_0_rgmii2_txc_out", 0);
+ clk_fixed("board_0_rmii1_ref_clk_out", 0);
+ clk_fixed("board_0_rmii2_ref_clk_out", 0);
+ clk_fixed("board_0_tck_out", 0);
+ clk_fixed("cpsw_3guss_main_0_mdio_mdclk_o", 0);
+ clk_fixed("cpsw_3guss_main_0_rgmii1_txc_o", 0);
+ clk_fixed("cpsw_3guss_main_0_rgmii2_txc_o", 0);
+ clk_fixed("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0);
+ clk_fixed("emmcsd8ss_main_0_emmcsdss_io_clk_o", 0);
+ clk_fixed("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0);
+ k3_clk_divider("hsdiv0_16fft_mcu_32khz_gen_0_hsdivout0_clk", "gluelogic_hfosc0_clkout", (void *)0x4508030, 0, 7, 0, 0);
+ clk_fixed("mshsi2c_main_0_porscl", 0);
+ k3_clk_pll("pllfracf_ssmod_16fft_main_0_foutvcop_clk", "gluelogic_hfosc0_clkout", (void *)0x680000, 0);
+ k3_clk_divider("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", (void *)0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED);
+ k3_clk_divider("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", (void *)0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED);
+ k3_clk_pll("pllfracf_ssmod_16fft_main_1_foutvcop_clk", "gluelogic_hfosc0_clkout", (void *)0x681000, 0);
+ k3_clk_divider("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", (void *)0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED);
+ k3_clk_divider("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", (void *)0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED);
+ k3_clk_pll("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "gluelogic_hfosc0_clkout", (void *)0x68c000, 0);
+ k3_clk_pll("pllfracf_ssmod_16fft_main_15_foutvcop_clk", "gluelogic_hfosc0_clkout", (void *)0x68f000, 0);
+ k3_clk_pll("pllfracf_ssmod_16fft_main_2_foutvcop_clk", "gluelogic_hfosc0_clkout", (void *)0x682000, 0);
+ k3_clk_divider("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", (void *)0x682038, 16, 3, 0, CLK_DIVIDER_ONE_BASED);
+ k3_clk_divider("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", (void *)0x682038, 24, 3, 0, CLK_DIVIDER_ONE_BASED);
+ k3_clk_pll("pllfracf_ssmod_16fft_main_8_foutvcop_clk", "gluelogic_hfosc0_clkout", (void *)0x688000, 0);
+ k3_clk_pll("pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", "gluelogic_hfosc0_clkout", (void *)0x4040000, 0);
+ k3_clk_divider("postdiv1_16fft_main_1_hsdivout5_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", (void *)0x681094, 0, 7, 0, 0);
+ k3_clk_divider("postdiv4_16ff_main_0_hsdivout5_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", (void *)0x680094, 0, 7, 0, 0);
+ k3_clk_divider("postdiv4_16ff_main_0_hsdivout6_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", (void *)0x680098, 0, 7, 0, 0);
+ k3_clk_divider("postdiv4_16ff_main_0_hsdivout8_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", (void *)0x6800a0, 0, 7, 0, 0);
+ k3_clk_divider("postdiv4_16ff_main_2_hsdivout5_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", (void *)0x682094, 0, 7, 0, 0);
+ k3_clk_divider("postdiv4_16ff_main_2_hsdivout8_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", (void *)0x6820a0, 0, 7, 0, 0);
+ k3_clk_divider("postdiv4_16ff_main_2_hsdivout9_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", (void *)0x6820a4, 0, 7, 0, 0);
+ k3_clk_mux("main_emmcsd0_io_clklb_sel_out0", main_emmcsd0_io_clklb_sel_out0_parents, 2, (void *)0x108160, 16, 1, 0);
+ k3_clk_mux("main_emmcsd1_io_clklb_sel_out0", main_emmcsd1_io_clklb_sel_out0_parents, 2, (void *)0x108168, 16, 1, 0);
+ k3_clk_mux("main_ospi_loopback_clk_sel_out0", main_ospi_loopback_clk_sel_out0_parents, 2, (void *)0x108500, 4, 1, 0);
+ k3_clk_mux("main_usb0_refclk_sel_out0", main_usb0_refclk_sel_out0_parents, 2, (void *)0x43008190, 0, 1, 0);
+ k3_clk_mux("main_usb1_refclk_sel_out0", main_usb1_refclk_sel_out0_parents, 2, (void *)0x43008194, 0, 1, 0);
+ k3_clk_divider("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", (void *)0x68c080, 0, 7, 0, 0);
+ k3_clk_divider("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", (void *)0x688080, 0, 7, 0, 0);
+ k3_clk_divider("hsdiv1_16fft_main_15_hsdivout0_clk", "pllfracf_ssmod_16fft_main_15_foutvcop_clk", (void *)0x68f080, 0, 7, 0, 0);
+ k3_clk_divider("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", (void *)0x680080, 0, 7, 0, 0);
+ k3_clk_divider("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", (void *)0x680084, 0, 7, 0, 0);
+ k3_clk_divider("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", (void *)0x680088, 0, 7, 0, 0);
+ k3_clk_divider("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", (void *)0x68008c, 0, 7, 0, 0);
+ k3_clk_divider("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", (void *)0x680090, 0, 7, 0, 0);
+ k3_clk_div_devfreq("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", (void *)0x681080, 0, 7, 0, 0, 192000000);
+ k3_clk_divider("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", (void *)0x681084, 0, 7, 0, 0);
+ k3_clk_divider("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", (void *)0x681088, 0, 7, 0, 0);
+ k3_clk_divider("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", (void *)0x682084, 0, 7, 0, 0);
+ k3_clk_divider("hsdiv4_16fft_main_2_hsdivout1_clk10", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", (void *)0x682084, 0, 7, 0, 0);
+ k3_clk_divider("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", (void *)0x682088, 0, 7, 0, 0);
+ k3_clk_divider("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", (void *)0x4040080, 0, 7, 0, 0);
+ k3_clk_mux_pllctrl("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, (void *)0x410000, 0);
+ k3_clk_divider("sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", (void *)0x410118, 0, 5, 0, 0);
+ k3_clk_mux_pllctrl("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, (void *)0x4020000, 0);
+ k3_clk_divider("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", (void *)0x4020118, 0, 5, 0, 0);
+ k3_clk_mux("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, (void *)0x108010, 0, 1, 0);
+ k3_clk_mux("clk_32k_rc_sel_out0", clk_32k_rc_sel_out0_parents, 4, (void *)0x4508058, 0, 2, 0);
+ k3_clk_mux("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, (void *)0x108140, 0, 3, 0);
+ k3_clk_mux("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, (void *)0x108160, 0, 1, 0);
+ k3_clk_mux("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, (void *)0x108168, 0, 1, 0);
+ k3_clk_mux("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, (void *)0x43008030, 0, 3, 0);
+ k3_clk_mux("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, (void *)0x108500, 0, 1, 0);
+ k3_clk_div_devfreq("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", (void *)0x108240, 0, 2, 0, 0, 48000000);
+ k3_clk_mux("wkup_clkout_sel_out0", wkup_clkout_sel_out0_parents, 8, (void *)0x43008020, 0, 3, 0);
+ k3_clk_mux("wkup_clksel_out0", wkup_clksel_out0_parents, 2, (void *)0x43008010, 0, 1, 0);
+ k3_clk_mux("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, (void *)0x108280, 0, 1, 0);
+ k3_clk_divider("hsdiv4_16fft_mcu_0_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", (void *)0x4040084, 0, 7, 0, 0);
+ clk_fixed("mshsi2c_wkup_0_porscl", 0);
+ k3_clk_divider("sam62_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", (void *)0x41011c, 0, 5, 0, 0);
+ k3_clk_divider("sam62_pll_ctrl_wrap_mcu_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", (void *)0x402011c, 0, 5, 0, 0);
+
+ ret = of_clk_add_provider(dev->of_node, of_clk_ti_k3_get, &am625_lookup);
+ if (ret < 0)
+ pr_err("failed to register clks for i.MX8MM\n");
+
+ return 0;
+};
+
+static int ti_k3_clk_probe(struct device *dev)
+{
+ if (of_machine_is_compatible("ti,am625"))
+ return am625_clk_init(dev);
+
+ return dev_err_probe(dev, -EINVAL, "Unknown SoC\n");
+}
+
+static __maybe_unused struct of_device_id ti_k3_clk_dt_ids[] = {
+ {
+ .compatible = "ti,k2g-sci-clk",
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct driver ti_k3_clk_driver = {
+ .probe = ti_k3_clk_probe,
+ .name = "ti-k3-clk",
+ .of_compatible = ti_k3_clk_dt_ids,
+};
+
+core_platform_driver(ti_k3_clk_driver);
diff --git a/drivers/clk/k3/pll.c b/drivers/clk/k3/pll.c
new file mode 100644
index 0000000000..c76a91b1d0
--- /dev/null
+++ b/drivers/clk/k3/pll.c
@@ -0,0 +1,375 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments K3 SoC PLL clock driver
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Tero Kristo <t-kristo@ti.com>
+ */
+
+#include <io.h>
+#include <errno.h>
+#include <linux/clk-provider.h>
+#include <linux/rational.h>
+#include <linux/slab.h>
+#include <linux/bitmap.h>
+#include <linux/printk.h>
+#include <soc/k3/clk.h>
+
+#include "ti-k3-clk.h"
+
+/* 16FFT register offsets */
+#define PLL_16FFT_CFG 0x08
+#define PLL_KICK0 0x10
+#define PLL_KICK1 0x14
+#define PLL_16FFT_CTRL 0x20
+#define PLL_16FFT_STAT 0x24
+#define PLL_16FFT_FREQ_CTRL0 0x30
+#define PLL_16FFT_FREQ_CTRL1 0x34
+#define PLL_16FFT_DIV_CTRL 0x38
+#define PLL_16FFT_CAL_CTRL 0x60
+#define PLL_16FFT_CAL_STAT 0x64
+
+/* CAL STAT register bits */
+#define PLL_16FFT_CAL_STAT_CAL_LOCK BIT(31)
+
+/* CFG register bits */
+#define PLL_16FFT_CFG_PLL_TYPE_SHIFT (0)
+#define PLL_16FFT_CFG_PLL_TYPE_MASK (0x3 << 0)
+#define PLL_16FFT_CFG_PLL_TYPE_FRACF 1
+
+/* CAL CTRL register bits */
+#define PLL_16FFT_CAL_CTRL_CAL_EN BIT(31)
+#define PLL_16FFT_CAL_CTRL_FAST_CAL BIT(20)
+#define PLL_16FFT_CAL_CTRL_CAL_BYP BIT(15)
+#define PLL_16FFT_CAL_CTRL_CAL_CNT_SHIFT 16
+#define PLL_16FFT_CAL_CTRL_CAL_CNT_MASK (0x7 << 16)
+
+/* CTRL register bits */
+#define PLL_16FFT_CTRL_BYPASS_EN BIT(31)
+#define PLL_16FFT_CTRL_PLL_EN BIT(15)
+#define PLL_16FFT_CTRL_DSM_EN BIT(1)
+
+/* STAT register bits */
+#define PLL_16FFT_STAT_LOCK BIT(0)
+
+/* FREQ_CTRL0 bits */
+#define PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK 0xfff
+
+/* DIV CTRL register bits */
+#define PLL_16FFT_DIV_CTRL_REF_DIV_MASK 0x3f
+
+/* HSDIV register bits*/
+#define PLL_16FFT_HSDIV_CTRL_CLKOUT_EN BIT(15)
+
+/* FREQ_CTRL1 bits */
+#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS 24
+#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_MASK 0xffffff
+#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_SHIFT 0
+
+/* KICK register magic values */
+#define PLL_KICK0_VALUE 0x68ef3490
+#define PLL_KICK1_VALUE 0xd172bc5a
+
+/**
+ * struct ti_pll_clk - TI PLL clock data info structure
+ * @clk: core clock structure
+ * @reg: memory address of the PLL controller
+ */
+struct ti_pll_clk {
+ struct clk_hw hw;
+ void __iomem *reg;
+ const char *parent;
+};
+
+static inline struct ti_pll_clk *to_pll(struct clk_hw *hw)
+{
+ return container_of(hw, struct ti_pll_clk, hw);
+}
+
+static int ti_pll_wait_for_lock(struct ti_pll_clk *pll)
+{
+ u32 stat;
+ u32 cfg;
+ u32 cal;
+ u32 freq_ctrl1;
+ int i;
+ u32 pllfm;
+ u32 pll_type;
+ int success;
+
+ for (i = 0; i < 100000; i++) {
+ stat = readl(pll->reg + PLL_16FFT_STAT);
+ if (stat & PLL_16FFT_STAT_LOCK) {
+ success = 1;
+ break;
+ }
+ }
+
+ /* Enable calibration if not in fractional mode of the FRACF PLL */
+ freq_ctrl1 = readl(pll->reg + PLL_16FFT_FREQ_CTRL1);
+ pllfm = freq_ctrl1 & PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_MASK;
+ pllfm >>= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_SHIFT;
+ cfg = readl(pll->reg + PLL_16FFT_CFG);
+ pll_type = (cfg & PLL_16FFT_CFG_PLL_TYPE_MASK) >> PLL_16FFT_CFG_PLL_TYPE_SHIFT;
+
+ if (success && pll_type == PLL_16FFT_CFG_PLL_TYPE_FRACF && pllfm == 0) {
+ cal = readl(pll->reg + PLL_16FFT_CAL_CTRL);
+
+ /* Enable calibration for FRACF */
+ cal |= PLL_16FFT_CAL_CTRL_CAL_EN;
+
+ /* Enable fast cal mode */
+ cal |= PLL_16FFT_CAL_CTRL_FAST_CAL;
+
+ /* Disable calibration bypass */
+ cal &= ~PLL_16FFT_CAL_CTRL_CAL_BYP;
+
+ /* Set CALCNT to 2 */
+ cal &= ~PLL_16FFT_CAL_CTRL_CAL_CNT_MASK;
+ cal |= 2 << PLL_16FFT_CAL_CTRL_CAL_CNT_SHIFT;
+
+ /* Note this register does not readback the written value. */
+ writel(cal, pll->reg + PLL_16FFT_CAL_CTRL);
+
+ success = 0;
+ for (i = 0; i < 100000; i++) {
+ stat = readl(pll->reg + PLL_16FFT_CAL_STAT);
+ if (stat & PLL_16FFT_CAL_STAT_CAL_LOCK) {
+ success = 1;
+ break;
+ }
+ }
+ }
+
+ if (success == 0) {
+ pr_err("%s: pll (%s) failed to lock\n", __func__,
+ pll->hw.clk.name);
+ return -EBUSY;
+ } else {
+ return 0;
+ }
+}
+
+static unsigned long ti_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+ struct ti_pll_clk *pll = to_pll(hw);
+ u64 current_freq;
+ u64 parent_freq = parent_rate;
+ u32 pllm;
+ u32 plld;
+ u32 pllfm;
+ u32 ctrl;
+
+ /* Check if we are in bypass */
+ ctrl = readl(pll->reg + PLL_16FFT_CTRL);
+ if (ctrl & PLL_16FFT_CTRL_BYPASS_EN)
+ return parent_freq;
+
+ pllm = readl(pll->reg + PLL_16FFT_FREQ_CTRL0);
+ pllfm = readl(pll->reg + PLL_16FFT_FREQ_CTRL1);
+
+ plld = readl(pll->reg + PLL_16FFT_DIV_CTRL) &
+ PLL_16FFT_DIV_CTRL_REF_DIV_MASK;
+
+ current_freq = parent_freq * pllm;
+
+ do_div(current_freq, plld);
+
+ if (pllfm) {
+ u64 tmp;
+
+ tmp = parent_freq * pllfm;
+ do_div(tmp, plld);
+ tmp >>= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS;
+ current_freq += tmp;
+ }
+
+ return current_freq;
+}
+
+static int ti_pll_clk_set_rate(struct ti_pll_clk *pll, unsigned long rate,
+ unsigned long parent_rate)
+{
+ u64 parent_freq = parent_rate;
+ int ret;
+ u32 ctrl;
+ unsigned long pllm;
+ u32 pllfm = 0;
+ unsigned long plld;
+ u32 div_ctrl;
+ u32 rem;
+ int shift;
+
+ if (rate != parent_freq)
+ /*
+ * Attempt with higher max multiplier value first to give
+ * some space for fractional divider to kick in.
+ */
+ for (shift = 8; shift >= 0; shift -= 8) {
+ rational_best_approximation(rate, parent_freq,
+ ((PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK + 1) << shift) - 1,
+ PLL_16FFT_DIV_CTRL_REF_DIV_MASK, &pllm, &plld);
+ if (pllm / plld <= PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK)
+ break;
+ }
+
+ /* Put PLL to bypass mode */
+ ctrl = readl(pll->reg + PLL_16FFT_CTRL);
+ ctrl |= PLL_16FFT_CTRL_BYPASS_EN;
+ writel(ctrl, pll->reg + PLL_16FFT_CTRL);
+
+ if (rate == parent_freq)
+ return 0;
+
+ pr_debug("%s: pre-frac-calc: rate=%u, parent_freq=%u, plld=%u, pllm=%u\n",
+ __func__, (u32)rate, (u32)parent_freq, (u32)plld, (u32)pllm);
+
+ /* Check if we need fractional config */
+ if (plld > 1) {
+ pllfm = pllm % plld;
+ pllfm <<= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS;
+ rem = pllfm % plld;
+ pllfm /= plld;
+ if (rem)
+ pllfm++;
+ pllm /= plld;
+ plld = 1;
+ }
+
+ if (pllfm)
+ ctrl |= PLL_16FFT_CTRL_DSM_EN;
+ else
+ ctrl &= ~PLL_16FFT_CTRL_DSM_EN;
+
+ writel(pllm, pll->reg + PLL_16FFT_FREQ_CTRL0);
+ writel(pllfm, pll->reg + PLL_16FFT_FREQ_CTRL1);
+
+ /*
+ * div_ctrl register contains other divider values, so rmw
+ * only plld and leave existing values alone
+ */
+ div_ctrl = readl(pll->reg + PLL_16FFT_DIV_CTRL);
+ div_ctrl &= ~PLL_16FFT_DIV_CTRL_REF_DIV_MASK;
+ div_ctrl |= plld;
+ writel(div_ctrl, pll->reg + PLL_16FFT_DIV_CTRL);
+
+ ctrl &= ~PLL_16FFT_CTRL_BYPASS_EN;
+ ctrl |= PLL_16FFT_CTRL_PLL_EN;
+ writel(ctrl, pll->reg + PLL_16FFT_CTRL);
+
+ ret = ti_pll_wait_for_lock(pll);
+ if (ret)
+ return ret;
+
+ pr_debug("%s: pllm=%u, plld=%u, pllfm=%u, parent_freq=%u\n",
+ __func__, (u32)pllm, (u32)plld, (u32)pllfm, (u32)parent_freq);
+
+ return 0;
+}
+
+static int __ti_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct ti_pll_clk *pll = to_pll(hw);
+
+ return ti_pll_clk_set_rate(pll, rate, parent_rate);
+}
+
+static long ti_pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ return rate; /* FIXME */
+}
+
+static int ti_pll_clk_enable(struct clk_hw *hw)
+{
+ struct ti_pll_clk *pll = to_pll(hw);
+ u32 ctrl;
+
+ ctrl = readl(pll->reg + PLL_16FFT_CTRL);
+ ctrl &= ~PLL_16FFT_CTRL_BYPASS_EN;
+ ctrl |= PLL_16FFT_CTRL_PLL_EN;
+ writel(ctrl, pll->reg + PLL_16FFT_CTRL);
+
+ return ti_pll_wait_for_lock(pll);
+}
+
+static void ti_pll_clk_disable(struct clk_hw *hw)
+{
+ struct ti_pll_clk *pll = to_pll(hw);
+ u32 ctrl;
+
+ ctrl = readl(pll->reg + PLL_16FFT_CTRL);
+ ctrl |= PLL_16FFT_CTRL_BYPASS_EN;
+ writel(ctrl, pll->reg + PLL_16FFT_CTRL);
+}
+
+static const struct clk_ops ti_pll_clk_ops = {
+ .recalc_rate = ti_pll_clk_recalc_rate,
+ .round_rate = ti_pll_clk_round_rate,
+ .set_rate = __ti_pll_clk_set_rate,
+ .enable = ti_pll_clk_enable,
+ .disable = ti_pll_clk_disable,
+};
+
+void ti_k3_pll_init(void __iomem *reg)
+{
+ u32 cfg, ctrl, hsdiv_presence_bit, hsdiv_ctrl_offs;
+ int i;
+
+ /* Unlock the PLL registers */
+ writel(PLL_KICK0_VALUE, reg + PLL_KICK0);
+ writel(PLL_KICK1_VALUE, reg + PLL_KICK1);
+
+ /* Enable all HSDIV outputs */
+ cfg = readl(reg + PLL_16FFT_CFG);
+ for (i = 0; i < 16; i++) {
+ hsdiv_presence_bit = BIT(16 + i);
+ hsdiv_ctrl_offs = 0x80 + (i * 4);
+ /* Enable HSDIV output if present */
+ if ((hsdiv_presence_bit & cfg) != 0UL) {
+ ctrl = readl(reg + hsdiv_ctrl_offs);
+ ctrl |= PLL_16FFT_HSDIV_CTRL_CLKOUT_EN;
+ writel(ctrl, reg + hsdiv_ctrl_offs);
+ }
+ }
+}
+
+int ti_k3_pll_set_rate(void __iomem *reg, unsigned long rate, unsigned long parent_rate)
+{
+ struct ti_pll_clk pll = {
+ .reg = reg,
+ .hw.clk.name = "PBL",
+ };
+
+ return ti_pll_clk_set_rate(&pll, rate, parent_rate);
+}
+
+struct clk *clk_register_ti_k3_pll(const char *name, const char *parent_name,
+ void __iomem *reg)
+{
+ struct ti_pll_clk *pll;
+ int ret;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ pll->reg = reg;
+
+ pll->parent = parent_name;
+ pll->hw.clk.ops = &ti_pll_clk_ops;
+ pll->hw.clk.name = name;
+ pll->hw.clk.parent_names = &pll->parent;
+ pll->hw.clk.num_parents = 1;
+
+ ti_k3_pll_init(pll->reg);
+
+ ret = bclk_register(&pll->hw.clk);
+ if (ret) {
+ kfree(pll);
+ return ERR_PTR(ret);
+ }
+
+ return &pll->hw.clk;
+}
diff --git a/drivers/clk/k3/ti-k3-clk.h b/drivers/clk/k3/ti-k3-clk.h
new file mode 100644
index 0000000000..88980412bf
--- /dev/null
+++ b/drivers/clk/k3/ti-k3-clk.h
@@ -0,0 +1,8 @@
+#ifndef __TI_K3_CLK_H
+#define __TI_K3_CLK_H
+
+struct clk *clk_register_ti_k3_pll(const char *name, const char *parent_name,
+ void __iomem *reg);
+
+#endif
+
diff --git a/include/soc/k3/clk.h b/include/soc/k3/clk.h
new file mode 100644
index 0000000000..a9921f5a9c
--- /dev/null
+++ b/include/soc/k3/clk.h
@@ -0,0 +1,7 @@
+#ifndef __SOC_K3_CLK_H
+#define __SOC_K3_CLK_H
+
+void ti_k3_pll_init(void __iomem *reg);
+int ti_k3_pll_set_rate(void __iomem *reg, unsigned long rate, unsigned long parent_rate);
+
+#endif /* __SOC_K3_CLK_H */
--
2.39.5
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v3 09/23] pmdomain: add K3 driver
2025-01-13 11:26 [PATCH v3 00/23] ARM: K3: Add R5 boot support Sascha Hauer
` (6 preceding siblings ...)
2025-01-13 11:26 ` [PATCH v3 08/23] clk: add K3 clk driver Sascha Hauer
@ 2025-01-13 11:26 ` Sascha Hauer
2025-01-13 11:26 ` [PATCH v3 10/23] rproc: add K3 arm64 rproc driver Sascha Hauer
` (14 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Sascha Hauer @ 2025-01-13 11:26 UTC (permalink / raw)
To: open list:BAREBOX
The power domain support for K3 SoCs is implemented on the Cortex-R5
boot processor by the ti-dm firmware binary. The A53 cores access the
power domains via mailboxes. However, during early boot we are running
barebox on the Cortex-R5 processor and the ti-dm firmware is not yet
running, so we must implement our own driver for the power domains.
Code is based on U-Boot-2025.01-rc1.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/pmdomain/ti/Kconfig | 4 +
drivers/pmdomain/ti/Makefile | 1 +
drivers/pmdomain/ti/ti-k3.c | 479 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 484 insertions(+)
diff --git a/drivers/pmdomain/ti/Kconfig b/drivers/pmdomain/ti/Kconfig
index f34a5146c1..fc65e34118 100644
--- a/drivers/pmdomain/ti/Kconfig
+++ b/drivers/pmdomain/ti/Kconfig
@@ -6,3 +6,7 @@ config TI_SCI_PM_DOMAINS
help
Generic power domain implementation for TI device implementing
the TI SCI protocol.
+
+config TI_K3_PM_DOMAINS
+ bool "TI K3 PM Domains Driver"
+ depends on MACH_K3_CORTEX_R5 || COMPILE_TEST
diff --git a/drivers/pmdomain/ti/Makefile b/drivers/pmdomain/ti/Makefile
index ab582e04a8..e5d56da052 100644
--- a/drivers/pmdomain/ti/Makefile
+++ b/drivers/pmdomain/ti/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_TI_SCI_PM_DOMAINS) += ti_sci_pm_domains.o
+obj-$(CONFIG_TI_K3_PM_DOMAINS) += ti-k3.o
diff --git a/drivers/pmdomain/ti/ti-k3.c b/drivers/pmdomain/ti/ti-k3.c
new file mode 100644
index 0000000000..33bffeaca0
--- /dev/null
+++ b/drivers/pmdomain/ti/ti-k3.c
@@ -0,0 +1,479 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments power domain driver
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Tero Kristo <t-kristo@ti.com>
+ */
+
+#define pr_fmt(fmt) "ti-k3-pm-domain: " fmt
+
+#include <io.h>
+#include <of_device.h>
+#include <malloc.h>
+#include <init.h>
+#include <pm_domain.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+
+#define PSC_PTCMD 0x120
+#define PSC_PTCMD_H 0x124
+#define PSC_PTSTAT 0x128
+#define PSC_PTSTAT_H 0x12C
+#define PSC_PDSTAT 0x200
+#define PSC_PDCTL 0x300
+#define PSC_MDSTAT 0x800
+#define PSC_MDCTL 0xa00
+
+#define PDCTL_STATE_MASK 0x1
+#define PDCTL_STATE_OFF 0x0
+#define PDCTL_STATE_ON 0x1
+
+#define MDSTAT_STATE_MASK 0x3f
+#define MDSTAT_BUSY_MASK 0x30
+#define MDSTAT_STATE_SWRSTDISABLE 0x0
+#define MDSTAT_STATE_ENABLE 0x3
+
+#define LPSC_TIMEOUT 1000
+#define PD_TIMEOUT 1000
+
+#define LPSC_MODULE_EXISTS BIT(0)
+#define LPSC_NO_CLOCK_GATING BIT(1)
+#define LPSC_DEPENDS BIT(2)
+#define LPSC_HAS_RESET_ISO BIT(3)
+#define LPSC_HAS_LOCAL_RESET BIT(4)
+#define LPSC_NO_MODULE_RESET BIT(5)
+
+#define PSC_PD_EXISTS BIT(0)
+#define PSC_PD_ALWAYSON BIT(1)
+#define PSC_PD_DEPENDS BIT(2)
+
+#define MDSTAT_STATE_MASK 0x3f
+#define MDSTAT_BUSY_MASK 0x30
+#define MDSTAT_STATE_SWRSTDISABLE 0x0
+#define MDSTAT_STATE_ENABLE 0x3
+
+struct ti_psc {
+ int id;
+ void __iomem *base;
+};
+
+struct ti_pd;
+
+struct ti_pd {
+ int id;
+ int usecount;
+ struct ti_psc *psc;
+ struct ti_pd *depend;
+};
+
+struct ti_lpsc;
+
+struct ti_lpsc {
+ int id;
+ int usecount;
+ struct ti_psc *psc;
+ struct ti_pd *pd;
+ struct ti_lpsc *depend;
+};
+
+struct ti_dev {
+ int lpsc;
+ int id;
+};
+
+/**
+ * struct ti_k3_pd_platdata - pm domain controller information structure
+ */
+struct ti_k3_pd_platdata {
+ struct ti_psc *psc;
+ struct ti_pd *pd;
+ struct ti_lpsc *lpsc;
+ struct ti_dev *devs;
+ int num_psc;
+ int num_pd;
+ int num_lpsc;
+ int num_devs;
+};
+
+struct ti_k3_pm_domain {
+ struct generic_pm_domain genpd;
+ struct ti_lpsc *lpsc;
+};
+
+struct ti_k3_priv {
+ const struct ti_k3_pd_platdata *data;
+ struct genpd_onecell_data pd_data;
+ struct ti_k3_pm_domain *pd;
+};
+
+static u32 psc_read(struct ti_psc *psc, u32 reg)
+{
+ return readl(psc->base + reg);
+}
+
+static void psc_write(u32 val, struct ti_psc *psc, u32 reg)
+{
+ writel(val, psc->base + reg);
+}
+
+static u32 pd_read(struct ti_pd *pd, u32 reg)
+{
+ return psc_read(pd->psc, reg + 4 * pd->id);
+}
+
+static void pd_write(u32 val, struct ti_pd *pd, u32 reg)
+{
+ psc_write(val, pd->psc, reg + 4 * pd->id);
+}
+
+static u32 lpsc_read(struct ti_lpsc *lpsc, u32 reg)
+{
+ return psc_read(lpsc->psc, reg + 4 * lpsc->id);
+}
+
+static void lpsc_write(u32 val, struct ti_lpsc *lpsc, u32 reg)
+{
+ psc_write(val, lpsc->psc, reg + 4 * lpsc->id);
+}
+
+static int ti_pd_wait(struct ti_pd *pd)
+{
+ u32 ptstat;
+ u32 pdoffset = 0;
+ u32 ptstatreg = PSC_PTSTAT;
+ int ret;
+
+ if (pd->id > 31) {
+ pdoffset = 32;
+ ptstatreg = PSC_PTSTAT_H;
+ }
+
+ ret = readl_poll_timeout(pd->psc->base + ptstatreg, ptstat,
+ !(ptstat & BIT(pd->id - pdoffset)), PD_TIMEOUT);
+
+ if (ret)
+ pr_err("%s: psc%d, pd%d failed to transition.\n", __func__,
+ pd->psc->id, pd->id);
+
+ return ret;
+}
+
+static void ti_pd_transition(struct ti_pd *pd)
+{
+ u32 pdoffset = 0;
+ u32 ptcmdreg = PSC_PTCMD;
+
+ if (pd->id > 31) {
+ pdoffset = 32;
+ ptcmdreg = PSC_PTCMD_H;
+ }
+
+ psc_write(BIT(pd->id - pdoffset), pd->psc, ptcmdreg);
+}
+
+static int ti_pd_get(struct ti_pd *pd)
+{
+ u32 pdctl;
+ int ret;
+
+ pd->usecount++;
+
+ if (pd->usecount > 1)
+ return 0;
+
+ if (pd->depend) {
+ ret = ti_pd_get(pd->depend);
+ if (ret)
+ return ret;
+ ti_pd_transition(pd->depend);
+ ret = ti_pd_wait(pd->depend);
+ if (ret)
+ return ret;
+ }
+
+ pdctl = pd_read(pd, PSC_PDCTL);
+
+ if ((pdctl & PDCTL_STATE_MASK) == PDCTL_STATE_ON)
+ return 0;
+
+ pr_debug("%s: enabling psc:%d, pd:%d\n", __func__, pd->psc->id, pd->id);
+
+ pdctl &= ~PDCTL_STATE_MASK;
+ pdctl |= PDCTL_STATE_ON;
+
+ pd_write(pdctl, pd, PSC_PDCTL);
+
+ return 0;
+}
+
+static int ti_pd_put(struct ti_pd *pd)
+{
+ u32 pdctl;
+ int ret;
+
+ pd->usecount--;
+
+ if (pd->usecount > 0)
+ return 0;
+
+ pdctl = pd_read(pd, PSC_PDCTL);
+ if ((pdctl & PDCTL_STATE_MASK) == PDCTL_STATE_OFF)
+ return 0;
+
+ pdctl &= ~PDCTL_STATE_MASK;
+ pdctl |= PDCTL_STATE_OFF;
+
+ pr_debug("%s: disabling psc:%d, pd:%d\n", __func__, pd->psc->id, pd->id);
+
+ pd_write(pdctl, pd, PSC_PDCTL);
+
+ if (pd->depend) {
+ ti_pd_transition(pd);
+ ret = ti_pd_wait(pd);
+ if (ret)
+ return ret;
+
+ ret = ti_pd_put(pd->depend);
+ if (ret)
+ return ret;
+ ti_pd_transition(pd->depend);
+ ret = ti_pd_wait(pd->depend);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ti_lpsc_wait(struct ti_lpsc *lpsc)
+{
+ u32 mdstat;
+ int ret;
+
+ ret = readl_poll_timeout(lpsc->psc->base + PSC_MDSTAT + lpsc->id * 4,
+ mdstat,
+ !(mdstat & MDSTAT_BUSY_MASK), LPSC_TIMEOUT);
+
+ if (ret)
+ pr_err("%s: module %d failed to transition.\n", __func__,
+ lpsc->id);
+
+ return ret;
+}
+
+static int ti_lpsc_transition(struct ti_lpsc *lpsc, u8 state)
+{
+ struct ti_pd *psc_pd;
+ int ret;
+ u32 mdctl;
+
+ psc_pd = lpsc->pd;
+
+ if (state == MDSTAT_STATE_ENABLE) {
+ lpsc->usecount++;
+ if (lpsc->usecount > 1)
+ return 0;
+ } else {
+ lpsc->usecount--;
+ if (lpsc->usecount >= 1)
+ return 0;
+ }
+
+ pr_debug("%s: transitioning psc:%d, lpsc:%d to %x\n", __func__,
+ lpsc->psc->id, lpsc->id, state);
+
+ if (lpsc->depend)
+ ti_lpsc_transition(lpsc->depend, state);
+
+ mdctl = lpsc_read(lpsc, PSC_MDCTL);
+ if ((mdctl & MDSTAT_STATE_MASK) == state)
+ return 0;
+
+ if (state == MDSTAT_STATE_ENABLE)
+ ti_pd_get(psc_pd);
+ else
+ ti_pd_put(psc_pd);
+
+ mdctl &= ~MDSTAT_STATE_MASK;
+ mdctl |= state;
+
+ lpsc_write(mdctl, lpsc, PSC_MDCTL);
+
+ ti_pd_transition(psc_pd);
+
+ ret = ti_pd_wait(psc_pd);
+ if (ret)
+ return ret;
+
+ return ti_lpsc_wait(lpsc);
+}
+
+static inline struct ti_k3_pm_domain *to_ti_k3_pd(struct generic_pm_domain *gpd)
+{
+ return container_of(gpd, struct ti_k3_pm_domain, genpd);
+}
+
+static int ti_k3_pm_domain_on(struct generic_pm_domain *domain)
+{
+ struct ti_k3_pm_domain *pd = to_ti_k3_pd(domain);
+
+ return ti_lpsc_transition(pd->lpsc, MDSTAT_STATE_ENABLE);
+}
+
+static int ti_k3_pm_domain_off(struct generic_pm_domain *domain)
+{
+ struct ti_k3_pm_domain *pd = to_ti_k3_pd(domain);
+
+ return ti_lpsc_transition(pd->lpsc, MDSTAT_STATE_SWRSTDISABLE);
+}
+
+static struct ti_psc am625_psc[] = {
+ [0] = { .id = 0, .base = (void *)0x04000000 },
+ [1] = { .id = 1, .base = (void *)0x00400000 },
+};
+
+static struct ti_pd am625_pd[] = {
+ [0] = { .id = 0, .psc = &am625_psc[1], },
+ [1] = { .id = 2, .psc = &am625_psc[1], .depend = &am625_pd[0] },
+ [2] = { .id = 3, .psc = &am625_psc[1], .depend = &am625_pd[0] },
+ [3] = { .id = 4, .psc = &am625_psc[1], .depend = &am625_pd[2] },
+ [4] = { .id = 5, .psc = &am625_psc[1], .depend = &am625_pd[2] },
+};
+
+static struct ti_lpsc am625_lpsc[] = {
+ [0] = { .id = 0, .psc = &am625_psc[1], .pd = &am625_pd[0], },
+ [1] = { .id = 9, .psc = &am625_psc[1], .pd = &am625_pd[0], .depend = &am625_lpsc[11] },
+ [2] = { .id = 10, .psc = &am625_psc[1], .pd = &am625_pd[0], .depend = &am625_lpsc[1] },
+ [3] = { .id = 11, .psc = &am625_psc[1], .pd = &am625_pd[0], .depend = &am625_lpsc[2] },
+ [4] = { .id = 12, .psc = &am625_psc[1], .pd = &am625_pd[0], .depend = &am625_lpsc[8] },
+ [5] = { .id = 13, .psc = &am625_psc[1], .pd = &am625_pd[0], .depend = &am625_lpsc[9] },
+ [6] = { .id = 20, .psc = &am625_psc[1], .pd = &am625_pd[0], .depend = &am625_lpsc[11] },
+ [7] = { .id = 21, .psc = &am625_psc[1], .pd = &am625_pd[0], .depend = &am625_lpsc[11] },
+ [8] = { .id = 23, .psc = &am625_psc[1], .pd = &am625_pd[0], .depend = &am625_lpsc[11] },
+ [9] = { .id = 24, .psc = &am625_psc[1], .pd = &am625_pd[0], .depend = &am625_lpsc[11] },
+ [10] = { .id = 28, .psc = &am625_psc[1], .pd = &am625_pd[0], .depend = &am625_lpsc[11] },
+ [11] = { .id = 34, .psc = &am625_psc[1], .pd = &am625_pd[0], },
+ [12] = { .id = 41, .psc = &am625_psc[1], .pd = &am625_pd[1], .depend = &am625_lpsc[11] },
+ [13] = { .id = 42, .psc = &am625_psc[1], .pd = &am625_pd[2], .depend = &am625_lpsc[11] },
+ [14] = { .id = 45, .psc = &am625_psc[1], .pd = &am625_pd[3], .depend = &am625_lpsc[13] },
+ [15] = { .id = 46, .psc = &am625_psc[1], .pd = &am625_pd[4], .depend = &am625_lpsc[13] },
+};
+
+static struct ti_dev am625_dev[] = {
+ { .id = 16, .lpsc = 0 },
+ { .id = 77, .lpsc = 0 },
+ { .id = 61, .lpsc = 0 },
+ { .id = 95, .lpsc = 0 },
+ { .id = 107, .lpsc = 0 },
+ { .id = 170, .lpsc = 1 },
+ { .id = 177, .lpsc = 2 },
+ { .id = 55, .lpsc = 3 },
+ { .id = 178, .lpsc = 4 },
+ { .id = 179, .lpsc = 5 },
+ { .id = 57, .lpsc = 6 },
+ { .id = 58, .lpsc = 7 },
+ { .id = 161, .lpsc = 8 },
+ { .id = 162, .lpsc = 9 },
+ { .id = 75, .lpsc = 10 },
+ { .id = 36, .lpsc = 11 },
+ { .id = 102, .lpsc = 11 },
+ { .id = 146, .lpsc = 11 },
+ { .id = 13, .lpsc = 12 },
+ { .id = 166, .lpsc = 13 },
+ { .id = 135, .lpsc = 14 },
+ { .id = 136, .lpsc = 15 },
+};
+
+const struct ti_k3_pd_platdata am62x_pd_platdata = {
+ .psc = am625_psc,
+ .pd = am625_pd,
+ .lpsc = am625_lpsc,
+ .devs = am625_dev,
+ .num_psc = ARRAY_SIZE(am625_psc),
+ .num_pd = ARRAY_SIZE(am625_pd),
+ .num_lpsc = ARRAY_SIZE(am625_lpsc),
+ .num_devs = ARRAY_SIZE(am625_dev),
+};
+
+static struct generic_pm_domain *ti_k3_pd_xlate(struct of_phandle_args *args,
+ void *data)
+{
+ struct genpd_onecell_data *genpd_data = data;
+ struct ti_k3_priv *priv = container_of(genpd_data, struct ti_k3_priv, pd_data);
+ unsigned int idx = args->args[0];
+ int i;
+
+ for (i = 0; i < priv->data->num_devs; i++)
+ if (priv->data->devs[i].id == idx) {
+ unsigned int lpsc = priv->data->devs[i].lpsc;
+ pr_debug("Translate: %d -> %d\n", idx, lpsc);
+ return &priv->pd[lpsc].genpd;
+ }
+
+ return 0;
+}
+
+static int ti_k3_pm_domain_probe(struct device *dev)
+{
+ struct ti_k3_priv *priv;
+ const struct ti_k3_pd_platdata *data;
+ struct ti_k3_pm_domain *pd;
+ struct generic_pm_domain **domains;
+ struct genpd_onecell_data *pd_data;
+ int num_domains;
+ int i;
+
+ priv = xzalloc(sizeof(*priv));
+
+ if (of_machine_is_compatible("ti,am625"))
+ data = &am62x_pd_platdata;
+ else
+ return dev_err_probe(dev, -EINVAL, "Unknown SoC\n");
+
+ priv->data = data;
+
+ num_domains = data->num_lpsc;
+
+ pd = devm_kcalloc(dev, num_domains, sizeof(*pd), GFP_KERNEL);
+ if (!pd)
+ return -ENOMEM;
+
+ domains = devm_kcalloc(dev, num_domains, sizeof(*domains), GFP_KERNEL);
+ if (!domains)
+ return -ENOMEM;
+
+ priv->pd = pd;
+
+ for (i = 0; i < num_domains; i++, pd++) {
+ pd->genpd.name = basprintf("pd:%d", i);
+ pd->lpsc = &data->lpsc[i];
+ pd->genpd.power_off = ti_k3_pm_domain_off;
+ pd->genpd.power_on = ti_k3_pm_domain_on;
+
+ pm_genpd_init(&pd->genpd, NULL, true);
+
+ domains[i] = &pd->genpd;
+ }
+
+ pd_data = &priv->pd_data;
+
+ pd_data->domains = domains;
+ pd_data->num_domains = num_domains;
+ pd_data->xlate = ti_k3_pd_xlate;
+
+ return of_genpd_add_provider_onecell(dev->of_node, pd_data);
+}
+
+static const struct of_device_id ti_k3_power_domain_of_match[] = {
+ { .compatible = "ti,sci-pm-domain" },
+ { /* sentinel */ }
+};
+
+static struct driver ti_k3_pm_domains_driver = {
+ .probe = ti_k3_pm_domain_probe,
+ .name = "ti_k3_pm_domains",
+ .of_match_table = ti_k3_power_domain_of_match,
+};
+core_platform_driver(ti_k3_pm_domains_driver);
--
2.39.5
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v3 10/23] rproc: add K3 arm64 rproc driver
2025-01-13 11:26 [PATCH v3 00/23] ARM: K3: Add R5 boot support Sascha Hauer
` (7 preceding siblings ...)
2025-01-13 11:26 ` [PATCH v3 09/23] pmdomain: add K3 driver Sascha Hauer
@ 2025-01-13 11:26 ` Sascha Hauer
2025-01-13 11:26 ` [PATCH v3 11/23] ARM: k3: add k3_debug_ll_init() Sascha Hauer
` (13 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Sascha Hauer @ 2025-01-13 11:26 UTC (permalink / raw)
To: open list:BAREBOX
This adds support for starting the A53 cores from the Cortex-R5 core.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/remoteproc/ti_k3_arm64_rproc.c | 226 +++++++++++++++++++++++++++++++++
drivers/remoteproc/ti_sci_proc.h | 149 ++++++++++++++++++++++
2 files changed, 375 insertions(+)
diff --git a/drivers/remoteproc/ti_k3_arm64_rproc.c b/drivers/remoteproc/ti_k3_arm64_rproc.c
new file mode 100644
index 0000000000..47fe570408
--- /dev/null
+++ b/drivers/remoteproc/ti_k3_arm64_rproc.c
@@ -0,0 +1,226 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments' K3 ARM64 Remoteproc driver
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ *
+ */
+
+#include <driver.h>
+#include <linux/remoteproc.h>
+#include <linux/printk.h>
+#include <errno.h>
+#include <linux/clk.h>
+#include <io.h>
+#include <of.h>
+#include <soc/ti/ti_sci_protocol.h>
+#include <pm_domain.h>
+#include <mach/k3/r5.h>
+
+#include "ti_sci_proc.h"
+
+#define INVALID_ID 0xffff
+
+#define GTC_CNTCR_REG 0x0
+#define GTC_CNTFID0_REG 0x20
+#define GTC_CNTR_EN 0x3
+
+/**
+ * struct k3_arm64_privdata - Structure representing Remote processor data.
+ * @rproc_pwrdmn: rproc power domain data
+ * @rproc_rst: rproc reset control data
+ * @sci: Pointer to TISCI handle
+ * @tsp: TISCI processor control helper structure
+ * @gtc_clk: GTC clock description
+ * @gtc_base: Timer base address.
+ */
+struct k3_arm64_privdata {
+ struct device *dev;
+ struct reset_control *rproc_rst;
+ struct ti_sci_proc tsp;
+ struct clk *gtc_clk;
+ void *gtc_base;
+ struct rproc *rproc;
+ struct device *cluster_pwrdmn;
+ struct device *rproc_pwrdmn;
+ struct device *gtc_pwrdmn;
+};
+
+/**
+ * k3_arm64_load() - Load up the Remote processor image
+ * @dev: rproc device pointer
+ * @addr: Address at which image is available
+ * @size: size of the image
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+static int k3_arm64_load(struct rproc *rproc, const struct firmware *fw)
+{
+ struct k3_arm64_privdata *priv = rproc->priv;
+ ulong gtc_rate;
+ int ret;
+
+ dev_dbg(priv->dev, "%s\n", __func__);
+
+ /* request for the processor */
+ ret = ti_sci_proc_request(&priv->tsp);
+ if (ret)
+ return ret;
+
+ ret = pm_runtime_resume_and_get_genpd(priv->gtc_pwrdmn);
+ if (ret)
+ return ret;
+
+ gtc_rate = clk_get_rate(priv->gtc_clk);
+ dev_dbg(priv->dev, "GTC RATE= %lu\n", gtc_rate);
+
+ /* Store the clock frequency down for GTC users to pick up */
+ writel((u32)gtc_rate, priv->gtc_base + GTC_CNTFID0_REG);
+
+ /* Enable the timer before starting remote core */
+ writel(GTC_CNTR_EN, priv->gtc_base + GTC_CNTCR_REG);
+
+ /*
+ * Setting the right clock frequency would have taken care by
+ * assigned-clock-rates during the device probe. So no need to
+ * set the frequency again here.
+ */
+ if (priv->cluster_pwrdmn) {
+ ret = pm_runtime_resume_and_get_genpd(priv->cluster_pwrdmn);
+ if (ret)
+ return ret;
+ }
+
+ return ti_sci_proc_set_config(&priv->tsp, (unsigned long)fw->data, 0, 0);
+}
+
+/**
+ * k3_arm64_start() - Start the remote processor
+ * @dev: rproc device pointer
+ *
+ * Return: 0 if all went ok, else return appropriate error
+ */
+static int k3_arm64_start(struct rproc *rproc)
+{
+ struct k3_arm64_privdata *priv = rproc->priv;
+ int ret;
+
+ dev_dbg(priv->dev, "%s\n", __func__);
+ ret = pm_runtime_resume_and_get_genpd(priv->rproc_pwrdmn);
+ if (ret)
+ return ret;
+
+ return ti_sci_proc_release(&priv->tsp);
+}
+
+static const struct rproc_ops k3_arm64_ops = {
+ .load = k3_arm64_load,
+ .start = k3_arm64_start,
+};
+
+static int ti_sci_proc_of_to_priv(struct k3_arm64_privdata *priv, struct ti_sci_proc *tsp)
+{
+ u32 val;
+ int ret;
+
+ tsp->sci = ti_sci_get_by_phandle(priv->dev, "ti,sci");
+ if (IS_ERR(tsp->sci)) {
+ dev_err(priv->dev, "ti_sci get failed: %ld\n", PTR_ERR(tsp->sci));
+ return PTR_ERR(tsp->sci);
+ }
+
+ ret = of_property_read_u32(priv->dev->of_node, "ti,sci-proc-id", &val);
+ if (ret) {
+ dev_err(priv->dev, "proc id not populated\n");
+ return -ENOENT;
+ }
+ tsp->proc_id = val;
+
+ ret = of_property_read_u32(priv->dev->of_node, "ti,sci-host-id", &val);
+ if (ret)
+ val = INVALID_ID;
+
+ tsp->host_id = val;
+
+ tsp->ops = &tsp->sci->ops.proc_ops;
+
+ return 0;
+}
+
+static struct rproc *ti_k3_am64_rproc;
+
+struct rproc *ti_k3_am64_get_handle(void)
+{
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, "ti,am654-rproc");
+ if (!np)
+ return ERR_PTR(-ENODEV);
+ of_device_ensure_probed(np);
+
+ return ti_k3_am64_rproc;
+}
+
+
+static int ti_k3_rproc_probe(struct device *dev)
+{
+ struct k3_arm64_privdata *priv;
+ struct rproc *rproc;
+ int ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+
+ rproc = rproc_alloc(dev, dev_name(dev), &k3_arm64_ops, sizeof(*priv));
+ if (!rproc)
+ return -ENOMEM;
+
+ priv = rproc->priv;
+ priv->dev = dev;
+
+ priv->cluster_pwrdmn = dev_pm_domain_attach_by_id(dev, 2);
+ if (IS_ERR(priv->cluster_pwrdmn))
+ priv->cluster_pwrdmn = NULL;
+
+ priv->rproc_pwrdmn = dev_pm_domain_attach_by_id(dev, 1);
+ if (IS_ERR(priv->rproc_pwrdmn))
+ return dev_err_probe(dev, PTR_ERR(priv->rproc_pwrdmn), "no rproc pm domain\n");
+
+ priv->gtc_pwrdmn = dev_pm_domain_attach_by_id(dev, 0);
+ if (IS_ERR(priv->gtc_pwrdmn))
+ return dev_err_probe(dev, PTR_ERR(priv->gtc_pwrdmn), "no gtc pm domain\n");
+
+ priv->gtc_clk = clk_get(dev, 0);
+ if (IS_ERR(priv->gtc_clk))
+ return dev_err_probe(dev, PTR_ERR(priv->gtc_clk), "No clock\n");
+
+ ret = ti_sci_proc_of_to_priv(priv, &priv->tsp);
+ if (ret)
+ return ret;
+
+ priv->gtc_base = dev_request_mem_region(dev, 0);
+ if (IS_ERR(priv->gtc_base))
+ return dev_err_probe(dev, PTR_ERR(priv->gtc_base), "No iomem\n");
+
+ ret = rproc_add(rproc);
+ if (ret)
+ return dev_err_probe(dev, ret, "rproc_add failed\n");
+
+ ti_k3_am64_rproc = rproc;
+
+ dev_dbg(dev, "Remoteproc successfully probed\n");
+
+ return 0;
+}
+
+static const struct of_device_id k3_arm64_ids[] = {
+ { .compatible = "ti,am654-rproc"},
+ {}
+};
+
+static struct driver ti_k3_arm64_rproc_driver = {
+ .name = "ti-k3-rproc",
+ .probe = ti_k3_rproc_probe,
+ .of_compatible = DRV_OF_COMPAT(k3_arm64_ids),
+};
+device_platform_driver(ti_k3_arm64_rproc_driver);
diff --git a/drivers/remoteproc/ti_sci_proc.h b/drivers/remoteproc/ti_sci_proc.h
new file mode 100644
index 0000000000..980f5188dd
--- /dev/null
+++ b/drivers/remoteproc/ti_sci_proc.h
@@ -0,0 +1,149 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Texas Instruments TI-SCI Processor Controller Helper Functions
+ *
+ * Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ * Suman Anna <s-anna@ti.com>
+ */
+
+#ifndef REMOTEPROC_TI_SCI_PROC_H
+#define REMOTEPROC_TI_SCI_PROC_H
+
+#include <linux/printk.h>
+#define TISCI_INVALID_HOST 0xff
+
+/**
+ * struct ti_sci_proc - structure representing a processor control client
+ * @sci: cached TI-SCI protocol handle
+ * @ops: cached TI-SCI proc ops
+ * @proc_id: processor id for the consumer remoteproc device
+ * @host_id: host id to pass the control over for this consumer remoteproc
+ * device
+ * @dev_id: Device ID as identified by system controller.
+ */
+struct ti_sci_proc {
+ const struct ti_sci_handle *sci;
+ const struct ti_sci_proc_ops *ops;
+ u8 proc_id;
+ u8 host_id;
+ u16 dev_id;
+};
+
+static inline int ti_sci_proc_request(struct ti_sci_proc *tsp)
+{
+ int ret;
+
+ pr_debug("%s: proc_id = %d\n", __func__, tsp->proc_id);
+
+ ret = tsp->ops->proc_request(tsp->sci, tsp->proc_id);
+ if (ret)
+ pr_err("ti-sci processor request failed: %d\n", ret);
+ return ret;
+}
+
+static inline int ti_sci_proc_release(struct ti_sci_proc *tsp)
+{
+ int ret;
+
+ pr_debug("%s: proc_id = %d\n", __func__, tsp->proc_id);
+
+ if (tsp->host_id != TISCI_INVALID_HOST)
+ ret = tsp->ops->proc_handover(tsp->sci, tsp->proc_id,
+ tsp->host_id);
+ else
+ ret = tsp->ops->proc_release(tsp->sci, tsp->proc_id);
+
+ if (ret)
+ pr_err("ti-sci processor release failed: %d\n", ret);
+ return ret;
+}
+
+static inline int ti_sci_proc_handover(struct ti_sci_proc *tsp)
+{
+ int ret;
+
+ pr_debug("%s: proc_id = %d\n", __func__, tsp->proc_id);
+
+ ret = tsp->ops->proc_handover(tsp->sci, tsp->proc_id, tsp->host_id);
+ if (ret)
+ pr_err("ti-sci processor handover of %d to %d failed: %d\n",
+ tsp->proc_id, tsp->host_id, ret);
+ return ret;
+}
+
+static inline int ti_sci_proc_get_status(struct ti_sci_proc *tsp,
+ u64 *boot_vector, u32 *cfg_flags,
+ u32 *ctrl_flags, u32 *status_flags)
+{
+ int ret;
+
+ ret = tsp->ops->get_proc_boot_status(tsp->sci, tsp->proc_id,
+ boot_vector, cfg_flags, ctrl_flags,
+ status_flags);
+ if (ret)
+ pr_err("ti-sci processor get_status failed: %d\n", ret);
+
+ pr_debug("%s: proc_id = %d, boot_vector = 0x%llx, cfg_flags = 0x%x, ctrl_flags = 0x%x, sts = 0x%x\n",
+ __func__, tsp->proc_id, *boot_vector, *cfg_flags, *ctrl_flags,
+ *status_flags);
+ return ret;
+}
+
+static inline int ti_sci_proc_set_config(struct ti_sci_proc *tsp,
+ u64 boot_vector,
+ u32 cfg_set, u32 cfg_clr)
+{
+ int ret;
+
+ pr_debug("%s: proc_id = %d, boot_vector = 0x%llx, cfg_set = 0x%x, cfg_clr = 0x%x\n",
+ __func__, tsp->proc_id, boot_vector, cfg_set, cfg_clr);
+
+ ret = tsp->ops->set_proc_boot_cfg(tsp->sci, tsp->proc_id, boot_vector,
+ cfg_set, cfg_clr);
+ if (ret)
+ pr_err("ti-sci processor set_config failed: %d\n", ret);
+ return ret;
+}
+
+static inline int ti_sci_proc_set_control(struct ti_sci_proc *tsp,
+ u32 ctrl_set, u32 ctrl_clr)
+{
+ int ret;
+
+ pr_debug("%s: proc_id = %d, ctrl_set = 0x%x, ctrl_clr = 0x%x\n", __func__,
+ tsp->proc_id, ctrl_set, ctrl_clr);
+
+ ret = tsp->ops->set_proc_boot_ctrl(tsp->sci, tsp->proc_id, ctrl_set,
+ ctrl_clr);
+ if (ret)
+ pr_err("ti-sci processor set_control failed: %d\n", ret);
+ return ret;
+}
+
+static inline int ti_sci_proc_power_domain_on(struct ti_sci_proc *tsp)
+{
+ int ret;
+
+ pr_debug("%s: dev_id = %d\n", __func__, tsp->dev_id);
+
+ ret = tsp->sci->ops.dev_ops.get_device_exclusive(tsp->sci, tsp->dev_id);
+ if (ret)
+ pr_err("Power-domain on failed for dev = %d\n", tsp->dev_id);
+
+ return ret;
+}
+
+static inline int ti_sci_proc_power_domain_off(struct ti_sci_proc *tsp)
+{
+ int ret;
+
+ pr_debug("%s: dev_id = %d\n", __func__, tsp->dev_id);
+
+ ret = tsp->sci->ops.dev_ops.put_device(tsp->sci, tsp->dev_id);
+ if (ret)
+ pr_err("Power-domain off failed for dev = %d\n", tsp->dev_id);
+
+ return ret;
+}
+#endif /* REMOTEPROC_TI_SCI_PROC_H */
--
2.39.5
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v3 11/23] ARM: k3: add k3_debug_ll_init()
2025-01-13 11:26 [PATCH v3 00/23] ARM: K3: Add R5 boot support Sascha Hauer
` (8 preceding siblings ...)
2025-01-13 11:26 ` [PATCH v3 10/23] rproc: add K3 arm64 rproc driver Sascha Hauer
@ 2025-01-13 11:26 ` Sascha Hauer
2025-01-13 11:26 ` [PATCH v3 12/23] ARM: K3: use debug_ll code for regular PBL console Sascha Hauer
` (12 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Sascha Hauer @ 2025-01-13 11:26 UTC (permalink / raw)
To: open list:BAREBOX
Add a function to initialize the ns16550 compatible UART for debug_ll.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
include/mach/k3/debug_ll.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/include/mach/k3/debug_ll.h b/include/mach/k3/debug_ll.h
index 29bd4015ab..a37b50c726 100644
--- a/include/mach/k3/debug_ll.h
+++ b/include/mach/k3/debug_ll.h
@@ -33,6 +33,14 @@ static inline void debug_ll_init(void)
/* already configured */
}
+static inline void k3_debug_ll_init(void __iomem *base)
+{
+ debug_ll_ns16550_init(base, 26);
+
+ debug_ll_write_reg(base, 8, 0x07);
+ debug_ll_write_reg(base, 8, 0x00);
+}
+
static inline void PUTC_LL(int c)
{
void __iomem *base = (void *)K3_UART_BASE(K3_DEBUG_SOC,
--
2.39.5
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v3 12/23] ARM: K3: use debug_ll code for regular PBL console
2025-01-13 11:26 [PATCH v3 00/23] ARM: K3: Add R5 boot support Sascha Hauer
` (9 preceding siblings ...)
2025-01-13 11:26 ` [PATCH v3 11/23] ARM: k3: add k3_debug_ll_init() Sascha Hauer
@ 2025-01-13 11:26 ` Sascha Hauer
2025-01-13 11:27 ` [PATCH v3 13/23] elf: use iomem regions as fallback when loading to non-sdram memory Sascha Hauer
` (11 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Sascha Hauer @ 2025-01-13 11:26 UTC (permalink / raw)
To: open list:BAREBOX
Move parts of the K3 debug_ll code outside the #ifdef
CONFIG_DEBUG_AM62X_UART. This allows us to use the debug_ll provided
functions as a regular console with pbl_set_putc().
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
include/mach/k3/debug_ll.h | 38 +++++++++++++++++++-------------------
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/include/mach/k3/debug_ll.h b/include/mach/k3/debug_ll.h
index a37b50c726..13321c6134 100644
--- a/include/mach/k3/debug_ll.h
+++ b/include/mach/k3/debug_ll.h
@@ -2,20 +2,6 @@
#define __MACH_K3_DEBUG_LL_H__
#include <io.h>
-#define AM62X_UART_UART0_BASE 0x02800000
-#define AM62X_UART_UART1_BASE 0x02810000
-#define AM62X_UART_UART2_BASE 0x02820000
-#define AM62X_UART_UART3_BASE 0x02830000
-#define AM62X_UART_UART4_BASE 0x02840000
-#define AM62X_UART_UART5_BASE 0x02850000
-#define AM62X_UART_UART6_BASE 0x02860000
-
-#if defined CONFIG_DEBUG_AM62X_UART
-#define K3_DEBUG_SOC AM62X_UART
-
-#define __K3_UART_BASE(soc, num) soc##_UART##num##_BASE
-#define K3_UART_BASE(soc, num) __K3_UART_BASE(soc, num)
-
static inline uint8_t debug_ll_read_reg(void __iomem *base, int reg)
{
return readb(base + (reg << 2));
@@ -28,11 +14,6 @@ static inline void debug_ll_write_reg(void __iomem *base, int reg, uint8_t val)
#include <debug_ll/ns16550.h>
-static inline void debug_ll_init(void)
-{
- /* already configured */
-}
-
static inline void k3_debug_ll_init(void __iomem *base)
{
debug_ll_ns16550_init(base, 26);
@@ -41,6 +22,25 @@ static inline void k3_debug_ll_init(void __iomem *base)
debug_ll_write_reg(base, 8, 0x00);
}
+#define AM62X_UART_UART0_BASE 0x02800000
+#define AM62X_UART_UART1_BASE 0x02810000
+#define AM62X_UART_UART2_BASE 0x02820000
+#define AM62X_UART_UART3_BASE 0x02830000
+#define AM62X_UART_UART4_BASE 0x02840000
+#define AM62X_UART_UART5_BASE 0x02850000
+#define AM62X_UART_UART6_BASE 0x02860000
+
+#if defined CONFIG_DEBUG_AM62X_UART
+#define K3_DEBUG_SOC AM62X_UART
+
+#define __K3_UART_BASE(soc, num) soc##_UART##num##_BASE
+#define K3_UART_BASE(soc, num) __K3_UART_BASE(soc, num)
+
+static inline void debug_ll_init(void)
+{
+ /* already configured */
+}
+
static inline void PUTC_LL(int c)
{
void __iomem *base = (void *)K3_UART_BASE(K3_DEBUG_SOC,
--
2.39.5
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v3 13/23] elf: use iomem regions as fallback when loading to non-sdram memory
2025-01-13 11:26 [PATCH v3 00/23] ARM: K3: Add R5 boot support Sascha Hauer
` (10 preceding siblings ...)
2025-01-13 11:26 ` [PATCH v3 12/23] ARM: K3: use debug_ll code for regular PBL console Sascha Hauer
@ 2025-01-13 11:27 ` Sascha Hauer
2025-01-13 11:27 ` [PATCH v3 14/23] rproc: add K3 system_controller Sascha Hauer
` (10 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Sascha Hauer @ 2025-01-13 11:27 UTC (permalink / raw)
To: open list:BAREBOX
The ELF code uses request_sdram_region() to request the regions the
binary shall be copied to. However, not all of these regions are
actually SDRAM. Some specialized ELF files might also use SoC SRAM
which is not registered as SDRAM, so use request_region as a fallback
in these cases.
This is needed on the TI K3 AM625 SoC to successfully load the ti-dm
firmware binary.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
common/elf.c | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/common/elf.c b/common/elf.c
index ec78e45bf1..3cbe63f6b2 100644
--- a/common/elf.c
+++ b/common/elf.c
@@ -18,6 +18,7 @@ struct elf_section {
struct list_head list;
struct resource *r;
void *phdr;
+ bool is_iomem_region;
};
static int elf_request_region(struct elf_image *elf, resource_size_t start,
@@ -33,8 +34,12 @@ static int elf_request_region(struct elf_image *elf, resource_size_t start,
r_new = request_sdram_region("elf_section", start, size);
if (!r_new) {
- pr_err("Failed to request region: %pa %pa\n", &start, &size);
- return -EINVAL;
+ r_new = request_iomem_region("elf_section", start, size);
+ if (!r_new) {
+ pr_err("Failed to request region: %pa %pa\n", &start, &size);
+ return -EINVAL;
+ }
+ r->is_iomem_region = true;
}
r->r = r_new;
@@ -50,7 +55,10 @@ static void elf_release_regions(struct elf_image *elf)
struct elf_section *r, *r_tmp;
list_for_each_entry_safe(r, r_tmp, list, list) {
- release_sdram_region(r->r);
+ if (r->is_iomem_region)
+ release_region(r->r);
+ else
+ release_sdram_region(r->r);
list_del(&r->list);
free(r);
}
--
2.39.5
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v3 14/23] rproc: add K3 system_controller
2025-01-13 11:26 [PATCH v3 00/23] ARM: K3: Add R5 boot support Sascha Hauer
` (11 preceding siblings ...)
2025-01-13 11:27 ` [PATCH v3 13/23] elf: use iomem regions as fallback when loading to non-sdram memory Sascha Hauer
@ 2025-01-13 11:27 ` Sascha Hauer
2025-01-13 11:27 ` [PATCH v3 15/23] firmware: ti_sci: add function to get global handle Sascha Hauer
` (9 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Sascha Hauer @ 2025-01-13 11:27 UTC (permalink / raw)
To: open list:BAREBOX
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/remoteproc/Kconfig | 6 +
drivers/remoteproc/Makefile | 2 +
drivers/remoteproc/ti_k3_system_controller.c | 214 +++++++++++++++++++++++++++
3 files changed, 222 insertions(+)
diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
index 94babd28ff..39c1f5869b 100644
--- a/drivers/remoteproc/Kconfig
+++ b/drivers/remoteproc/Kconfig
@@ -31,6 +31,12 @@ config STM32_REMOTEPROC
It's safe to say N here.
+config REMOTEPROC_TI_K3_ARM64
+ bool
+
+config REMOTEPROC_K3_SYSTEM_CONTROLLER
+ bool
+
endif # REMOTEPROC
endmenu
diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile
index 185e12a7c0..47230cb2a1 100644
--- a/drivers/remoteproc/Makefile
+++ b/drivers/remoteproc/Makefile
@@ -6,3 +6,5 @@
obj-$(CONFIG_REMOTEPROC) += remoteproc_core.o remoteproc_elf_loader.o
obj-$(CONFIG_IMX_REMOTEPROC) += imx_rproc.o
obj-$(CONFIG_STM32_REMOTEPROC) += stm32_rproc.o
+obj-$(CONFIG_REMOTEPROC_TI_K3_ARM64) += ti_k3_arm64_rproc.o
+obj-$(CONFIG_REMOTEPROC_K3_SYSTEM_CONTROLLER) += ti_k3_system_controller.o
diff --git a/drivers/remoteproc/ti_k3_system_controller.c b/drivers/remoteproc/ti_k3_system_controller.c
new file mode 100644
index 0000000000..d48de9d18e
--- /dev/null
+++ b/drivers/remoteproc/ti_k3_system_controller.c
@@ -0,0 +1,214 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments' K3 System Controller Driver
+ *
+ * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ */
+
+#include <driver.h>
+#include <linux/remoteproc.h>
+#include <linux/printk.h>
+#include <errno.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <io.h>
+#include <of.h>
+#include <soc/ti/k3-sec-proxy.h>
+#include <mailbox.h>
+
+#define K3_MSG_R5_TO_M3_M3FW 0x8105
+#define K3_MSG_M3_TO_R5_CERT_RESULT 0x8805
+#define K3_MSG_M3_TO_R5_BOOT_NOTIFICATION 0x000A
+
+#define K3_FLAGS_MSG_CERT_AUTH_PASS 0x555555
+#define K3_FLAGS_MSG_CERT_AUTH_FAIL 0xffffff
+
+/**
+ * struct k3_sysctrler_msg_hdr - Generic Header for Messages and responses.
+ * @cmd_id: Message ID. One of K3_MSG_*
+ * @host_id: Host ID of the message
+ * @seq_ne: Message identifier indicating a transfer sequence.
+ * @flags: Flags for the message.
+ */
+struct k3_sysctrler_msg_hdr {
+ u16 cmd_id;
+ u8 host_id;
+ u8 seq_nr;
+ u32 flags;
+} __packed;
+
+/**
+ * struct k3_sysctrler_load_msg - Message format for Firmware loading
+ * @hdr: Generic message hdr
+ * @buffer_address: Address at which firmware is located.
+ * @buffer_size: Size of the firmware.
+ */
+struct k3_sysctrler_load_msg {
+ struct k3_sysctrler_msg_hdr hdr;
+ u32 buffer_address;
+ u32 buffer_size;
+} __packed;
+
+/**
+ * struct k3_sysctrler_boot_notification_msg - Message format for boot
+ * notification
+ * @checksum: Checksum for the entire message
+ * @reserved: Reserved for future use.
+ * @hdr: Generic message hdr
+ */
+struct k3_sysctrler_boot_notification_msg {
+ u16 checksum;
+ u16 reserved;
+ struct k3_sysctrler_msg_hdr hdr;
+} __packed;
+
+/**
+ * struct k3_sysctrler_desc - Description of SoC integration.
+ * @host_id: Host identifier representing the compute entity
+ * @max_rx_timeout_ms: Timeout for communication with SoC (in Milliseconds)
+ * @max_msg_size: Maximum size of data per message that can be handled.
+ */
+struct k3_sysctrler_desc {
+ u8 host_id;
+ int max_rx_timeout_us;
+ int max_msg_size;
+};
+
+/**
+ * struct k3_sysctrler_privdata - Structure representing System Controller data.
+ * @chan_tx: Transmit mailbox channel
+ * @chan_rx: Receive mailbox channel
+ * @chan_boot_notify: Boot notification channel
+ * @desc: SoC description for this instance
+ * @seq_nr: Counter for number of messages sent.
+ * @has_boot_notify: Has separate boot notification channel
+ */
+struct k3_sysctrler_privdata {
+ struct device *dev;
+ struct mbox_chan *chan_tx;
+ struct mbox_chan *chan_rx;
+ struct mbox_chan *chan_boot_notify;
+ const struct k3_sysctrler_desc *desc;
+ u32 seq_nr;
+ bool has_boot_notify;
+};
+
+static int k3_sysctrler_boot_notification_response(struct k3_sysctrler_privdata *priv,
+ void *buf)
+{
+ struct k3_sysctrler_boot_notification_msg *boot = buf;
+
+ /* ToDo: Verify checksum */
+
+ /* Check for proper response ID */
+ if (boot->hdr.cmd_id != K3_MSG_M3_TO_R5_BOOT_NOTIFICATION) {
+ dev_err(priv->dev, "%s: Command expected 0x%x, but received 0x%x\n",
+ __func__, K3_MSG_M3_TO_R5_BOOT_NOTIFICATION,
+ boot->hdr.cmd_id);
+ return -EINVAL;
+ }
+
+ debug("%s: Boot notification received\n", __func__);
+
+ return 0;
+}
+
+/**
+ * k3_sysctrler_start() - Start the remote processor
+ * Note that while technically the K3 system controller starts up
+ * automatically after its firmware got loaded we still want to
+ * utilize the rproc start operation for other startup-related
+ * tasks.
+ * @dev: device to operate upon
+ *
+ * Return: 0 if all went ok, else return appropriate error
+ */
+static int k3_sysctrler_start(struct k3_sysctrler_privdata *priv)
+{
+ struct k3_sec_proxy_msg msg;
+ int ret;
+
+ /* Receive the boot notification. Note that it is sent only once. */
+ ret = mbox_recv(priv->has_boot_notify ? priv->chan_boot_notify :
+ priv->chan_rx, &msg, priv->desc->max_rx_timeout_us);
+ if (ret) {
+ dev_err(priv->dev, "%s: Boot Notification response failed. ret = %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ /* Process the response */
+ ret = k3_sysctrler_boot_notification_response(priv, msg.buf);
+ if (ret)
+ return ret;
+
+ dev_info(priv->dev, "%s: Boot notification received successfully\n",
+ __func__);
+
+ return 0;
+}
+
+/**
+ * k3_sysctrler_probe() - Basic probe
+ * @dev: corresponding k3 remote processor device
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+static int k3_sysctrler_probe(struct device *dev)
+{
+ struct k3_sysctrler_privdata *priv;
+ int ret;
+
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ priv = xzalloc(sizeof(*priv));
+
+ priv->dev = dev;
+
+ priv->chan_tx = mbox_request_channel_byname(dev, "tx");
+ if (IS_ERR(priv->chan_tx))
+ return dev_err_probe(dev, PTR_ERR(priv->chan_tx), "No tx mbox\n");
+
+ priv->chan_rx = mbox_request_channel_byname(dev, "rx");
+ if (IS_ERR(priv->chan_rx))
+ return dev_err_probe(dev, PTR_ERR(priv->chan_tx), "No rx mbox\n");
+
+ /* Some SoCs may have a optional channel for boot notification. */
+ priv->has_boot_notify = 1;
+ priv->chan_boot_notify = mbox_request_channel_byname(dev, "boot_notify");
+ if (IS_ERR(priv->chan_boot_notify)) {
+ dev_dbg(dev, "%s: Acquiring optional Boot_notify failed. ret = %d. Using Rx\n",
+ __func__, ret);
+ priv->has_boot_notify = 0;
+ }
+
+ priv->desc = device_get_match_data(dev);
+ priv->seq_nr = 0;
+
+ k3_sysctrler_start(priv);
+
+ return 0;
+}
+
+static const struct k3_sysctrler_desc k3_sysctrler_am654_desc = {
+ .host_id = 4, /* HOST_ID_R5_1 */
+ .max_rx_timeout_us = 800000,
+ .max_msg_size = 60,
+};
+
+static const struct of_device_id k3_sysctrler_ids[] = {
+ {
+ .compatible = "ti,am654-system-controller",
+ .data = &k3_sysctrler_am654_desc,
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct driver ti_k3_arm64_rproc_driver = {
+ .name = "ti-k3-systemcontroller",
+ .probe = k3_sysctrler_probe,
+ .of_compatible = k3_sysctrler_ids,
+};
+device_platform_driver(ti_k3_arm64_rproc_driver);
--
2.39.5
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v3 15/23] firmware: ti_sci: add function to get global handle
2025-01-13 11:26 [PATCH v3 00/23] ARM: K3: Add R5 boot support Sascha Hauer
` (12 preceding siblings ...)
2025-01-13 11:27 ` [PATCH v3 14/23] rproc: add K3 system_controller Sascha Hauer
@ 2025-01-13 11:27 ` Sascha Hauer
2025-01-13 11:27 ` [PATCH v3 16/23] ARM: k3: Add initial r5 support Sascha Hauer
` (8 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Sascha Hauer @ 2025-01-13 11:27 UTC (permalink / raw)
To: open list:BAREBOX
Most users access the ti_sci interface by ti,sci phandles in their
device nodes. The code setting up the images on the A53 cores doesn't
have a device node though, so add a function for accessing the ti_sci
without having a phandle.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/firmware/ti_sci.c | 59 ++++++++++++++--------------------------
include/soc/ti/ti_sci_protocol.h | 7 -----
2 files changed, 21 insertions(+), 45 deletions(-)
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index 27cd46b70f..638893a1ed 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -281,7 +281,7 @@ static int ti_sci_do_xfer(struct ti_sci_info *info,
*
* Return: 0 if all went fine, else return appropriate error.
*/
-static int ti_sci_cmd_get_revision(struct ti_sci_handle *handle)
+static __maybe_unused int ti_sci_cmd_get_revision(struct ti_sci_handle *handle)
{
struct ti_sci_msg_resp_version *rev_info;
struct ti_sci_version_info *ver;
@@ -2654,29 +2654,20 @@ static void ti_sci_setup_ops(struct ti_sci_info *info)
fwl_ops->change_fwl_owner = ti_sci_cmd_change_fwl_owner;
}
-/**
- * ti_sci_get_handle_from_sysfw() - Get the TI SCI handle of the SYSFW
- * @dev: Pointer to the SYSFW device
- *
- * Return: pointer to handle if successful, else EINVAL if invalid conditions
- * are encountered.
- */
-const
-struct ti_sci_handle *ti_sci_get_handle_from_sysfw(struct device *sci_dev)
+static struct ti_sci_handle *ti_sci_get_by_node(struct device_node *np)
{
- struct ti_sci_info *info;
- int ret;
+ struct ti_sci_info *entry, *info = NULL;
- if (!sci_dev)
- return ERR_PTR(-EINVAL);
+ of_device_ensure_probed(np);
- info = dev_get_priv(sci_dev);
- if (!info)
- return ERR_PTR(-EINVAL);
+ list_for_each_entry(entry, &ti_sci_list, list)
+ if (dev_of_node(entry->dev) == np) {
+ info = entry;
+ break;
+ }
- ret = ti_sci_cmd_get_revision(&info->handle);
- if (ret)
- return ERR_PTR(-EINVAL);
+ if (!info)
+ return ERR_PTR(-ENODEV);
return &info->handle;
}
@@ -2690,14 +2681,17 @@ struct ti_sci_handle *ti_sci_get_handle_from_sysfw(struct device *sci_dev)
*/
const struct ti_sci_handle *ti_sci_get_handle(struct device *dev)
{
- struct device *sci_dev;
-
- if (!dev)
- return ERR_PTR(-EINVAL);
+ struct device_node *np;
- sci_dev = dev->parent;
+ if (dev) {
+ np = dev->parent->of_node;
+ } else {
+ np = of_find_compatible_node(NULL, NULL, "ti,k2g-sci");
+ if (!np)
+ return ERR_PTR(-ENODEV);
+ }
- return ti_sci_get_handle_from_sysfw(sci_dev);
+ return ti_sci_get_by_node(np);
}
/**
@@ -2710,25 +2704,14 @@ const struct ti_sci_handle *ti_sci_get_handle(struct device *dev)
const struct ti_sci_handle *ti_sci_get_by_phandle(struct device *dev,
const char *property)
{
- struct ti_sci_info *entry, *info = NULL;
struct device_node *np;
np = of_parse_phandle(dev->of_node, property, 0);
if (!np)
return ERR_PTR(-EINVAL);
- of_device_ensure_probed(np);
-
- list_for_each_entry(entry, &ti_sci_list, list)
- if (dev_of_node(entry->dev) == np) {
- info = entry;
- break;
- }
-
- if (!info)
- return ERR_PTR(-ENODEV);
- return &info->handle;
+ return ti_sci_get_by_node(np);
}
/**
diff --git a/include/soc/ti/ti_sci_protocol.h b/include/soc/ti/ti_sci_protocol.h
index f41ed82b91..e1c9956eb1 100644
--- a/include/soc/ti/ti_sci_protocol.h
+++ b/include/soc/ti/ti_sci_protocol.h
@@ -654,7 +654,6 @@ struct ti_sci_resource {
#if IS_ENABLED(CONFIG_TI_SCI_PROTOCOL)
-const struct ti_sci_handle *ti_sci_get_handle_from_sysfw(struct device *dev);
const struct ti_sci_handle *ti_sci_get_handle(struct device *dev);
const struct ti_sci_handle *ti_sci_get_by_phandle(struct device *dev,
const char *property);
@@ -663,12 +662,6 @@ devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
struct device *dev, u32 dev_id, char *of_prop);
#else /* CONFIG_TI_SCI_PROTOCOL */
-static inline
-const struct ti_sci_handle *ti_sci_get_handle_from_sysfw(struct device *dev)
-{
- return ERR_PTR(-EINVAL);
-}
-
static inline const struct ti_sci_handle *ti_sci_get_handle(struct device *dev)
{
return ERR_PTR(-EINVAL);
--
2.39.5
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v3 16/23] ARM: k3: Add initial r5 support
2025-01-13 11:26 [PATCH v3 00/23] ARM: K3: Add R5 boot support Sascha Hauer
` (13 preceding siblings ...)
2025-01-13 11:27 ` [PATCH v3 15/23] firmware: ti_sci: add function to get global handle Sascha Hauer
@ 2025-01-13 11:27 ` Sascha Hauer
2025-01-13 11:27 ` [PATCH v3 17/23] scripts: k3: add script to generate cfg files from yaml Sascha Hauer
` (7 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Sascha Hauer @ 2025-01-13 11:27 UTC (permalink / raw)
To: open list:BAREBOX
K3 SoCs initially boot from a Cortex-R5 processor. This patch adds
initial support for this processor along with a dtsi file to make some
adjustments to the regular device trees needed to describe the
differences between the A53 and the R5 processors.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/Kconfig | 2 -
arch/arm/dts/k3-am625-r5.dtsi | 103 ++++++++++++++++
arch/arm/mach-k3/Kconfig | 21 ++++
arch/arm/mach-k3/Makefile | 1 +
arch/arm/mach-k3/r5.c | 280 ++++++++++++++++++++++++++++++++++++++++++
include/mach/k3/r5.h | 9 ++
6 files changed, 414 insertions(+), 2 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f2c0f44e74..e897c4937d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -157,8 +157,6 @@ config ARCH_IMX
config ARCH_K3
bool "Texas Instruments Inc. K3 multicore SoC architecture"
- depends on 64BIT
- select CPU_V8
select GPIOLIB
select COMMON_CLK
select HAS_DEBUG_LL
diff --git a/arch/arm/dts/k3-am625-r5.dtsi b/arch/arm/dts/k3-am625-r5.dtsi
new file mode 100644
index 0000000000..e6e9d135b4
--- /dev/null
+++ b/arch/arm/dts/k3-am625-r5.dtsi
@@ -0,0 +1,103 @@
+
+&a53_timer0 {
+ status = "disabled";
+};
+
+&main_timer0 {
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+};
+
+&main_timer1 {
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+};
+
+&main_timer2 {
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+};
+
+&main_timer3 {
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+};
+
+&main_timer4 {
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+};
+
+&main_timer5 {
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+};
+
+&main_timer6 {
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+};
+
+&main_timer7 {
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+};
+
+&cbass_main {
+ sysctrler: sysctrler {
+ compatible = "ti,am654-system-controller";
+ mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>;
+ mbox-names = "tx", "rx", "boot_notify";
+ };
+};
+
+&secure_proxy_sa3 {
+ /* We require this for boot handshake */
+ status = "okay";
+};
+
+/ {
+ a53_0: a53@0 {
+ compatible = "ti,am654-rproc";
+ reg = <0x00 0x00a90000 0x00 0x10>;
+ power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
+ resets = <&k3_reset 135 0>;
+ clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+ clock-names = "gtc", "core";
+ assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+ assigned-clock-parents = <&k3_clks 61 2>;
+ assigned-clock-rates = <200000000>, <1250000000>;
+ ti,sci = <&dmsc>;
+ ti,sci-proc-id = <32>;
+ ti,sci-host-id = <10>;
+ };
+
+ dm_tifs: dm-tifs {
+ compatible = "ti,j721e-dm-sci";
+ ti,host-id = <36>;
+ ti,secure-host;
+ mbox-names = "rx", "tx";
+ mboxes= <&secure_proxy_main 22>,
+ <&secure_proxy_main 23>;
+ };
+};
+
+&dmsc {
+ mboxes = <&secure_proxy_main 0>,
+ <&secure_proxy_main 1>,
+ <&secure_proxy_main 0>;
+ mbox-names = "rx", "tx", "notify";
+ ti,host-id = <35>;
+ ti,secure-host;
+};
+
+&sdhci2 {
+ /* Doesn't work currently, no clocks defined */
+ status = "disabled";
+};
+
+&dss_vp1_clk {
+ /* Doesn't work, no support for input clock */
+ status = "disabled";
+};
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index 152d231a56..2ea9f32696 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -3,6 +3,27 @@
menu "K3 boards"
depends on ARCH_K3
+config MACH_K3_CORTEX_R5
+ bool
+ select CPU_V7
+ select CLOCKSOURCE_TI_DM
+ select REMOTEPROC
+ select REMOTEPROC_TI_K3_ARM64
+ select REMOTEPROC_K3_SYSTEM_CONTROLLER
+ select PM_GENERIC_DOMAINS
+ select TI_K3_PM_DOMAINS
+ select ARMV7R_MPU
+ select ELF
+ select K3_DDRSS
+ depends on 32BIT
+ default y
+
+config MACH_K3_CORTEX_A
+ bool
+ select CPU_V8
+ depends on 64BIT
+ default y
+
config MACH_BEAGLEPLAY
bool "BeagleBoard BeaglePlay"
help
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index f95691b59a..0efc1e0239 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -1 +1,2 @@
obj-y += common.o
+obj-pbl-$(CONFIG_MACH_K3_CORTEX_R5) += r5.o
diff --git a/arch/arm/mach-k3/r5.c b/arch/arm/mach-k3/r5.c
new file mode 100644
index 0000000000..0a1585570c
--- /dev/null
+++ b/arch/arm/mach-k3/r5.c
@@ -0,0 +1,280 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <io.h>
+#include <linux/kernel.h>
+#include <mach/k3/r5.h>
+#include <asm/armv7r-mpu.h>
+#include <init.h>
+#include <libfile.h>
+#include <fs.h>
+#include <firmware.h>
+#include <linux/remoteproc.h>
+#include <soc/ti/ti_sci_protocol.h>
+#include <linux/clk.h>
+#include <elf.h>
+#include <asm/cache.h>
+#include <linux/sizes.h>
+#include <barebox.h>
+
+#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
+#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
+#define CTRLMMR_LOCK_KICK0 0x1008
+#define CTRLMMR_LOCK_KICK1 0x100c
+#define CTRL_MMR0_PARTITION_SIZE 0x4000
+#define WKUP_CTRL_MMR0_BASE 0x43000000
+#define CTRL_MMR0_BASE 0x00100000
+#define MCU_CTRL_MMR0_BASE 0x04500000
+#define PADCFG_MMR0_BASE 0x04080000
+#define PADCFG_MMR1_BASE 0x000f0000
+
+static void mmr_unlock(uintptr_t base, u32 partition)
+{
+ /* Translate the base address */
+ uintptr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
+
+ /* Unlock the requested partition if locked using two-step sequence */
+ writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
+ writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
+}
+
+void k3_ctrl_mmr_unlock(void)
+{
+ /* Unlock all WKUP_CTRL_MMR0 module registers */
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 5);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
+
+ /* Unlock all CTRL_MMR0 module registers */
+ mmr_unlock(CTRL_MMR0_BASE, 0);
+ mmr_unlock(CTRL_MMR0_BASE, 1);
+ mmr_unlock(CTRL_MMR0_BASE, 2);
+ mmr_unlock(CTRL_MMR0_BASE, 4);
+ mmr_unlock(CTRL_MMR0_BASE, 6);
+
+ /* Unlock all MCU_CTRL_MMR0 module registers */
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
+
+ /* Unlock PADCFG_CTRL_MMR padconf registers */
+ mmr_unlock(PADCFG_MMR0_BASE, 1);
+ mmr_unlock(PADCFG_MMR1_BASE, 1);
+}
+
+#define CONFIG_SPL_TEXT_BASE 0x43c00000 /* FIXME */
+#define CFG_SYS_SDRAM_BASE 0x80000000 /* FIXME */
+
+static struct mpu_region_config k3_mpu_regions[] = {
+ {
+ .start_addr = 0x00000000,
+ .region_no = REGION_0,
+ .xn = XN_EN,
+ .ap = PRIV_RW_USR_RW,
+ .mr_attr = SHARED_WRITE_BUFFERED,
+ .reg_size = REGION_4GB,
+ }, {
+ /* SPL SRAM WB and Write allocate. */
+ .start_addr = 0x43c00000,
+ .region_no = REGION_1,
+ .xn = XN_DIS,
+ .ap = PRIV_RW_USR_RW,
+ .mr_attr = O_I_WB_RD_WR_ALLOC,
+ .reg_size = REGION_8MB,
+ }, {
+ /* DRAM area WB and Write allocate */
+ .start_addr = 0x80000000,
+ .region_no = REGION_2,
+ .xn = XN_DIS,
+ .ap = PRIV_RW_USR_RW,
+ .mr_attr = O_I_WB_RD_WR_ALLOC,
+ .reg_size = REGION_2GB,
+ }, {
+ /* mcu_r5fss0_core0 WB and Write allocate */
+ .start_addr = 0x41010000,
+ .region_no = REGION_3,
+ .xn = XN_DIS,
+ .ap = PRIV_RW_USR_RW,
+ .mr_attr = O_I_WB_RD_WR_ALLOC,
+ .reg_size = REGION_8MB,
+ },
+};
+
+void k3_mpu_setup_regions(void)
+{
+ armv7r_mpu_setup_regions(k3_mpu_regions, ARRAY_SIZE(k3_mpu_regions));
+}
+
+#include <soc/k3/clk.h>
+
+#define PSC_PTCMD 0x120
+#define PSC_PTCMD_H 0x124
+#define PSC_PTSTAT 0x128
+#define PSC_PTSTAT_H 0x12C
+#define PSC_PDSTAT 0x200
+#define PSC_PDCTL 0x300
+#define PSC_MDSTAT 0x800
+#define PSC_MDCTL 0xa00
+
+#define MDSTAT_STATE_MASK 0x3f
+#define MDSTAT_BUSY_MASK 0x30
+#define MDSTAT_STATE_SWRSTDISABLE 0x0
+#define MDSTAT_STATE_ENABLE 0x3
+
+static void ti_pd_wait(void __iomem *base, int id)
+{
+ u32 pdoffset = 0;
+ u32 ptstatreg = PSC_PTSTAT;
+
+ if (id > 31) {
+ pdoffset = 32;
+ ptstatreg = PSC_PTSTAT_H;
+ }
+
+ while (readl(base + ptstatreg) & BIT(id - pdoffset));
+}
+
+void am625_early_init(void)
+{
+ void __iomem *pd_base = (void *)0x400000;
+ u32 val;
+ volatile int i;
+
+ ti_k3_pll_init((void *)0x68c000);
+
+ /* hsdiv0_16fft_main_12_hsdivout0_clk divide by 2 */
+ val = readl(0x68c080);
+ val &= ~0xff;
+ val |= 31;
+ writel(val, 0x68c080);
+
+ /* PLL needs a rest, barebox would hang during PLL setup without this delay */
+ for (i = 0; i < 1000000; i++);
+
+ /*
+ * configure PLL to 800MHz, with the above divider DDR frequency
+ * results in 400MHz.
+ */
+ ti_k3_pll_set_rate((void *)0x68c000, 800000000, 25000000);
+
+ /* Enable DDR controller power domains */
+ writel(0x103, pd_base + 0x00000a24);
+ writel(0x1, pd_base + 0x00000120);
+ ti_pd_wait(pd_base, 0);
+ writel(0x103, pd_base + 0x00000a28);
+ writel(0x1, pd_base + 0x00000120);
+ ti_pd_wait(pd_base, 0);
+ writel(0x103, pd_base + 0x00000a2c);
+ writel(0x1, pd_base + 0x00000120);
+ ti_pd_wait(pd_base, 0);
+}
+
+/*
+ * The bl31 and optee binaries are relocatable, but these addresses
+ * are hardcoded as reserved mem regions in the upstream device trees.
+ */
+#define BL31_ADDRESS 0x9e780000
+#define OPTEE_ADDRESS 0x9e800000
+
+static int k3_r5_start_image(void)
+{
+ int err;
+ void *ti_dm_buf;
+ ssize_t size;
+ struct firmware fw;
+ const struct ti_sci_handle *ti_sci;
+ void *bl31 = (void *)BL31_ADDRESS;
+ void *barebox = (void *)0x80080000;
+ void *optee = (void *)OPTEE_ADDRESS;
+ struct elf_image *elf;
+ void __noreturn (*ti_dm)(void);
+ struct rproc *arm64_rproc;
+
+ ti_sci = ti_sci_get_handle(NULL);
+ if (IS_ERR(ti_sci))
+ return -EINVAL;
+
+ arm64_rproc = ti_k3_am64_get_handle();
+ if (!arm64_rproc) {
+ pr_err("Cannot get rproc handle\n");
+ return -EINVAL;
+ }
+
+ size = read_file_into_buf("/boot/optee.bin", optee, SZ_32M);
+ if (size < 0) {
+ pr_err("Cannot load optee.bin: %pe\n", ERR_PTR(size));
+ return size;
+ }
+ pr_debug("Loaded optee.bin (size %u) to 0x%p\n", size, optee);
+
+ size = read_file_into_buf("/boot/barebox.bin", barebox, optee - barebox);
+ if (size < 0) {
+ pr_err("Cannot load barebox.bin: %pe\n", ERR_PTR(size));
+ return size;
+ }
+ pr_debug("Loaded barebox.bin (size %u) to 0x%p\n", size, barebox);
+
+ size = read_file_into_buf("/boot/bl31.bin", bl31, barebox - optee);
+ if (size < 0) {
+ pr_err("Cannot load bl31.bin: %pe\n", ERR_PTR(size));
+ return size;
+ }
+ pr_debug("Loaded bl31.bin (size %u) to 0x%p\n", size, bl31);
+
+ err = read_file_2("/boot/ti-dm.bin", &size, &ti_dm_buf, FILESIZE_MAX);
+ if (err) {
+ pr_err("Cannot load ti-dm.bin: %pe\n", ERR_PTR(err));
+ return err;
+ }
+ pr_debug("Loaded ti-dm.bin (size %u)\n", size);
+
+ elf = elf_open_binary(ti_dm_buf);
+ if (IS_ERR(elf)) {
+ pr_err("Cannot open ELF image %pe\n", elf);
+ return PTR_ERR(elf);
+ }
+
+ err = elf_load(elf);
+ if (err) {
+ pr_err("Cannot load ELF image %pe\n", ERR_PTR(err));
+ elf_close(elf);
+ }
+
+ free(ti_dm_buf);
+
+ fw.data = bl31;
+
+ /* Release all the exclusive devices held by SPL before starting ATF */
+ pr_info("Starting TF-A on A53 core\n");
+
+ sync_caches_for_execution();
+
+ ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci);
+ arm64_rproc->ops->load(arm64_rproc, &fw);
+ arm64_rproc->ops->start(arm64_rproc);
+
+ pr_debug("Starting ti-dm at 0x%08llx\n", elf->entry);
+
+ ti_dm = (void *)(unsigned long)elf->entry;
+
+ ti_dm();
+}
+
+static int xload(void)
+{
+ int ret;
+
+ ret = k3_r5_start_image();
+
+ pr_crit("Starting image failed with: %pe\n", ERR_PTR(ret));
+ pr_crit("Nothing left to do\n");
+
+ hang();
+}
+postenvironment_initcall(xload);
diff --git a/include/mach/k3/r5.h b/include/mach/k3/r5.h
new file mode 100644
index 0000000000..f40639ed5b
--- /dev/null
+++ b/include/mach/k3/r5.h
@@ -0,0 +1,9 @@
+#ifndef __MACH_K3_R5_H
+#define __MACH_K3_R5_H
+
+void k3_ctrl_mmr_unlock(void);
+void k3_mpu_setup_regions(void);
+void am625_early_init(void);
+struct rproc *ti_k3_am64_get_handle(void);
+
+#endif /* __MACH_K3_R5_H */
--
2.39.5
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v3 17/23] scripts: k3: add script to generate cfg files from yaml
2025-01-13 11:26 [PATCH v3 00/23] ARM: K3: Add R5 boot support Sascha Hauer
` (14 preceding siblings ...)
2025-01-13 11:27 ` [PATCH v3 16/23] ARM: k3: Add initial r5 support Sascha Hauer
@ 2025-01-13 11:27 ` Sascha Hauer
2025-01-14 9:29 ` Ahmad Fatoum
2025-01-13 11:27 ` [PATCH v3 18/23] ARM: k3: Add k3img tool Sascha Hauer
` (6 subsequent siblings)
22 siblings, 1 reply; 26+ messages in thread
From: Sascha Hauer @ 2025-01-13 11:27 UTC (permalink / raw)
To: open list:BAREBOX
The K3 images need some config binary snippets. In U-Boot these snippets
are generated from board specific YAML files using binman. This patch
adds a small python which does the same for barebox. The python script
is based on the corresponding binman code in U-Boot.
The YAML files are board specific in U-Boot, but mostly are identical
for all boards of a specific SoC type, so we provide common SoC specific
YAML files in barebox for now.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-k3/Makefile | 16 +
arch/arm/mach-k3/board-cfg-am625.yaml | 36 ++
arch/arm/mach-k3/pm-cfg-am625.yaml | 12 +
arch/arm/mach-k3/rm-cfg-am625.yaml | 981 ++++++++++++++++++++++++++++++++++
arch/arm/mach-k3/schema.yaml | 436 +++++++++++++++
arch/arm/mach-k3/sec-cfg-am625.yaml | 379 +++++++++++++
scripts/Makefile.lib | 3 +
scripts/ti-board-config.py | 170 ++++++
8 files changed, 2033 insertions(+)
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index 0efc1e0239..6e105095da 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -1,2 +1,18 @@
obj-y += common.o
obj-pbl-$(CONFIG_MACH_K3_CORTEX_R5) += r5.o
+
+extra-y += combined-dm-cfg-am625.k3cfg combined-sysfw-cfg-am625.k3cfg
+
+$(obj)/combined-dm-cfg-am625.k3cfg: $(srctree)/arch/arm/mach-k3/schema.yaml \
+ $(obj)/pm-cfg-am625.yaml \
+ $(obj)/rm-cfg-am625.yaml \
+ FORCE
+ $(call if_changed,k3_cfg)
+
+$(obj)/combined-sysfw-cfg-am625.k3cfg: $(srctree)/arch/arm/mach-k3/schema.yaml \
+ $(obj)/board-cfg-am625.yaml \
+ $(obj)/sec-cfg-am625.yaml \
+ $(obj)/pm-cfg-am625.yaml \
+ $(obj)/rm-cfg-am625.yaml \
+ FORCE
+ $(call if_changed,k3_cfg)
diff --git a/arch/arm/mach-k3/board-cfg-am625.yaml b/arch/arm/mach-k3/board-cfg-am625.yaml
new file mode 100644
index 0000000000..45c89dd15f
--- /dev/null
+++ b/arch/arm/mach-k3/board-cfg-am625.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Board configuration for AM62
+#
+
+---
+
+board-cfg:
+ rev:
+ boardcfg_abi_maj: 0x0
+ boardcfg_abi_min: 0x1
+ control:
+ subhdr:
+ magic: 0xC1D3
+ size: 7
+ main_isolation_enable: 0x5A
+ main_isolation_hostid: 0x2
+ secproxy:
+ subhdr:
+ magic: 0x1207
+ size: 7
+ scaling_factor: 0x1
+ scaling_profile: 0x1
+ disable_main_nav_secure_proxy: 0
+ msmc:
+ subhdr:
+ magic: 0xA5C3
+ size: 5
+ msmc_cache_size: 0x0
+ debug_cfg:
+ subhdr:
+ magic: 0x020C
+ size: 8
+ trace_dst_enables: 0x00
+ trace_src_enables: 0x00
diff --git a/arch/arm/mach-k3/pm-cfg-am625.yaml b/arch/arm/mach-k3/pm-cfg-am625.yaml
new file mode 100644
index 0000000000..9853a25eb8
--- /dev/null
+++ b/arch/arm/mach-k3/pm-cfg-am625.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Power management configuration for AM62
+#
+
+---
+
+pm-cfg:
+ rev:
+ boardcfg_abi_maj: 0x0
+ boardcfg_abi_min: 0x1
diff --git a/arch/arm/mach-k3/rm-cfg-am625.yaml b/arch/arm/mach-k3/rm-cfg-am625.yaml
new file mode 100644
index 0000000000..725f7c83f0
--- /dev/null
+++ b/arch/arm/mach-k3/rm-cfg-am625.yaml
@@ -0,0 +1,981 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for AM62X
+#
+
+---
+
+rm-cfg:
+ rm_boardcfg:
+ rev:
+ boardcfg_abi_maj: 0x0
+ boardcfg_abi_min: 0x1
+ host_cfg:
+ subhdr:
+ magic: 0x4C41
+ size: 356
+ host_cfg_entries:
+ - # 1
+ host_id: 12
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 2
+ host_id: 30
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 3
+ host_id: 36
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 4
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 5
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 6
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 7
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 8
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 9
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 10
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 11
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 12
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 13
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 14
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 15
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 16
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 17
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 18
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 19
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 20
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 21
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 22
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 23
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 24
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 25
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 26
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 27
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 28
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 29
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 30
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 31
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 32
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ resasg:
+ subhdr:
+ magic: 0x7B25
+ size: 8
+ resasg_entries_size: 976
+ reserved: 0
+ resasg_entries:
+ -
+ start_resource: 0
+ num_resource: 16
+ type: 64
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 4
+ type: 64
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 4
+ type: 64
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 20
+ num_resource: 22
+ type: 64
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 16
+ type: 192
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 34
+ num_resource: 2
+ type: 192
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 2
+ type: 320
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 2
+ num_resource: 2
+ type: 320
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 2
+ num_resource: 2
+ type: 320
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 4
+ num_resource: 4
+ type: 320
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 26
+ type: 384
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 50176
+ num_resource: 164
+ type: 1666
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 1667
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 18
+ type: 1677
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 18
+ num_resource: 6
+ type: 1677
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 18
+ num_resource: 6
+ type: 1677
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 24
+ num_resource: 2
+ type: 1677
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 26
+ num_resource: 6
+ type: 1677
+ host_id: 128
+ reserved: 0
+ -
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+ type: 1678
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+ reserved: 0
+ -
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+ type: 1678
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+ reserved: 0
+ -
+ start_resource: 72
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+ type: 1678
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+ reserved: 0
+ -
+ start_resource: 78
+ num_resource: 2
+ type: 1678
+ host_id: 30
+ reserved: 0
+ -
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+ reserved: 0
+ -
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+ num_resource: 12
+ type: 1679
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+ reserved: 0
+ -
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+ num_resource: 6
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+ host_id: 35
+ reserved: 0
+ -
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+ num_resource: 6
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+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 50
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+ reserved: 0
+ -
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+ num_resource: 2
+ type: 1679
+ host_id: 128
+ reserved: 0
+ -
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+ type: 1696
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 18
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+ type: 1696
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+ reserved: 0
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+ start_resource: 18
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+ type: 1696
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+ reserved: 0
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+ host_id: 128
+ reserved: 0
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+ reserved: 0
+ -
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+ -
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+ reserved: 0
+ -
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+ -
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+ -
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+ reserved: 0
+ -
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+ type: 1936
+ host_id: 30
+ reserved: 0
+ -
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+ num_resource: 3
+ type: 1936
+ host_id: 128
+ reserved: 0
+ -
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+ type: 1937
+ host_id: 12
+ reserved: 0
+ -
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+ num_resource: 64
+ type: 1937
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+ reserved: 0
+ -
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+ num_resource: 8
+ type: 1938
+ host_id: 12
+ reserved: 0
+ -
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+ num_resource: 8
+ type: 1939
+ host_id: 12
+ reserved: 0
+ -
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+ num_resource: 10
+ type: 1942
+ host_id: 12
+ reserved: 0
+ -
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+ num_resource: 3
+ type: 1942
+ host_id: 35
+ reserved: 0
+ -
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+ num_resource: 3
+ type: 1942
+ host_id: 36
+ reserved: 0
+ -
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+ num_resource: 3
+ type: 1942
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+ reserved: 0
+ -
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+ num_resource: 3
+ type: 1942
+ host_id: 128
+ reserved: 0
+ -
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+ num_resource: 16
+ type: 1943
+ host_id: 12
+ reserved: 0
+ -
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+ num_resource: 16
+ type: 1943
+ host_id: 36
+ reserved: 0
+ -
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+ num_resource: 8
+ type: 1944
+ host_id: 12
+ reserved: 0
+ -
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+ num_resource: 8
+ type: 1945
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 142
+ num_resource: 8
+ type: 1946
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 142
+ num_resource: 8
+ type: 1947
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1955
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1955
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1955
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1955
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1955
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 8
+ type: 1956
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 8
+ type: 1956
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 27
+ num_resource: 1
+ type: 1957
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 28
+ num_resource: 1
+ type: 1958
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1961
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1961
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1961
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1961
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1961
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1962
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1962
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1962
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1962
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1962
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 1
+ type: 1963
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 1
+ type: 1963
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 16
+ type: 1964
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 16
+ type: 1964
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 20
+ num_resource: 1
+ type: 1965
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 35
+ num_resource: 8
+ type: 1966
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 21
+ num_resource: 1
+ type: 1967
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 35
+ num_resource: 8
+ type: 1968
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 22
+ num_resource: 1
+ type: 1969
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 43
+ num_resource: 8
+ type: 1970
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 23
+ num_resource: 1
+ type: 1971
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 43
+ num_resource: 8
+ type: 1972
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 2112
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 2
+ num_resource: 2
+ type: 2122
+ host_id: 12
+ reserved: 0
diff --git a/arch/arm/mach-k3/schema.yaml b/arch/arm/mach-k3/schema.yaml
new file mode 100644
index 0000000000..c8dd2e79e7
--- /dev/null
+++ b/arch/arm/mach-k3/schema.yaml
@@ -0,0 +1,436 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Config schema for TI K3 devices
+#
+
+---
+
+definitions:
+ u8:
+ type: integer
+ minimum: 0
+ maximum: 0xff
+ u16:
+ type: integer
+ minimum: 0
+ maximum: 0xffff
+ u32:
+ type: integer
+ minimum: 0
+ maximum: 0xffffffff
+
+
+
+type: object
+properties:
+ pm-cfg:
+ type: object
+ properties:
+ rev:
+ type: object
+ properties:
+ boardcfg_abi_maj:
+ $ref: "#/definitions/u8"
+ boardcfg_abi_min:
+ $ref: "#/definitions/u8"
+ board-cfg:
+ type: object
+ properties:
+ rev:
+ type: object
+ properties:
+ boardcfg_abi_maj:
+ $ref: "#/definitions/u8"
+ boardcfg_abi_min:
+ $ref: "#/definitions/u8"
+ control:
+ type: object
+ properties:
+ subhdr:
+ type: object
+ properties:
+ magic:
+ $ref: "#/definitions/u16"
+ size:
+ $ref: "#/definitions/u16"
+ main_isolation_enable:
+ $ref: "#/definitions/u8"
+ main_isolation_hostid:
+ $ref: "#/definitions/u16"
+
+
+ secproxy:
+ type: object
+ properties:
+ subhdr:
+ type: object
+ properties:
+ magic:
+ $ref: "#/definitions/u16"
+ size:
+ $ref: "#/definitions/u16"
+ scaling_factor:
+ $ref: "#/definitions/u8"
+ scaling_profile:
+ $ref: "#/definitions/u8"
+ disable_main_nav_secure_proxy:
+ $ref: "#/definitions/u8"
+
+ msmc:
+ type: object
+ properties:
+ subhdr:
+ type: object
+ properties:
+ magic:
+ $ref: "#/definitions/u16"
+ size:
+ $ref: "#/definitions/u16"
+ msmc_cache_size:
+ $ref: "#/definitions/u8"
+ debug_cfg:
+ type: object
+ properties:
+ subhdr:
+ type: object
+ properties:
+ magic:
+ $ref: "#/definitions/u16"
+ size:
+ $ref: "#/definitions/u16"
+ trace_dst_enables:
+ $ref: "#/definitions/u16"
+ trace_src_enables:
+ $ref: "#/definitions/u16"
+
+ sec-cfg:
+ type: object
+ properties:
+ rev:
+ type: object
+ properties:
+ boardcfg_abi_maj:
+ $ref: "#/definitions/u8"
+ boardcfg_abi_min:
+ $ref: "#/definitions/u8"
+
+ processor_acl_list:
+ type: object
+ properties:
+ subhdr:
+ type: object
+ properties:
+ magic:
+ $ref: "#/definitions/u16"
+ size:
+ $ref: "#/definitions/u16"
+ proc_acl_entries:
+ type: array
+ minItems: 32
+ maxItems: 32
+ items:
+ type: object
+ properties:
+ processor_id:
+ $ref: "#/definitions/u8"
+ proc_access_master:
+ $ref: "#/definitions/u8"
+ proc_access_secondary:
+ type: array
+ minItems: 3
+ maxItems: 3
+ items:
+ $ref: "#/definitions/u8"
+ host_hierarchy:
+ type: object
+ properties:
+ subhdr:
+ type: object
+ properties:
+ magic:
+ $ref: "#/definitions/u16"
+ size:
+ $ref: "#/definitions/u16"
+ host_hierarchy_entries:
+ type: array
+ minItems: 32
+ maxItems: 32
+ items:
+ type: object
+ properties:
+ host_id:
+ $ref: "#/definitions/u8"
+ supervisor_host_id:
+ $ref: "#/definitions/u8"
+
+ otp_config:
+ type: object
+ properties:
+ subhdr:
+ type: object
+ properties:
+ magic:
+ $ref: "#/definitions/u16"
+ size:
+ $ref: "#/definitions/u16"
+ otp_entry:
+ type: array
+ minItems: 32
+ maxItems: 32
+ items:
+ type: object
+ properties:
+ host_id:
+ $ref: "#/definitions/u8"
+ host_perms:
+ $ref: "#/definitions/u8"
+ write_host_id:
+ $ref: "#/definitions/u8"
+
+ dkek_config:
+ type: object
+ properties:
+ subhdr:
+ type: object
+ properties:
+ magic:
+ $ref: "#/definitions/u16"
+ size:
+ $ref: "#/definitions/u16"
+ allowed_hosts:
+ type: array
+ minItems: 4
+ maxItems: 4
+ items:
+ $ref: "#/definitions/u8"
+ allow_dkek_export_tisci:
+ $ref: "#/definitions/u8"
+ rsvd:
+ type: array
+ minItems: 3
+ maxItems: 3
+ items:
+ $ref: "#/definitions/u8"
+
+ sa2ul_cfg:
+ type: object
+ properties:
+ subhdr:
+ type: object
+ properties:
+ magic:
+ $ref: "#/definitions/u16"
+ size:
+ $ref: "#/definitions/u16"
+ rsvd:
+ type: array
+ minItems: 2
+ maxItems: 4
+ items:
+ $ref: "#/definitions/u8"
+ enable_saul_psil_global_config_writes:
+ $ref: "#/definitions/u8"
+ auth_resource_owner:
+ $ref: "#/definitions/u8"
+
+ sec_dbg_config:
+ type: object
+ properties:
+ subhdr:
+ type: object
+ properties:
+ magic:
+ $ref: "#/definitions/u16"
+ size:
+ $ref: "#/definitions/u16"
+ allow_jtag_unlock:
+ $ref: "#/definitions/u8"
+ allow_wildcard_unlock:
+ $ref: "#/definitions/u8"
+ allowed_debug_level_rsvd:
+ $ref: "#/definitions/u8"
+ rsvd:
+ $ref: "#/definitions/u8"
+ min_cert_rev:
+ $ref: "#/definitions/u32"
+ jtag_unlock_hosts:
+ type: array
+ minItems: 4
+ maxItems: 4
+ items:
+ $ref: "#/definitions/u8"
+
+
+ sec_handover_cfg:
+ type: object
+ properties:
+ subhdr:
+ type: object
+ properties:
+ magic:
+ $ref: "#/definitions/u16"
+ size:
+ $ref: "#/definitions/u16"
+ handover_msg_sender:
+ $ref: "#/definitions/u8"
+ handover_to_host_id:
+ $ref: "#/definitions/u8"
+ rsvd:
+ type: array
+ minItems: 4
+ maxItems: 4
+ items:
+ $ref: "#/definitions/u8"
+
+ rm-cfg:
+ type: object
+ properties:
+ rm_boardcfg:
+ type: object
+ properties:
+ rev:
+ type: object
+ properties:
+ boardcfg_abi_maj:
+ $ref: "#/definitions/u8"
+ boardcfg_abi_min:
+ $ref: "#/definitions/u8"
+
+ host_cfg:
+ type: object
+ properties:
+ subhdr:
+ type: object
+ properties:
+ magic:
+ $ref: "#/definitions/u16"
+ size:
+ $ref: "#/definitions/u16"
+ host_cfg_entries:
+ type: array
+ minItems: 0
+ maxItems: 32
+ items:
+ type: object
+ properties:
+ host_id:
+ $ref: "#/definitions/u8"
+ allowed_atype:
+ $ref: "#/definitions/u8"
+ allowed_qos:
+ $ref: "#/definitions/u16"
+ allowed_orderid:
+ $ref: "#/definitions/u32"
+ allowed_priority:
+ $ref: "#/definitions/u16"
+ allowed_sched_priority:
+ $ref: "#/definitions/u8"
+ resasg:
+ type: object
+ properties:
+ subhdr:
+ type: object
+ properties:
+ magic:
+ $ref: "#/definitions/u16"
+ size:
+ $ref: "#/definitions/u16"
+ resasg_entries_size:
+ $ref: "#/definitions/u16"
+ reserved:
+ $ref: "#/definitions/u16"
+
+ resasg_entries:
+ type: array
+ minItems: 0
+ maxItems: 468
+ items:
+ type: object
+ properties:
+ start_resource:
+ $ref: "#/definitions/u16"
+ num_resource:
+ $ref: "#/definitions/u16"
+ type:
+ $ref: "#/definitions/u16"
+ host_id:
+ $ref: "#/definitions/u8"
+ reserved:
+ $ref: "#/definitions/u8"
+
+ tifs-rm-cfg:
+ type: object
+ properties:
+ rm_boardcfg:
+ type: object
+ properties:
+ rev:
+ type: object
+ properties:
+ boardcfg_abi_maj:
+ $ref: "#/definitions/u8"
+ boardcfg_abi_min:
+ $ref: "#/definitions/u8"
+
+ host_cfg:
+ type: object
+ properties:
+ subhdr:
+ type: object
+ properties:
+ magic:
+ $ref: "#/definitions/u16"
+ size:
+ $ref: "#/definitions/u16"
+ host_cfg_entries:
+ type: array
+ minItems: 0
+ maxItems: 32
+ items:
+ type: object
+ properties:
+ host_id:
+ $ref: "#/definitions/u8"
+ allowed_atype:
+ $ref: "#/definitions/u8"
+ allowed_qos:
+ $ref: "#/definitions/u16"
+ allowed_orderid:
+ $ref: "#/definitions/u32"
+ allowed_priority:
+ $ref: "#/definitions/u16"
+ allowed_sched_priority:
+ $ref: "#/definitions/u8"
+ resasg:
+ type: object
+ properties:
+ subhdr:
+ type: object
+ properties:
+ magic:
+ $ref: "#/definitions/u16"
+ size:
+ $ref: "#/definitions/u16"
+ resasg_entries_size:
+ $ref: "#/definitions/u16"
+ reserved:
+ $ref: "#/definitions/u16"
+
+ resasg_entries:
+ type: array
+ minItems: 0
+ maxItems: 468
+ items:
+ type: object
+ properties:
+ start_resource:
+ $ref: "#/definitions/u16"
+ num_resource:
+ $ref: "#/definitions/u16"
+ type:
+ $ref: "#/definitions/u16"
+ host_id:
+ $ref: "#/definitions/u8"
+ reserved:
+ $ref: "#/definitions/u8"
diff --git a/arch/arm/mach-k3/sec-cfg-am625.yaml b/arch/arm/mach-k3/sec-cfg-am625.yaml
new file mode 100644
index 0000000000..088b2dbaf1
--- /dev/null
+++ b/arch/arm/mach-k3/sec-cfg-am625.yaml
@@ -0,0 +1,379 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Security management configuration for AM62
+#
+
+---
+
+sec-cfg:
+ rev:
+ boardcfg_abi_maj: 0x0
+ boardcfg_abi_min: 0x1
+ processor_acl_list:
+ subhdr:
+ magic: 0xF1EA
+ size: 164
+ proc_acl_entries:
+ - # 1
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 2
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 3
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 4
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 5
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 6
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 7
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 8
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 9
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 10
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 11
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 12
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 13
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 14
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 15
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 16
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 17
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 18
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 19
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 20
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 21
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 22
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 23
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 24
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 25
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 26
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 27
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 28
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 29
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 30
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 31
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 32
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ host_hierarchy:
+ subhdr:
+ magic: 0x8D27
+ size: 68
+ host_hierarchy_entries:
+ - # 1
+ host_id: 0
+ supervisor_host_id: 0
+ - # 2
+ host_id: 0
+ supervisor_host_id: 0
+ - # 3
+ host_id: 0
+ supervisor_host_id: 0
+ - # 4
+ host_id: 0
+ supervisor_host_id: 0
+ - # 5
+ host_id: 0
+ supervisor_host_id: 0
+ - # 6
+ host_id: 0
+ supervisor_host_id: 0
+ - # 7
+ host_id: 0
+ supervisor_host_id: 0
+ - # 8
+ host_id: 0
+ supervisor_host_id: 0
+ - # 9
+ host_id: 0
+ supervisor_host_id: 0
+ - # 10
+ host_id: 0
+ supervisor_host_id: 0
+ - # 11
+ host_id: 0
+ supervisor_host_id: 0
+ - # 12
+ host_id: 0
+ supervisor_host_id: 0
+ - # 13
+ host_id: 0
+ supervisor_host_id: 0
+ - # 14
+ host_id: 0
+ supervisor_host_id: 0
+ - # 15
+ host_id: 0
+ supervisor_host_id: 0
+ - # 16
+ host_id: 0
+ supervisor_host_id: 0
+ - # 17
+ host_id: 0
+ supervisor_host_id: 0
+ - # 18
+ host_id: 0
+ supervisor_host_id: 0
+ - # 19
+ host_id: 0
+ supervisor_host_id: 0
+ - # 20
+ host_id: 0
+ supervisor_host_id: 0
+ - # 21
+ host_id: 0
+ supervisor_host_id: 0
+ - # 22
+ host_id: 0
+ supervisor_host_id: 0
+ - # 23
+ host_id: 0
+ supervisor_host_id: 0
+ - # 24
+ host_id: 0
+ supervisor_host_id: 0
+ - # 25
+ host_id: 0
+ supervisor_host_id: 0
+ - # 26
+ host_id: 0
+ supervisor_host_id: 0
+ - # 27
+ host_id: 0
+ supervisor_host_id: 0
+ - # 28
+ host_id: 0
+ supervisor_host_id: 0
+ - # 29
+ host_id: 0
+ supervisor_host_id: 0
+ - # 30
+ host_id: 0
+ supervisor_host_id: 0
+ - # 31
+ host_id: 0
+ supervisor_host_id: 0
+ - # 32
+ host_id: 0
+ supervisor_host_id: 0
+ otp_config:
+ subhdr:
+ magic: 0x4081
+ size: 69
+ write_host_id: 0
+ otp_entry:
+ - # 1
+ host_id: 0
+ host_perms: 0
+ - # 2
+ host_id: 0
+ host_perms: 0
+ - # 3
+ host_id: 0
+ host_perms: 0
+ - # 4
+ host_id: 0
+ host_perms: 0
+ - # 5
+ host_id: 0
+ host_perms: 0
+ - # 6
+ host_id: 0
+ host_perms: 0
+ - # 7
+ host_id: 0
+ host_perms: 0
+ - # 8
+ host_id: 0
+ host_perms: 0
+ - # 9
+ host_id: 0
+ host_perms: 0
+ - # 10
+ host_id: 0
+ host_perms: 0
+ - # 11
+ host_id: 0
+ host_perms: 0
+ - # 12
+ host_id: 0
+ host_perms: 0
+ - # 13
+ host_id: 0
+ host_perms: 0
+ - # 14
+ host_id: 0
+ host_perms: 0
+ - # 15
+ host_id: 0
+ host_perms: 0
+ - # 16
+ host_id: 0
+ host_perms: 0
+ - # 17
+ host_id: 0
+ host_perms: 0
+ - # 18
+ host_id: 0
+ host_perms: 0
+ - # 19
+ host_id: 0
+ host_perms: 0
+ - # 20
+ host_id: 0
+ host_perms: 0
+ - # 21
+ host_id: 0
+ host_perms: 0
+ - # 22
+ host_id: 0
+ host_perms: 0
+ - # 23
+ host_id: 0
+ host_perms: 0
+ - # 24
+ host_id: 0
+ host_perms: 0
+ - # 25
+ host_id: 0
+ host_perms: 0
+ - # 26
+ host_id: 0
+ host_perms: 0
+ - # 27
+ host_id: 0
+ host_perms: 0
+ - # 28
+ host_id: 0
+ host_perms: 0
+ - # 29
+ host_id: 0
+ host_perms: 0
+ - # 30
+ host_id: 0
+ host_perms: 0
+ - # 31
+ host_id: 0
+ host_perms: 0
+ - # 32
+ host_id: 0
+ host_perms: 0
+ dkek_config:
+ subhdr:
+ magic: 0x5170
+ size: 12
+ allowed_hosts: [128, 0, 0, 0]
+ allow_dkek_export_tisci: 0x5A
+ rsvd: [0, 0, 0]
+ sa2ul_cfg:
+ subhdr:
+ magic: 0x23BE
+ size: 0
+ auth_resource_owner: 0
+ enable_saul_psil_global_config_writes: 0x5A
+ rsvd: [0, 0]
+ sec_dbg_config:
+ subhdr:
+ magic: 0x42AF
+ size: 16
+ allow_jtag_unlock: 0x5A
+ allow_wildcard_unlock: 0x5A
+ allowed_debug_level_rsvd: 0
+ rsvd: 0
+ min_cert_rev: 0x0
+ jtag_unlock_hosts: [0, 0, 0, 0]
+ sec_handover_cfg:
+ subhdr:
+ magic: 0x608F
+ size: 10
+ handover_msg_sender: 0
+ handover_to_host_id: 0
+ rsvd: [0, 0, 0, 0]
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index c32adf07cc..6e8f1c8e9a 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -539,6 +539,9 @@ quiet_cmd_check_missing_fw = # no message as we collect info for later
$(OBJCOPY) -O binary --only-section=.missing_fw $3 $2.missing-firmware; \
[ -s $2.missing-firmware ] || rm -f $2.missing-firmware
+quiet_cmd_k3_cfg = K3CFG $@
+ cmd_k3_cfg = $(srctree)/scripts/ti-board-config.py $@ $(filter-out FORCE,$^)
+
quiet_cmd_imximage__S_dcd= DCD_S $@
cmd_imximage_S_dcd= \
( \
diff --git a/scripts/ti-board-config.py b/scripts/ti-board-config.py
new file mode 100755
index 0000000000..4b6214c299
--- /dev/null
+++ b/scripts/ti-board-config.py
@@ -0,0 +1,170 @@
+#!/usr/bin/env python3
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+# Written by Neha Malcom Francis <n-francis@ti.com>
+#
+# Entry-type module for generating schema validated TI board
+# configuration binary
+#
+
+import os
+import struct
+import yaml
+import yamllint
+import sys
+
+from jsonschema import validate
+
+from yamllint import config
+
+BOARDCFG = 0xB
+BOARDCFG_SEC = 0xD
+BOARDCFG_PM = 0xE
+BOARDCFG_RM = 0xC
+
+class cfgentry:
+ def __init__(self, cfgtype, data):
+ self.cfgtype = cfgtype
+ self.data = data
+
+class Entry_ti_board_config:
+ def __init__(self, schema):
+ self._config = None
+ self._schema = None
+ self._fmt = '<HHHBB'
+ self._index = 0
+ self._sw_rev = 1
+ self._devgrp = 0
+ self.cfgentries = []
+ self.header = struct.pack('<BB', 4, 1)
+ self._binary_offset = len(self.header)
+ self._schema_file = schema
+
+ def _convert_to_byte_chunk(self, val, data_type):
+ """Convert value into byte array
+
+ Args:
+ val: value to convert into byte array
+ data_type: data type used in schema, supported data types are u8,
+ u16 and u32
+
+ Returns:
+ array of bytes representing value
+ """
+ size = 0
+ if (data_type == '#/definitions/u8'):
+ size = 1
+ elif (data_type == '#/definitions/u16'):
+ size = 2
+ else:
+ size = 4
+ if type(val) == int:
+ br = val.to_bytes(size, byteorder='little')
+ return br
+
+ def _compile_yaml(self, schema_yaml, file_yaml):
+ """Convert YAML file into byte array based on YAML schema
+
+ Args:
+ schema_yaml: file containing YAML schema
+ file_yaml: file containing config to compile
+
+ Returns:
+ array of bytes repesenting YAML file against YAML schema
+ """
+ br = bytearray()
+ for key, node in file_yaml.items():
+ node_schema = schema_yaml['properties'][key]
+ node_type = node_schema.get('type')
+ if not 'type' in node_schema:
+ br += self._convert_to_byte_chunk(node,
+ node_schema.get('$ref'))
+ elif node_type == 'object':
+ br += self._compile_yaml(node_schema, node)
+ elif node_type == 'array':
+ for item in node:
+ if not isinstance(item, dict):
+ br += self._convert_to_byte_chunk(
+ item, schema_yaml['properties'][key]['items']['$ref'])
+ else:
+ br += self._compile_yaml(node_schema.get('items'), item)
+ return br
+
+ def _generate_binaries(self):
+ """Generate config binary artifacts from the loaded YAML configuration file
+
+ Returns:
+ byte array containing config binary artifacts
+ or None if generation fails
+ """
+ cfg_binary = bytearray()
+ for key, node in self.file_yaml.items():
+ node_schema = self.schema_yaml['properties'][key]
+ br = self._compile_yaml(node_schema, node)
+ cfg_binary += br
+ return cfg_binary
+
+ def _add_boardcfg(self, bcfgtype, bcfgdata):
+ """Add board config to combined board config binary
+
+ Args:
+ bcfgtype (int): board config type
+ bcfgdata (byte array): board config data
+ """
+ size = len(bcfgdata)
+
+ desc = struct.pack(self._fmt, bcfgtype,
+ self._binary_offset, size, self._devgrp, 0)
+ self._binary_offset += size
+ self._index += 1
+ return desc
+
+ def add_data(self, configfile):
+ self._config_file = configfile
+ with open(self._config_file, 'r') as f:
+ self.file_yaml = yaml.safe_load(f)
+ with open(self._schema_file, 'r') as sch:
+ self.schema_yaml = yaml.safe_load(sch)
+
+ if self.file_yaml.get('board-cfg') != None:
+ cfgtype = BOARDCFG
+ if self.file_yaml.get('sec-cfg') != None:
+ cfgtype = BOARDCFG_SEC
+ if self.file_yaml.get('pm-cfg') != None:
+ cfgtype = BOARDCFG_PM
+ if self.file_yaml.get('rm-cfg') != None:
+ cfgtype = BOARDCFG_RM
+
+ yaml_config = config.YamlLintConfig("extends: default")
+ for p in yamllint.linter.run(open(self._config_file, "r"), yaml_config):
+ self.Raise(f"Yamllint error: {p.line}: {p.rule}")
+ try:
+ validate(self.file_yaml, self.schema_yaml)
+ except Exception as e:
+ self.Raise(f"Schema validation error: {e}")
+
+ data = self._generate_binaries()
+ entry = cfgentry(cfgtype, data)
+ self.cfgentries.append(entry)
+ return data
+
+ def save(self, filename):
+ with open(filename, "wb") as binary_file:
+ binary_file.write(self.header)
+ for i in self.cfgentries:
+ obj._binary_offset += 8
+ for i in self.cfgentries:
+ binary_file.write(self._add_boardcfg(i.cfgtype, i.data))
+ for i in self.cfgentries:
+ binary_file.write(i.data)
+ binary_file.close()
+
+outfile = sys.argv[1]
+schema = sys.argv[2]
+
+obj = Entry_ti_board_config(schema)
+
+for i in sys.argv[3:]:
+ obj.add_data(i)
+
+obj.save(outfile)
--
2.39.5
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v3 18/23] ARM: k3: Add k3img tool
2025-01-13 11:26 [PATCH v3 00/23] ARM: K3: Add R5 boot support Sascha Hauer
` (15 preceding siblings ...)
2025-01-13 11:27 ` [PATCH v3 17/23] scripts: k3: add script to generate cfg files from yaml Sascha Hauer
@ 2025-01-13 11:27 ` Sascha Hauer
2025-01-13 11:27 ` [PATCH v3 19/23] ARM: beagleplay: add Cortex-R5 boot support Sascha Hauer
` (5 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Sascha Hauer @ 2025-01-13 11:27 UTC (permalink / raw)
To: open list:BAREBOX
The image format for the TI K3 SoCs is basically a x509 certificate
file. In U-Boot this image is generated with binman. This patch adds
a simple shell script using openssl directly. This is by far not so
sophisticated as the U-Boot variant, but is enough for now to get a
beagleplay up and running.
The keys in this patch are taken from U-Boot-2025.01-rc4.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-k3/custMpk.pem | 51 +++++++++
arch/arm/mach-k3/ti-degenerate-key.pem | 10 ++
images/.gitignore | 1 +
images/Makefile.k3 | 28 +++++
scripts/k3img | 187 +++++++++++++++++++++++++++++++++
5 files changed, 277 insertions(+)
diff --git a/arch/arm/mach-k3/custMpk.pem b/arch/arm/mach-k3/custMpk.pem
new file mode 100644
index 0000000000..adba378c80
--- /dev/null
+++ b/arch/arm/mach-k3/custMpk.pem
@@ -0,0 +1,51 @@
+-----BEGIN RSA PRIVATE KEY-----
+MIIJKQIBAAKCAgEAvxSuSdh/ctNrI83rSA5l3CJN8g5PgvbttfLd23yR+m5Z/9X3
+tt4EHYrM0pXZ0eDEwfhQv/9IDJEiUJpMe4vzlgooJrOk2eCpVUEa+z5bJ2y/ysBx
+ry9yIu5GASVirT7HBPaxGLYswBJuD+KbPuWmoKgGRQNBF04WH6l01oRO1nmnELgR
+qQ6SHyXdf7Hy0bnyaNgzWUuCfXfM0Zz6I7T7WIjyzerVFvIsdS36YsPBCW7gBnDg
+tQcJmWLZ1uTnbG3IggdQk/fi2O3RX+PQns+TVNlf3V3ON2DxqxSKBHtlp7p/30VF
+fEuhW65OxpQ9jE6H0pQ8pPOf2vzyNnznDa1aQjfxKoHQbqGnZwMeh+0Au3NKaCgx
+ooKaowTB6If/RX6qwZ/UOwXHg/0hcf69fzjJFhlSDuYDM40dHsk2HM1OnYIpiM2b
+Kr5sX3uysjp5AGp99a0anR7NWCrPXvROgKs7T9341N40osQg2VkZLYUCXh9osUyN
+uREG6S12tViMUKg3bmZ4b4MwRk00n7QYSrm7+nvFrtYyEISEbD+agDM1/E281W5g
+VFDPfm2AlwT6jwsg/b2YK6E3vVn9SuxFoQmLF8lyFDO3BV4SXeJaHc4hVPbh6tVV
+qifrTQnfGUCCLmaJF2XZbrPWOE6NYRbWdNTeFl9RGdVCuIPSyN5LqWmXto0CAwEA
+AQKCAgAzkAwcJ0z1GnId/lJQZno8NhGckRoJuEKbR8dwlCP8VUz6Ca5H7Y9kvXDa
+Hs/hn+rYgP6hYOz7XyrIX2rmJ/T6dxEwqGeC1+o59FConcIRWHpE5zuGT6JYJL5F
+TuZa48bm4v8VMQvQZOjIZpkIFwao8c6HTwKAnHTB5IN/48I2hCt+Cn3RhfoOZ7Rm
+4gkpaSkt+7GXlhXHb82YfujNO+hbktEamhUYlQ9EK70Wa8aqmf3gHxO0JgsEFjW8
+lJaSnultlTW8SDcx3LMUUjCYumECk4oX/VlJfmKYjPlVjkr3QQ+Cm3nNucb4K4hc
+c+JL+2ERhSj8RjXL7VgbNgdPnIjvQDJuTNqecTU8xWPYrkOLQpNibbLjnutLkhJz
+fMyRtmDtrsey8WiCDuCHkPJ8/f8RjL2zWI9fzTDDIzdlEKouUFGOovaHVnbua6pn
+hymcu9d9FV3p2rcbj0ivCs7e8j+vhSxFJEJoAbcQdXCTi/n2uR7pLtoMNiUzsejy
+d46Uz+KEU920NTwE2z6JJq8I2vegnxjc7PDDrV3/5rK04B93aXiqvwWseCpxelrI
+xaMkRHbXrIXRO6MXQ3N+zNq8Dg3hjGTTvaBKuwgvqLwlXY8+Aa3ooFzEOInIOSsI
+XcWqXxt/tgZgsj9RwpC42t8kbA+BkbNk9EIUa+P5kEr2P/fO7QKCAQEA4EtArnOX
+D6tQF8uTw8USOZC2P9s/ez1z4jRq3oKP0Kv4tJiuIObJ/dUvGVD7aM5v2xaCfhm8
+xpk09VPUgghfG5jR5qVvQr75kCNToJQudWi4ngk1HwKJzzTO11giFEdybvTUA+Pj
+fmxCM0dYYqRWZoj0hLqXlUCwxE74BFIhJVjeYbf+nTQrqpllTLoW7MTZHzGx5SXx
+4dNzyVAUH49Yt2D8mgXXCkf5sGLh762wj34b/rR10Kr4O5utGMZrfTRIbuQ1pNjU
+m66baPzq+mC0BzqZEW70TgEb7lOr8rcVXLOi3r36omfd9/MHx7iZD6o3K1axSO15
+grD4ZrN7Ac3QJwKCAQEA2heCoBdpvy6YUk8AO2k8qDygTdmPQRuwjjT+Z2fMslBt
+D7DkpKwZ6Bl9OclcpiiLHmH+hv65KqYg+tR0RRb7PcogB9El9x7yKkGTPZEYWGky
+n8P84rJpKwjnwWQvPQktI1cs3YGvZA9DQTFBavRrwuzgd1oSJq5aPQ2tme0kMvWp
+l1/B/cPK+PKCi/Wfisaze1TjijP9qIeUwkdNN6WLrLU3QgsGppcg2I7RQtAIikT6
+GkuiOQAvWMsrJVV6PNrVKz4fJDJ59Rz6jbDHZNi1MEYNxQoB/Pl7QIakbfjWpHLv
+8Ey7cB2JKxjQy8tmyl8WNQVbXbE6daPXcMTUmaRAKwKCAQBv1lYMJmq+T2eCVen6
+BbvOpE+bi5EdvEiaFBTtmiBnpjg+pJq+oRU60h/H+c9CNR0lGxY6Fk9An4f+g6xE
+ojP6KLsQzJCrsVny+wpp2TlJJcxYULMCIVvhy60PR0zG29E9biqBPhJjKUvhEcQK
+e3LxcXyq6fdHXphFajLUxLbuTl+kTgBRFoBnclFGbsubh5PTsA3J+p+fQLZNPPar
+veg4l82cZykQYU8pGkUaI3sUMYd3+zd7sqRP5JHs9pMGPRmY4YW2CsAIWIn5UZNB
+ARMDP76vKKn8cyUgMuxb+9pU/OVLN2NPs4bEaZQJjAwV+YPEwldny7F47xEM9JVz
+EtKlAoIBAQDUt62u3GdGE/p5/ZgqWoDRTyDEDfmN9aYFbmbdEP80xQE7FrxMaZhz
+K7laja6SWmUm40nQ/c45bQQp4uLtKHcxU15egX7YRBTLZl5o5IasZR79ebnEm2O8
+l9kEZeU1USf3mmWmP4GExOZCRfqaiYA6BbUCdJXTqKdXeWnkAssV8UrS3JFoJHpq
+yo7OWGqefyQ8nRW6jO9SW7uaqtUD+7H6aF5XSk3YWvusfdBZrHNH+fM/hpnZovaL
+Us7ogTDS/laA8PyK37jYfMVdQhmZoU1Iomt3zkUWK3gt/aWPpfAlQf4Jka4YspZB
+tNiijefaZ1hPqsPs5Joyd/YAhdsfaHc1AoIBAQCn/9j6RRjRaw0ip756oad4AXHz
+XBwVB2CrY96qT6Hj9Sq7tGgdskqGkOQkAivBLBizUdcWv0t1yenOsSgasQeMlvlh
+B8md9cLvpKXPB3HM3rTDH/xNXe0TpVKLf7SXC8HfDyIweHwMW3QgO2DWrvI4BV/T
+ckBatRNQ90HxkqGFhC/Mp529lQlyg3ifxPxJsvZOyPMUnrflAvsKQk5c2ZiQg3nZ
+h7I2pjSYgCl+Ib52l8p9bf1kcrVGgPM+auzm496i0RPobFeDBoBvSoznJktHJ7+3
+NnZH+jLiZCODiQPGtQUi+T6eIZUIJF0YASpsCCtUzXCxwW3lYIDNy7UlMivF
+-----END RSA PRIVATE KEY-----
diff --git a/arch/arm/mach-k3/ti-degenerate-key.pem b/arch/arm/mach-k3/ti-degenerate-key.pem
new file mode 100644
index 0000000000..bd7d3745ad
--- /dev/null
+++ b/arch/arm/mach-k3/ti-degenerate-key.pem
@@ -0,0 +1,10 @@
+-----BEGIN RSA PRIVATE KEY-----
+MIIBWwIBAAKBgQDRfrnXQaP0k6vRK/gZ+bDflSU6y1JagGeQ/b+QYuiDz14japog
+8fRSu5WBsAxaSaySAUwS3L9Ppw+hGMecmyIJ494aMfZTtk1g49gU58joduiRnu7e
+QSZHMnehhuNlfD7A2tAAKnxIYuabs8zHYM/SS9Ne7t3kIQMbKfUSzNy6qQIBAQIB
+AQJBAOelUA376o6w3HkShXfN+shaOZYqFuTJ9exLMwsLp7DZKXB5F9I4JJ+Vkvho
+k6QWs7vkhleLSYUZknXHYm26ZE0CQQDnhTtd4PTBoZPjPXOeYMJFtEdMNy0XP6ey
+bcce389ugoY7BEkvASrd8PHgJQHziepgWOG4DGp33c64Hfq4zI3NAgEBAgEBAkA0
+RbK4uqoLciQluesTPU6lBy7Se3Dw0F9xBqlF5SR4KI6q+zQrHpBKyFOofMHZgizR
+iCrL55cxEM146zMw3AnF
+-----END RSA PRIVATE KEY-----
diff --git a/images/.gitignore b/images/.gitignore
index ec31293766..8d5bd4a410 100644
--- a/images/.gitignore
+++ b/images/.gitignore
@@ -40,3 +40,4 @@ barebox.sum
*.itb
*.fit
*.missing-firmware
+*.k3img
diff --git a/images/Makefile.k3 b/images/Makefile.k3
index 7988defe79..ff35ddfa2e 100644
--- a/images/Makefile.k3
+++ b/images/Makefile.k3
@@ -3,6 +3,8 @@
# barebox image generation Makefile for K3 images
#
+ifdef CONFIG_MACH_K3_CORTEX_A
+
pblb-$(CONFIG_MACH_BEAGLEPLAY) += start_beagleplay
FILE_barebox-beagleplay.img = start_beagleplay.pblb
image-$(CONFIG_MACH_BEAGLEPLAY) += barebox-beagleplay.img
@@ -11,3 +13,29 @@ $(obj)/k3-am625-beagleplay.itb: $(obj)/barebox-beagleplay.img
FILE_barebox-beagleplay-fit.img = k3-am625-beagleplay.itb
image-$(CONFIG_MACH_BEAGLEPLAY) += barebox-beagleplay-fit.img
+endif
+
+ifdef CONFIG_MACH_K3_CORTEX_R5
+
+SYSFWDATA_am625=$(objtree)/arch/arm/mach-k3/combined-sysfw-cfg-am625.k3cfg
+DMDATA_am625=$(objtree)/arch/arm/mach-k3/combined-dm-cfg-am625.k3cfg
+SYSFW_am625_hs_fs=$(srctree)/firmware/ti-fs-firmware-am62x-hs-fs-enc.bin
+SYSFW_am625_gp=$(srctree)/firmware/ti-fs-firmware-am62x-hs-fs-enc.bin
+INNERDATA_am625=$(srctree)/firmware/ti-fs-firmware-am62x-hs-fs-cert.bin
+KEY_custmpk=$(srctree)/arch/arm/mach-k3/custMpk.pem
+KEY_degenerate=$(srctree)/arch/arm/mach-k3/ti-degenerate-key.pem
+
+endif
+
+quiet_cmd_k3_image = K3IMG $@
+ cmd_k3_image = \
+ if [ -n "$(INNERDATA_$(@F))" ]; then \
+ inner="--innerdata $(INNERDATA_$(@F))"; \
+ fi; \
+ \
+ $(srctree)/scripts/k3img --sysfw $(SYSFW_$(@F)) \
+ --sysfwdata $(SYSFWDATA_$(@F)) --dmdata $(DMDATA_$(@F)) \
+ --key $(KEY_$(@F)) $$inner --sbl $< --out $@
+
+$(obj)/%.k3img: $(obj)/% scripts/k3img FORCE
+ $(call if_changed,k3_image)
diff --git a/scripts/k3img b/scripts/k3img
new file mode 100755
index 0000000000..048da82b92
--- /dev/null
+++ b/scripts/k3img
@@ -0,0 +1,187 @@
+#!/bin/bash
+
+TEMP=$(getopt -o '' --long 'sysfw:,sysfwdata:,dmdata:,out:,sbl:,key:,innerdata:' -n 'k3img' -- "$@")
+
+if [ $? -ne 0 ]; then
+ echo 'Terminating...' >&2
+ exit 1
+fi
+
+# Note the quotes around "$TEMP": they are essential!
+eval set -- "$TEMP"
+unset TEMP
+
+while true; do
+ case "$1" in
+ '--sysfw')
+ sysfw="$2"
+ shift 2
+ continue
+ ;;
+ '--sysfwdata')
+ sysfwdata="$2"
+ shift 2
+ continue
+ ;;
+ '--sysfw')
+ sysfw="$2"
+ shift 2
+ continue
+ ;;
+ '--dmdata')
+ dmdata="$2"
+ shift 2
+ continue
+ ;;
+ '--out')
+ out="$2"
+ shift 2
+ continue
+ ;;
+ '--sbl')
+ sbl="$2"
+ shift 2
+ continue
+ ;;
+ '--key')
+ key="$2"
+ shift 2
+ continue
+ ;;
+ '--innerdata')
+ innerdata="$2"
+ shift 2
+ continue
+ ;;
+ '--')
+ shift
+ break
+ ;;
+ *)
+ echo 'Internal error!' >&2
+ exit 1
+ ;;
+ esac
+done
+
+shasbl=$(sha512sum $sbl | sed 's/ .*//')
+shasysfw=$(sha512sum $sysfw | sed 's/ .*//')
+shasysfwdata=$(sha512sum $sysfwdata | sed 's/ .*//')
+shadmdata=$(sha512sum $dmdata | sed 's/ .*//')
+
+sblsize=$(stat -c%s $sbl)
+sysfwsize=$(stat -c%s $sysfw)
+sysfwdatasize=$(stat -c%s $sysfwdata)
+dmdatasize=$(stat -c%s $dmdata)
+
+total=$(($sblsize + $sysfwsize + $sysfwdatasize + $dmdatasize))
+
+certcfg=$(mktemp k3img.XXXXXXX)
+cert=$(mktemp k3img.XXXXXXX)
+
+num_comp=4
+
+if [ -n "${innerdata}" ]; then
+ shainnerdata=$(sha512sum $innerdata | sed 's/ .*//')
+ innerdatasize=$(stat -c%s $innerdata)
+
+ innercert=$(cat <<EOF
+[sysfw_inner_cert]
+compType = INTEGER:3
+bootCore = INTEGER:0
+compOpts = INTEGER:0
+destAddr = FORMAT:HEX,OCT:00000000
+compSize = INTEGER:$innerdatasize
+shaType = OID:2.16.840.1.101.3.4.2.3
+shaValue = FORMAT:HEX,OCT:$shainnerdata
+EOF
+)
+
+ num_comp=$((num_comp + 1))
+ total=$((total + innerdatasize))
+ sysfw_inner_cert="sysfw_inner_cert=SEQUENCE:sysfw_inner_cert"
+fi
+
+cat > $certcfg <<EndOfHereDocument
+[ req ]
+distinguished_name = req_distinguished_name
+x509_extensions = v3_ca
+prompt = no
+dirstring_type = nobmp
+
+[ req_distinguished_name ]
+C = US
+ST = TX
+L = Dallas
+O = Texas Instruments Incorporated
+OU = Processors
+CN = TI Support
+emailAddress = support@ti.com
+
+[ v3_ca ]
+basicConstraints = CA:true
+1.3.6.1.4.1.294.1.3=ASN1:SEQUENCE:swrv
+1.3.6.1.4.1.294.1.9=ASN1:SEQUENCE:ext_boot_info
+1.3.6.1.4.1.294.1.8=ASN1:SEQUENCE:debug
+
+[swrv]
+swrv=INTEGER:1
+
+[ext_boot_info]
+extImgSize=INTEGER:$total
+numComp=INTEGER:$num_comp
+sbl=SEQUENCE:sbl
+sysfw=SEQUENCE:sysfw
+sysfw_data=SEQUENCE:sysfw_data
+$sysfw_inner_cert
+dm_data=SEQUENCE:dm_data
+
+[sbl]
+compType = INTEGER:1
+bootCore = INTEGER:16
+compOpts = INTEGER:0
+destAddr = FORMAT:HEX,OCT:43c00000
+compSize = INTEGER:$sblsize
+shaType = OID:2.16.840.1.101.3.4.2.3
+shaValue = FORMAT:HEX,OCT:$shasbl
+
+[sysfw]
+compType = INTEGER:2
+bootCore = INTEGER:0
+compOpts = INTEGER:0
+destAddr = FORMAT:HEX,OCT:00040000
+compSize = INTEGER:$sysfwsize
+shaType = OID:2.16.840.1.101.3.4.2.3
+shaValue = FORMAT:HEX,OCT:$shasysfw
+
+[sysfw_data]
+compType = INTEGER:18
+bootCore = INTEGER:0
+compOpts = INTEGER:0
+destAddr = FORMAT:HEX,OCT:00067000
+compSize = INTEGER:$sysfwdatasize
+shaType = OID:2.16.840.1.101.3.4.2.3
+shaValue = FORMAT:HEX,OCT:$shasysfwdata
+
+[ debug ]
+debugUID = FORMAT:HEX,OCT:0000000000000000000000000000000000000000000000000000000000000000
+debugType = INTEGER:4
+coreDbgEn = INTEGER:0
+coreDbgSecEn = INTEGER:0
+
+$innercert
+
+[dm_data]
+compType = INTEGER:17
+bootCore = INTEGER:16
+compOpts = INTEGER:0
+destAddr = FORMAT:HEX,OCT:43c3a800
+compSize = INTEGER:$dmdatasize
+shaType = OID:2.16.840.1.101.3.4.2.3
+shaValue = FORMAT:HEX,OCT:$shadmdata
+
+EndOfHereDocument
+
+openssl req -new -x509 -key $key -nodes -outform DER -out $cert -config $certcfg -sha512
+
+cat $cert $sbl $sysfw $sysfwdata $innerdata $dmdata > $out
--
2.39.5
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v3 19/23] ARM: beagleplay: add Cortex-R5 boot support
2025-01-13 11:26 [PATCH v3 00/23] ARM: K3: Add R5 boot support Sascha Hauer
` (16 preceding siblings ...)
2025-01-13 11:27 ` [PATCH v3 18/23] ARM: k3: Add k3img tool Sascha Hauer
@ 2025-01-13 11:27 ` Sascha Hauer
2025-01-13 11:27 ` [PATCH v3 20/23] Documentation: add build documentation for TI K3 SoCs Sascha Hauer
` (4 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Sascha Hauer @ 2025-01-13 11:27 UTC (permalink / raw)
To: open list:BAREBOX
This adds a new image for the beagleplay board for running on the
Cortex-R5 boot processor. It will setup the SDRAM and load and start
the following stages from the boot medium.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/beagleplay/Makefile | 4 +-
arch/arm/boards/beagleplay/ddr.c | 586 ++++++++++++++++++++++++++++++++
arch/arm/boards/beagleplay/ddr.h | 6 +
arch/arm/boards/beagleplay/entry-r5.S | 18 +
arch/arm/boards/beagleplay/lowlevel.c | 38 +++
arch/arm/dts/Makefile | 2 +-
arch/arm/dts/k3-am625-r5-beagleplay.dts | 4 +
images/Makefile.k3 | 11 +
8 files changed, 667 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boards/beagleplay/Makefile b/arch/arm/boards/beagleplay/Makefile
index 69935cc168..396dff29a2 100644
--- a/arch/arm/boards/beagleplay/Makefile
+++ b/arch/arm/boards/beagleplay/Makefile
@@ -1 +1,3 @@
-pbl-y += lowlevel.o entry.o
+pbl-y += lowlevel.o
+pbl-$(CONFIG_MACH_K3_CORTEX_A) += entry.o
+pbl-$(CONFIG_MACH_K3_CORTEX_R5) += entry-r5.o ddr.o
diff --git a/arch/arm/boards/beagleplay/ddr.c b/arch/arm/boards/beagleplay/ddr.c
new file mode 100644
index 0000000000..3f8b36026a
--- /dev/null
+++ b/arch/arm/boards/beagleplay/ddr.c
@@ -0,0 +1,586 @@
+#include <soc/k3/ddr.h>
+
+#include "ddr.h"
+
+#define DDRSS_CTL_REG_INIT_COUNT (423U)
+#define DDRSS_PHY_INDEP_REG_INIT_COUNT (345U)
+#define DDRSS_PHY_REG_INIT_COUNT (1406U)
+
+static uint32_t DDRSS_ctlReg[] = {
+ 0x00000a00, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x000890b8,
+ 0x00000000, 0x00000000, 0x00000000, 0x000890b8,
+ 0x00000000, 0x00000000, 0x00000000, 0x000890b8,
+ 0x00000000, 0x00000000, 0x00000000, 0x01010100,
+ 0x01000100, 0x01000110, 0x02010002, 0x00027100,
+ 0x00061a80, 0x04000400, 0x00000400, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x0400091c, 0x1c1c1c1c,
+ 0x0400091c, 0x1c1c1c1c, 0x0400091c, 0x1c1c1c1c,
+ 0x05050404, 0x00002706, 0x0602001d, 0x05001d0b,
+ 0x00270605, 0x0602001d, 0x05001d0b, 0x00270605,
+ 0x0602001d, 0x07001d0b, 0x00180807, 0x0400db60,
+ 0x07070009, 0x00001808, 0x0400db60, 0x07070009,
+ 0x00001808, 0x0400db60, 0x03000009, 0x0d0c0002,
+ 0x0d0c0d0c, 0x01010000, 0x03191919, 0x0b0b0b0b,
+ 0x00000b0b, 0x00000101, 0x00000000, 0x01000000,
+ 0x01180803, 0x00001860, 0x00000118, 0x00001860,
+ 0x00000118, 0x00001860, 0x00000005, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00090009,
+ 0x00000009, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00010001, 0x00040001,
+ 0x04000120, 0x04000120, 0x01200120, 0x01200120,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x03010000, 0x00010000,
+ 0x00000000, 0x01000000, 0x80104002, 0x00040003,
+ 0x00040005, 0x00030000, 0x00050004, 0x00000004,
+ 0x00040003, 0x00040005, 0x00000000, 0x00061800,
+ 0x00061800, 0x00061800, 0x00061800, 0x00061800,
+ 0x00000000, 0x0000aaa0, 0x00061800, 0x00061800,
+ 0x00061800, 0x00061800, 0x00061800, 0x00000000,
+ 0x0000aaa0, 0x00061800, 0x00061800, 0x00061800,
+ 0x00061800, 0x00061800, 0x00000000, 0x0000aaa0,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x080c0000, 0x080c080c, 0x08000000, 0x00000808,
+ 0x000e0000, 0x00080808, 0x0e000000, 0x08080800,
+ 0x00000000, 0x0000080e, 0x00040003, 0x00000007,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x01000000, 0x00000000,
+ 0x00001500, 0x0000100e, 0x00000000, 0x00000000,
+ 0x00000001, 0x00000002, 0x00000c00, 0x00001000,
+ 0x00000c00, 0x00001000, 0x00000c00, 0x00001000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00042400, 0x00000301, 0x00000000, 0x00000424,
+ 0x00000301, 0x00000000, 0x00000424, 0x00000301,
+ 0x00000000, 0x00000424, 0x00000301, 0x00000000,
+ 0x00000424, 0x00000301, 0x00000000, 0x00000424,
+ 0x00000301, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00001401, 0x00001401, 0x00001401, 0x00001401,
+ 0x00001401, 0x00001401, 0x00000493, 0x00000493,
+ 0x00000493, 0x00000493, 0x00000493, 0x00000493,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00010000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000101, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x0c181511, 0x00000304,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00040000, 0x00800200, 0x00000000,
+ 0x02000400, 0x00000080, 0x00040000, 0x00800200,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000100,
+ 0x01010000, 0x00000000, 0x3fff0000, 0x000fff00,
+ 0xffffffff, 0x00ffff00, 0x0a000000, 0x0001ffff,
+ 0x01010101, 0x01010101, 0x00000118, 0x00000c01,
+ 0x00000000, 0x00000000, 0x00000000, 0x01000000,
+ 0x00000100, 0x00010000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x0c000000, 0x060c0606,
+ 0x06060c06, 0x00010101, 0x02000000, 0x05020101,
+ 0x00000505, 0x02020200, 0x02020202, 0x02020202,
+ 0x02020202, 0x00000000, 0x00000000, 0x04000100,
+ 0x1e000004, 0x000030c0, 0x00000200, 0x00000200,
+ 0x00000200, 0x00000200, 0x0000db60, 0x0001e780,
+ 0x0c0d0302, 0x001e090a, 0x000030c0, 0x00000200,
+ 0x00000200, 0x00000200, 0x00000200, 0x0000db60,
+ 0x0001e780, 0x0c0d0302, 0x001e090a, 0x000030c0,
+ 0x00000200, 0x00000200, 0x00000200, 0x00000200,
+ 0x0000db60, 0x0001e780, 0x0c0d0302, 0x0000090a,
+ 0x00000000, 0x0302000a, 0x01000500, 0x01010001,
+ 0x00010001, 0x01010001, 0x02010000, 0x00000200,
+ 0x02000201, 0x00000000, 0x00202020
+};
+
+static uint32_t DDRSS_phyIndepReg[] = {
+ 0x00000a00, 0x00000000, 0x00000000, 0x01000000,
+ 0x00000001, 0x00010064, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00010001, 0x00000000, 0x00010001,
+ 0x00000005, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x280d0001, 0x00000000, 0x00010000, 0x00003200,
+ 0x00000000, 0x00000000, 0x00060602, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000001, 0x00000055,
+ 0x000000aa, 0x000000ad, 0x00000052, 0x0000006a,
+ 0x00000095, 0x00000095, 0x000000ad, 0x00000000,
+ 0x00000000, 0x00010100, 0x00000014, 0x000007d0,
+ 0x00000300, 0x00000000, 0x00000000, 0x01000000,
+ 0x00010101, 0x01000000, 0x00000000, 0x00010000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00001400, 0x00000000, 0x01000000, 0x00000404,
+ 0x00000001, 0x0001010e, 0x02040100, 0x00010000,
+ 0x00000034, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000005,
+ 0x01000000, 0x04000100, 0x00020000, 0x00010002,
+ 0x00000001, 0x00020001, 0x00020002, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000300,
+ 0x0a090b0c, 0x04060708, 0x01000005, 0x00000800,
+ 0x00000000, 0x00010008, 0x00000000, 0x0000aa00,
+ 0x00000000, 0x00010000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000008, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00010100, 0x00000000, 0x00000000,
+ 0x00027100, 0x00061a80, 0x00000100, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x01000000, 0x00010003, 0x02000101, 0x01030001,
+ 0x00010400, 0x06000105, 0x01070001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00010000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00010000,
+ 0x00000004, 0x00000000, 0x00000000, 0x00000000,
+ 0x00007800, 0x00780078, 0x00141414, 0x0000003a,
+ 0x0000003a, 0x0004003a, 0x04000400, 0xc8040009,
+ 0x0400091c, 0x00091cc8, 0x001cc804, 0x00000118,
+ 0x00001860, 0x00000118, 0x00001860, 0x00000118,
+ 0x04001860, 0x01010404, 0x00001901, 0x00190019,
+ 0x010c010c, 0x0000010c, 0x00000000, 0x05000000,
+ 0x01010505, 0x01010101, 0x00181818, 0x00000000,
+ 0x00000000, 0x0d000000, 0x0a0a0d0d, 0x0303030a,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x0d090000, 0x0d09000d, 0x0d09000d,
+ 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x16000000, 0x001600c8, 0x001600c8,
+ 0x010100c8, 0x00001b01, 0x1f0f0053, 0x05000001,
+ 0x001b0a0d, 0x1f0f0053, 0x05000001, 0x001b0a0d,
+ 0x1f0f0053, 0x05000001, 0x00010a0d, 0x0c0b0700,
+ 0x000d0605, 0x0000c570, 0x0000001d, 0x180a0800,
+ 0x0b071c1c, 0x0d06050c, 0x0000c570, 0x0000001d,
+ 0x180a0800, 0x0b071c1c, 0x0d06050c, 0x0000c570,
+ 0x0000001d, 0x180a0800, 0x00001c1c, 0x000030c0,
+ 0x0001e780, 0x000030c0, 0x0001e780, 0x000030c0,
+ 0x0001e780, 0x04000400, 0x03030400, 0x00040003,
+ 0x04000400, 0x0c080c08, 0x00000c08, 0x000890b8,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000120,
+ 0x000890b8, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000120, 0x000890b8, 0x00000000, 0x00000000,
+ 0x00000000, 0x02000120, 0x00000080, 0x00020000,
+ 0x00000080, 0x00020000, 0x00000080, 0x00000000,
+ 0x00000000, 0x00040404, 0x00000000, 0x02010102,
+ 0x67676767, 0x00000202, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x0d100f00,
+ 0x0003020e, 0x00000001, 0x01000000, 0x00020201,
+ 0x00000000, 0x00000424, 0x00000301, 0x00000000,
+ 0x00000000, 0x00000000, 0x00001401, 0x00000493,
+ 0x00000000, 0x00000424, 0x00000301, 0x00000000,
+ 0x00000000, 0x00000000, 0x00001401, 0x00000493,
+ 0x00000000, 0x00000424, 0x00000301, 0x00000000,
+ 0x00000000, 0x00000000, 0x00001401, 0x00000493,
+ 0x00000000, 0x00000424, 0x00000301, 0x00000000,
+ 0x00000000, 0x00000000, 0x00001401, 0x00000493,
+ 0x00000000, 0x00000424, 0x00000301, 0x00000000,
+ 0x00000000, 0x00000000, 0x00001401, 0x00000493,
+ 0x00000000, 0x00000424, 0x00000301, 0x00000000,
+ 0x00000000, 0x00000000, 0x00001401, 0x00000493,
+ 0x00000000
+};
+
+static uint32_t DDRSS_phyReg[] = {
+ 0x04c00000, 0x00000000, 0x00000200, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000001, 0x00000000, 0x00000000, 0x010101ff,
+ 0x00010000, 0x00c00004, 0x00cc0008, 0x00660201,
+ 0x00000000, 0x00000000, 0x00000000, 0x0000aaaa,
+ 0x00005555, 0x0000b5b5, 0x00004a4a, 0x00005656,
+ 0x0000a9a9, 0x0000b7b7, 0x00004848, 0x00000000,
+ 0x00000000, 0x08000000, 0x0f000008, 0x00000f0f,
+ 0x00e4e400, 0x00070820, 0x000c0020, 0x00062000,
+ 0x00000000, 0x55555555, 0xaaaaaaaa, 0x55555555,
+ 0xaaaaaaaa, 0x00005555, 0x01000100, 0x00800180,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000004, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x041f07ff, 0x00000000, 0x01ccb001, 0x2000ccb0,
+ 0x20000140, 0x07ff0200, 0x0000dd01, 0x10100303,
+ 0x10101010, 0x10101010, 0x00021010, 0x00100010,
+ 0x00100010, 0x00100010, 0x00100010, 0x02020010,
+ 0x51515041, 0x31804000, 0x04bf0340, 0x01008080,
+ 0x04050001, 0x00000504, 0x42100010, 0x010c053e,
+ 0x000f0c14, 0x01000140, 0x007a0120, 0x00000c00,
+ 0x000001cc, 0x20100200, 0x00000005, 0x76543210,
+ 0x00000008, 0x02800280, 0x02800280, 0x02800280,
+ 0x02800280, 0x00000280, 0x00008000, 0x00800080,
+ 0x00800080, 0x00800080, 0x00800080, 0x00800080,
+ 0x00800080, 0x00800080, 0x00800080, 0x01000080,
+ 0x01000000, 0x00000000, 0x00000000, 0x00080200,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x04c00000, 0x00000000, 0x00000200, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000001, 0x00000000, 0x00000000, 0x010101ff,
+ 0x00010000, 0x00c00004, 0x00cc0008, 0x00660201,
+ 0x00000000, 0x00000000, 0x00000000, 0x0000aaaa,
+ 0x00005555, 0x0000b5b5, 0x00004a4a, 0x00005656,
+ 0x0000a9a9, 0x0000b7b7, 0x00004848, 0x00000000,
+ 0x00000000, 0x08000000, 0x0f000008, 0x00000f0f,
+ 0x00e4e400, 0x00070820, 0x000c0020, 0x00062000,
+ 0x00000000, 0x55555555, 0xaaaaaaaa, 0x55555555,
+ 0xaaaaaaaa, 0x00005555, 0x01000100, 0x00800180,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000004, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x041f07ff, 0x00000000, 0x01ccb001, 0x2000ccb0,
+ 0x20000140, 0x07ff0200, 0x0000dd01, 0x10100303,
+ 0x10101010, 0x10101010, 0x00021010, 0x00100010,
+ 0x00100010, 0x00100010, 0x00100010, 0x02020010,
+ 0x51515041, 0x31804000, 0x04bf0340, 0x01008080,
+ 0x04050001, 0x00000504, 0x42100010, 0x010c053e,
+ 0x000f0c14, 0x01000140, 0x007a0120, 0x00000c00,
+ 0x000001cc, 0x20100200, 0x00000005, 0x76543210,
+ 0x00000008, 0x02800280, 0x02800280, 0x02800280,
+ 0x02800280, 0x00000280, 0x00008000, 0x00800080,
+ 0x00800080, 0x00800080, 0x00800080, 0x00800080,
+ 0x00800080, 0x00800080, 0x00800080, 0x01000080,
+ 0x01000000, 0x00000000, 0x00000000, 0x00080200,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000100, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000100, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00dcba98, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x0a418820, 0x103f0000, 0x000f0100, 0x0000000f,
+ 0x020002cc, 0x00030000, 0x00000300, 0x00000300,
+ 0x00000300, 0x00000300, 0x00000300, 0x42080010,
+ 0x0000003e, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000100, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000100, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00dcba98, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x16a4a0e6, 0x103f0000, 0x000f0000, 0x0000000f,
+ 0x020002cc, 0x00030000, 0x00000300, 0x00000300,
+ 0x00000300, 0x00000300, 0x00000300, 0x42080010,
+ 0x0000003e, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000100, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000100, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00dcba98, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x2307b9ac, 0x10030000, 0x000f0000, 0x0000000f,
+ 0x020002cc, 0x00030000, 0x00000300, 0x00000300,
+ 0x00000300, 0x00000300, 0x00000300, 0x42080010,
+ 0x0000003e, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000100, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00050000, 0x04000100,
+ 0x00000055, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x01002000, 0x00004001, 0x00020028,
+ 0x00010100, 0x00000001, 0x00000000, 0x0f0f0e06,
+ 0x00010101, 0x010f0004, 0x00000000, 0x00000000,
+ 0x00000064, 0x00000000, 0x00000000, 0x01020103,
+ 0x0f020102, 0x03030303, 0x03030303, 0x00040000,
+ 0x00004201, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x07070001,
+ 0x00005400, 0x000040a2, 0x00024410, 0x00004410,
+ 0x00004410, 0x00004410, 0x00004410, 0x00004410,
+ 0x00004410, 0x00004410, 0x00004410, 0x00004410,
+ 0x00000000, 0x00000046, 0x00000400, 0x00000008,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x03000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x04102006, 0x00041020, 0x01c98c98,
+ 0x3f400000, 0x3f3f1f3f, 0x0000001f, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x76543210,
+ 0x00000098, 0x00000000, 0x00000000, 0x00000000,
+ 0x00040700, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000002, 0x00000100, 0x00000000, 0x00000fc3,
+ 0x00020002, 0x00000000, 0x00001142, 0x03020400,
+ 0x00000080, 0x03900390, 0x03900390, 0x03900390,
+ 0x03900390, 0x03900390, 0x03900390, 0x00000300,
+ 0x00000300, 0x00000300, 0x00000300, 0x31823fc7,
+ 0x00000000, 0x0c000d3f, 0x30000d3f, 0x300d3f11,
+ 0x01990000, 0x000d3fcc, 0x00000c11, 0x300d3f11,
+ 0x01990000, 0x300c3f11, 0x01990000, 0x300c3f11,
+ 0x01990000, 0x300d3f11, 0x01990000, 0x300d3f11
+};
+
+static struct reginitdata ctl_regs = {
+ .regs = DDRSS_ctlReg,
+ .num = DDRSS_CTL_REG_INIT_COUNT,
+};
+
+static struct reginitdata pi_regs = {
+ .regs = DDRSS_phyIndepReg,
+ .num = DDRSS_PHY_INDEP_REG_INIT_COUNT,
+};
+
+static struct reginitdata phy_regs = {
+ .regs = DDRSS_phyReg,
+ .num = DDRSS_PHY_REG_INIT_COUNT,
+};
+
+static struct k3_ddr_initdata initdata = {
+ .ctl_regs = &ctl_regs,
+ .pi_regs = &pi_regs,
+ .phy_regs = &phy_regs,
+};
+
+void beagleplay_ddr_init(void)
+{
+ k3_ddrss_init(&initdata);
+}
diff --git a/arch/arm/boards/beagleplay/ddr.h b/arch/arm/boards/beagleplay/ddr.h
new file mode 100644
index 0000000000..8f35c03ed4
--- /dev/null
+++ b/arch/arm/boards/beagleplay/ddr.h
@@ -0,0 +1,6 @@
+#ifndef __BEAGLEPLAY_DDR_H
+#define __BEAGLEPLAY_DDR_H
+
+void beagleplay_ddr_init(void);
+
+#endif /* __BEAGLEPLAY_DDR_H */
diff --git a/arch/arm/boards/beagleplay/entry-r5.S b/arch/arm/boards/beagleplay/entry-r5.S
new file mode 100644
index 0000000000..712f0f4b8c
--- /dev/null
+++ b/arch/arm/boards/beagleplay/entry-r5.S
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <linux/linkage.h>
+
+#define SRAM_BASE 0x43c00000
+
+#define STACK_TOP SRAM_BASE + 0x3d000
+
+.arm
+.section .text_head_entry_start_beagleplay_r5;
+
+ENTRY(start_beagleplay_r5)
+ ldr r3, =STACK_TOP
+ mov sp, r3
+ ldr pc, _reset
+
+_reset: .word SRAM_BASE + beagleplay_r5_entry
+
+ENDPROC(start_beagleplay_r5)
diff --git a/arch/arm/boards/beagleplay/lowlevel.c b/arch/arm/boards/beagleplay/lowlevel.c
index 228484bf4e..744f78d009 100644
--- a/arch/arm/boards/beagleplay/lowlevel.c
+++ b/arch/arm/boards/beagleplay/lowlevel.c
@@ -3,10 +3,15 @@
#include <common.h>
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
+#include <mach/k3/debug_ll.h>
#include <debug_ll.h>
#include <pbl.h>
#include <pbl/handoff-data.h>
#include <compressed-dtb.h>
+#include <cache.h>
+#include <mach/k3/r5.h>
+
+#include "ddr.h"
/* Called from assembly */
void beagleplay(void *dtb);
@@ -37,3 +42,36 @@ void beagleplay(void *dtb)
beagleplay_continue(dtb);
}
+
+extern char __dtb_k3_am625_r5_beagleplay_start[];
+
+static noinline void beagleplay_r5_continue(void)
+{
+ pbl_set_putc((void *)debug_ll_ns16550_putc, (void *)AM62X_UART_UART0_BASE);
+
+ putc_ll('>');
+
+ k3_mpu_setup_regions();
+
+ am625_early_init();
+ beagleplay_ddr_init();
+
+ barebox_arm_entry(0x80000000, 0x80000000, __dtb_k3_am625_r5_beagleplay_start);
+}
+
+void beagleplay_r5_entry(void);
+
+void beagleplay_r5_entry(void)
+{
+ k3_ctrl_mmr_unlock();
+
+ writel(0x00050000, 0xf41c8);
+ writel(0x00010000, 0xf41cc);
+
+ k3_debug_ll_init((void *)AM62X_UART_UART0_BASE);
+
+ relocate_to_current_adr();
+ setup_c();
+
+ beagleplay_r5_continue();
+}
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b1c73b47aa..2352b6ef09 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -7,7 +7,7 @@ obj- += dummy.o
lwl-$(CONFIG_MACH_ADVANTECH_ROM_742X) += imx6dl-advantech-rom-7421.dtb.o
lwl-$(CONFIG_MACH_AFI_GF) += am335x-afi-gf.dtb.o
lwl-$(CONFIG_MACH_BEAGLEBONE) += am335x-bone.dtb.o am335x-boneblack.dtb.o am335x-bone-common.dtb.o
-lwl-$(CONFIG_MACH_BEAGLEPLAY) += k3-am625-beagleplay.dtb.o
+lwl-$(CONFIG_MACH_BEAGLEPLAY) += k3-am625-beagleplay.dtb.o k3-am625-r5-beagleplay.dtb.o
lwl-$(CONFIG_MACH_CLEP7212) += ep7212-clep7212.dtb.o
lwl-$(CONFIG_MACH_CM_FX6) += imx6dl-cm-fx6.dtb.o imx6q-cm-fx6.dtb.o imx6q-utilite.dtb.o
lwl-$(CONFIG_MACH_DFI_FS700_M60) += imx6q-dfi-fs700-m60-6q.dtb.o imx6dl-dfi-fs700-m60-6s.dtb.o
diff --git a/arch/arm/dts/k3-am625-r5-beagleplay.dts b/arch/arm/dts/k3-am625-r5-beagleplay.dts
new file mode 100644
index 0000000000..49649acc3e
--- /dev/null
+++ b/arch/arm/dts/k3-am625-r5-beagleplay.dts
@@ -0,0 +1,4 @@
+/dts-v1/;
+
+#include "k3-am625-beagleplay.dts"
+#include "k3-am625-r5.dtsi"
diff --git a/images/Makefile.k3 b/images/Makefile.k3
index ff35ddfa2e..6ca0851e1a 100644
--- a/images/Makefile.k3
+++ b/images/Makefile.k3
@@ -5,6 +5,7 @@
ifdef CONFIG_MACH_K3_CORTEX_A
+## BeaglePlay ##
pblb-$(CONFIG_MACH_BEAGLEPLAY) += start_beagleplay
FILE_barebox-beagleplay.img = start_beagleplay.pblb
image-$(CONFIG_MACH_BEAGLEPLAY) += barebox-beagleplay.img
@@ -25,6 +26,16 @@ INNERDATA_am625=$(srctree)/firmware/ti-fs-firmware-am62x-hs-fs-cert.bin
KEY_custmpk=$(srctree)/arch/arm/mach-k3/custMpk.pem
KEY_degenerate=$(srctree)/arch/arm/mach-k3/ti-degenerate-key.pem
+## BeaglePlay ##
+SYSFW_start_beagleplay_r5.pblb.k3img=$(SYSFW_am625_gp)
+SYSFWDATA_start_beagleplay_r5.pblb.k3img=$(SYSFWDATA_am625)
+DMDATA_start_beagleplay_r5.pblb.k3img=$(DMDATA_am625)
+KEY_start_beagleplay_r5.pblb.k3img=$(KEY_degenerate)
+
+pblb-$(CONFIG_MACH_BEAGLEPLAY) += start_beagleplay_r5
+FILE_barebox-beagleplay-r5.img = start_beagleplay_r5.pblb.k3img
+image-$(CONFIG_MACH_BEAGLEPLAY) += barebox-beagleplay-r5.img
+
endif
quiet_cmd_k3_image = K3IMG $@
--
2.39.5
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v3 20/23] Documentation: add build documentation for TI K3 SoCs
2025-01-13 11:26 [PATCH v3 00/23] ARM: K3: Add R5 boot support Sascha Hauer
` (17 preceding siblings ...)
2025-01-13 11:27 ` [PATCH v3 19/23] ARM: beagleplay: add Cortex-R5 boot support Sascha Hauer
@ 2025-01-13 11:27 ` Sascha Hauer
2025-01-13 11:27 ` [PATCH v3 21/23] ARM: am625: disable secondary watchdogs Sascha Hauer
` (3 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Sascha Hauer @ 2025-01-13 11:27 UTC (permalink / raw)
To: open list:BAREBOX
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
Documentation/boards/ti-k3.rst | 79 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 79 insertions(+)
diff --git a/Documentation/boards/ti-k3.rst b/Documentation/boards/ti-k3.rst
new file mode 100644
index 0000000000..a1bf0b92e8
--- /dev/null
+++ b/Documentation/boards/ti-k3.rst
@@ -0,0 +1,79 @@
+TI K3 based boards
+==================
+
+The TI K3 is a line of 64-bit ARM SoCs.
+
+The boot process of the TI K3 SoCs is a two step process. The first stage boot loader
+is loaded by the ROM code and executed on a Cortex-R5 processor. The code on this
+processor is responsible for setting up the initial clocks, power domains and DRAM.
+It then loads the binaries for the A53 cores into DRAM and starts the A53 core. From
+this point on the Cortex-R5 processor is used as a system controller which controls
+clocks and power domains of the SoC.
+
+Prerequisites
+-------------
+
+There are several binary blobs required for building barebox for TI K3 SoCs. Find them
+in git://git.ti.com/processor-firmware/ti-linux-firmware.git. The repository is assumed
+to be checked out at ``$TI_LINUX_FIRMWARE``. The K3 SoCs boot from a FAT partition on
+SD/eMMC cards. During the next steps the files are copied to ``$TI_BOOT``. This is assumed
+to be an empty directory. After the build process copy its contents to a FAT filesystem
+on an SD/eMMC card.
+
+The Cortex-R5 is a 32-bit processors whereas the Cortex-A53 are 64-bit processors, so
+both 32-bit and 64-bit toolchains are needed::
+
+ export CROSS_COMPILE_32=arm-linux-gnueabihf-
+ export CROSS_COMPILE_64=aarch64-v8a-linux-gnu-
+
+Building barebox for the Cortex-R5 processor
+--------------------------------------------
+
+The following assumes barebox is built for a BeaglePlay board. The exact filenames
+need to be adjusted for other boards.
+
+There's a single ``k3-r5_defconfig`` for all K3 boards. This builds the boot images
+for the Cortex-R5 processors::
+
+ cp $TI_LINUX_FIRMWARE/ti-linux-firmware/ti-sysfw/ti-fs-firmware-am62x-gp.bin firmware/
+ export ARCH=arm CROSS_COMPILE=$CROSS_COMPILE_32
+ make k3-r5_defconfig
+ make
+ cp images/barebox-beagleplay-r5.img $TI_BOOT/tiboot3.bin
+
+Building barebox for the Cortex-A53 processors
+----------------------------------------------
+
+The BeaglePlay image is built as part of the ``multi_v8_defconfig``::
+
+ export ARCH=arm CROSS_COMPILE=CROSS_COMPILE_64
+ make multi_v8_defconfig
+ make
+ cp images/barebox-beagleplay.img $TI_BOOT/barebox.bin
+
+Building TF-A
+-------------
+
+The Arm Trusted Firmware is built from https://github.com/ARM-software/arm-trusted-firmware.git::
+
+ make CROSS_COMPILE=$CROSS_COMPILE_64 ARCH=aarch64 PLAT=k3 SPD=opteed \
+ TARGET_BOARD=lite
+ cp build/k3/lite/release/bl31.bin $TI_BOOT/bl31.bin
+
+Bulding OP-TEE
+--------------
+
+OP-TEE is built from https://github.com/OP-TEE/optee_os.git::
+
+ make CROSS_COMPILE64=$CC64 CFG_ARM64_core=y CFG_WITH_SOFTWARE_PRNG=y \
+ PLATFORM=k3-am62x
+ cp out/arm-plat-k3/core/tee-raw.bin $TI_BOOT/optee.bin
+
+Copying ti-dm.bin
+-----------------
+
+The ``ti-dm.bin`` binary is part of ti-linux-firmware.git, this needs to be
+copied to the eMMC/SD as well::
+
+ cp $TI_LINUX_FIRMWARE/ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f $TI_BOOT/ti-dm.bin
+
--
2.39.5
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v3 21/23] ARM: am625: disable secondary watchdogs
2025-01-13 11:26 [PATCH v3 00/23] ARM: K3: Add R5 boot support Sascha Hauer
` (18 preceding siblings ...)
2025-01-13 11:27 ` [PATCH v3 20/23] Documentation: add build documentation for TI K3 SoCs Sascha Hauer
@ 2025-01-13 11:27 ` Sascha Hauer
2025-01-13 11:27 ` [PATCH v3 22/23] ARM: k3: Add DRAM size detection Sascha Hauer
` (2 subsequent siblings)
22 siblings, 0 replies; 26+ messages in thread
From: Sascha Hauer @ 2025-01-13 11:27 UTC (permalink / raw)
To: open list:BAREBOX
The main_rti* watchdogs seem to be related to the secondary CPUs.
Letting the driver probe means the associated power domains are
turned on in barebox. With the power domains being enabled the
secondary CPUs do not come up under Linux. Just disable the watchdogs
for barebox.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/dts/k3-am625.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/dts/k3-am625.dtsi b/arch/arm/dts/k3-am625.dtsi
index 7d49198aa2..7910cf3e6c 100644
--- a/arch/arm/dts/k3-am625.dtsi
+++ b/arch/arm/dts/k3-am625.dtsi
@@ -11,3 +11,18 @@ &phy_gmii_sel {
compatible = "ti,am654-phy-gmii-sel", "syscon";
};
+&main_rti1 {
+ status = "disabled";
+};
+
+&main_rti2 {
+ status = "disabled";
+};
+
+&main_rti3 {
+ status = "disabled";
+};
+
+&main_rti15 {
+ status = "disabled";
+};
--
2.39.5
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v3 22/23] ARM: k3: Add DRAM size detection
2025-01-13 11:26 [PATCH v3 00/23] ARM: K3: Add R5 boot support Sascha Hauer
` (19 preceding siblings ...)
2025-01-13 11:27 ` [PATCH v3 21/23] ARM: am625: disable secondary watchdogs Sascha Hauer
@ 2025-01-13 11:27 ` Sascha Hauer
2025-01-13 11:27 ` [PATCH v3 23/23] ARM: k3: am625-sk board support Sascha Hauer
2025-01-14 8:32 ` [PATCH v3 00/23] ARM: K3: Add R5 boot support Sascha Hauer
22 siblings, 0 replies; 26+ messages in thread
From: Sascha Hauer @ 2025-01-13 11:27 UTC (permalink / raw)
To: open list:BAREBOX
This adds support for reading the DRAM size back from the DDRSS memory
controller.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-k3/Makefile | 1 +
arch/arm/mach-k3/common.c | 1 +
| 76 +++++++++++++++++++++++++++++++++++++++++++++++
include/mach/k3/common.h | 4 +++
4 files changed, 82 insertions(+)
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index 6e105095da..b9b987d211 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -1,5 +1,6 @@
obj-y += common.o
obj-pbl-$(CONFIG_MACH_K3_CORTEX_R5) += r5.o
+obj-pbl-y += ddrss.o
extra-y += combined-dm-cfg-am625.k3cfg combined-sysfw-cfg-am625.k3cfg
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index d7b44f31e8..d8bed194d6 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -171,6 +171,7 @@ static int am625_init(void)
am625_get_bootsource(&src, &instance);
bootsource_set(src, instance);
+ am625_register_dram();
genpd_activate();
--git a/arch/arm/mach-k3/ddrss.c b/arch/arm/mach-k3/ddrss.c
new file mode 100644
index 0000000000..b51371d661
--- /dev/null
+++ b/arch/arm/mach-k3/ddrss.c
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <memory.h>
+#include <linux/bitfield.h>
+#include <mach/k3/common.h>
+#include <linux/bits.h>
+#include <io.h>
+#include <asm/memory.h>
+#include <linux/kernel.h>
+
+#define CTLPHY_CTL_CFG_CTLCFG_DENALI_CTL_0 0x0
+
+#define DRAM_CLASS GENMASK(11, 8)
+
+#define CTLPHY_CTL_CFG_CTLCFG_DENALI_CTL_327 0x51c
+
+#define CTLPHY_CTL_CFG_CTLCFG_DENALI_CTL_317 0x4f4
+
+#define ROW_DIFF_0 GENMASK(2, 0)
+#define ROW_DIFF_1 GENMASK(10, 8)
+#define COL_DIFF_0 GENMASK(19, 16)
+#define COL_DIFF_1 GENMASK(27, 24)
+
+#define CTLPHY_CTL_CFG_CTLCFG_DENALI_CTL_3 0xc
+
+#define MAX_ROW GENMASK(4, 0)
+#define MAX_COL GENMASK(11, 8)
+
+#define AM625_DDRSS_BASE 0x0f308000
+
+#define DENALI_CTL_0_DRAM_CLASS_DDR4 0xa
+#define DENALI_CTL_0_DRAM_CLASS_LPDDR4 0xb
+
+u64 am625_sdram_size(void)
+{
+ void __iomem *base = IOMEM(AM625_DDRSS_BASE);
+ u32 ctl0 = readl(base + CTLPHY_CTL_CFG_CTLCFG_DENALI_CTL_0);
+ u32 ctl3 = readl(base + CTLPHY_CTL_CFG_CTLCFG_DENALI_CTL_3);
+ u32 ctl317 = readl(base + CTLPHY_CTL_CFG_CTLCFG_DENALI_CTL_317);
+ u32 ctl327 = readl(base + CTLPHY_CTL_CFG_CTLCFG_DENALI_CTL_327);
+ unsigned int cols, rows, banks;
+ u64 size = 0;
+
+ if (FIELD_GET(DRAM_CLASS, ctl0) == DENALI_CTL_0_DRAM_CLASS_LPDDR4)
+ banks = 8;
+ else if (FIELD_GET(DRAM_CLASS, ctl0) == DENALI_CTL_0_DRAM_CLASS_DDR4)
+ banks = 16;
+ else
+ return 0;
+
+ if (ctl327 & BIT(0)) {
+ cols = FIELD_GET(MAX_COL, ctl3) - FIELD_GET(COL_DIFF_0, ctl317);
+ rows = FIELD_GET(MAX_ROW, ctl3) - FIELD_GET(ROW_DIFF_0, ctl317);
+ size += memory_sdram_size(cols, rows, banks, 2);
+ }
+
+ if (ctl327 & BIT(1)) {
+ cols = FIELD_GET(MAX_COL, ctl3) - FIELD_GET(COL_DIFF_1, ctl317);
+ rows = FIELD_GET(MAX_ROW, ctl3) - FIELD_GET(ROW_DIFF_1, ctl317);
+ size += memory_sdram_size(cols, rows, banks, 2);
+ }
+
+ return size;
+}
+
+void am625_register_dram(void)
+{
+ u64 size = am625_sdram_size();
+ u64 lowmem = min_t(u64, size, SZ_2G);
+
+ arm_add_mem_device("ram0", 0x80000000, lowmem);
+
+#ifdef CONFIG_64BIT
+ if (size - lowmem)
+ arm_add_mem_device("ram0", 0x880000000ULL, size - lowmem);
+#endif
+}
diff --git a/include/mach/k3/common.h b/include/mach/k3/common.h
index 448ec1343c..d7ceea51d7 100644
--- a/include/mach/k3/common.h
+++ b/include/mach/k3/common.h
@@ -1,6 +1,10 @@
#ifndef __MACH_K3_COMMON_H
#define __MACH_K3_COMMON_H
+#include <bootsource.h>
+
void am625_get_bootsource(enum bootsource *src, int *instance);
+u64 am625_sdram_size(void);
+void am625_register_dram(void);
#endif /* __MACH_K3_COMMON_H */
--
2.39.5
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v3 23/23] ARM: k3: am625-sk board support
2025-01-13 11:26 [PATCH v3 00/23] ARM: K3: Add R5 boot support Sascha Hauer
` (20 preceding siblings ...)
2025-01-13 11:27 ` [PATCH v3 22/23] ARM: k3: Add DRAM size detection Sascha Hauer
@ 2025-01-13 11:27 ` Sascha Hauer
2025-01-14 8:32 ` [PATCH v3 00/23] ARM: K3: Add R5 boot support Sascha Hauer
22 siblings, 0 replies; 26+ messages in thread
From: Sascha Hauer @ 2025-01-13 11:27 UTC (permalink / raw)
To: open list:BAREBOX
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/Makefile | 1 +
arch/arm/boards/am625-sk/Makefile | 3 +
arch/arm/boards/am625-sk/am625-sk-ddr.c | 2223 +++++++++++++++++++++++++++
arch/arm/boards/am625-sk/am625sip-sk-ddr.c | 2229 ++++++++++++++++++++++++++++
arch/arm/boards/am625-sk/ddr.h | 7 +
arch/arm/boards/am625-sk/entry-r5.S | 29 +
arch/arm/boards/am625-sk/entry.S | 29 +
arch/arm/boards/am625-sk/lowlevel.c | 119 ++
arch/arm/dts/Makefile | 1 +
arch/arm/dts/k3-am625-r5-sk.dts | 4 +
arch/arm/dts/k3-am625-sk.dts | 9 +
arch/arm/dts/k3-am625sip-r5-sk.dts | 4 +
arch/arm/mach-k3/Kconfig | 6 +
images/Makefile.k3 | 26 +
14 files changed, 4690 insertions(+)
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index d8ca3fa1b5..c6104d0432 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -4,6 +4,7 @@
obj-$(CONFIG_MACH_ADVANTECH_ROM_742X) += advantech-mx6/
obj-$(CONFIG_MACH_AFI_GF) += afi-gf/
obj-$(CONFIG_MACH_ANIMEO_IP) += animeo_ip/
+obj-$(CONFIG_MACH_AM625_SK) += am625-sk/
obj-$(CONFIG_MACH_AT91RM9200EK) += at91rm9200ek/
obj-$(CONFIG_MACH_AT91SAM9260EK) += at91sam9260ek/
obj-$(CONFIG_MACH_AT91SAM9261EK) += at91sam9261ek/
diff --git a/arch/arm/boards/am625-sk/Makefile b/arch/arm/boards/am625-sk/Makefile
new file mode 100644
index 0000000000..1ff9e75a00
--- /dev/null
+++ b/arch/arm/boards/am625-sk/Makefile
@@ -0,0 +1,3 @@
+pbl-y += lowlevel.o
+pbl-$(CONFIG_MACH_K3_CORTEX_A) += entry.o
+pbl-$(CONFIG_MACH_K3_CORTEX_R5) += entry-r5.o am625-sk-ddr.o am625sip-sk-ddr.o
diff --git a/arch/arm/boards/am625-sk/am625-sk-ddr.c b/arch/arm/boards/am625-sk/am625-sk-ddr.c
new file mode 100644
index 0000000000..13a43b296d
--- /dev/null
+++ b/arch/arm/boards/am625-sk/am625-sk-ddr.c
@@ -0,0 +1,2223 @@
+#include <linux/kernel.h>
+#include <soc/k3/ddr.h>
+
+#include "ddr.h"
+
+#define DDRSS_PLL_FHS_CNT 3
+#define DDRSS_PLL_FREQUENCY_1 400000000
+#define DDRSS_PLL_FREQUENCY_2 400000000
+#define DDRSS_SDRAM_IDX 13
+#define DDRSS_REGION_IDX 16
+
+static uint32_t DDRSS_ctlReg[] = {
+ 0x00000A00,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x000890B8,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x000890B8,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x000890B8,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x01010100,
+ 0x01000100,
+ 0x01000110,
+ 0x02010002,
+ 0x00027100,
+ 0x00061A80,
+ 0x02550255,
+ 0x00000255,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x0400091C,
+ 0x1C1C1C1C,
+ 0x0400091C,
+ 0x1C1C1C1C,
+ 0x0400091C,
+ 0x1C1C1C1C,
+ 0x05050404,
+ 0x00002706,
+ 0x0602001D,
+ 0x05001D0B,
+ 0x00270605,
+ 0x0602001D,
+ 0x05001D0B,
+ 0x00270605,
+ 0x0602001D,
+ 0x07001D0B,
+ 0x00180807,
+ 0x0400DB60,
+ 0x07070009,
+ 0x00001808,
+ 0x0400DB60,
+ 0x07070009,
+ 0x00001808,
+ 0x0400DB60,
+ 0x03000009,
+ 0x0D0C0002,
+ 0x0D0C0D0C,
+ 0x01010000,
+ 0x03191919,
+ 0x0B0B0B0B,
+ 0x00000B0B,
+ 0x00000101,
+ 0x00000000,
+ 0x01000000,
+ 0x01180803,
+ 0x00001860,
+ 0x00000118,
+ 0x00001860,
+ 0x00000118,
+ 0x00001860,
+ 0x00000005,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00090009,
+ 0x00000009,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00010001,
+ 0x00025501,
+ 0x02550120,
+ 0x02550120,
+ 0x01200120,
+ 0x01200120,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x03010000,
+ 0x00010000,
+ 0x00000000,
+ 0x01000000,
+ 0x80104002,
+ 0x00040003,
+ 0x00040005,
+ 0x00030000,
+ 0x00050004,
+ 0x00000004,
+ 0x00040003,
+ 0x00040005,
+ 0x00000000,
+ 0x00061800,
+ 0x00061800,
+ 0x00061800,
+ 0x00061800,
+ 0x00061800,
+ 0x00000000,
+ 0x0000AAA0,
+ 0x00061800,
+ 0x00061800,
+ 0x00061800,
+ 0x00061800,
+ 0x00061800,
+ 0x00000000,
+ 0x0000AAA0,
+ 0x00061800,
+ 0x00061800,
+ 0x00061800,
+ 0x00061800,
+ 0x00061800,
+ 0x00000000,
+ 0x0000AAA0,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x080C0000,
+ 0x080C080C,
+ 0x08000000,
+ 0x00000808,
+ 0x000E0000,
+ 0x00080808,
+ 0x0E000000,
+ 0x08080800,
+ 0x00000000,
+ 0x0000080E,
+ 0x00040003,
+ 0x00000007,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x01000000,
+ 0x00000000,
+ 0x00001500,
+ 0x0000100E,
+ 0x00000000,
+ 0x00000000,
+ 0x00000001,
+ 0x00000002,
+ 0x00000C00,
+ 0x00001000,
+ 0x00000C00,
+ 0x00001000,
+ 0x00000C00,
+ 0x00001000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00042400,
+ 0x00000301,
+ 0x00000000,
+ 0x00000424,
+ 0x00000301,
+ 0x00000000,
+ 0x00000424,
+ 0x00000301,
+ 0x00000000,
+ 0x00000424,
+ 0x00000301,
+ 0x00000000,
+ 0x00000424,
+ 0x00000301,
+ 0x00000000,
+ 0x00000424,
+ 0x00000301,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00001401,
+ 0x00001401,
+ 0x00001401,
+ 0x00001401,
+ 0x00001401,
+ 0x00001401,
+ 0x00000493,
+ 0x00000493,
+ 0x00000493,
+ 0x00000493,
+ 0x00000493,
+ 0x00000493,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00010000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000101,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x0C181511,
+ 0x00000304,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00040000,
+ 0x00800200,
+ 0x00000000,
+ 0x02000400,
+ 0x00000080,
+ 0x00040000,
+ 0x00800200,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000100,
+ 0x01010000,
+ 0x00000000,
+ 0x3FFF0000,
+ 0x000FFF00,
+ 0xFFFFFFFF,
+ 0x00FFFF00,
+ 0x0A000000,
+ 0x0001FFFF,
+ 0x01010101,
+ 0x01010101,
+ 0x00000118,
+ 0x00000C01,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x01000000,
+ 0x00000100,
+ 0x00010000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x0C000000,
+ 0x060C0606,
+ 0x06060C06,
+ 0x00010101,
+ 0x02000000,
+ 0x05020101,
+ 0x00000505,
+ 0x02020200,
+ 0x02020202,
+ 0x02020202,
+ 0x02020202,
+ 0x00000000,
+ 0x00000000,
+ 0x04000100,
+ 0x1E000004,
+ 0x000030C0,
+ 0x00000200,
+ 0x00000200,
+ 0x00000200,
+ 0x00000200,
+ 0x0000DB60,
+ 0x0001E780,
+ 0x0C0D0302,
+ 0x001E090A,
+ 0x000030C0,
+ 0x00000200,
+ 0x00000200,
+ 0x00000200,
+ 0x00000200,
+ 0x0000DB60,
+ 0x0001E780,
+ 0x0C0D0302,
+ 0x001E090A,
+ 0x000030C0,
+ 0x00000200,
+ 0x00000200,
+ 0x00000200,
+ 0x00000200,
+ 0x0000DB60,
+ 0x0001E780,
+ 0x0C0D0302,
+ 0x0000090A,
+ 0x00000000,
+ 0x0302000A,
+ 0x01000500,
+ 0x01010001,
+ 0x00010001,
+ 0x01010001,
+ 0x02010000,
+ 0x00000200,
+ 0x02000201,
+ 0x00000000,
+ 0x00202020,
+};
+
+static uint32_t DDRSS_phyIndepReg[] = {
+ 0x00000A00,
+ 0x00000000,
+ 0x00000000,
+ 0x01000000,
+ 0x00000001,
+ 0x00010064,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00010001,
+ 0x00000000,
+ 0x00010001,
+ 0x00000005,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x280D0001,
+ 0x00000000,
+ 0x00010000,
+ 0x00003200,
+ 0x00000000,
+ 0x00000000,
+ 0x00060602,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000001,
+ 0x00000055,
+ 0x000000AA,
+ 0x000000AD,
+ 0x00000052,
+ 0x0000006A,
+ 0x00000095,
+ 0x00000095,
+ 0x000000AD,
+ 0x00000000,
+ 0x00000000,
+ 0x00010100,
+ 0x00000014,
+ 0x000007D0,
+ 0x00000300,
+ 0x00000000,
+ 0x00000000,
+ 0x01000000,
+ 0x00010101,
+ 0x01000000,
+ 0x00000000,
+ 0x00010000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00001400,
+ 0x00000000,
+ 0x01000000,
+ 0x00000404,
+ 0x00000001,
+ 0x0001010E,
+ 0x02040100,
+ 0x00010000,
+ 0x00000034,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000005,
+ 0x01000000,
+ 0x04000100,
+ 0x00020000,
+ 0x00010002,
+ 0x00000001,
+ 0x00020001,
+ 0x00020002,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000300,
+ 0x0A090B0C,
+ 0x04060708,
+ 0x01000005,
+ 0x00000800,
+ 0x00000000,
+ 0x00010008,
+ 0x00000000,
+ 0x0000AA00,
+ 0x00000000,
+ 0x00010000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000008,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00010100,
+ 0x00000000,
+ 0x00000000,
+ 0x00027100,
+ 0x00061A80,
+ 0x00000100,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x01000000,
+ 0x00010003,
+ 0x02000101,
+ 0x01030001,
+ 0x00010400,
+ 0x06000105,
+ 0x01070001,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00010000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00010000,
+ 0x00000004,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00007800,
+ 0x00780078,
+ 0x00141414,
+ 0x0000003A,
+ 0x0000003A,
+ 0x0004003A,
+ 0x04000400,
+ 0xC8040009,
+ 0x0400091C,
+ 0x00091CC8,
+ 0x001CC804,
+ 0x00000118,
+ 0x00001860,
+ 0x00000118,
+ 0x00001860,
+ 0x00000118,
+ 0x04001860,
+ 0x01010404,
+ 0x00001901,
+ 0x00190019,
+ 0x010C010C,
+ 0x0000010C,
+ 0x00000000,
+ 0x05000000,
+ 0x01010505,
+ 0x01010101,
+ 0x00181818,
+ 0x00000000,
+ 0x00000000,
+ 0x0D000000,
+ 0x0A0A0D0D,
+ 0x0303030A,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x0D090000,
+ 0x0D09000D,
+ 0x0D09000D,
+ 0x0000000D,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x16000000,
+ 0x001600C8,
+ 0x001600C8,
+ 0x010100C8,
+ 0x00001B01,
+ 0x1F0F0053,
+ 0x05000001,
+ 0x001B0A0D,
+ 0x1F0F0053,
+ 0x05000001,
+ 0x001B0A0D,
+ 0x1F0F0053,
+ 0x05000001,
+ 0x00010A0D,
+ 0x0C0B0700,
+ 0x000D0605,
+ 0x0000C570,
+ 0x0000001D,
+ 0x180A0800,
+ 0x0B071C1C,
+ 0x0D06050C,
+ 0x0000C570,
+ 0x0000001D,
+ 0x180A0800,
+ 0x0B071C1C,
+ 0x0D06050C,
+ 0x0000C570,
+ 0x0000001D,
+ 0x180A0800,
+ 0x00001C1C,
+ 0x000030C0,
+ 0x0001E780,
+ 0x000030C0,
+ 0x0001E780,
+ 0x000030C0,
+ 0x0001E780,
+ 0x02550255,
+ 0x03030255,
+ 0x00025503,
+ 0x02550255,
+ 0x0C080C08,
+ 0x00000C08,
+ 0x000890B8,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000120,
+ 0x000890B8,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000120,
+ 0x000890B8,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x02000120,
+ 0x00000080,
+ 0x00020000,
+ 0x00000080,
+ 0x00020000,
+ 0x00000080,
+ 0x00000000,
+ 0x00000000,
+ 0x00040404,
+ 0x00000000,
+ 0x02010102,
+ 0x67676767,
+ 0x00000202,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x0D100F00,
+ 0x0003020E,
+ 0x00000001,
+ 0x01000000,
+ 0x00020201,
+ 0x00000000,
+ 0x00000424,
+ 0x00000301,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00001401,
+ 0x00000493,
+ 0x00000000,
+ 0x00000424,
+ 0x00000301,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00001401,
+ 0x00000493,
+ 0x00000000,
+ 0x00000424,
+ 0x00000301,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00001401,
+ 0x00000493,
+ 0x00000000,
+ 0x00000424,
+ 0x00000301,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00001401,
+ 0x00000493,
+ 0x00000000,
+ 0x00000424,
+ 0x00000301,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00001401,
+ 0x00000493,
+ 0x00000000,
+ 0x00000424,
+ 0x00000301,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00001401,
+ 0x00000493,
+ 0x00000000,
+};
+
+static uint32_t DDRSS_phyReg[] = {
+ 0x04C00000,
+ 0x00000000,
+ 0x00000200,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000001,
+ 0x00000000,
+ 0x00000000,
+ 0x010101FF,
+ 0x00010000,
+ 0x00C00004,
+ 0x00CC0008,
+ 0x00660201,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x0000AAAA,
+ 0x00005555,
+ 0x0000B5B5,
+ 0x00004A4A,
+ 0x00005656,
+ 0x0000A9A9,
+ 0x0000B7B7,
+ 0x00004848,
+ 0x00000000,
+ 0x00000000,
+ 0x08000000,
+ 0x0F000008,
+ 0x00000F0F,
+ 0x00E4E400,
+ 0x00070820,
+ 0x000C0020,
+ 0x00062000,
+ 0x00000000,
+ 0x55555555,
+ 0xAAAAAAAA,
+ 0x55555555,
+ 0xAAAAAAAA,
+ 0x00005555,
+ 0x01000100,
+ 0x00800180,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000004,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x041F07FF,
+ 0x00000000,
+ 0x01CCB001,
+ 0x2000CCB0,
+ 0x20000140,
+ 0x07FF0200,
+ 0x0000DD01,
+ 0x10100303,
+ 0x10101010,
+ 0x10101010,
+ 0x00021010,
+ 0x00100010,
+ 0x00100010,
+ 0x00100010,
+ 0x00100010,
+ 0x02020010,
+ 0x51515041,
+ 0x31804000,
+ 0x04BF0340,
+ 0x01008080,
+ 0x04050001,
+ 0x00000504,
+ 0x42100010,
+ 0x010C053E,
+ 0x000F0C14,
+ 0x01000140,
+ 0x007A0120,
+ 0x00000C00,
+ 0x000001CC,
+ 0x20100200,
+ 0x00000005,
+ 0x76543210,
+ 0x00000008,
+ 0x02800280,
+ 0x02800280,
+ 0x02800280,
+ 0x02800280,
+ 0x00000280,
+ 0x00008000,
+ 0x00800080,
+ 0x00800080,
+ 0x00800080,
+ 0x00800080,
+ 0x00800080,
+ 0x00800080,
+ 0x00800080,
+ 0x00800080,
+ 0x01000080,
+ 0x01000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00080200,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x04C00000,
+ 0x00000000,
+ 0x00000200,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000001,
+ 0x00000000,
+ 0x00000000,
+ 0x010101FF,
+ 0x00010000,
+ 0x00C00004,
+ 0x00CC0008,
+ 0x00660201,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x0000AAAA,
+ 0x00005555,
+ 0x0000B5B5,
+ 0x00004A4A,
+ 0x00005656,
+ 0x0000A9A9,
+ 0x0000B7B7,
+ 0x00004848,
+ 0x00000000,
+ 0x00000000,
+ 0x08000000,
+ 0x0F000008,
+ 0x00000F0F,
+ 0x00E4E400,
+ 0x00070820,
+ 0x000C0020,
+ 0x00062000,
+ 0x00000000,
+ 0x55555555,
+ 0xAAAAAAAA,
+ 0x55555555,
+ 0xAAAAAAAA,
+ 0x00005555,
+ 0x01000100,
+ 0x00800180,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000004,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x041F07FF,
+ 0x00000000,
+ 0x01CCB001,
+ 0x2000CCB0,
+ 0x20000140,
+ 0x07FF0200,
+ 0x0000DD01,
+ 0x10100303,
+ 0x10101010,
+ 0x10101010,
+ 0x00021010,
+ 0x00100010,
+ 0x00100010,
+ 0x00100010,
+ 0x00100010,
+ 0x02020010,
+ 0x51515041,
+ 0x31804000,
+ 0x04BF0340,
+ 0x01008080,
+ 0x04050001,
+ 0x00000504,
+ 0x42100010,
+ 0x010C053E,
+ 0x000F0C14,
+ 0x01000140,
+ 0x007A0120,
+ 0x00000C00,
+ 0x000001CC,
+ 0x20100200,
+ 0x00000005,
+ 0x76543210,
+ 0x00000008,
+ 0x02800280,
+ 0x02800280,
+ 0x02800280,
+ 0x02800280,
+ 0x00000280,
+ 0x00008000,
+ 0x00800080,
+ 0x00800080,
+ 0x00800080,
+ 0x00800080,
+ 0x00800080,
+ 0x00800080,
+ 0x00800080,
+ 0x00800080,
+ 0x01000080,
+ 0x01000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00080200,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000100,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000100,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00DCBA98,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x0A418820,
+ 0x103F0000,
+ 0x000F0100,
+ 0x0000000F,
+ 0x020002CC,
+ 0x00030000,
+ 0x00000300,
+ 0x00000300,
+ 0x00000300,
+ 0x00000300,
+ 0x00000300,
+ 0x42080010,
+ 0x0000003E,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
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+ 0x00000000,
+ 0x16A4A0E6,
+ 0x103F0000,
+ 0x000F0000,
+ 0x0000000F,
+ 0x020002CC,
+ 0x00030000,
+ 0x00000300,
+ 0x00000300,
+ 0x00000300,
+ 0x00000300,
+ 0x00000300,
+ 0x42080010,
+ 0x0000003E,
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+ 0x00DCBA98,
+ 0x00000000,
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+ 0x00000000,
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+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x2307B9AC,
+ 0x10030000,
+ 0x000F0000,
+ 0x0000000F,
+ 0x020002CC,
+ 0x00030000,
+ 0x00000300,
+ 0x00000300,
+ 0x00000300,
+ 0x00000300,
+ 0x00000300,
+ 0x42080010,
+ 0x0000003E,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
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+ 0x00000000,
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+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000100,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00050000,
+ 0x04000100,
+ 0x00000055,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x01002000,
+ 0x00004001,
+ 0x00020028,
+ 0x00010100,
+ 0x00000001,
+ 0x00000000,
+ 0x0F0F0E06,
+ 0x00010101,
+ 0x010F0004,
+ 0x00000000,
+ 0x00000000,
+ 0x00000064,
+ 0x00000000,
+ 0x00000000,
+ 0x01020103,
+ 0x0F020102,
+ 0x03030303,
+ 0x03030303,
+ 0x00040000,
+ 0x00005201,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x07070001,
+ 0x00005400,
+ 0x000040A2,
+ 0x00024410,
+ 0x00004410,
+ 0x00004410,
+ 0x00004410,
+ 0x00004410,
+ 0x00004410,
+ 0x00004410,
+ 0x00004410,
+ 0x00004410,
+ 0x00004410,
+ 0x00000000,
+ 0x00000046,
+ 0x00000400,
+ 0x00000008,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x03000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x04102006,
+ 0x00041020,
+ 0x01C98C98,
+ 0x3F400000,
+ 0x3F3F1F3F,
+ 0x0000001F,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000001,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x76543210,
+ 0x00000098,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00040700,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000002,
+ 0x00000100,
+ 0x00000000,
+ 0x0001F7C2,
+ 0x00020002,
+ 0x00000000,
+ 0x00001142,
+ 0x03020400,
+ 0x00000080,
+ 0x03900390,
+ 0x03900390,
+ 0x03900390,
+ 0x03900390,
+ 0x03900390,
+ 0x03900390,
+ 0x00000300,
+ 0x00000300,
+ 0x00000300,
+ 0x00000300,
+ 0x31823FC7,
+ 0x00000000,
+ 0x0C000D3F,
+ 0x30000D3F,
+ 0x300D3F11,
+ 0x01990000,
+ 0x000D3FCC,
+ 0x00000C11,
+ 0x300D3F11,
+ 0x01990000,
+ 0x300C3F11,
+ 0x01990000,
+ 0x300C3F11,
+ 0x01990000,
+ 0x300D3F11,
+ 0x01990000,
+ 0x300D3F11,
+ 0x01990000,
+ 0x20040004,
+};
+
+static struct reginitdata ctl_regs = {
+ .regs = DDRSS_ctlReg,
+ .num = ARRAY_SIZE(DDRSS_ctlReg),
+};
+
+static struct reginitdata pi_regs = {
+ .regs = DDRSS_phyIndepReg,
+ .num = ARRAY_SIZE(DDRSS_phyIndepReg),
+};
+
+static struct reginitdata phy_regs = {
+ .regs = DDRSS_phyReg,
+ .num = ARRAY_SIZE(DDRSS_phyReg),
+};
+
+static struct k3_ddr_initdata initdata = {
+ .ctl_regs = &ctl_regs,
+ .pi_regs = &pi_regs,
+ .phy_regs = &phy_regs,
+ .freq0 = 25000000,
+ .freq1 = DDRSS_PLL_FREQUENCY_1,
+ .freq2 = DDRSS_PLL_FREQUENCY_2,
+ .fhs_cnt = DDRSS_PLL_FHS_CNT,
+};
+
+void am625_sk_ddr_init(void)
+{
+ k3_ddrss_init(&initdata);
+}
diff --git a/arch/arm/boards/am625-sk/am625sip-sk-ddr.c b/arch/arm/boards/am625-sk/am625sip-sk-ddr.c
new file mode 100644
index 0000000000..cf7d260c63
--- /dev/null
+++ b/arch/arm/boards/am625-sk/am625sip-sk-ddr.c
@@ -0,0 +1,2229 @@
+#include <linux/kernel.h>
+#include <soc/k3/ddr.h>
+
+#include "ddr.h"
+
+/*
+ * The data in this file was taken from
+ * https://git.ti.com/cgit/ti-u-boot/ti-u-boot/tree/arch/arm/dts/k3-am62x-sip-ddr-lp4-50-800.dtsi?h=ti-u-boot-2024.04
+ *
+ */
+
+#define DDRSS_PLL_FHS_CNT 3
+#define DDRSS_PLL_FREQUENCY_1 400000000
+#define DDRSS_PLL_FREQUENCY_2 400000000
+#define DDRSS_SDRAM_IDX 13
+#define DDRSS_REGION_IDX 16
+
+static uint32_t DDRSS_ctlReg[] = {
+ 0x00000B00,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00002710,
+ 0x000186A0,
+ 0x00000005,
+ 0x00000064,
+ 0x00027100,
+ 0x00186A00,
+ 0x00000005,
+ 0x00000640,
+ 0x00027100,
+ 0x00186A00,
+ 0x00000005,
+ 0x00000640,
+ 0x01010100,
+ 0x01010100,
+ 0x01000110,
+ 0x02010002,
+ 0x0000000A,
+ 0x000186A0,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00020200,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x08000010,
+ 0x00002020,
+ 0x00000000,
+ 0x00000000,
+ 0x0000040C,
+ 0x00000000,
+ 0x0000081C,
+ 0x00000000,
+ 0x0000081C,
+ 0x00000000,
+ 0x05000804,
+ 0x00000700,
+ 0x09090004,
+ 0x00000303,
+ 0x00320007,
+ 0x09090023,
+ 0x0000210F,
+ 0x00320007,
+ 0x09090023,
+ 0x0900210F,
+ 0x000A0A09,
+ 0x040006DB,
+ 0x09092004,
+ 0x00000C0A,
+ 0x06006DB0,
+ 0x09092006,
+ 0x00000C0A,
+ 0x06006DB0,
+ 0x03042006,
+ 0x04050002,
+ 0x100F100F,
+ 0x01010008,
+ 0x041F1F07,
+ 0x03111103,
+ 0x00001111,
+ 0x00000101,
+ 0x00000000,
+ 0x01000000,
+ 0x00090803,
+ 0x000000BB,
+ 0x00000090,
+ 0x00000C2B,
+ 0x00000090,
+ 0x00000C2B,
+ 0x00000005,
+ 0x00000005,
+ 0x00000010,
+ 0x00000048,
+ 0x0000017E,
+ 0x00000048,
+ 0x0000017E,
+ 0x03004000,
+ 0x00001201,
+ 0x00060005,
+ 0x00000006,
+ 0x00000000,
+ 0x05121208,
+ 0x05030A05,
+ 0x05030C06,
+ 0x01030C06,
+ 0x02010201,
+ 0x00000A01,
+ 0x0096000A,
+ 0x00960096,
+ 0x00000096,
+ 0x00000000,
+ 0x05010303,
+ 0x0C040505,
+ 0x06050203,
+ 0x030C0605,
+ 0x05060502,
+ 0x03030306,
+ 0x03010000,
+ 0x00010000,
+ 0x00000000,
+ 0x01000000,
+ 0x80104002,
+ 0x00040003,
+ 0x00040005,
+ 0x00030000,
+ 0x00050004,
+ 0x00000004,
+ 0x00040003,
+ 0x00040005,
+ 0x00000000,
+ 0x00002EC0,
+ 0x00002EC0,
+ 0x00002EC0,
+ 0x00002EC0,
+ 0x00002EC0,
+ 0x00000000,
+ 0x0000051D,
+ 0x00030AC0,
+ 0x00030AC0,
+ 0x00030AC0,
+ 0x00030AC0,
+ 0x00030AC0,
+ 0x00000000,
+ 0x0000552D,
+ 0x00030AC0,
+ 0x00030AC0,
+ 0x00030AC0,
+ 0x00030AC0,
+ 0x00030AC0,
+ 0x00000000,
+ 0x0000552D,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x03050000,
+ 0x03050305,
+ 0x00000000,
+ 0x08010000,
+ 0x000E0808,
+ 0x01000000,
+ 0x0E080808,
+ 0x00000000,
+ 0x08080801,
+ 0x0000080E,
+ 0x00040003,
+ 0x00000007,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x01000000,
+ 0x00000000,
+ 0x00001500,
+ 0x0000100E,
+ 0x00000002,
+ 0x00000000,
+ 0x00000001,
+ 0x00000002,
+ 0x00000C00,
+ 0x00001000,
+ 0x00000C00,
+ 0x00001000,
+ 0x00000C00,
+ 0x00001000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x0005000A,
+ 0x0404000D,
+ 0x0000000D,
+ 0x005000A0,
+ 0x060600C8,
+ 0x000000C8,
+ 0x005000A0,
+ 0x060600C8,
+ 0x000000C8,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000004,
+ 0x00000000,
+ 0x00000000,
+ 0x00000024,
+ 0x00000012,
+ 0x00000000,
+ 0x00000024,
+ 0x00000012,
+ 0x00000000,
+ 0x00000004,
+ 0x00000000,
+ 0x00000000,
+ 0x00000024,
+ 0x00000012,
+ 0x00000000,
+ 0x00000024,
+ 0x00000012,
+ 0x00000000,
+ 0x00000000,
+ 0x00000031,
+ 0x000000B1,
+ 0x000000B1,
+ 0x00000031,
+ 0x000000B1,
+ 0x000000B1,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x65006565,
+ 0x00002765,
+ 0x00000027,
+ 0x00000027,
+ 0x00000027,
+ 0x00000027,
+ 0x00000027,
+ 0x00000000,
+ 0x00000000,
+ 0x0000000F,
+ 0x0000000F,
+ 0x0000000F,
+ 0x0000000F,
+ 0x0000000F,
+ 0x0000000F,
+ 0x00000000,
+ 0x00001000,
+ 0x00000015,
+ 0x00000015,
+ 0x00000010,
+ 0x00000015,
+ 0x00000015,
+ 0x00000020,
+ 0x00010000,
+ 0x00000100,
+ 0x00000000,
+ 0x00000000,
+ 0x00000101,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x0C181511,
+ 0x00000304,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00020000,
+ 0x00400100,
+ 0x00080032,
+ 0x01000200,
+ 0x03200040,
+ 0x00020018,
+ 0x00400100,
+ 0x00180320,
+ 0x00030000,
+ 0x00280028,
+ 0x00000100,
+ 0x01010000,
+ 0x00000202,
+ 0x0FFF0000,
+ 0x000FFF00,
+ 0xFFFFFFFF,
+ 0x00FFFF00,
+ 0x0B000000,
+ 0x0001FFFF,
+ 0x01010101,
+ 0x01010101,
+ 0x00000118,
+ 0x00000C01,
+ 0x01000100,
+ 0x00000000,
+ 0x00000000,
+ 0x01030303,
+ 0x00000001,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x01000101,
+ 0x01010001,
+ 0x00010101,
+ 0x01050503,
+ 0x05020201,
+ 0x08080C0C,
+ 0x00080308,
+ 0x000B030E,
+ 0x000B0310,
+ 0x0B0B0810,
+ 0x01000000,
+ 0x03020301,
+ 0x04000102,
+ 0x1B000004,
+ 0x00000176,
+ 0x00000200,
+ 0x00000200,
+ 0x00000200,
+ 0x00000200,
+ 0x00000693,
+ 0x00000E9C,
+ 0x03050202,
+ 0x00250201,
+ 0x00001856,
+ 0x00000200,
+ 0x00000200,
+ 0x00000200,
+ 0x00000200,
+ 0x00006D83,
+ 0x0000F35C,
+ 0x070D0402,
+ 0x00250405,
+ 0x00001856,
+ 0x00000200,
+ 0x00000200,
+ 0x00000200,
+ 0x00000200,
+ 0x00006D83,
+ 0x0000F35C,
+ 0x070D0402,
+ 0x00000405,
+ 0x00000000,
+ 0x0302000A,
+ 0x01000500,
+ 0x01010001,
+ 0x00010001,
+ 0x01010001,
+ 0x02010000,
+ 0x00000200,
+ 0x02000201,
+ 0x10100600,
+ 0x00202020,
+};
+
+static uint32_t DDRSS_phyIndepReg[] = {
+ 0x00000B00,
+ 0x00000000,
+ 0x00000000,
+ 0x01000000,
+ 0x00000001,
+ 0x00010064,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000002,
+ 0x00000005,
+ 0x00010001,
+ 0x08000000,
+ 0x00010300,
+ 0x00000005,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00010000,
+ 0x280A0001,
+ 0x00000000,
+ 0x00010000,
+ 0x00003200,
+ 0x00000000,
+ 0x00000000,
+ 0x01010102,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000001,
+ 0x000000AA,
+ 0x00000055,
+ 0x000000B5,
+ 0x0000004A,
+ 0x00000056,
+ 0x000000A9,
+ 0x000000A9,
+ 0x000000B5,
+ 0x00000000,
+ 0x00000000,
+ 0x00010100,
+ 0x00000015,
+ 0x000007D0,
+ 0x00000300,
+ 0x00000000,
+ 0x00000000,
+ 0x01000000,
+ 0x00010101,
+ 0x01000000,
+ 0x03000000,
+ 0x00000000,
+ 0x00001701,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x0A0A140A,
+ 0x10020101,
+ 0x01000210,
+ 0x05000404,
+ 0x00010001,
+ 0x0001000E,
+ 0x01010100,
+ 0x00010000,
+ 0x00000034,
+ 0x00000000,
+ 0x00000000,
+ 0x0000FFFF,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x01000000,
+ 0x08020100,
+ 0x00020000,
+ 0x00010002,
+ 0x00000001,
+ 0x00020001,
+ 0x00020002,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000400,
+ 0x0A090B0C,
+ 0x04060708,
+ 0x01000005,
+ 0x00000800,
+ 0x00000000,
+ 0x00010008,
+ 0x00000000,
+ 0x0000AA00,
+ 0x00000000,
+ 0x00010000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000008,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00010000,
+ 0x00000000,
+ 0x00000000,
+ 0x0000000A,
+ 0x000186A0,
+ 0x00000100,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x01000000,
+ 0x00010003,
+ 0x02000101,
+ 0x01030001,
+ 0x00010400,
+ 0x06000105,
+ 0x01070001,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00010001,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00010000,
+ 0x00000004,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000800,
+ 0x00780078,
+ 0x00101001,
+ 0x00000034,
+ 0x00000042,
+ 0x00020042,
+ 0x02000200,
+ 0x00000004,
+ 0x0000080C,
+ 0x00081C00,
+ 0x001C0000,
+ 0x00000009,
+ 0x000000BB,
+ 0x00000090,
+ 0x00000C2B,
+ 0x00000090,
+ 0x04000C2B,
+ 0x01010404,
+ 0x00001501,
+ 0x001D001D,
+ 0x01000100,
+ 0x00000100,
+ 0x00000000,
+ 0x05050503,
+ 0x01010C0C,
+ 0x01010101,
+ 0x000C0C0A,
+ 0x00000000,
+ 0x00000000,
+ 0x04000000,
+ 0x04020808,
+ 0x04040204,
+ 0x00090031,
+ 0x00110039,
+ 0x00110039,
+ 0x01010101,
+ 0x0002000D,
+ 0x000200C8,
+ 0x010000C8,
+ 0x000E000E,
+ 0x00C90100,
+ 0x010000C9,
+ 0x00C900C9,
+ 0x32103200,
+ 0x01013210,
+ 0x0A070601,
+ 0x0D09070D,
+ 0x0D09070D,
+ 0x000C000D,
+ 0x00001000,
+ 0x00000C00,
+ 0x00001000,
+ 0x00000C00,
+ 0x02001000,
+ 0x0016000D,
+ 0x001600C8,
+ 0x000000C8,
+ 0x00001900,
+ 0x32000056,
+ 0x06000101,
+ 0x001D0204,
+ 0x32120058,
+ 0x05000101,
+ 0x001D0408,
+ 0x32120058,
+ 0x05000101,
+ 0x00000408,
+ 0x05030900,
+ 0x00040900,
+ 0x0000062B,
+ 0x20010004,
+ 0x0A0A0A03,
+ 0x11090000,
+ 0x1009000F,
+ 0x000062B8,
+ 0x20030023,
+ 0x0C0A0C0C,
+ 0x11090000,
+ 0x1009000F,
+ 0x000062B8,
+ 0x20030023,
+ 0x0C0A0C0C,
+ 0x00000000,
+ 0x00000176,
+ 0x00000E9C,
+ 0x00001856,
+ 0x0000F35C,
+ 0x00001856,
+ 0x0000F35C,
+ 0x0096000A,
+ 0x03030096,
+ 0x00000003,
+ 0x00000000,
+ 0x05030503,
+ 0x00000503,
+ 0x00002710,
+ 0x000186A0,
+ 0x00000005,
+ 0x00000064,
+ 0x0000000A,
+ 0x00027100,
+ 0x000186A0,
+ 0x00000005,
+ 0x00000640,
+ 0x00000096,
+ 0x00027100,
+ 0x000186A0,
+ 0x00000005,
+ 0x00000640,
+ 0x01000096,
+ 0x00320040,
+ 0x00010008,
+ 0x03200040,
+ 0x00010018,
+ 0x03200040,
+ 0x00000318,
+ 0x00280028,
+ 0x03040404,
+ 0x00000303,
+ 0x02020101,
+ 0x67676767,
+ 0x00000000,
+ 0x55000000,
+ 0x00000000,
+ 0x3C00005A,
+ 0x00005500,
+ 0x00005A00,
+ 0x0D100F3C,
+ 0x0003020E,
+ 0x00000001,
+ 0x01000000,
+ 0x00020201,
+ 0x00000000,
+ 0x00000000,
+ 0x00000004,
+ 0x00000000,
+ 0x00000031,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00100F27,
+ 0x00000000,
+ 0x00000024,
+ 0x00000012,
+ 0x000000B1,
+ 0x00000000,
+ 0x00000000,
+ 0x65000000,
+ 0x00150F27,
+ 0x00000000,
+ 0x00000024,
+ 0x00000012,
+ 0x000000B1,
+ 0x00000000,
+ 0x00000000,
+ 0x65000000,
+ 0x00150F27,
+ 0x00000000,
+ 0x00000004,
+ 0x00000000,
+ 0x00000031,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00100F27,
+ 0x00000000,
+ 0x00000024,
+ 0x00000012,
+ 0x000000B1,
+ 0x00000000,
+ 0x00000000,
+ 0x65000000,
+ 0x00150F27,
+ 0x00000000,
+ 0x00000024,
+ 0x00000012,
+ 0x000000B1,
+ 0x00000000,
+ 0x00000000,
+ 0x65000000,
+ 0x00150F27,
+};
+
+static uint32_t DDRSS_phyReg[] = {
+ 0x04F00000,
+ 0x00000000,
+ 0x00030200,
+ 0x00000000,
+ 0x00000000,
+ 0x01000000,
+ 0x03000400,
+ 0x00000001,
+ 0x00000001,
+ 0x00000000,
+ 0x00000000,
+ 0x01010000,
+ 0x00010000,
+ 0x00C00001,
+ 0x00CC0008,
+ 0x00660601,
+ 0x00000003,
+ 0x00000000,
+ 0x00000000,
+ 0x0000AAAA,
+ 0x00005555,
+ 0x0000B5B5,
+ 0x00004A4A,
+ 0x00005656,
+ 0x0000A9A9,
+ 0x0000B7B7,
+ 0x00004848,
+ 0x00000000,
+ 0x00000000,
+ 0x08000000,
+ 0x0F000008,
+ 0x00000F0F,
+ 0x00E4E400,
+ 0x00071020,
+ 0x000C0020,
+ 0x00062000,
+ 0x00000000,
+ 0x55555555,
+ 0xAAAAAAAA,
+ 0x55555555,
+ 0xAAAAAAAA,
+ 0x00005555,
+ 0x01000100,
+ 0x00800180,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000004,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x041F07FF,
+ 0x00000000,
+ 0x01CC0B01,
+ 0x1003CC0B,
+ 0x20000140,
+ 0x07FF0200,
+ 0x0000DD01,
+ 0x00100303,
+ 0x00000000,
+ 0x00000000,
+ 0x00021000,
+ 0x00100010,
+ 0x00100010,
+ 0x00100010,
+ 0x00100010,
+ 0x02020010,
+ 0x51516041,
+ 0x31C06000,
+ 0x07AB0340,
+ 0x0000C0C0,
+ 0x04050000,
+ 0x00000504,
+ 0x42100010,
+ 0x010C053E,
+ 0x000F0C1D,
+ 0x01000140,
+ 0x007A0120,
+ 0x00000C00,
+ 0x000001CC,
+ 0x20100200,
+ 0x00000005,
+ 0x56743210,
+ 0x00000008,
+ 0x034C034C,
+ 0x034C034C,
+ 0x034C034C,
+ 0x034C034C,
+ 0x0000034C,
+ 0x00008000,
+ 0x00800080,
+ 0x00800080,
+ 0x00800080,
+ 0x00800080,
+ 0x00800080,
+ 0x00800080,
+ 0x00800080,
+ 0x00800080,
+ 0x01800080,
+ 0x01000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00080200,
+ 0x00000000,
+ 0x0000F0F0,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x04F00000,
+ 0x00000000,
+ 0x00030200,
+ 0x00000000,
+ 0x00000000,
+ 0x01000000,
+ 0x03000400,
+ 0x00000001,
+ 0x00000001,
+ 0x00000000,
+ 0x00000000,
+ 0x01010000,
+ 0x00010000,
+ 0x00C00001,
+ 0x00CC0008,
+ 0x00660601,
+ 0x00000003,
+ 0x00000000,
+ 0x00000000,
+ 0x0000AAAA,
+ 0x00005555,
+ 0x0000B5B5,
+ 0x00004A4A,
+ 0x00005656,
+ 0x0000A9A9,
+ 0x0000B7B7,
+ 0x00004848,
+ 0x00000000,
+ 0x00000000,
+ 0x08000000,
+ 0x0F000008,
+ 0x00000F0F,
+ 0x00E4E400,
+ 0x00071020,
+ 0x000C0020,
+ 0x00062000,
+ 0x00000000,
+ 0x55555555,
+ 0xAAAAAAAA,
+ 0x55555555,
+ 0xAAAAAAAA,
+ 0x00005555,
+ 0x01000100,
+ 0x00800180,
+ 0x00000001,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000004,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x041F07FF,
+ 0x00000000,
+ 0x01CC0B01,
+ 0x1003CC0B,
+ 0x20000140,
+ 0x07FF0200,
+ 0x0000DD01,
+ 0x00100303,
+ 0x00000000,
+ 0x00000000,
+ 0x00021000,
+ 0x00100010,
+ 0x00100010,
+ 0x00100010,
+ 0x00100010,
+ 0x02020010,
+ 0x51516041,
+ 0x31C06000,
+ 0x07AB0340,
+ 0x0000C0C0,
+ 0x04050000,
+ 0x00000504,
+ 0x42100010,
+ 0x010C053E,
+ 0x000F0C1D,
+ 0x01000140,
+ 0x007A0120,
+ 0x00000C00,
+ 0x000001CC,
+ 0x20100200,
+ 0x00000005,
+ 0x01324567,
+ 0x00000008,
+ 0x034C034C,
+ 0x034C034C,
+ 0x034C034C,
+ 0x034C034C,
+ 0x0000034C,
+ 0x00008000,
+ 0x00800080,
+ 0x00800080,
+ 0x00800080,
+ 0x00800080,
+ 0x00800080,
+ 0x00800080,
+ 0x00800080,
+ 0x00800080,
+ 0x01800080,
+ 0x01000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00080200,
+ 0x00000000,
+ 0x0000F0F0,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000100,
+ 0x00000200,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00400000,
+ 0x00000080,
+ 0x00DCBA98,
+ 0x03000000,
+ 0x00200000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x0000002A,
+ 0x00000015,
+ 0x00000015,
+ 0x0000002A,
+ 0x00000033,
+ 0x0000000C,
+ 0x0000000C,
+ 0x00000033,
+ 0x0A418820,
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+ 0x00010101,
+ 0x010F0004,
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+ 0x00000064,
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+ 0x00041B42,
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+ 0x00000000,
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+ 0x00004410,
+ 0x00004410,
+ 0x00004410,
+ 0x00004410,
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+ 0x00004410,
+ 0x00004410,
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+ 0x00000400,
+ 0x00000008,
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+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x03000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x04102006,
+ 0x00041020,
+ 0x01C98C98,
+ 0x3F400000,
+ 0x3F3F1F3F,
+ 0x0000001F,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000001,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x76543201,
+ 0x00040198,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00040700,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000002,
+ 0x00000000,
+ 0x00000000,
+ 0x0001F7C2,
+ 0x00020002,
+ 0x00000000,
+ 0x00001142,
+ 0x03020000,
+ 0x00000080,
+ 0x03900390,
+ 0x03900390,
+ 0x03900390,
+ 0x03900390,
+ 0x03000300,
+ 0x03000300,
+ 0x00000300,
+ 0x00000300,
+ 0x00000300,
+ 0x00000300,
+ 0x3183BF77,
+ 0x00000000,
+ 0x0C000DFF,
+ 0x30000DFF,
+ 0x3F0DFF11,
+ 0x01990000,
+ 0x780DFFCC,
+ 0x00000C11,
+ 0x00018011,
+ 0x0089FF00,
+ 0x000C3F11,
+ 0x01990000,
+ 0x000C3F91,
+ 0x01990000,
+ 0x3F0DFF11,
+ 0x01990000,
+ 0x00018011,
+ 0x0089FF00,
+ 0x20040004,
+};
+
+static struct reginitdata ctl_regs = {
+ .regs = DDRSS_ctlReg,
+ .num = ARRAY_SIZE(DDRSS_ctlReg),
+};
+
+static struct reginitdata pi_regs = {
+ .regs = DDRSS_phyIndepReg,
+ .num = ARRAY_SIZE(DDRSS_phyIndepReg),
+};
+
+static struct reginitdata phy_regs = {
+ .regs = DDRSS_phyReg,
+ .num = ARRAY_SIZE(DDRSS_phyReg),
+};
+
+static struct k3_ddr_initdata initdata = {
+ .ctl_regs = &ctl_regs,
+ .pi_regs = &pi_regs,
+ .phy_regs = &phy_regs,
+ .freq0 = 25000000,
+ .freq1 = DDRSS_PLL_FREQUENCY_1,
+ .freq2 = DDRSS_PLL_FREQUENCY_2,
+ .fhs_cnt = DDRSS_PLL_FHS_CNT,
+};
+
+void am625sip_sk_ddr_init(void)
+{
+ k3_ddrss_init(&initdata);
+}
diff --git a/arch/arm/boards/am625-sk/ddr.h b/arch/arm/boards/am625-sk/ddr.h
new file mode 100644
index 0000000000..22d2f5b718
--- /dev/null
+++ b/arch/arm/boards/am625-sk/ddr.h
@@ -0,0 +1,7 @@
+#ifndef __AM625_SK_DDR_H
+#define __AM625_SK_DDR_H
+
+void am625_sk_ddr_init(void);
+void am625sip_sk_ddr_init(void);
+
+#endif /* __AM625_SK_DDR_H */
diff --git a/arch/arm/boards/am625-sk/entry-r5.S b/arch/arm/boards/am625-sk/entry-r5.S
new file mode 100644
index 0000000000..e724e5550c
--- /dev/null
+++ b/arch/arm/boards/am625-sk/entry-r5.S
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <linux/linkage.h>
+
+#define SRAM_BASE 0x43c00000
+
+#define STACK_TOP SRAM_BASE + 0x3d000
+
+.arm
+.section .text_head_entry_start_am625_sk_r5;
+
+ENTRY(start_am625_sk_r5)
+ ldr r3, =STACK_TOP
+ mov sp, r3
+ ldr pc, _reset_am625_sk
+
+_reset_am625_sk: .word SRAM_BASE + am625_sk_r5_entry
+
+ENDPROC(start_am625_sk_r5)
+
+.section .text_head_entry_start_am625sip_sk_r5;
+
+ENTRY(start_am625sip_sk_r5)
+ ldr r3, =STACK_TOP
+ mov sp, r3
+ ldr pc, _reset_am625sip_sk
+
+_reset_am625sip_sk: .word SRAM_BASE + am625sip_sk_r5_entry
+
+ENDPROC(start_am625sip_sk_r5)
diff --git a/arch/arm/boards/am625-sk/entry.S b/arch/arm/boards/am625-sk/entry.S
new file mode 100644
index 0000000000..5fc9297d50
--- /dev/null
+++ b/arch/arm/boards/am625-sk/entry.S
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <linux/linkage.h>
+#include <asm/barebox-arm64.h>
+#include <asm/image.h>
+
+#define IMAGE_FLAGS \
+ (ARM64_IMAGE_FLAG_PAGE_SIZE_4K << ARM64_IMAGE_FLAG_PAGE_SIZE_SHIFT) | \
+ (ARM64_IMAGE_FLAG_PHYS_BASE << ARM64_IMAGE_FLAG_PHYS_BASE_SHIFT)
+
+.section .text_head_entry_start_vivavis_cu33d
+ENTRY("start_am625_sk")
+ adr x1, 0 /* code0 */
+ b 2f /* code1 */
+ .xword 0x80000 /* Image load offset */
+ .xword _barebox_image_size /* Effective Image size */
+ .xword IMAGE_FLAGS /* Kernel flags */
+ .xword 0 /* reserved */
+ .xword 0 /* reserved */
+ .xword 0 /* reserved */
+ .ascii ARM64_IMAGE_MAGIC /* magic number */
+ .int 0 /* reserved (PE-COFF offset) */
+ .asciz "barebox" /* unused for now */
+2:
+ mov sp, x1
+ /* Stack now grows into the 0x80000 image load offset specified
+ * above. This is more than enough until FDT /memory is decoded.
+ */
+ b am625_sk
+ENTRY_PROC_END(start_am625_sk)
diff --git a/arch/arm/boards/am625-sk/lowlevel.c b/arch/arm/boards/am625-sk/lowlevel.c
new file mode 100644
index 0000000000..5c1c38e325
--- /dev/null
+++ b/arch/arm/boards/am625-sk/lowlevel.c
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <common.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <mach/k3/debug_ll.h>
+#include <debug_ll.h>
+#include <pbl.h>
+#include <cache.h>
+#include <mach/k3/r5.h>
+#include <pbl/handoff-data.h>
+#include <compressed-dtb.h>
+#include <mach/k3/common.h>
+
+#include "ddr.h"
+
+/* Called from assembly */
+void am625_sk(void *dtb);
+
+static noinline void am625_sk_continue(void *dtb)
+{
+ unsigned long membase = 0x80000000, memsize;
+ extern char __dtb_z_k3_am625_sk_start[];
+ unsigned int size;
+
+ memsize = am625_sdram_size();
+
+ pr_info("Detected DRAM size: %ldMiB\n", memsize >> 20);
+
+ if (memsize > SZ_2G)
+ memsize = SZ_2G; /* only need initial memory here */
+
+ if (memsize == SZ_512M)
+ memsize = SZ_512M - 0x04000000; /* substract space needed for TF-A, OP-TEE, ... */
+
+ if (blob_is_valid_fdt_ptr(dtb, membase, memsize, &size))
+ handoff_data_add(HANDOFF_DATA_EXTERNAL_DT, dtb, size);
+
+ barebox_arm_entry(membase, memsize, __dtb_z_k3_am625_sk_start);
+}
+
+void am625_sk(void *dtb)
+{
+ putc_ll('>');
+
+ arm_cpu_lowlevel_init();
+
+ relocate_to_current_adr();
+
+ setup_c();
+
+ am625_sk_continue(dtb);
+}
+
+static noinline void am625_sk_r5_continue(void)
+{
+ extern char __dtb_z_k3_am625_r5_sk_start[];
+
+ pbl_set_putc((void *)debug_ll_ns16550_putc, IOMEM(AM62X_UART_UART0_BASE));
+
+ putc_ll('>');
+
+ k3_mpu_setup_regions();
+
+ am625_early_init();
+ am625_sk_ddr_init();
+
+ barebox_arm_entry(0x80000000, SZ_2G, __dtb_z_k3_am625_r5_sk_start);
+}
+
+void am625_sk_r5_entry(void);
+
+void am625_sk_r5_entry(void)
+{
+ k3_ctrl_mmr_unlock();
+
+ writel(0x00050000, 0xf41c8);
+ writel(0x00010000, 0xf41cc);
+
+ k3_debug_ll_init(IOMEM(AM62X_UART_UART0_BASE));
+
+ relocate_to_current_adr();
+ setup_c();
+
+ am625_sk_r5_continue();
+}
+
+static noinline void am625sip_sk_r5_continue(void)
+{
+ extern char __dtb_z_k3_am625sip_r5_sk_start[];
+
+ pbl_set_putc((void *)debug_ll_ns16550_putc, IOMEM(AM62X_UART_UART0_BASE));
+
+ putc_ll('>');
+
+ k3_mpu_setup_regions();
+
+ am625_early_init();
+ am625sip_sk_ddr_init();
+
+ barebox_arm_entry(0x80000000, SZ_512M - 0x04000000, __dtb_z_k3_am625sip_r5_sk_start);
+}
+
+void am625sip_sk_r5_entry(void);
+
+void am625sip_sk_r5_entry(void)
+{
+ k3_ctrl_mmr_unlock();
+
+ writel(0x00050000, 0xf41c8);
+ writel(0x00010000, 0xf41cc);
+
+ k3_debug_ll_init(IOMEM(AM62X_UART_UART0_BASE));
+
+ relocate_to_current_adr();
+ setup_c();
+
+ am625sip_sk_r5_continue();
+}
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2352b6ef09..48b2824fc1 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -6,6 +6,7 @@ obj- += dummy.o
lwl-$(CONFIG_MACH_ADVANTECH_ROM_742X) += imx6dl-advantech-rom-7421.dtb.o
lwl-$(CONFIG_MACH_AFI_GF) += am335x-afi-gf.dtb.o
+lwl-$(CONFIG_MACH_AM625_SK) += k3-am625-sk.dtb.o k3-am625-r5-sk.dtb.o k3-am625sip-r5-sk.dtb.o
lwl-$(CONFIG_MACH_BEAGLEBONE) += am335x-bone.dtb.o am335x-boneblack.dtb.o am335x-bone-common.dtb.o
lwl-$(CONFIG_MACH_BEAGLEPLAY) += k3-am625-beagleplay.dtb.o k3-am625-r5-beagleplay.dtb.o
lwl-$(CONFIG_MACH_CLEP7212) += ep7212-clep7212.dtb.o
diff --git a/arch/arm/dts/k3-am625-r5-sk.dts b/arch/arm/dts/k3-am625-r5-sk.dts
new file mode 100644
index 0000000000..97b281729b
--- /dev/null
+++ b/arch/arm/dts/k3-am625-r5-sk.dts
@@ -0,0 +1,4 @@
+/dts-v1/;
+
+#include "k3-am625-sk.dts"
+#include "k3-am625-r5.dtsi"
diff --git a/arch/arm/dts/k3-am625-sk.dts b/arch/arm/dts/k3-am625-sk.dts
new file mode 100644
index 0000000000..1982c34388
--- /dev/null
+++ b/arch/arm/dts/k3-am625-sk.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include <arm64/ti/k3-am625-sk.dts>
+#include "k3-am625.dtsi"
+
+/*
+ * DRAM size differs between board variants. Real size is read from DDRSS
+ */
+/delete-node/ &{/memory@80000000};
diff --git a/arch/arm/dts/k3-am625sip-r5-sk.dts b/arch/arm/dts/k3-am625sip-r5-sk.dts
new file mode 100644
index 0000000000..97b281729b
--- /dev/null
+++ b/arch/arm/dts/k3-am625sip-r5-sk.dts
@@ -0,0 +1,4 @@
+/dts-v1/;
+
+#include "k3-am625-sk.dts"
+#include "k3-am625-r5.dtsi"
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index 2ea9f32696..51b02b697c 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -16,6 +16,7 @@ config MACH_K3_CORTEX_R5
select ELF
select K3_DDRSS
depends on 32BIT
+ select ARM_USE_COMPRESSED_DTB
default y
config MACH_K3_CORTEX_A
@@ -24,6 +25,11 @@ config MACH_K3_CORTEX_A
depends on 64BIT
default y
+config MACH_AM625_SK
+ bool "TI AM625 SK"
+ help
+ Say Y here if you are using a TI AM625 SK board
+
config MACH_BEAGLEPLAY
bool "BeagleBoard BeaglePlay"
help
diff --git a/images/Makefile.k3 b/images/Makefile.k3
index 6ca0851e1a..b182b06701 100644
--- a/images/Makefile.k3
+++ b/images/Makefile.k3
@@ -5,6 +5,11 @@
ifdef CONFIG_MACH_K3_CORTEX_A
+## TI am625(sip)-SK ##
+pblb-$(CONFIG_MACH_AM625_SK) += start_am625_sk
+FILE_barebox-am625-sk.img = start_am625_sk.pblb
+image-$(CONFIG_MACH_AM625_SK) += barebox-am625-sk.img
+
## BeaglePlay ##
pblb-$(CONFIG_MACH_BEAGLEPLAY) += start_beagleplay
FILE_barebox-beagleplay.img = start_beagleplay.pblb
@@ -26,6 +31,27 @@ INNERDATA_am625=$(srctree)/firmware/ti-fs-firmware-am62x-hs-fs-cert.bin
KEY_custmpk=$(srctree)/arch/arm/mach-k3/custMpk.pem
KEY_degenerate=$(srctree)/arch/arm/mach-k3/ti-degenerate-key.pem
+## TI am625(sip)-SK ##
+SYSFW_start_am625_sk_r5.pblb.k3img=$(SYSFW_am625_hs_fs)
+SYSFWDATA_start_am625_sk_r5.pblb.k3img=$(SYSFWDATA_am625)
+DMDATA_start_am625_sk_r5.pblb.k3img=$(DMDATA_am625)
+INNERDATA_start_am625_sk_r5.pblb.k3img=$(INNERDATA_am625)
+KEY_start_am625_sk_r5.pblb.k3img=$(KEY_custmpk)
+
+pblb-$(CONFIG_MACH_AM625_SK) += start_am625_sk_r5
+FILE_barebox-am625-sk-r5.img = start_am625_sk_r5.pblb.k3img
+image-$(CONFIG_MACH_AM625_SK) += barebox-am625-sk-r5.img
+
+SYSFW_start_am625sip_sk_r5.pblb.k3img=$(SYSFW_am625_hs_fs)
+SYSFWDATA_start_am625sip_sk_r5.pblb.k3img=$(SYSFWDATA_am625)
+DMDATA_start_am625sip_sk_r5.pblb.k3img=$(DMDATA_am625)
+INNERDATA_start_am625sip_sk_r5.pblb.k3img=$(INNERDATA_am625)
+KEY_start_am625sip_sk_r5.pblb.k3img=$(KEY_custmpk)
+
+pblb-$(CONFIG_MACH_AM625_SK) += start_am625sip_sk_r5
+FILE_barebox-am625sip-sk-r5.img = start_am625sip_sk_r5.pblb.k3img
+image-$(CONFIG_MACH_AM625_SK) += barebox-am625sip-sk-r5.img
+
## BeaglePlay ##
SYSFW_start_beagleplay_r5.pblb.k3img=$(SYSFW_am625_gp)
SYSFWDATA_start_beagleplay_r5.pblb.k3img=$(SYSFWDATA_am625)
--
2.39.5
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v3 00/23] ARM: K3: Add R5 boot support
2025-01-13 11:26 [PATCH v3 00/23] ARM: K3: Add R5 boot support Sascha Hauer
` (21 preceding siblings ...)
2025-01-13 11:27 ` [PATCH v3 23/23] ARM: k3: am625-sk board support Sascha Hauer
@ 2025-01-14 8:32 ` Sascha Hauer
22 siblings, 0 replies; 26+ messages in thread
From: Sascha Hauer @ 2025-01-14 8:32 UTC (permalink / raw)
To: open list:BAREBOX, Sascha Hauer
On Mon, 13 Jan 2025 12:26:47 +0100, Sascha Hauer wrote:
> So far we only supported the TI K3 SoCs booting 2nd stage after U-Boot.
> This series adds full boot support for K3 SoCs, or more specifically,
> the AM625 SoC.
>
>
Applied, thanks!
[01/23] ARM: add ARMv7R MPU support
https://git.pengutronix.de/cgit/barebox/commit/?id=20a8958e0a67 (link may not be stable)
[02/23] lib/rationale: compile for pbl
https://git.pengutronix.de/cgit/barebox/commit/?id=d68c949537f5 (link may not be stable)
[04/23] ARM: move ARM_CPU_PART_* defines to header
https://git.pengutronix.de/cgit/barebox/commit/?id=c27b06e5d318 (link may not be stable)
[05/23] nommu_v7_vectors_init: disable for r5
https://git.pengutronix.de/cgit/barebox/commit/?id=5ccc4e4a21ea (link may not be stable)
[06/23] clocksource: timer-ti-dm: add support for K3 SoCs
https://git.pengutronix.de/cgit/barebox/commit/?id=2b390d5a649f (link may not be stable)
[07/23] ARM: K3: mount /boot even with env handling disabled
https://git.pengutronix.de/cgit/barebox/commit/?id=2aae4a687287 (link may not be stable)
[08/23] clk: add K3 clk driver
https://git.pengutronix.de/cgit/barebox/commit/?id=657d39593b2f (link may not be stable)
[09/23] pmdomain: add K3 driver
https://git.pengutronix.de/cgit/barebox/commit/?id=9f1a0e6e3635 (link may not be stable)
[10/23] rproc: add K3 arm64 rproc driver
https://git.pengutronix.de/cgit/barebox/commit/?id=61f81b932adf (link may not be stable)
[11/23] ARM: k3: add k3_debug_ll_init()
https://git.pengutronix.de/cgit/barebox/commit/?id=bce0ba123e7c (link may not be stable)
[12/23] ARM: K3: use debug_ll code for regular PBL console
https://git.pengutronix.de/cgit/barebox/commit/?id=90cfb1651e5f (link may not be stable)
[13/23] elf: use iomem regions as fallback when loading to non-sdram memory
https://git.pengutronix.de/cgit/barebox/commit/?id=520eb1225c6b (link may not be stable)
[14/23] rproc: add K3 system_controller
https://git.pengutronix.de/cgit/barebox/commit/?id=1bd00031e3c6 (link may not be stable)
[15/23] firmware: ti_sci: add function to get global handle
https://git.pengutronix.de/cgit/barebox/commit/?id=6cbfc1370d28 (link may not be stable)
[16/23] ARM: k3: Add initial r5 support
https://git.pengutronix.de/cgit/barebox/commit/?id=c6840f7a1a48 (link may not be stable)
[17/23] scripts: k3: add script to generate cfg files from yaml
https://git.pengutronix.de/cgit/barebox/commit/?id=de445696adf0 (link may not be stable)
[18/23] ARM: k3: Add k3img tool
https://git.pengutronix.de/cgit/barebox/commit/?id=cf9081dff9fb (link may not be stable)
[19/23] ARM: beagleplay: add Cortex-R5 boot support
https://git.pengutronix.de/cgit/barebox/commit/?id=216fc9b4efaf (link may not be stable)
[20/23] Documentation: add build documentation for TI K3 SoCs
https://git.pengutronix.de/cgit/barebox/commit/?id=32a8e25abea8 (link may not be stable)
[21/23] ARM: am625: disable secondary watchdogs
https://git.pengutronix.de/cgit/barebox/commit/?id=ded22be60797 (link may not be stable)
[22/23] ARM: k3: Add DRAM size detection
https://git.pengutronix.de/cgit/barebox/commit/?id=322380802713 (link may not be stable)
[23/23] ARM: k3: am625-sk board support
https://git.pengutronix.de/cgit/barebox/commit/?id=be8f0946ea1e (link may not be stable)
Best regards,
--
Sascha Hauer <s.hauer@pengutronix.de>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v3 17/23] scripts: k3: add script to generate cfg files from yaml
2025-01-13 11:27 ` [PATCH v3 17/23] scripts: k3: add script to generate cfg files from yaml Sascha Hauer
@ 2025-01-14 9:29 ` Ahmad Fatoum
2025-01-14 9:38 ` Sascha Hauer
0 siblings, 1 reply; 26+ messages in thread
From: Ahmad Fatoum @ 2025-01-14 9:29 UTC (permalink / raw)
To: Sascha Hauer, open list:BAREBOX
Hi,
On 13.01.25 12:27, Sascha Hauer wrote:
> The K3 images need some config binary snippets. In U-Boot these snippets
> are generated from board specific YAML files using binman. This patch
> adds a small python which does the same for barebox. The python script
> is based on the corresponding binman code in U-Boot.
>
> The YAML files are board specific in U-Boot, but mostly are identical
> for all boards of a specific SoC type, so we provide common SoC specific
> YAML files in barebox for now.
I thought the YAML files are only required for the Cortex-R5? This adds
a yamllint dependency to multi_v8_defconfig now:
K3CFG arch/arm/mach-k3/combined-dm-cfg-am625.k3cfg
K3CFG arch/arm/mach-k3/combined-sysfw-cfg-am625.k3cfg
Traceback (most recent call last):
File "/src/barebox-sandbox/scripts/ti-board-config.py", line 13, in <module>
Traceback (most recent call last):
File "/src/barebox-sandbox/scripts/ti-board-config.py", line 13, in <module>
import yamllint
ModuleNotFoundError: No module named 'yamllint'
import yamllint
ModuleNotFoundError: No module named 'yamllint'
Thanks,
Ahmad
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> arch/arm/mach-k3/Makefile | 16 +
> arch/arm/mach-k3/board-cfg-am625.yaml | 36 ++
> arch/arm/mach-k3/pm-cfg-am625.yaml | 12 +
> arch/arm/mach-k3/rm-cfg-am625.yaml | 981 ++++++++++++++++++++++++++++++++++
> arch/arm/mach-k3/schema.yaml | 436 +++++++++++++++
> arch/arm/mach-k3/sec-cfg-am625.yaml | 379 +++++++++++++
> scripts/Makefile.lib | 3 +
> scripts/ti-board-config.py | 170 ++++++
> 8 files changed, 2033 insertions(+)
>
> diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
> index 0efc1e0239..6e105095da 100644
> --- a/arch/arm/mach-k3/Makefile
> +++ b/arch/arm/mach-k3/Makefile
> @@ -1,2 +1,18 @@
> obj-y += common.o
> obj-pbl-$(CONFIG_MACH_K3_CORTEX_R5) += r5.o
> +
> +extra-y += combined-dm-cfg-am625.k3cfg combined-sysfw-cfg-am625.k3cfg
> +
> +$(obj)/combined-dm-cfg-am625.k3cfg: $(srctree)/arch/arm/mach-k3/schema.yaml \
> + $(obj)/pm-cfg-am625.yaml \
> + $(obj)/rm-cfg-am625.yaml \
> + FORCE
> + $(call if_changed,k3_cfg)
> +
> +$(obj)/combined-sysfw-cfg-am625.k3cfg: $(srctree)/arch/arm/mach-k3/schema.yaml \
> + $(obj)/board-cfg-am625.yaml \
> + $(obj)/sec-cfg-am625.yaml \
> + $(obj)/pm-cfg-am625.yaml \
> + $(obj)/rm-cfg-am625.yaml \
> + FORCE
> + $(call if_changed,k3_cfg)
> diff --git a/arch/arm/mach-k3/board-cfg-am625.yaml b/arch/arm/mach-k3/board-cfg-am625.yaml
> new file mode 100644
> index 0000000000..45c89dd15f
> --- /dev/null
> +++ b/arch/arm/mach-k3/board-cfg-am625.yaml
> @@ -0,0 +1,36 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
> +#
> +# Board configuration for AM62
> +#
> +
> +---
> +
> +board-cfg:
> + rev:
> + boardcfg_abi_maj: 0x0
> + boardcfg_abi_min: 0x1
> + control:
> + subhdr:
> + magic: 0xC1D3
> + size: 7
> + main_isolation_enable: 0x5A
> + main_isolation_hostid: 0x2
> + secproxy:
> + subhdr:
> + magic: 0x1207
> + size: 7
> + scaling_factor: 0x1
> + scaling_profile: 0x1
> + disable_main_nav_secure_proxy: 0
> + msmc:
> + subhdr:
> + magic: 0xA5C3
> + size: 5
> + msmc_cache_size: 0x0
> + debug_cfg:
> + subhdr:
> + magic: 0x020C
> + size: 8
> + trace_dst_enables: 0x00
> + trace_src_enables: 0x00
> diff --git a/arch/arm/mach-k3/pm-cfg-am625.yaml b/arch/arm/mach-k3/pm-cfg-am625.yaml
> new file mode 100644
> index 0000000000..9853a25eb8
> --- /dev/null
> +++ b/arch/arm/mach-k3/pm-cfg-am625.yaml
> @@ -0,0 +1,12 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
> +#
> +# Power management configuration for AM62
> +#
> +
> +---
> +
> +pm-cfg:
> + rev:
> + boardcfg_abi_maj: 0x0
> + boardcfg_abi_min: 0x1
> diff --git a/arch/arm/mach-k3/rm-cfg-am625.yaml b/arch/arm/mach-k3/rm-cfg-am625.yaml
> new file mode 100644
> index 0000000000..725f7c83f0
> --- /dev/null
> +++ b/arch/arm/mach-k3/rm-cfg-am625.yaml
> @@ -0,0 +1,981 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
> +#
> +# Resource management configuration for AM62X
> +#
> +
> +---
> +
> +rm-cfg:
> + rm_boardcfg:
> + rev:
> + boardcfg_abi_maj: 0x0
> + boardcfg_abi_min: 0x1
> + host_cfg:
> + subhdr:
> + magic: 0x4C41
> + size: 356
> + host_cfg_entries:
> + - # 1
> + host_id: 12
> + allowed_atype: 0x2A
> + allowed_qos: 0xAAAA
> + allowed_orderid: 0xAAAAAAAA
> + allowed_priority: 0xAAAA
> + allowed_sched_priority: 0xAA
> + - # 2
> + host_id: 30
> + allowed_atype: 0x2A
> + allowed_qos: 0xAAAA
> + allowed_orderid: 0xAAAAAAAA
> + allowed_priority: 0xAAAA
> + allowed_sched_priority: 0xAA
> + - # 3
> + host_id: 36
> + allowed_atype: 0x2A
> + allowed_qos: 0xAAAA
> + allowed_orderid: 0xAAAAAAAA
> + allowed_priority: 0xAAAA
> + allowed_sched_priority: 0xAA
> + - # 4
> + host_id: 0
> + allowed_atype: 0
> + allowed_qos: 0
> + allowed_orderid: 0
> + allowed_priority: 0
> + allowed_sched_priority: 0
> + - # 5
> + host_id: 0
> + allowed_atype: 0
> + allowed_qos: 0
> + allowed_orderid: 0
> + allowed_priority: 0
> + allowed_sched_priority: 0
> + - # 6
> + host_id: 0
> + allowed_atype: 0
> + allowed_qos: 0
> + allowed_orderid: 0
> + allowed_priority: 0
> + allowed_sched_priority: 0
> + - # 7
> + host_id: 0
> + allowed_atype: 0
> + allowed_qos: 0
> + allowed_orderid: 0
> + allowed_priority: 0
> + allowed_sched_priority: 0
> + - # 8
> + host_id: 0
> + allowed_atype: 0
> + allowed_qos: 0
> + allowed_orderid: 0
> + allowed_priority: 0
> + allowed_sched_priority: 0
> + - # 9
> + host_id: 0
> + allowed_atype: 0
> + allowed_qos: 0
> + allowed_orderid: 0
> + allowed_priority: 0
> + allowed_sched_priority: 0
> + - # 10
> + host_id: 0
> + allowed_atype: 0
> + allowed_qos: 0
> + allowed_orderid: 0
> + allowed_priority: 0
> + allowed_sched_priority: 0
> + - # 11
> + host_id: 0
> + allowed_atype: 0
> + allowed_qos: 0
> + allowed_orderid: 0
> + allowed_priority: 0
> + allowed_sched_priority: 0
> + - # 12
> + host_id: 0
> + allowed_atype: 0
> + allowed_qos: 0
> + allowed_orderid: 0
> + allowed_priority: 0
> + allowed_sched_priority: 0
> + - # 13
> + host_id: 0
> + allowed_atype: 0
> + allowed_qos: 0
> + allowed_orderid: 0
> + allowed_priority: 0
> + allowed_sched_priority: 0
> + - # 14
> + host_id: 0
> + allowed_atype: 0
> + allowed_qos: 0
> + allowed_orderid: 0
> + allowed_priority: 0
> + allowed_sched_priority: 0
> + - # 15
> + host_id: 0
> + allowed_atype: 0
> + allowed_qos: 0
> + allowed_orderid: 0
> + allowed_priority: 0
> + allowed_sched_priority: 0
> + - # 16
> + host_id: 0
> + allowed_atype: 0
> + allowed_qos: 0
> + allowed_orderid: 0
> + allowed_priority: 0
> + allowed_sched_priority: 0
> + - # 17
> + host_id: 0
> + allowed_atype: 0
> + allowed_qos: 0
> + allowed_orderid: 0
> + allowed_priority: 0
> + allowed_sched_priority: 0
> + - # 18
> + host_id: 0
> + allowed_atype: 0
> + allowed_qos: 0
> + allowed_orderid: 0
> + allowed_priority: 0
> + allowed_sched_priority: 0
> + - # 19
> + host_id: 0
> + allowed_atype: 0
> + allowed_qos: 0
> + allowed_orderid: 0
> + allowed_priority: 0
> + allowed_sched_priority: 0
> + - # 20
> + host_id: 0
> + allowed_atype: 0
> + allowed_qos: 0
> + allowed_orderid: 0
> + allowed_priority: 0
> + allowed_sched_priority: 0
> + - # 21
> + host_id: 0
> + allowed_atype: 0
> + allowed_qos: 0
> + allowed_orderid: 0
> + allowed_priority: 0
> + allowed_sched_priority: 0
> + - # 22
> + host_id: 0
> + allowed_atype: 0
> + allowed_qos: 0
> + allowed_orderid: 0
> + allowed_priority: 0
> + allowed_sched_priority: 0
> + - # 23
> + host_id: 0
> + allowed_atype: 0
> + allowed_qos: 0
> + allowed_orderid: 0
> + allowed_priority: 0
> + allowed_sched_priority: 0
> + - # 24
> + host_id: 0
> + allowed_atype: 0
> + allowed_qos: 0
> + allowed_orderid: 0
> + allowed_priority: 0
> + allowed_sched_priority: 0
> + - # 25
> + host_id: 0
> + allowed_atype: 0
> + allowed_qos: 0
> + allowed_orderid: 0
> + allowed_priority: 0
> + allowed_sched_priority: 0
> + - # 26
> + host_id: 0
> + allowed_atype: 0
> + allowed_qos: 0
> + allowed_orderid: 0
> + allowed_priority: 0
> + allowed_sched_priority: 0
> + - # 27
> + host_id: 0
> + allowed_atype: 0
> + allowed_qos: 0
> + allowed_orderid: 0
> + allowed_priority: 0
> + allowed_sched_priority: 0
> + - # 28
> + host_id: 0
> + allowed_atype: 0
> + allowed_qos: 0
> + allowed_orderid: 0
> + allowed_priority: 0
> + allowed_sched_priority: 0
> + - # 29
> + host_id: 0
> + allowed_atype: 0
> + allowed_qos: 0
> + allowed_orderid: 0
> + allowed_priority: 0
> + allowed_sched_priority: 0
> + - # 30
> + host_id: 0
> + allowed_atype: 0
> + allowed_qos: 0
> + allowed_orderid: 0
> + allowed_priority: 0
> + allowed_sched_priority: 0
> + - # 31
> + host_id: 0
> + allowed_atype: 0
> + allowed_qos: 0
> + allowed_orderid: 0
> + allowed_priority: 0
> + allowed_sched_priority: 0
> + - # 32
> + host_id: 0
> + allowed_atype: 0
> + allowed_qos: 0
> + allowed_orderid: 0
> + allowed_priority: 0
> + allowed_sched_priority: 0
> + resasg:
> + subhdr:
> + magic: 0x7B25
> + size: 8
> + resasg_entries_size: 976
> + reserved: 0
> + resasg_entries:
> + -
> + start_resource: 0
> + num_resource: 16
> + type: 64
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 16
> + num_resource: 4
> + type: 64
> + host_id: 35
> + reserved: 0
> + -
> + start_resource: 16
> + num_resource: 4
> + type: 64
> + host_id: 36
> + reserved: 0
> + -
> + start_resource: 20
> + num_resource: 22
> + type: 64
> + host_id: 30
> + reserved: 0
> + -
> + start_resource: 0
> + num_resource: 16
> + type: 192
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 34
> + num_resource: 2
> + type: 192
> + host_id: 30
> + reserved: 0
> + -
> + start_resource: 0
> + num_resource: 2
> + type: 320
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 2
> + num_resource: 2
> + type: 320
> + host_id: 35
> + reserved: 0
> + -
> + start_resource: 2
> + num_resource: 2
> + type: 320
> + host_id: 36
> + reserved: 0
> + -
> + start_resource: 4
> + num_resource: 4
> + type: 320
> + host_id: 30
> + reserved: 0
> + -
> + start_resource: 0
> + num_resource: 26
> + type: 384
> + host_id: 128
> + reserved: 0
> + -
> + start_resource: 50176
> + num_resource: 164
> + type: 1666
> + host_id: 128
> + reserved: 0
> + -
> + start_resource: 0
> + num_resource: 1
> + type: 1667
> + host_id: 128
> + reserved: 0
> + -
> + start_resource: 0
> + num_resource: 18
> + type: 1677
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 18
> + num_resource: 6
> + type: 1677
> + host_id: 35
> + reserved: 0
> + -
> + start_resource: 18
> + num_resource: 6
> + type: 1677
> + host_id: 36
> + reserved: 0
> + -
> + start_resource: 24
> + num_resource: 2
> + type: 1677
> + host_id: 30
> + reserved: 0
> + -
> + start_resource: 26
> + num_resource: 6
> + type: 1677
> + host_id: 128
> + reserved: 0
> + -
> + start_resource: 54
> + num_resource: 18
> + type: 1678
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 72
> + num_resource: 6
> + type: 1678
> + host_id: 35
> + reserved: 0
> + -
> + start_resource: 72
> + num_resource: 6
> + type: 1678
> + host_id: 36
> + reserved: 0
> + -
> + start_resource: 78
> + num_resource: 2
> + type: 1678
> + host_id: 30
> + reserved: 0
> + -
> + start_resource: 80
> + num_resource: 2
> + type: 1678
> + host_id: 128
> + reserved: 0
> + -
> + start_resource: 32
> + num_resource: 12
> + type: 1679
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 44
> + num_resource: 6
> + type: 1679
> + host_id: 35
> + reserved: 0
> + -
> + start_resource: 44
> + num_resource: 6
> + type: 1679
> + host_id: 36
> + reserved: 0
> + -
> + start_resource: 50
> + num_resource: 2
> + type: 1679
> + host_id: 30
> + reserved: 0
> + -
> + start_resource: 52
> + num_resource: 2
> + type: 1679
> + host_id: 128
> + reserved: 0
> + -
> + start_resource: 0
> + num_resource: 18
> + type: 1696
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 18
> + num_resource: 6
> + type: 1696
> + host_id: 35
> + reserved: 0
> + -
> + start_resource: 18
> + num_resource: 6
> + type: 1696
> + host_id: 36
> + reserved: 0
> + -
> + start_resource: 24
> + num_resource: 2
> + type: 1696
> + host_id: 30
> + reserved: 0
> + -
> + start_resource: 26
> + num_resource: 6
> + type: 1696
> + host_id: 128
> + reserved: 0
> + -
> + start_resource: 0
> + num_resource: 18
> + type: 1697
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 18
> + num_resource: 6
> + type: 1697
> + host_id: 35
> + reserved: 0
> + -
> + start_resource: 18
> + num_resource: 6
> + type: 1697
> + host_id: 36
> + reserved: 0
> + -
> + start_resource: 24
> + num_resource: 2
> + type: 1697
> + host_id: 30
> + reserved: 0
> + -
> + start_resource: 26
> + num_resource: 2
> + type: 1697
> + host_id: 128
> + reserved: 0
> + -
> + start_resource: 0
> + num_resource: 12
> + type: 1698
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 12
> + num_resource: 6
> + type: 1698
> + host_id: 35
> + reserved: 0
> + -
> + start_resource: 12
> + num_resource: 6
> + type: 1698
> + host_id: 36
> + reserved: 0
> + -
> + start_resource: 18
> + num_resource: 2
> + type: 1698
> + host_id: 30
> + reserved: 0
> + -
> + start_resource: 20
> + num_resource: 2
> + type: 1698
> + host_id: 128
> + reserved: 0
> + -
> + start_resource: 5
> + num_resource: 35
> + type: 1802
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 44
> + num_resource: 36
> + type: 1802
> + host_id: 35
> + reserved: 0
> + -
> + start_resource: 44
> + num_resource: 36
> + type: 1802
> + host_id: 36
> + reserved: 0
> + -
> + start_resource: 168
> + num_resource: 8
> + type: 1802
> + host_id: 30
> + reserved: 0
> + -
> + start_resource: 13
> + num_resource: 512
> + type: 1805
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 525
> + num_resource: 256
> + type: 1805
> + host_id: 35
> + reserved: 0
> + -
> + start_resource: 525
> + num_resource: 256
> + type: 1805
> + host_id: 36
> + reserved: 0
> + -
> + start_resource: 781
> + num_resource: 128
> + type: 1805
> + host_id: 30
> + reserved: 0
> + -
> + start_resource: 909
> + num_resource: 627
> + type: 1805
> + host_id: 128
> + reserved: 0
> + -
> + start_resource: 0
> + num_resource: 1024
> + type: 1807
> + host_id: 128
> + reserved: 0
> + -
> + start_resource: 4096
> + num_resource: 29
> + type: 1808
> + host_id: 128
> + reserved: 0
> + -
> + start_resource: 4608
> + num_resource: 99
> + type: 1809
> + host_id: 128
> + reserved: 0
> + -
> + start_resource: 5120
> + num_resource: 24
> + type: 1810
> + host_id: 128
> + reserved: 0
> + -
> + start_resource: 5632
> + num_resource: 51
> + type: 1811
> + host_id: 128
> + reserved: 0
> + -
> + start_resource: 6144
> + num_resource: 51
> + type: 1812
> + host_id: 128
> + reserved: 0
> + -
> + start_resource: 6656
> + num_resource: 51
> + type: 1813
> + host_id: 128
> + reserved: 0
> + -
> + start_resource: 8192
> + num_resource: 32
> + type: 1814
> + host_id: 128
> + reserved: 0
> + -
> + start_resource: 8704
> + num_resource: 32
> + type: 1815
> + host_id: 128
> + reserved: 0
> + -
> + start_resource: 9216
> + num_resource: 32
> + type: 1816
> + host_id: 128
> + reserved: 0
> + -
> + start_resource: 9728
> + num_resource: 22
> + type: 1817
> + host_id: 128
> + reserved: 0
> + -
> + start_resource: 10240
> + num_resource: 22
> + type: 1818
> + host_id: 128
> + reserved: 0
> + -
> + start_resource: 10752
> + num_resource: 22
> + type: 1819
> + host_id: 128
> + reserved: 0
> + -
> + start_resource: 11264
> + num_resource: 28
> + type: 1820
> + host_id: 128
> + reserved: 0
> + -
> + start_resource: 11776
> + num_resource: 28
> + type: 1821
> + host_id: 128
> + reserved: 0
> + -
> + start_resource: 12288
> + num_resource: 28
> + type: 1822
> + host_id: 128
> + reserved: 0
> + -
> + start_resource: 0
> + num_resource: 1
> + type: 1923
> + host_id: 128
> + reserved: 0
> + -
> + start_resource: 0
> + num_resource: 10
> + type: 1936
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 10
> + num_resource: 3
> + type: 1936
> + host_id: 35
> + reserved: 0
> + -
> + start_resource: 10
> + num_resource: 3
> + type: 1936
> + host_id: 36
> + reserved: 0
> + -
> + start_resource: 13
> + num_resource: 3
> + type: 1936
> + host_id: 30
> + reserved: 0
> + -
> + start_resource: 16
> + num_resource: 3
> + type: 1936
> + host_id: 128
> + reserved: 0
> + -
> + start_resource: 19
> + num_resource: 64
> + type: 1937
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 19
> + num_resource: 64
> + type: 1937
> + host_id: 36
> + reserved: 0
> + -
> + start_resource: 83
> + num_resource: 8
> + type: 1938
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 91
> + num_resource: 8
> + type: 1939
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 99
> + num_resource: 10
> + type: 1942
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 109
> + num_resource: 3
> + type: 1942
> + host_id: 35
> + reserved: 0
> + -
> + start_resource: 109
> + num_resource: 3
> + type: 1942
> + host_id: 36
> + reserved: 0
> + -
> + start_resource: 112
> + num_resource: 3
> + type: 1942
> + host_id: 30
> + reserved: 0
> + -
> + start_resource: 115
> + num_resource: 3
> + type: 1942
> + host_id: 128
> + reserved: 0
> + -
> + start_resource: 118
> + num_resource: 16
> + type: 1943
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 118
> + num_resource: 16
> + type: 1943
> + host_id: 36
> + reserved: 0
> + -
> + start_resource: 134
> + num_resource: 8
> + type: 1944
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 134
> + num_resource: 8
> + type: 1945
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 142
> + num_resource: 8
> + type: 1946
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 142
> + num_resource: 8
> + type: 1947
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 0
> + num_resource: 10
> + type: 1955
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 10
> + num_resource: 3
> + type: 1955
> + host_id: 35
> + reserved: 0
> + -
> + start_resource: 10
> + num_resource: 3
> + type: 1955
> + host_id: 36
> + reserved: 0
> + -
> + start_resource: 13
> + num_resource: 3
> + type: 1955
> + host_id: 30
> + reserved: 0
> + -
> + start_resource: 16
> + num_resource: 3
> + type: 1955
> + host_id: 128
> + reserved: 0
> + -
> + start_resource: 19
> + num_resource: 8
> + type: 1956
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 19
> + num_resource: 8
> + type: 1956
> + host_id: 36
> + reserved: 0
> + -
> + start_resource: 27
> + num_resource: 1
> + type: 1957
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 28
> + num_resource: 1
> + type: 1958
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 0
> + num_resource: 10
> + type: 1961
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 10
> + num_resource: 3
> + type: 1961
> + host_id: 35
> + reserved: 0
> + -
> + start_resource: 10
> + num_resource: 3
> + type: 1961
> + host_id: 36
> + reserved: 0
> + -
> + start_resource: 13
> + num_resource: 3
> + type: 1961
> + host_id: 30
> + reserved: 0
> + -
> + start_resource: 16
> + num_resource: 3
> + type: 1961
> + host_id: 128
> + reserved: 0
> + -
> + start_resource: 0
> + num_resource: 10
> + type: 1962
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 10
> + num_resource: 3
> + type: 1962
> + host_id: 35
> + reserved: 0
> + -
> + start_resource: 10
> + num_resource: 3
> + type: 1962
> + host_id: 36
> + reserved: 0
> + -
> + start_resource: 13
> + num_resource: 3
> + type: 1962
> + host_id: 30
> + reserved: 0
> + -
> + start_resource: 16
> + num_resource: 3
> + type: 1962
> + host_id: 128
> + reserved: 0
> + -
> + start_resource: 19
> + num_resource: 1
> + type: 1963
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 19
> + num_resource: 1
> + type: 1963
> + host_id: 36
> + reserved: 0
> + -
> + start_resource: 19
> + num_resource: 16
> + type: 1964
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 19
> + num_resource: 16
> + type: 1964
> + host_id: 36
> + reserved: 0
> + -
> + start_resource: 20
> + num_resource: 1
> + type: 1965
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 35
> + num_resource: 8
> + type: 1966
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 21
> + num_resource: 1
> + type: 1967
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 35
> + num_resource: 8
> + type: 1968
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 22
> + num_resource: 1
> + type: 1969
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 43
> + num_resource: 8
> + type: 1970
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 23
> + num_resource: 1
> + type: 1971
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 43
> + num_resource: 8
> + type: 1972
> + host_id: 12
> + reserved: 0
> + -
> + start_resource: 0
> + num_resource: 1
> + type: 2112
> + host_id: 128
> + reserved: 0
> + -
> + start_resource: 2
> + num_resource: 2
> + type: 2122
> + host_id: 12
> + reserved: 0
> diff --git a/arch/arm/mach-k3/schema.yaml b/arch/arm/mach-k3/schema.yaml
> new file mode 100644
> index 0000000000..c8dd2e79e7
> --- /dev/null
> +++ b/arch/arm/mach-k3/schema.yaml
> @@ -0,0 +1,436 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
> +#
> +# Config schema for TI K3 devices
> +#
> +
> +---
> +
> +definitions:
> + u8:
> + type: integer
> + minimum: 0
> + maximum: 0xff
> + u16:
> + type: integer
> + minimum: 0
> + maximum: 0xffff
> + u32:
> + type: integer
> + minimum: 0
> + maximum: 0xffffffff
> +
> +
> +
> +type: object
> +properties:
> + pm-cfg:
> + type: object
> + properties:
> + rev:
> + type: object
> + properties:
> + boardcfg_abi_maj:
> + $ref: "#/definitions/u8"
> + boardcfg_abi_min:
> + $ref: "#/definitions/u8"
> + board-cfg:
> + type: object
> + properties:
> + rev:
> + type: object
> + properties:
> + boardcfg_abi_maj:
> + $ref: "#/definitions/u8"
> + boardcfg_abi_min:
> + $ref: "#/definitions/u8"
> + control:
> + type: object
> + properties:
> + subhdr:
> + type: object
> + properties:
> + magic:
> + $ref: "#/definitions/u16"
> + size:
> + $ref: "#/definitions/u16"
> + main_isolation_enable:
> + $ref: "#/definitions/u8"
> + main_isolation_hostid:
> + $ref: "#/definitions/u16"
> +
> +
> + secproxy:
> + type: object
> + properties:
> + subhdr:
> + type: object
> + properties:
> + magic:
> + $ref: "#/definitions/u16"
> + size:
> + $ref: "#/definitions/u16"
> + scaling_factor:
> + $ref: "#/definitions/u8"
> + scaling_profile:
> + $ref: "#/definitions/u8"
> + disable_main_nav_secure_proxy:
> + $ref: "#/definitions/u8"
> +
> + msmc:
> + type: object
> + properties:
> + subhdr:
> + type: object
> + properties:
> + magic:
> + $ref: "#/definitions/u16"
> + size:
> + $ref: "#/definitions/u16"
> + msmc_cache_size:
> + $ref: "#/definitions/u8"
> + debug_cfg:
> + type: object
> + properties:
> + subhdr:
> + type: object
> + properties:
> + magic:
> + $ref: "#/definitions/u16"
> + size:
> + $ref: "#/definitions/u16"
> + trace_dst_enables:
> + $ref: "#/definitions/u16"
> + trace_src_enables:
> + $ref: "#/definitions/u16"
> +
> + sec-cfg:
> + type: object
> + properties:
> + rev:
> + type: object
> + properties:
> + boardcfg_abi_maj:
> + $ref: "#/definitions/u8"
> + boardcfg_abi_min:
> + $ref: "#/definitions/u8"
> +
> + processor_acl_list:
> + type: object
> + properties:
> + subhdr:
> + type: object
> + properties:
> + magic:
> + $ref: "#/definitions/u16"
> + size:
> + $ref: "#/definitions/u16"
> + proc_acl_entries:
> + type: array
> + minItems: 32
> + maxItems: 32
> + items:
> + type: object
> + properties:
> + processor_id:
> + $ref: "#/definitions/u8"
> + proc_access_master:
> + $ref: "#/definitions/u8"
> + proc_access_secondary:
> + type: array
> + minItems: 3
> + maxItems: 3
> + items:
> + $ref: "#/definitions/u8"
> + host_hierarchy:
> + type: object
> + properties:
> + subhdr:
> + type: object
> + properties:
> + magic:
> + $ref: "#/definitions/u16"
> + size:
> + $ref: "#/definitions/u16"
> + host_hierarchy_entries:
> + type: array
> + minItems: 32
> + maxItems: 32
> + items:
> + type: object
> + properties:
> + host_id:
> + $ref: "#/definitions/u8"
> + supervisor_host_id:
> + $ref: "#/definitions/u8"
> +
> + otp_config:
> + type: object
> + properties:
> + subhdr:
> + type: object
> + properties:
> + magic:
> + $ref: "#/definitions/u16"
> + size:
> + $ref: "#/definitions/u16"
> + otp_entry:
> + type: array
> + minItems: 32
> + maxItems: 32
> + items:
> + type: object
> + properties:
> + host_id:
> + $ref: "#/definitions/u8"
> + host_perms:
> + $ref: "#/definitions/u8"
> + write_host_id:
> + $ref: "#/definitions/u8"
> +
> + dkek_config:
> + type: object
> + properties:
> + subhdr:
> + type: object
> + properties:
> + magic:
> + $ref: "#/definitions/u16"
> + size:
> + $ref: "#/definitions/u16"
> + allowed_hosts:
> + type: array
> + minItems: 4
> + maxItems: 4
> + items:
> + $ref: "#/definitions/u8"
> + allow_dkek_export_tisci:
> + $ref: "#/definitions/u8"
> + rsvd:
> + type: array
> + minItems: 3
> + maxItems: 3
> + items:
> + $ref: "#/definitions/u8"
> +
> + sa2ul_cfg:
> + type: object
> + properties:
> + subhdr:
> + type: object
> + properties:
> + magic:
> + $ref: "#/definitions/u16"
> + size:
> + $ref: "#/definitions/u16"
> + rsvd:
> + type: array
> + minItems: 2
> + maxItems: 4
> + items:
> + $ref: "#/definitions/u8"
> + enable_saul_psil_global_config_writes:
> + $ref: "#/definitions/u8"
> + auth_resource_owner:
> + $ref: "#/definitions/u8"
> +
> + sec_dbg_config:
> + type: object
> + properties:
> + subhdr:
> + type: object
> + properties:
> + magic:
> + $ref: "#/definitions/u16"
> + size:
> + $ref: "#/definitions/u16"
> + allow_jtag_unlock:
> + $ref: "#/definitions/u8"
> + allow_wildcard_unlock:
> + $ref: "#/definitions/u8"
> + allowed_debug_level_rsvd:
> + $ref: "#/definitions/u8"
> + rsvd:
> + $ref: "#/definitions/u8"
> + min_cert_rev:
> + $ref: "#/definitions/u32"
> + jtag_unlock_hosts:
> + type: array
> + minItems: 4
> + maxItems: 4
> + items:
> + $ref: "#/definitions/u8"
> +
> +
> + sec_handover_cfg:
> + type: object
> + properties:
> + subhdr:
> + type: object
> + properties:
> + magic:
> + $ref: "#/definitions/u16"
> + size:
> + $ref: "#/definitions/u16"
> + handover_msg_sender:
> + $ref: "#/definitions/u8"
> + handover_to_host_id:
> + $ref: "#/definitions/u8"
> + rsvd:
> + type: array
> + minItems: 4
> + maxItems: 4
> + items:
> + $ref: "#/definitions/u8"
> +
> + rm-cfg:
> + type: object
> + properties:
> + rm_boardcfg:
> + type: object
> + properties:
> + rev:
> + type: object
> + properties:
> + boardcfg_abi_maj:
> + $ref: "#/definitions/u8"
> + boardcfg_abi_min:
> + $ref: "#/definitions/u8"
> +
> + host_cfg:
> + type: object
> + properties:
> + subhdr:
> + type: object
> + properties:
> + magic:
> + $ref: "#/definitions/u16"
> + size:
> + $ref: "#/definitions/u16"
> + host_cfg_entries:
> + type: array
> + minItems: 0
> + maxItems: 32
> + items:
> + type: object
> + properties:
> + host_id:
> + $ref: "#/definitions/u8"
> + allowed_atype:
> + $ref: "#/definitions/u8"
> + allowed_qos:
> + $ref: "#/definitions/u16"
> + allowed_orderid:
> + $ref: "#/definitions/u32"
> + allowed_priority:
> + $ref: "#/definitions/u16"
> + allowed_sched_priority:
> + $ref: "#/definitions/u8"
> + resasg:
> + type: object
> + properties:
> + subhdr:
> + type: object
> + properties:
> + magic:
> + $ref: "#/definitions/u16"
> + size:
> + $ref: "#/definitions/u16"
> + resasg_entries_size:
> + $ref: "#/definitions/u16"
> + reserved:
> + $ref: "#/definitions/u16"
> +
> + resasg_entries:
> + type: array
> + minItems: 0
> + maxItems: 468
> + items:
> + type: object
> + properties:
> + start_resource:
> + $ref: "#/definitions/u16"
> + num_resource:
> + $ref: "#/definitions/u16"
> + type:
> + $ref: "#/definitions/u16"
> + host_id:
> + $ref: "#/definitions/u8"
> + reserved:
> + $ref: "#/definitions/u8"
> +
> + tifs-rm-cfg:
> + type: object
> + properties:
> + rm_boardcfg:
> + type: object
> + properties:
> + rev:
> + type: object
> + properties:
> + boardcfg_abi_maj:
> + $ref: "#/definitions/u8"
> + boardcfg_abi_min:
> + $ref: "#/definitions/u8"
> +
> + host_cfg:
> + type: object
> + properties:
> + subhdr:
> + type: object
> + properties:
> + magic:
> + $ref: "#/definitions/u16"
> + size:
> + $ref: "#/definitions/u16"
> + host_cfg_entries:
> + type: array
> + minItems: 0
> + maxItems: 32
> + items:
> + type: object
> + properties:
> + host_id:
> + $ref: "#/definitions/u8"
> + allowed_atype:
> + $ref: "#/definitions/u8"
> + allowed_qos:
> + $ref: "#/definitions/u16"
> + allowed_orderid:
> + $ref: "#/definitions/u32"
> + allowed_priority:
> + $ref: "#/definitions/u16"
> + allowed_sched_priority:
> + $ref: "#/definitions/u8"
> + resasg:
> + type: object
> + properties:
> + subhdr:
> + type: object
> + properties:
> + magic:
> + $ref: "#/definitions/u16"
> + size:
> + $ref: "#/definitions/u16"
> + resasg_entries_size:
> + $ref: "#/definitions/u16"
> + reserved:
> + $ref: "#/definitions/u16"
> +
> + resasg_entries:
> + type: array
> + minItems: 0
> + maxItems: 468
> + items:
> + type: object
> + properties:
> + start_resource:
> + $ref: "#/definitions/u16"
> + num_resource:
> + $ref: "#/definitions/u16"
> + type:
> + $ref: "#/definitions/u16"
> + host_id:
> + $ref: "#/definitions/u8"
> + reserved:
> + $ref: "#/definitions/u8"
> diff --git a/arch/arm/mach-k3/sec-cfg-am625.yaml b/arch/arm/mach-k3/sec-cfg-am625.yaml
> new file mode 100644
> index 0000000000..088b2dbaf1
> --- /dev/null
> +++ b/arch/arm/mach-k3/sec-cfg-am625.yaml
> @@ -0,0 +1,379 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
> +#
> +# Security management configuration for AM62
> +#
> +
> +---
> +
> +sec-cfg:
> + rev:
> + boardcfg_abi_maj: 0x0
> + boardcfg_abi_min: 0x1
> + processor_acl_list:
> + subhdr:
> + magic: 0xF1EA
> + size: 164
> + proc_acl_entries:
> + - # 1
> + processor_id: 0
> + proc_access_master: 0
> + proc_access_secondary: [0, 0, 0]
> + - # 2
> + processor_id: 0
> + proc_access_master: 0
> + proc_access_secondary: [0, 0, 0]
> + - # 3
> + processor_id: 0
> + proc_access_master: 0
> + proc_access_secondary: [0, 0, 0]
> + - # 4
> + processor_id: 0
> + proc_access_master: 0
> + proc_access_secondary: [0, 0, 0]
> + - # 5
> + processor_id: 0
> + proc_access_master: 0
> + proc_access_secondary: [0, 0, 0]
> + - # 6
> + processor_id: 0
> + proc_access_master: 0
> + proc_access_secondary: [0, 0, 0]
> + - # 7
> + processor_id: 0
> + proc_access_master: 0
> + proc_access_secondary: [0, 0, 0]
> + - # 8
> + processor_id: 0
> + proc_access_master: 0
> + proc_access_secondary: [0, 0, 0]
> + - # 9
> + processor_id: 0
> + proc_access_master: 0
> + proc_access_secondary: [0, 0, 0]
> + - # 10
> + processor_id: 0
> + proc_access_master: 0
> + proc_access_secondary: [0, 0, 0]
> + - # 11
> + processor_id: 0
> + proc_access_master: 0
> + proc_access_secondary: [0, 0, 0]
> + - # 12
> + processor_id: 0
> + proc_access_master: 0
> + proc_access_secondary: [0, 0, 0]
> + - # 13
> + processor_id: 0
> + proc_access_master: 0
> + proc_access_secondary: [0, 0, 0]
> + - # 14
> + processor_id: 0
> + proc_access_master: 0
> + proc_access_secondary: [0, 0, 0]
> + - # 15
> + processor_id: 0
> + proc_access_master: 0
> + proc_access_secondary: [0, 0, 0]
> + - # 16
> + processor_id: 0
> + proc_access_master: 0
> + proc_access_secondary: [0, 0, 0]
> + - # 17
> + processor_id: 0
> + proc_access_master: 0
> + proc_access_secondary: [0, 0, 0]
> + - # 18
> + processor_id: 0
> + proc_access_master: 0
> + proc_access_secondary: [0, 0, 0]
> + - # 19
> + processor_id: 0
> + proc_access_master: 0
> + proc_access_secondary: [0, 0, 0]
> + - # 20
> + processor_id: 0
> + proc_access_master: 0
> + proc_access_secondary: [0, 0, 0]
> + - # 21
> + processor_id: 0
> + proc_access_master: 0
> + proc_access_secondary: [0, 0, 0]
> + - # 22
> + processor_id: 0
> + proc_access_master: 0
> + proc_access_secondary: [0, 0, 0]
> + - # 23
> + processor_id: 0
> + proc_access_master: 0
> + proc_access_secondary: [0, 0, 0]
> + - # 24
> + processor_id: 0
> + proc_access_master: 0
> + proc_access_secondary: [0, 0, 0]
> + - # 25
> + processor_id: 0
> + proc_access_master: 0
> + proc_access_secondary: [0, 0, 0]
> + - # 26
> + processor_id: 0
> + proc_access_master: 0
> + proc_access_secondary: [0, 0, 0]
> + - # 27
> + processor_id: 0
> + proc_access_master: 0
> + proc_access_secondary: [0, 0, 0]
> + - # 28
> + processor_id: 0
> + proc_access_master: 0
> + proc_access_secondary: [0, 0, 0]
> + - # 29
> + processor_id: 0
> + proc_access_master: 0
> + proc_access_secondary: [0, 0, 0]
> + - # 30
> + processor_id: 0
> + proc_access_master: 0
> + proc_access_secondary: [0, 0, 0]
> + - # 31
> + processor_id: 0
> + proc_access_master: 0
> + proc_access_secondary: [0, 0, 0]
> + - # 32
> + processor_id: 0
> + proc_access_master: 0
> + proc_access_secondary: [0, 0, 0]
> + host_hierarchy:
> + subhdr:
> + magic: 0x8D27
> + size: 68
> + host_hierarchy_entries:
> + - # 1
> + host_id: 0
> + supervisor_host_id: 0
> + - # 2
> + host_id: 0
> + supervisor_host_id: 0
> + - # 3
> + host_id: 0
> + supervisor_host_id: 0
> + - # 4
> + host_id: 0
> + supervisor_host_id: 0
> + - # 5
> + host_id: 0
> + supervisor_host_id: 0
> + - # 6
> + host_id: 0
> + supervisor_host_id: 0
> + - # 7
> + host_id: 0
> + supervisor_host_id: 0
> + - # 8
> + host_id: 0
> + supervisor_host_id: 0
> + - # 9
> + host_id: 0
> + supervisor_host_id: 0
> + - # 10
> + host_id: 0
> + supervisor_host_id: 0
> + - # 11
> + host_id: 0
> + supervisor_host_id: 0
> + - # 12
> + host_id: 0
> + supervisor_host_id: 0
> + - # 13
> + host_id: 0
> + supervisor_host_id: 0
> + - # 14
> + host_id: 0
> + supervisor_host_id: 0
> + - # 15
> + host_id: 0
> + supervisor_host_id: 0
> + - # 16
> + host_id: 0
> + supervisor_host_id: 0
> + - # 17
> + host_id: 0
> + supervisor_host_id: 0
> + - # 18
> + host_id: 0
> + supervisor_host_id: 0
> + - # 19
> + host_id: 0
> + supervisor_host_id: 0
> + - # 20
> + host_id: 0
> + supervisor_host_id: 0
> + - # 21
> + host_id: 0
> + supervisor_host_id: 0
> + - # 22
> + host_id: 0
> + supervisor_host_id: 0
> + - # 23
> + host_id: 0
> + supervisor_host_id: 0
> + - # 24
> + host_id: 0
> + supervisor_host_id: 0
> + - # 25
> + host_id: 0
> + supervisor_host_id: 0
> + - # 26
> + host_id: 0
> + supervisor_host_id: 0
> + - # 27
> + host_id: 0
> + supervisor_host_id: 0
> + - # 28
> + host_id: 0
> + supervisor_host_id: 0
> + - # 29
> + host_id: 0
> + supervisor_host_id: 0
> + - # 30
> + host_id: 0
> + supervisor_host_id: 0
> + - # 31
> + host_id: 0
> + supervisor_host_id: 0
> + - # 32
> + host_id: 0
> + supervisor_host_id: 0
> + otp_config:
> + subhdr:
> + magic: 0x4081
> + size: 69
> + write_host_id: 0
> + otp_entry:
> + - # 1
> + host_id: 0
> + host_perms: 0
> + - # 2
> + host_id: 0
> + host_perms: 0
> + - # 3
> + host_id: 0
> + host_perms: 0
> + - # 4
> + host_id: 0
> + host_perms: 0
> + - # 5
> + host_id: 0
> + host_perms: 0
> + - # 6
> + host_id: 0
> + host_perms: 0
> + - # 7
> + host_id: 0
> + host_perms: 0
> + - # 8
> + host_id: 0
> + host_perms: 0
> + - # 9
> + host_id: 0
> + host_perms: 0
> + - # 10
> + host_id: 0
> + host_perms: 0
> + - # 11
> + host_id: 0
> + host_perms: 0
> + - # 12
> + host_id: 0
> + host_perms: 0
> + - # 13
> + host_id: 0
> + host_perms: 0
> + - # 14
> + host_id: 0
> + host_perms: 0
> + - # 15
> + host_id: 0
> + host_perms: 0
> + - # 16
> + host_id: 0
> + host_perms: 0
> + - # 17
> + host_id: 0
> + host_perms: 0
> + - # 18
> + host_id: 0
> + host_perms: 0
> + - # 19
> + host_id: 0
> + host_perms: 0
> + - # 20
> + host_id: 0
> + host_perms: 0
> + - # 21
> + host_id: 0
> + host_perms: 0
> + - # 22
> + host_id: 0
> + host_perms: 0
> + - # 23
> + host_id: 0
> + host_perms: 0
> + - # 24
> + host_id: 0
> + host_perms: 0
> + - # 25
> + host_id: 0
> + host_perms: 0
> + - # 26
> + host_id: 0
> + host_perms: 0
> + - # 27
> + host_id: 0
> + host_perms: 0
> + - # 28
> + host_id: 0
> + host_perms: 0
> + - # 29
> + host_id: 0
> + host_perms: 0
> + - # 30
> + host_id: 0
> + host_perms: 0
> + - # 31
> + host_id: 0
> + host_perms: 0
> + - # 32
> + host_id: 0
> + host_perms: 0
> + dkek_config:
> + subhdr:
> + magic: 0x5170
> + size: 12
> + allowed_hosts: [128, 0, 0, 0]
> + allow_dkek_export_tisci: 0x5A
> + rsvd: [0, 0, 0]
> + sa2ul_cfg:
> + subhdr:
> + magic: 0x23BE
> + size: 0
> + auth_resource_owner: 0
> + enable_saul_psil_global_config_writes: 0x5A
> + rsvd: [0, 0]
> + sec_dbg_config:
> + subhdr:
> + magic: 0x42AF
> + size: 16
> + allow_jtag_unlock: 0x5A
> + allow_wildcard_unlock: 0x5A
> + allowed_debug_level_rsvd: 0
> + rsvd: 0
> + min_cert_rev: 0x0
> + jtag_unlock_hosts: [0, 0, 0, 0]
> + sec_handover_cfg:
> + subhdr:
> + magic: 0x608F
> + size: 10
> + handover_msg_sender: 0
> + handover_to_host_id: 0
> + rsvd: [0, 0, 0, 0]
> diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
> index c32adf07cc..6e8f1c8e9a 100644
> --- a/scripts/Makefile.lib
> +++ b/scripts/Makefile.lib
> @@ -539,6 +539,9 @@ quiet_cmd_check_missing_fw = # no message as we collect info for later
> $(OBJCOPY) -O binary --only-section=.missing_fw $3 $2.missing-firmware; \
> [ -s $2.missing-firmware ] || rm -f $2.missing-firmware
>
> +quiet_cmd_k3_cfg = K3CFG $@
> + cmd_k3_cfg = $(srctree)/scripts/ti-board-config.py $@ $(filter-out FORCE,$^)
> +
> quiet_cmd_imximage__S_dcd= DCD_S $@
> cmd_imximage_S_dcd= \
> ( \
> diff --git a/scripts/ti-board-config.py b/scripts/ti-board-config.py
> new file mode 100755
> index 0000000000..4b6214c299
> --- /dev/null
> +++ b/scripts/ti-board-config.py
> @@ -0,0 +1,170 @@
> +#!/usr/bin/env python3
> +# SPDX-License-Identifier: GPL-2.0+
> +# Copyright (c) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
> +# Written by Neha Malcom Francis <n-francis@ti.com>
> +#
> +# Entry-type module for generating schema validated TI board
> +# configuration binary
> +#
> +
> +import os
> +import struct
> +import yaml
> +import yamllint
> +import sys
> +
> +from jsonschema import validate
> +
> +from yamllint import config
> +
> +BOARDCFG = 0xB
> +BOARDCFG_SEC = 0xD
> +BOARDCFG_PM = 0xE
> +BOARDCFG_RM = 0xC
> +
> +class cfgentry:
> + def __init__(self, cfgtype, data):
> + self.cfgtype = cfgtype
> + self.data = data
> +
> +class Entry_ti_board_config:
> + def __init__(self, schema):
> + self._config = None
> + self._schema = None
> + self._fmt = '<HHHBB'
> + self._index = 0
> + self._sw_rev = 1
> + self._devgrp = 0
> + self.cfgentries = []
> + self.header = struct.pack('<BB', 4, 1)
> + self._binary_offset = len(self.header)
> + self._schema_file = schema
> +
> + def _convert_to_byte_chunk(self, val, data_type):
> + """Convert value into byte array
> +
> + Args:
> + val: value to convert into byte array
> + data_type: data type used in schema, supported data types are u8,
> + u16 and u32
> +
> + Returns:
> + array of bytes representing value
> + """
> + size = 0
> + if (data_type == '#/definitions/u8'):
> + size = 1
> + elif (data_type == '#/definitions/u16'):
> + size = 2
> + else:
> + size = 4
> + if type(val) == int:
> + br = val.to_bytes(size, byteorder='little')
> + return br
> +
> + def _compile_yaml(self, schema_yaml, file_yaml):
> + """Convert YAML file into byte array based on YAML schema
> +
> + Args:
> + schema_yaml: file containing YAML schema
> + file_yaml: file containing config to compile
> +
> + Returns:
> + array of bytes repesenting YAML file against YAML schema
> + """
> + br = bytearray()
> + for key, node in file_yaml.items():
> + node_schema = schema_yaml['properties'][key]
> + node_type = node_schema.get('type')
> + if not 'type' in node_schema:
> + br += self._convert_to_byte_chunk(node,
> + node_schema.get('$ref'))
> + elif node_type == 'object':
> + br += self._compile_yaml(node_schema, node)
> + elif node_type == 'array':
> + for item in node:
> + if not isinstance(item, dict):
> + br += self._convert_to_byte_chunk(
> + item, schema_yaml['properties'][key]['items']['$ref'])
> + else:
> + br += self._compile_yaml(node_schema.get('items'), item)
> + return br
> +
> + def _generate_binaries(self):
> + """Generate config binary artifacts from the loaded YAML configuration file
> +
> + Returns:
> + byte array containing config binary artifacts
> + or None if generation fails
> + """
> + cfg_binary = bytearray()
> + for key, node in self.file_yaml.items():
> + node_schema = self.schema_yaml['properties'][key]
> + br = self._compile_yaml(node_schema, node)
> + cfg_binary += br
> + return cfg_binary
> +
> + def _add_boardcfg(self, bcfgtype, bcfgdata):
> + """Add board config to combined board config binary
> +
> + Args:
> + bcfgtype (int): board config type
> + bcfgdata (byte array): board config data
> + """
> + size = len(bcfgdata)
> +
> + desc = struct.pack(self._fmt, bcfgtype,
> + self._binary_offset, size, self._devgrp, 0)
> + self._binary_offset += size
> + self._index += 1
> + return desc
> +
> + def add_data(self, configfile):
> + self._config_file = configfile
> + with open(self._config_file, 'r') as f:
> + self.file_yaml = yaml.safe_load(f)
> + with open(self._schema_file, 'r') as sch:
> + self.schema_yaml = yaml.safe_load(sch)
> +
> + if self.file_yaml.get('board-cfg') != None:
> + cfgtype = BOARDCFG
> + if self.file_yaml.get('sec-cfg') != None:
> + cfgtype = BOARDCFG_SEC
> + if self.file_yaml.get('pm-cfg') != None:
> + cfgtype = BOARDCFG_PM
> + if self.file_yaml.get('rm-cfg') != None:
> + cfgtype = BOARDCFG_RM
> +
> + yaml_config = config.YamlLintConfig("extends: default")
> + for p in yamllint.linter.run(open(self._config_file, "r"), yaml_config):
> + self.Raise(f"Yamllint error: {p.line}: {p.rule}")
> + try:
> + validate(self.file_yaml, self.schema_yaml)
> + except Exception as e:
> + self.Raise(f"Schema validation error: {e}")
> +
> + data = self._generate_binaries()
> + entry = cfgentry(cfgtype, data)
> + self.cfgentries.append(entry)
> + return data
> +
> + def save(self, filename):
> + with open(filename, "wb") as binary_file:
> + binary_file.write(self.header)
> + for i in self.cfgentries:
> + obj._binary_offset += 8
> + for i in self.cfgentries:
> + binary_file.write(self._add_boardcfg(i.cfgtype, i.data))
> + for i in self.cfgentries:
> + binary_file.write(i.data)
> + binary_file.close()
> +
> +outfile = sys.argv[1]
> +schema = sys.argv[2]
> +
> +obj = Entry_ti_board_config(schema)
> +
> +for i in sys.argv[3:]:
> + obj.add_data(i)
> +
> +obj.save(outfile)
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v3 17/23] scripts: k3: add script to generate cfg files from yaml
2025-01-14 9:29 ` Ahmad Fatoum
@ 2025-01-14 9:38 ` Sascha Hauer
0 siblings, 0 replies; 26+ messages in thread
From: Sascha Hauer @ 2025-01-14 9:38 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: open list:BAREBOX
On Tue, Jan 14, 2025 at 10:29:55AM +0100, Ahmad Fatoum wrote:
> Hi,
>
> On 13.01.25 12:27, Sascha Hauer wrote:
> > The K3 images need some config binary snippets. In U-Boot these snippets
> > are generated from board specific YAML files using binman. This patch
> > adds a small python which does the same for barebox. The python script
> > is based on the corresponding binman code in U-Boot.
> >
> > The YAML files are board specific in U-Boot, but mostly are identical
> > for all boards of a specific SoC type, so we provide common SoC specific
> > YAML files in barebox for now.
>
> I thought the YAML files are only required for the Cortex-R5?
Indeed. As said the extra-y below should be a
extra-$(CONFIG_MACH_K3_CORTEX_R5). I fixed this in the meantime.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2025-01-14 9:38 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2025-01-13 11:26 [PATCH v3 00/23] ARM: K3: Add R5 boot support Sascha Hauer
2025-01-13 11:26 ` [PATCH v3 01/23] ARM: add ARMv7R MPU support Sascha Hauer
2025-01-13 11:26 ` [PATCH v3 02/23] lib/rationale: compile for pbl Sascha Hauer
2025-01-13 11:26 ` [PATCH v3 04/23] ARM: move ARM_CPU_PART_* defines to header Sascha Hauer
2025-01-13 11:26 ` [PATCH v3 05/23] nommu_v7_vectors_init: disable for r5 Sascha Hauer
2025-01-13 11:26 ` [PATCH v3 06/23] clocksource: timer-ti-dm: add support for K3 SoCs Sascha Hauer
2025-01-13 11:26 ` [PATCH v3 07/23] ARM: K3: mount /boot even with env handling disabled Sascha Hauer
2025-01-13 11:26 ` [PATCH v3 08/23] clk: add K3 clk driver Sascha Hauer
2025-01-13 11:26 ` [PATCH v3 09/23] pmdomain: add K3 driver Sascha Hauer
2025-01-13 11:26 ` [PATCH v3 10/23] rproc: add K3 arm64 rproc driver Sascha Hauer
2025-01-13 11:26 ` [PATCH v3 11/23] ARM: k3: add k3_debug_ll_init() Sascha Hauer
2025-01-13 11:26 ` [PATCH v3 12/23] ARM: K3: use debug_ll code for regular PBL console Sascha Hauer
2025-01-13 11:27 ` [PATCH v3 13/23] elf: use iomem regions as fallback when loading to non-sdram memory Sascha Hauer
2025-01-13 11:27 ` [PATCH v3 14/23] rproc: add K3 system_controller Sascha Hauer
2025-01-13 11:27 ` [PATCH v3 15/23] firmware: ti_sci: add function to get global handle Sascha Hauer
2025-01-13 11:27 ` [PATCH v3 16/23] ARM: k3: Add initial r5 support Sascha Hauer
2025-01-13 11:27 ` [PATCH v3 17/23] scripts: k3: add script to generate cfg files from yaml Sascha Hauer
2025-01-14 9:29 ` Ahmad Fatoum
2025-01-14 9:38 ` Sascha Hauer
2025-01-13 11:27 ` [PATCH v3 18/23] ARM: k3: Add k3img tool Sascha Hauer
2025-01-13 11:27 ` [PATCH v3 19/23] ARM: beagleplay: add Cortex-R5 boot support Sascha Hauer
2025-01-13 11:27 ` [PATCH v3 20/23] Documentation: add build documentation for TI K3 SoCs Sascha Hauer
2025-01-13 11:27 ` [PATCH v3 21/23] ARM: am625: disable secondary watchdogs Sascha Hauer
2025-01-13 11:27 ` [PATCH v3 22/23] ARM: k3: Add DRAM size detection Sascha Hauer
2025-01-13 11:27 ` [PATCH v3 23/23] ARM: k3: am625-sk board support Sascha Hauer
2025-01-14 8:32 ` [PATCH v3 00/23] ARM: K3: Add R5 boot support Sascha Hauer
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