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Thu, 16 Jan 2025 09:02:08 -0800 (PST) Received: from localhost.localdomain ([95.161.223.172]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5439af7390dsm41795e87.200.2025.01.16.09.02.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jan 2025 09:02:07 -0800 (PST) From: Alexander Shiyan To: barebox@lists.infradead.org Cc: Alexander Shiyan Date: Thu, 16 Jan 2025 20:01:52 +0300 Message-Id: <20250116170154.104253-1-eagle.alexander923@gmail.com> X-Mailer: git-send-email 2.38.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250116_090212_849175_5964F319 X-CRM114-Status: GOOD ( 12.42 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.whiteo.stw.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-5.0 required=4.0 tests=AWL,BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: [PATCH 1/3] aiodev: rockchip_saradc: Add reset control support X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.whiteo.stw.pengutronix.de) This adds reset control support for the Rockchip ADC driver. Signed-off-by: Alexander Shiyan --- drivers/aiodev/rockchip_saradc.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/aiodev/rockchip_saradc.c b/drivers/aiodev/rockchip_saradc.c index 3c5c0e94da..b31804fc39 100644 --- a/drivers/aiodev/rockchip_saradc.c +++ b/drivers/aiodev/rockchip_saradc.c @@ -8,8 +8,9 @@ #include #include -#include #include +#include +#include #define SARADC_DATA 0x00 @@ -37,6 +38,7 @@ struct rockchip_saradc_data { struct clk *pclk; struct aiodevice aiodev; struct aiochannel *channels; + struct reset_control *reset; }; static inline void rockchip_saradc_reg_wr(struct rockchip_saradc_data *data, @@ -51,6 +53,13 @@ static inline u32 rockchip_saradc_reg_rd(struct rockchip_saradc_data *data, return readl(data->base + reg); } +static void rockchip_saradc_reset_controller(struct reset_control *reset) +{ + reset_control_assert(reset); + udelay(20); + reset_control_deassert(reset); +} + static int rockchip_saradc_read(struct aiochannel *chan, int *val) { struct rockchip_saradc_data *data; @@ -163,14 +172,20 @@ static int rockchip_saradc_probe(struct device *dev) rockchip_saradc_reg_wr(data, 0, SARADC_CTRL); + data->reset = reset_control_get(dev, "saradc-apb"); + ret = aiodevice_register(&data->aiodev); if (ret) goto fail_channels; + rockchip_saradc_reset_controller(data->reset); + dev_info(dev, "registered as %s\n", dev_name(&data->aiodev.dev)); + return 0; fail_channels: + reset_control_put(data->reset); kfree(data->channels); kfree(data->aiodev.channels); -- 2.38.2