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Tue, 21 Jan 2025 04:18:19 -0800 (PST) Received: from localhost.localdomain ([95.161.223.172]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5439af074b1sm1815419e87.16.2025.01.21.04.18.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jan 2025 04:18:17 -0800 (PST) From: Alexander Shiyan To: barebox@lists.infradead.org Cc: Alexander Shiyan Date: Tue, 21 Jan 2025 15:18:00 +0300 Message-Id: <20250121121800.2806881-3-eagle.alexander923@gmail.com> X-Mailer: git-send-email 2.38.2 In-Reply-To: <20250121121800.2806881-1-eagle.alexander923@gmail.com> References: <20250121121800.2806881-1-eagle.alexander923@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250121_041822_263145_14E186D6 X-CRM114-Status: GOOD ( 15.94 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.whiteo.stw.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-5.2 required=4.0 tests=AWL,BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: [PATCH v2 3/3] aiodev: rockchip_saradc: Add support for RK3588 X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.whiteo.stw.pengutronix.de) This adds RK3588 SARADC support to the driver. Signed-off-by: Alexander Shiyan --- drivers/aiodev/rockchip_saradc.c | 81 +++++++++++++++++++++++++++----- 1 file changed, 69 insertions(+), 12 deletions(-) diff --git a/drivers/aiodev/rockchip_saradc.c b/drivers/aiodev/rockchip_saradc.c index aac4a65218..152d38ecc5 100644 --- a/drivers/aiodev/rockchip_saradc.c +++ b/drivers/aiodev/rockchip_saradc.c @@ -9,18 +9,30 @@ #include #include #include +#include #include #include -#define SARADC_DATA 0x00 - -#define SARADC_CTRL 0x08 -#define SARADC_CTRL_IRQ_STATUS (1 << 6) -#define SARADC_CTRL_IRQ_ENABLE (1 << 5) -#define SARADC_CTRL_POWER_CTRL (1 << 3) -#define SARADC_CTRL_CHN_MASK 0x07 - -#define SARADC_DLY_PU_SOC 0x0c +/* v1 registers */ +#define SARADC_DATA 0x00 +#define SARADC_CTRL 0x08 +# define SARADC_CTRL_IRQ_STATUS (1 << 6) +# define SARADC_CTRL_IRQ_ENABLE (1 << 5) +# define SARADC_CTRL_POWER_CTRL (1 << 3) +#define SARADC_CTRL_CHN_MASK 0x07 +#define SARADC_DLY_PU_SOC 0x0c + +/* v2 registers */ +#define SARADC2_CONV_CON 0x000 +# define SARADC2_CONV_CHANNELS GENMASK(3, 0) +# define SARADC2_START BIT(4) +# define SARADC2_SINGLE_MODE BIT(5) +#define SARADC_T_PD_SOC 0x004 +#define SARADC_T_DAS_SOC 0x00c +#define SARADC2_END_INT_EN 0x104 +# define SARADC2_EN_END_INT BIT(0) +#define SARADC2_END_INT_ST 0x110 +#define SARADC2_DATA_BASE 0x120 #define SARADC_TIMEOUT_NS (100 * MSECOND) @@ -72,9 +84,7 @@ static void rockchip_saradc_init_v1(struct rockchip_saradc_data *data) static int rockchip_saradc_read_v1(struct aiochannel *chan, int *val) { struct rockchip_saradc_data *data; - u32 value = 0; - u32 control = 0; - u32 mask; + u32 value, control, mask; u64 start; data = container_of(chan->aiodev, struct rockchip_saradc_data, aiodev); @@ -103,6 +113,46 @@ static int rockchip_saradc_read_v1(struct aiochannel *chan, int *val) return 0; } +static int rockchip_saradc_read_v2(struct aiochannel *chan, int *val) +{ + struct rockchip_saradc_data *data; + u32 value, status, mask; + u64 start; + + data = container_of(chan->aiodev, struct rockchip_saradc_data, aiodev); + + rockchip_saradc_reset_controller(data->reset); + + rockchip_saradc_reg_wr(data, 0xc, SARADC_T_DAS_SOC); + rockchip_saradc_reg_wr(data, 0x20, SARADC_T_PD_SOC); + value = FIELD_PREP(SARADC2_EN_END_INT, 1); + value |= SARADC2_EN_END_INT << 16; + rockchip_saradc_reg_wr(data, value, SARADC2_END_INT_EN); + value = FIELD_PREP(SARADC2_START, 1) | + FIELD_PREP(SARADC2_SINGLE_MODE, 1) | + FIELD_PREP(SARADC2_CONV_CHANNELS, chan->index); + value |= (SARADC2_START | SARADC2_SINGLE_MODE | SARADC2_CONV_CHANNELS) << 16; + rockchip_saradc_reg_wr(data, value, SARADC2_CONV_CON); + + start = get_time_ns(); + do { + status = rockchip_saradc_reg_rd(data, SARADC2_END_INT_ST); + + if (is_timeout(start, SARADC_TIMEOUT_NS)) + return -ETIMEDOUT; + } while (!(status & SARADC2_EN_END_INT)); + + mask = (1 << data->config->num_bits) - 1; + value = rockchip_saradc_reg_rd(data, SARADC2_DATA_BASE + chan->index * 4); + value &= mask; + + rockchip_saradc_reg_wr(data, SARADC2_EN_END_INT, SARADC2_END_INT_ST); + + *val = (value * data->ref_voltage_mv) / mask; + + return 0; +} + static int rockchip_saradc_probe(struct device *dev) { struct rockchip_saradc_data *data; @@ -213,8 +263,15 @@ static const struct rockchip_saradc_cfg rk3568_saradc_cfg = { .read = rockchip_saradc_read_v1, }; +static const struct rockchip_saradc_cfg rk3588_saradc_cfg = { + .num_bits = 12, + .num_channels = 8, + .read = rockchip_saradc_read_v2, +}; + static const struct of_device_id of_rockchip_saradc_match[] = { { .compatible = "rockchip,rk3568-saradc", .data = &rk3568_saradc_cfg }, + { .compatible = "rockchip,rk3588-saradc", .data = &rk3588_saradc_cfg }, { /* end */ } }; MODULE_DEVICE_TABLE(of, of_rockchip_saradc_match); -- 2.38.2