[PATCH] mci: am654-sdhci: Clear SDHCI_CTRL_HISPD bit for some speed modes

[PATCH] mci: am654-sdhci: Clear SDHCI_CTRL_HISPD bit for some speed modes

[Sascha Hauer]

Normally we would set the SDHCI_CTRL_HISPD bit for MMC_TIMING_SD_HS and
MMC_TIMING_MMC_HS. This however doesn't seem to work on AM62x and AM62L
SoCs.

Based on U-Boot commit 27a87c834fd ("mmc: am654_sdhci: Fix HISPD bit
configuration in some lower speed modes") clear the SDHCI_CTRL_HISPD bit
in these modes. Unfortunately I can't find the information in the data
sheet referenced in that commit, so I can't verify it, but it seems
to be necessary not only on AM6548, but on other SoCs as well.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/mci/am654-sdhci.c | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/mci/am654-sdhci.c b/drivers/mci/am654-sdhci.c
index 2c1fa5d804..8d6fa9c999 100644
--- a/drivers/mci/am654-sdhci.c
+++ b/drivers/mci/am654-sdhci.c
@@ -520,10 +520,20 @@ static void am654_sdhci_set_ios(struct mci_host *mci, struct mci_ios *ios)
 
 	val = sdhci_read8(&plat->sdhci, SDHCI_HOST_CONTROL);
 
-	if (ios->clock > 26000000)
-		val |= SDHCI_CTRL_HISPD;
-	else
+	switch (ios->timing) {
+	/*
+	 * According to the data manual, HISPD bit
+	 * should not be set in these speed modes.
+	 */
+	case MMC_TIMING_SD_HS:
+	case MMC_TIMING_MMC_HS:
+	case MMC_TIMING_LEGACY:
 		val &= ~SDHCI_CTRL_HISPD;
+		break;
+	default:
+		val |= SDHCI_CTRL_HISPD;
+		break;
+	}
 
 	sdhci_write8(&plat->sdhci, SDHCI_HOST_CONTROL, val);
 
-- 
2.39.5