From: Sascha Hauer <s.hauer@pengutronix.de>
To: BAREBOX <barebox@lists.infradead.org>
Subject: [PATCH 18/31] ARM: dts: am62l: Add ethernet ports
Date: Wed, 28 May 2025 13:45:30 +0200 [thread overview]
Message-ID: <20250528-arm-k3-am62l-v1-18-3f88e6d10d99@pengutronix.de> (raw)
In-Reply-To: <20250528-arm-k3-am62l-v1-0-3f88e6d10d99@pengutronix.de>
The AM62l device trees are based on the upstream submission which
currently lack the ethernet ports. Add them from the downstream Linux
repository.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/dts/k3-am62l-main.dtsi | 95 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 95 insertions(+)
diff --git a/arch/arm/dts/k3-am62l-main.dtsi b/arch/arm/dts/k3-am62l-main.dtsi
index d161df3215c35a2d3de67e8ca021b9a9a89edb80..95d387afd14e4f85df022673b8100830cbc6c410 100644
--- a/arch/arm/dts/k3-am62l-main.dtsi
+++ b/arch/arm/dts/k3-am62l-main.dtsi
@@ -670,4 +670,99 @@ scmi_shmem: sram@0 {
reg = <0x0 0x100>;
};
};
+
+ main_pktdma: dma-controller@485c0000 {
+ compatible = "ti,am62l-dmss-pktdma";
+ reg = <0x00 0x485c0000 0x00 0x4000>,
+ <0x00 0x48900000 0x00 0x80000>,
+ <0x00 0x47200000 0x00 0x100000>;
+ reg-names = "gcfg", "chanrt", "ringrt";
+ #address-cells = <2>;
+ #dma-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map = <0 0 0 &gic500 0 0 GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 1 &gic500 0 0 GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 2 &gic500 0 0 GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 3 &gic500 0 0 GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 4 &gic500 0 0 GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 5 &gic500 0 0 GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 6 &gic500 0 0 GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 7 &gic500 0 0 GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 8 &gic500 0 0 GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 9 &gic500 0 0 GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 10 &gic500 0 0 GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 11 &gic500 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 12 &gic500 0 0 GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 13 &gic500 0 0 GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 64 &gic500 0 0 GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 65 &gic500 0 0 GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 66 &gic500 0 0 GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 67 &gic500 0 0 GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 68 &gic500 0 0 GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 69 &gic500 0 0 GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 70 &gic500 0 0 GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 71 &gic500 0 0 GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 72 &gic500 0 0 GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 73 &gic500 0 0 GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 74 &gic500 0 0 GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 75 &gic500 0 0 GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 76 &gic500 0 0 GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 77 &gic500 0 0 GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 78 &gic500 0 0 GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 79 &gic500 0 0 GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 96 &gic500 0 0 GIC_SPI 484 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ cpsw3g: ethernet@8000000 {
+ compatible = "ti,am642-cpsw-nuss";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x00 0x08000000 0x00 0x200000>;
+ reg-names = "cpsw_nuss";
+ ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>;
+ clocks = <&scmi_clk 9>;
+ clock-names = "fck";
+ power-domains = <&scmi_pds 3>;
+ dmas = <&main_pktdma 0xc600 15>,
+ <&main_pktdma 0xc601 15>,
+ <&main_pktdma 0xc602 15>,
+ <&main_pktdma 0xc603 15>,
+ <&main_pktdma 0xc604 15>,
+ <&main_pktdma 0xc605 15>,
+ <&main_pktdma 0xc606 15>,
+ <&main_pktdma 0xc607 15>,
+ <&main_pktdma 0x4600 15>;
+ dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
+ "tx7", "rx";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpsw_port1: port@1 {
+ reg = <1>;
+ ti,mac-only;
+ label = "port1";
+ phys = <&phy_gmii_sel 1>;
+ };
+
+ cpsw_port2: port@2 {
+ reg = <2>;
+ ti,mac-only;
+ label = "port2";
+ phys = <&phy_gmii_sel 2>;
+ };
+ };
+
+ cpsw3g_mdio: mdio@f00 {
+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+ reg = <0x00 0xf00 0x00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&scmi_clk 13 0>;
+ clock-names = "fck";
+ bus_freq = <1000000>;
+ status = "disabled";
+ };
+ };
};
--
2.39.5
next prev parent reply other threads:[~2025-05-28 12:04 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-28 11:45 [PATCH 00/31] ARM: K3: add support for AM62L Sascha Hauer
2025-05-28 11:45 ` [PATCH 01/31] scripts: k3img: remove duplicate case value Sascha Hauer
2025-05-28 11:45 ` [PATCH 02/31] ARM: K3: prepare support for other SoCs Sascha Hauer
2025-05-28 11:45 ` [PATCH 03/31] ARM: k3: make k3img destination addresses configurable Sascha Hauer
2025-05-28 11:45 ` [PATCH 04/31] ARM: dts: add k3-am62l dts(i) files Sascha Hauer
2025-05-28 11:45 ` [PATCH 05/31] ARM: dts: am62l: Fix assigned-clock-parents Sascha Hauer
2025-05-28 11:45 ` [PATCH 06/31] ARM: K3: add am62lx base support Sascha Hauer
2025-05-28 11:45 ` [PATCH 07/31] ARM: Makefile: descend into mach-* for cleaning Sascha Hauer
2025-05-28 11:45 ` [PATCH 08/31] ARM: k3: rename yaml files from am625 to am62x Sascha Hauer
2025-05-28 11:45 ` [PATCH 09/31] scripts/ti-board-config.py: fix length Sascha Hauer
2025-05-28 11:45 ` [PATCH 10/31] ARM: k3: add yaml files for AM62l Sascha Hauer
2025-05-28 11:45 ` [PATCH 11/31] k3: ringacc: pass ringrt address in struct k3_ringacc_init_data Sascha Hauer
2025-05-28 11:45 ` [PATCH 12/31] drivers: soc: ti: k3-ringacc: handle absence of tisci Sascha Hauer
2025-05-28 11:45 ` [PATCH 13/31] drivers: soc: ti: k3-ringacc: fix k3_ringacc_ring_reset_sci Sascha Hauer
2025-05-28 11:45 ` [PATCH 14/31] dma: ti: k3-psil: Add PSIL data for AM62L Sascha Hauer
2025-05-28 11:45 ` [PATCH 15/31] dma: ti: k3-udma: Refactor common bits for AM62L support Sascha Hauer
2025-05-28 11:45 ` [PATCH 16/31] dma: ti: k3-udma-common: Update common code for AM62L DMAs Sascha Hauer
2025-05-28 11:45 ` [PATCH 17/31] dma: ti: k3-udma-am62l: Add AM62L support DMA drivers Sascha Hauer
2025-05-28 11:45 ` Sascha Hauer [this message]
2025-05-28 11:45 ` [PATCH 19/31] ARM: dts: am62l evm: Add ethernet ports Sascha Hauer
2025-05-28 11:45 ` [PATCH 20/31] ARM: k3: am62l: add barebox specific am62l.dtsi Sascha Hauer
2025-05-28 11:45 ` [PATCH 21/31] net: davinci_mdio: Use fallback clock rate Sascha Hauer
2025-05-28 11:45 ` [PATCH 22/31] firmware: arm_scmi: Add support for clock parents Sascha Hauer
2025-05-28 11:45 ` [PATCH 23/31] clk: add struct clk_parent_data Sascha Hauer
2025-05-28 11:45 ` [PATCH 24/31] clk: arm_scmi: implement clock parent setting Sascha Hauer
2025-05-28 11:45 ` [PATCH 25/31] ARM: dts: am62l3-evm: add MMC aliases Sascha Hauer
2025-05-28 11:45 ` [PATCH 26/31] dma: ti: k3-udma: limit asel to am625 Sascha Hauer
2025-05-28 11:45 ` [PATCH 27/31] gpio: increase ARCH_NR_GPIOS to 512 Sascha Hauer
2025-05-28 11:45 ` [PATCH 28/31] ARM: dts: k3-am62l: reserve memory for TF-A Sascha Hauer
2025-05-28 11:45 ` [PATCH 29/31] scripts: k3img: make dmdata optional Sascha Hauer
2025-05-28 11:45 ` [PATCH 30/31] scripts: k3img: handle bootcore_opts Sascha Hauer
2025-05-28 11:45 ` [PATCH 31/31] ARM: k3: add AM62l3 EVM board support Sascha Hauer
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250528-arm-k3-am62l-v1-18-3f88e6d10d99@pengutronix.de \
--to=s.hauer@pengutronix.de \
--cc=barebox@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox