* [PATCH 00/31] ARM: K3: add support for AM62L
@ 2025-05-28 11:45 Sascha Hauer
2025-05-28 11:45 ` [PATCH 01/31] scripts: k3img: remove duplicate case value Sascha Hauer
` (30 more replies)
0 siblings, 31 replies; 32+ messages in thread
From: Sascha Hauer @ 2025-05-28 11:45 UTC (permalink / raw)
To: BAREBOX
The AM62L is a new SoC from TI similar to the AM625, but still needs
some work to support it.
While the peripherals are quite similar to AM625, TI restructured the
startup process. Unlike the AM625 we no longer start on the Cortex-R5
core, but instead directly on the first Cortex A53 core. The SDRAM setup
is no longer part of barebox, but instead done in the TF-A. The initial
image is composed of a BL1 and several binary-only blobs. The second
stage is directly the BL31 image and our barebox image.
The dts(i) are not yet upstream, but currently posted for review, so we
need to import them into barebox for now. I hope this will be obsolete
soon.
The DMA driver needs some adjustments for the AM62L, patches for this
are taken from the TI downstrem U-Boot and the TI downstream Linux
repository.
The first board supported is the AM62L EVM board.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
Sascha Hauer (31):
scripts: k3img: remove duplicate case value
ARM: K3: prepare support for other SoCs
ARM: k3: make k3img destination addresses configurable
ARM: dts: add k3-am62l dts(i) files
ARM: dts: am62l: Fix assigned-clock-parents
ARM: K3: add am62lx base support
ARM: Makefile: descend into mach-* for cleaning
ARM: k3: rename yaml files from am625 to am62x
scripts/ti-board-config.py: fix length
ARM: k3: add yaml files for AM62l
k3: ringacc: pass ringrt address in struct k3_ringacc_init_data
drivers: soc: ti: k3-ringacc: handle absence of tisci
drivers: soc: ti: k3-ringacc: fix k3_ringacc_ring_reset_sci
dma: ti: k3-psil: Add PSIL data for AM62L
dma: ti: k3-udma: Refactor common bits for AM62L support
dma: ti: k3-udma-common: Update common code for AM62L DMAs
dma: ti: k3-udma-am62l: Add AM62L support DMA drivers
ARM: dts: am62l: Add ethernet ports
ARM: dts: am62l evm: Add ethernet ports
ARM: k3: am62l: add barebox specific am62l.dtsi
net: davinci_mdio: Use fallback clock rate
firmware: arm_scmi: Add support for clock parents
clk: add struct clk_parent_data
clk: arm_scmi: implement clock parent setting
ARM: dts: am62l3-evm: add MMC aliases
dma: ti: k3-udma: limit asel to am625
gpio: increase ARCH_NR_GPIOS to 512
ARM: dts: k3-am62l: reserve memory for TF-A
scripts: k3img: make dmdata optional
scripts: k3img: handle bootcore_opts
ARM: k3: add AM62l3 EVM board support
arch/arm/Makefile | 4 +-
arch/arm/boards/Makefile | 1 +
arch/arm/boards/am625-sk/board.c | 2 +-
arch/arm/boards/am625-sk/lowlevel.c | 2 +-
arch/arm/boards/am62lx-evm/Makefile | 1 +
arch/arm/boards/am62lx-evm/lowlevel.c | 35 +
arch/arm/boards/beagleplay/lowlevel.c | 2 +-
arch/arm/dts/Makefile | 1 +
arch/arm/dts/k3-am62l-barebox.dtsi | 30 +
arch/arm/dts/k3-am62l-main.dtsi | 768 +++++++++++
arch/arm/dts/k3-am62l-thermal.dtsi | 25 +
arch/arm/dts/k3-am62l-wakeup.dtsi | 133 ++
arch/arm/dts/k3-am62l.dtsi | 121 ++
arch/arm/dts/k3-am62l3-evm.dts | 378 ++++++
arch/arm/dts/k3-am62l3.dtsi | 67 +
arch/arm/dts/k3-pinctrl.h | 7 +
arch/arm/mach-k3/Kconfig | 14 +
arch/arm/mach-k3/Makefile | 27 +-
arch/arm/mach-k3/am62lx.c | 155 +++
arch/arm/mach-k3/am62x.c | 256 ++++
.../{board-cfg-am625.yaml => board-cfg-am62x.yaml} | 0
arch/arm/mach-k3/common.c | 260 +---
arch/arm/mach-k3/ddrss.c | 12 +-
.../{pm-cfg-am625.yaml => pm-cfg-am62x.yaml} | 0
.../{rm-cfg-am625.yaml => rm-cfg-am62x.yaml} | 0
arch/arm/mach-k3/sec-cfg-am62l.yaml | 379 ++++++
.../{sec-cfg-am625.yaml => sec-cfg-am62x.yaml} | 0
drivers/clk/clk-scmi.c | 80 +-
drivers/dma/ti/Makefile | 2 +-
drivers/dma/ti/k3-psil-am62l.c | 50 +
drivers/dma/ti/k3-psil-priv.h | 1 +
drivers/dma/ti/k3-psil.c | 2 +
drivers/dma/ti/k3-udma-am62l.c | 593 ++++++++
drivers/dma/ti/k3-udma-common.c | 1188 ++++++++++++++++
drivers/dma/ti/k3-udma-hwdef.h | 7 +
drivers/dma/ti/k3-udma.c | 1434 +-------------------
drivers/dma/ti/k3-udma.h | 357 +++++
drivers/firmware/arm_scmi/clock.c | 179 ++-
drivers/net/davinci_mdio.c | 9 +-
drivers/soc/ti/k3-navss-ringacc.c | 161 ++-
images/Makefile.k3 | 113 +-
include/gpio.h | 2 +-
include/linux/clk.h | 13 +
include/linux/scmi_protocol.h | 6 +
include/mach/k3/common.h | 9 +-
include/soc/ti/k3-navss-ringacc.h | 4 +
scripts/k3img | 73 +-
scripts/ti-board-config.py | 5 +-
48 files changed, 5180 insertions(+), 1788 deletions(-)
---
base-commit: a123526affb9bb81e9d18f1260d4df350420a389
change-id: 20250527-arm-k3-am62l-f70117f397f5
Best regards,
--
Sascha Hauer <s.hauer@pengutronix.de>
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 01/31] scripts: k3img: remove duplicate case value
2025-05-28 11:45 [PATCH 00/31] ARM: K3: add support for AM62L Sascha Hauer
@ 2025-05-28 11:45 ` Sascha Hauer
2025-05-28 11:45 ` [PATCH 02/31] ARM: K3: prepare support for other SoCs Sascha Hauer
` (29 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Sascha Hauer @ 2025-05-28 11:45 UTC (permalink / raw)
To: BAREBOX
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
scripts/k3img | 5 -----
1 file changed, 5 deletions(-)
diff --git a/scripts/k3img b/scripts/k3img
index a514852fcdf6369c33b1e291b59c121badc6f4bd..f622f877cb89ce5604b8cb7651b3c23d3a5459be 100755
--- a/scripts/k3img
+++ b/scripts/k3img
@@ -25,11 +25,6 @@ while true; do
shift 2
continue
;;
- '--sysfw')
- sysfw="$2"
- shift 2
- continue
- ;;
'--dmdata')
dmdata="$2"
shift 2
--
2.39.5
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 02/31] ARM: K3: prepare support for other SoCs
2025-05-28 11:45 [PATCH 00/31] ARM: K3: add support for AM62L Sascha Hauer
2025-05-28 11:45 ` [PATCH 01/31] scripts: k3img: remove duplicate case value Sascha Hauer
@ 2025-05-28 11:45 ` Sascha Hauer
2025-05-28 11:45 ` [PATCH 03/31] ARM: k3: make k3img destination addresses configurable Sascha Hauer
` (28 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Sascha Hauer @ 2025-05-28 11:45 UTC (permalink / raw)
To: BAREBOX
This does several preparations for merging code supporting other K3
SoCs:
- Several functions that we prefixed with am625_ are common to am62x_ as
suggested by similar U-Boot code, so rename these functions accordingly
- Move am625 boot source detection from common.c to am62x.c
- Add a Kconfig symbol MACH_AM62X to be selected from the board Kconfig
variables.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/am625-sk/board.c | 2 +-
arch/arm/boards/am625-sk/lowlevel.c | 2 +-
arch/arm/boards/beagleplay/lowlevel.c | 2 +-
arch/arm/mach-k3/Kconfig | 5 +
arch/arm/mach-k3/Makefile | 1 +
arch/arm/mach-k3/am62x.c | 256 ++++++++++++++++++++++++++++++++++
arch/arm/mach-k3/common.c | 255 ---------------------------------
| 12 +-
include/mach/k3/common.h | 8 +-
9 files changed, 275 insertions(+), 268 deletions(-)
diff --git a/arch/arm/boards/am625-sk/board.c b/arch/arm/boards/am625-sk/board.c
index c716f30e693d6555436c63f9cb83f79235ac83d3..d2fca2dae12d1c8ac250f51f462876b58697ff6d 100644
--- a/arch/arm/boards/am625-sk/board.c
+++ b/arch/arm/boards/am625-sk/board.c
@@ -9,7 +9,7 @@
static int am625_sk_probe(struct device *dev)
{
- am625_enable_32k_crystal();
+ am62x_enable_32k_crystal();
k3_bbu_emmc_register("emmc", "/dev/mmc0", BBU_HANDLER_FLAG_DEFAULT);
diff --git a/arch/arm/boards/am625-sk/lowlevel.c b/arch/arm/boards/am625-sk/lowlevel.c
index 10da8731caa208edf7b77e21972110bada3cd949..b1b4c5153d4633b614232049376c804197684c9d 100644
--- a/arch/arm/boards/am625-sk/lowlevel.c
+++ b/arch/arm/boards/am625-sk/lowlevel.c
@@ -19,7 +19,7 @@ static noinline void am625_sk_continue(void)
unsigned long membase = 0x80000000, memsize;
extern char __dtb_z_k3_am625_sk_start[];
- memsize = am625_sdram_size();
+ memsize = am62x_sdram_size();
pr_info("Detected DRAM size: %ldMiB\n", memsize >> 20);
diff --git a/arch/arm/boards/beagleplay/lowlevel.c b/arch/arm/boards/beagleplay/lowlevel.c
index 94300175680dc217808516a3a3620e3d8604bb56..eec6f586fffc44d05045d221bccc1147fe288209 100644
--- a/arch/arm/boards/beagleplay/lowlevel.c
+++ b/arch/arm/boards/beagleplay/lowlevel.c
@@ -19,7 +19,7 @@ static noinline void beagleplay_continue(void)
unsigned long membase = 0x80000000, memsize;
extern char __dtb_k3_am625_beagleplay_start[];
- memsize = am625_sdram_size();
+ memsize = am62x_sdram_size();
barebox_arm_entry(membase, memsize, __dtb_k3_am625_beagleplay_start);
}
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index 3dcdb20186b6a7530446da32b94c77952bbad3aa..1c236ef7648869ff3605bfb379298f0e6e6f3305 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -3,6 +3,9 @@
menu "K3 boards"
depends on ARCH_K3
+config MACH_AM62X
+ bool
+
config MACH_K3_CORTEX_R5
bool
select CPU_V7
@@ -30,11 +33,13 @@ config MACH_K3_CORTEX_A
config MACH_AM625_SK
bool "TI AM625 SK"
+ select MACH_AM62X
help
Say Y here if you are using a TI AM625 SK board
config MACH_BEAGLEPLAY
bool "BeagleBoard BeaglePlay"
+ select MACH_AM62X
help
Say Y here if you are using a TI AM62x based BeaglePlay board
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index b1dfb66d740b0b26bdaecc7d70f8c9fbe62e1091..b81088007426a1e2a43d84a0d09b49525370c4bf 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -1,4 +1,5 @@
obj-y += common.o
+obj-$(CONFIG_MACH_AM62X) += am62x.o
obj-pbl-$(CONFIG_MACH_K3_CORTEX_R5) += r5.o
obj-pbl-y += ddrss.o
obj-$(CONFIG_BAREBOX_UPDATE) += bbu.o
diff --git a/arch/arm/mach-k3/am62x.c b/arch/arm/mach-k3/am62x.c
new file mode 100644
index 0000000000000000000000000000000000000000..57f8efd74bb5e6607f18ee9cd825d057e238150d
--- /dev/null
+++ b/arch/arm/mach-k3/am62x.c
@@ -0,0 +1,256 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <io.h>
+#include <of.h>
+#include <stdio.h>
+#include <pm_domain.h>
+#include <linux/bits.h>
+#include <linux/bitfield.h>
+#include <bootsource.h>
+#include <mach/k3/common.h>
+
+/* Primary BootMode devices */
+#define BOOT_DEVICE_RAM 0x00
+#define BOOT_DEVICE_OSPI 0x01
+#define BOOT_DEVICE_QSPI 0x02
+#define BOOT_DEVICE_SPI 0x03
+#define BOOT_DEVICE_ETHERNET_RGMII 0x04
+#define BOOT_DEVICE_ETHERNET_RMII 0x05
+#define BOOT_DEVICE_I2C 0x06
+#define BOOT_DEVICE_UART 0x07
+#define BOOT_DEVICE_MMC 0x08
+#define BOOT_DEVICE_EMMC 0x09
+
+#define BOOT_DEVICE_USB 0x0A
+#define BOOT_DEVICE_GPMC_NAND 0x0B
+#define BOOT_DEVICE_GPMC_NOR 0x0C
+#define BOOT_DEVICE_XSPI 0x0E
+#define BOOT_DEVICE_NOBOOT 0x0F
+
+/* Backup BootMode devices */
+#define BACKUP_BOOT_DEVICE_USB 0x01
+#define BACKUP_BOOT_DEVICE_UART 0x03
+#define BACKUP_BOOT_DEVICE_ETHERNET 0x04
+#define BACKUP_BOOT_DEVICE_MMC 0x05
+#define BACKUP_BOOT_DEVICE_SPI 0x06
+#define BACKUP_BOOT_DEVICE_I2C 0x07
+
+#define K3_PRIMARY_BOOTMODE 0x0
+
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE GENMASK(12, 10)
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG BIT(13)
+#define MAIN_DEVSTAT_BACKUP_USB_MODE BIT(0)
+
+static void am62x_get_backup_bootsource(u32 devstat, enum bootsource *src, int *instance)
+{
+ u32 bkup_bootmode = FIELD_GET(MAIN_DEVSTAT_BACKUP_BOOTMODE, devstat);
+ u32 bkup_bootmode_cfg = FIELD_GET(MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG, devstat);
+
+ *src = BOOTSOURCE_UNKNOWN;
+
+ switch (bkup_bootmode) {
+ case BACKUP_BOOT_DEVICE_UART:
+ *src = BOOTSOURCE_SERIAL;
+ return;
+ case BACKUP_BOOT_DEVICE_ETHERNET:
+ *src = BOOTSOURCE_NET;
+ return;
+ case BACKUP_BOOT_DEVICE_MMC:
+ if (bkup_bootmode_cfg) {
+ *src = BOOTSOURCE_MMC;
+ *instance = 1;
+ } else {
+ *src = BOOTSOURCE_MMC;
+ *instance = 0;
+ }
+ return;
+ case BACKUP_BOOT_DEVICE_SPI:
+ *src = BOOTSOURCE_SPI;
+ return;
+ case BACKUP_BOOT_DEVICE_I2C:
+ *src = BOOTSOURCE_I2C;
+ return;
+ case BACKUP_BOOT_DEVICE_USB:
+ if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE)
+ *src = BOOTSOURCE_USB;
+ else
+ *src = BOOTSOURCE_SERIAL;
+ return;
+ };
+}
+
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE GENMASK(6, 3)
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG GENMASK(9, 7)
+#define MAIN_DEVSTAT_PRIMARY_USB_MODE BIT(1)
+#define MAIN_DEVSTAT_PRIMARY_MMC_PORT BIT(2)
+
+static void am62x_get_primary_bootsource(u32 devstat, enum bootsource *src, int *instance)
+{
+ u32 bootmode = FIELD_GET(MAIN_DEVSTAT_PRIMARY_BOOTMODE, devstat);
+ u32 bootmode_cfg = FIELD_GET(MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG, devstat);
+
+ switch (bootmode) {
+ case BOOT_DEVICE_OSPI:
+ case BOOT_DEVICE_QSPI:
+ case BOOT_DEVICE_XSPI:
+ case BOOT_DEVICE_SPI:
+ *src = BOOTSOURCE_SPI;
+ return;
+ case BOOT_DEVICE_ETHERNET_RGMII:
+ case BOOT_DEVICE_ETHERNET_RMII:
+ *src = BOOTSOURCE_NET;
+ return;
+ case BOOT_DEVICE_EMMC:
+ *src = BOOTSOURCE_MMC;
+ *instance = 0;
+ return;
+ case BOOT_DEVICE_MMC:
+ if (bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT) {
+ *src = BOOTSOURCE_MMC;
+ *instance = 1;
+ } else {
+ *src = BOOTSOURCE_MMC;
+ *instance = 0;
+ }
+ return;
+ case BOOT_DEVICE_USB:
+ if (bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE)
+ *src = BOOTSOURCE_USB;
+ else
+ *src = BOOTSOURCE_SERIAL;
+ return;
+ case BOOT_DEVICE_NOBOOT:
+ *src = BOOTSOURCE_UNKNOWN;
+ return;
+ }
+}
+
+#define AM625_BOOT_PARAM_TABLE_INDEX_OCRAM IOMEM(0x43c3f290)
+
+#define AM625_WKUP_CTRL_MMR0_BASE IOMEM(0x43000000)
+#define AM625_CTRLMMR_MAIN_DEVSTAT (AM625_WKUP_CTRL_MMR0_BASE + 0x30)
+
+void am62x_get_bootsource(enum bootsource *src, int *instance)
+{
+ u32 bootmode = readl(AM625_BOOT_PARAM_TABLE_INDEX_OCRAM);
+ u32 devstat;
+
+ devstat = readl(AM625_CTRLMMR_MAIN_DEVSTAT);
+
+ if (bootmode == K3_PRIMARY_BOOTMODE)
+ am62x_get_primary_bootsource(devstat, src, instance);
+ else
+ am62x_get_backup_bootsource(devstat, src, instance);
+}
+
+bool k3_boot_is_emmc(void)
+{
+ u32 bootmode = readl(AM625_BOOT_PARAM_TABLE_INDEX_OCRAM);
+ u32 devstat = readl(AM625_CTRLMMR_MAIN_DEVSTAT);
+
+ if (bootmode != K3_PRIMARY_BOOTMODE)
+ return false;
+ if (FIELD_GET(MAIN_DEVSTAT_PRIMARY_BOOTMODE, devstat) != BOOT_DEVICE_EMMC)
+ return false;
+
+ return true;
+}
+
+static void of_delete_node_path(struct device_node *root, const char *path)
+{
+ struct device_node *np;
+
+ np = of_find_node_by_path_from(root, path);
+ of_delete_node(np);
+}
+
+#define MCU_CTRL_MMR0_BASE 0x04500000
+#define MCU_CTRL_LFXOSC_CTRL (MCU_CTRL_MMR0_BASE + 0x8038)
+#define MCU_CTRL_LFXOSC_32K_DISABLE_VAL BIT(7)
+#define MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL (0x3)
+#define MCU_CTRL_DEVICE_CLKOUT_32K_CTRL (MCU_CTRL_MMR0_BASE + 0x8058)
+
+void am62x_enable_32k_crystal(void)
+{
+ u32 val;
+
+ /* Enable 32k crystal */
+ val = readl(MCU_CTRL_LFXOSC_CTRL);
+ val &= ~(MCU_CTRL_LFXOSC_32K_DISABLE_VAL);
+ writel(val, MCU_CTRL_LFXOSC_CTRL);
+
+ /* select 32k clock from LFOSC0 */
+ writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL,
+ MCU_CTRL_DEVICE_CLKOUT_32K_CTRL);
+}
+
+#define CTRLMMR_WKUP_JTAG_DEVICE_ID (AM625_WKUP_CTRL_MMR0_BASE + 0x18)
+
+#define JTAG_DEV_CORE_NR GENMASK(21, 19)
+#define JTAG_DEV_GPU BIT(18)
+#define JTAG_DEV_FEATURES GENMASK(17, 13)
+#define JTAG_DEV_FEATURE_NO_PRU 0x4
+
+static int am62x_of_fixup(struct device_node *root, void *unused)
+{
+ u32 full_devid = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
+ u32 feature_mask = FIELD_GET(JTAG_DEV_FEATURES, full_devid);
+ int num_cores = FIELD_GET(JTAG_DEV_CORE_NR, full_devid);
+ bool has_gpu = full_devid & JTAG_DEV_GPU;
+ bool has_pru = !(feature_mask & JTAG_DEV_FEATURE_NO_PRU);
+ char path[32];
+ int i;
+
+ for (i = num_cores; i < 4; i++) {
+ snprintf(path, sizeof(path), "/cpus/cpu@%d", i);
+ of_delete_node_path(root, path);
+
+ snprintf(path, sizeof(path), "/cpus/cpu-map/cluster0/core%d", i);
+ of_delete_node_path(root, path);
+
+ snprintf(path, sizeof(path), "/bus@f0000/watchdog@e0%d0000", i);
+ of_delete_node_path(root, path);
+ }
+
+ if (!has_gpu) {
+ of_delete_node_path(root, "/bus@f0000/gpu@fd00000");
+ of_delete_node_path(root, "/bus@f0000/watchdog@e0f0000");
+ }
+
+ if (!has_pru)
+ of_delete_node_path(root, "/bus@f0000/pruss@30040000");
+
+ return 0;
+}
+
+#define CTRLMMR_MCU_RST_CTRL IOMEM(0x04518170)
+#define RST_CTRL_ESM_ERROR_RST_EN_Z_MASK BIT(17)
+
+static void am62x_enable_mcu_esm_reset(void)
+{
+ /* activate reset of main by ESMO */
+ u32 stat = readl(CTRLMMR_MCU_RST_CTRL);
+ stat &= ~RST_CTRL_ESM_ERROR_RST_EN_Z_MASK;
+ writel(stat, CTRLMMR_MCU_RST_CTRL);
+}
+
+static int am62x_init(void)
+{
+ enum bootsource src = BOOTSOURCE_UNKNOWN;
+ int instance = 0;
+
+ if (!of_machine_is_compatible("ti,am625"))
+ return 0;
+
+ am62x_get_bootsource(&src, &instance);
+ bootsource_set(src, instance);
+ am62x_register_dram();
+
+ genpd_activate();
+
+ of_register_fixup(am62x_of_fixup, NULL);
+
+ am62x_enable_mcu_esm_reset();
+
+ return 0;
+}
+postcore_initcall(am62x_init);
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index a324e2d5f60d9dc813f4e117b1eeb1551586cf91..7299355eecef1c38e0d53a8feda60d233d74e2cd 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -12,8 +12,6 @@
#include <command.h>
#include <getopt.h>
#include <libfile.h>
-#include <pm_domain.h>
-#include <bootsource.h>
#include <linux/bits.h>
#include <linux/bitfield.h>
#include <mach/k3/common.h>
@@ -27,259 +25,6 @@ static const struct of_device_id k3_of_match[] = {
};
BAREBOX_DEEP_PROBE_ENABLE(k3_of_match);
-/* Primary BootMode devices */
-#define BOOT_DEVICE_RAM 0x00
-#define BOOT_DEVICE_OSPI 0x01
-#define BOOT_DEVICE_QSPI 0x02
-#define BOOT_DEVICE_SPI 0x03
-#define BOOT_DEVICE_ETHERNET_RGMII 0x04
-#define BOOT_DEVICE_ETHERNET_RMII 0x05
-#define BOOT_DEVICE_I2C 0x06
-#define BOOT_DEVICE_UART 0x07
-#define BOOT_DEVICE_MMC 0x08
-#define BOOT_DEVICE_EMMC 0x09
-
-#define BOOT_DEVICE_USB 0x0A
-#define BOOT_DEVICE_GPMC_NAND 0x0B
-#define BOOT_DEVICE_GPMC_NOR 0x0C
-#define BOOT_DEVICE_XSPI 0x0E
-#define BOOT_DEVICE_NOBOOT 0x0F
-
-/* Backup BootMode devices */
-#define BACKUP_BOOT_DEVICE_USB 0x01
-#define BACKUP_BOOT_DEVICE_UART 0x03
-#define BACKUP_BOOT_DEVICE_ETHERNET 0x04
-#define BACKUP_BOOT_DEVICE_MMC 0x05
-#define BACKUP_BOOT_DEVICE_SPI 0x06
-#define BACKUP_BOOT_DEVICE_I2C 0x07
-
-#define K3_PRIMARY_BOOTMODE 0x0
-
-#define MAIN_DEVSTAT_BACKUP_BOOTMODE GENMASK(12, 10)
-#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG BIT(13)
-#define MAIN_DEVSTAT_BACKUP_USB_MODE BIT(0)
-
-static void k3_get_backup_bootsource(u32 devstat, enum bootsource *src, int *instance)
-{
- u32 bkup_bootmode = FIELD_GET(MAIN_DEVSTAT_BACKUP_BOOTMODE, devstat);
- u32 bkup_bootmode_cfg = FIELD_GET(MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG, devstat);
-
- *src = BOOTSOURCE_UNKNOWN;
-
- switch (bkup_bootmode) {
- case BACKUP_BOOT_DEVICE_UART:
- *src = BOOTSOURCE_SERIAL;
- return;
- case BACKUP_BOOT_DEVICE_ETHERNET:
- *src = BOOTSOURCE_NET;
- return;
- case BACKUP_BOOT_DEVICE_MMC:
- if (bkup_bootmode_cfg) {
- *src = BOOTSOURCE_MMC;
- *instance = 1;
- } else {
- *src = BOOTSOURCE_MMC;
- *instance = 0;
- }
- return;
- case BACKUP_BOOT_DEVICE_SPI:
- *src = BOOTSOURCE_SPI;
- return;
- case BACKUP_BOOT_DEVICE_I2C:
- *src = BOOTSOURCE_I2C;
- return;
- case BACKUP_BOOT_DEVICE_USB:
- if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE)
- *src = BOOTSOURCE_USB;
- else
- *src = BOOTSOURCE_SERIAL;
- return;
- };
-}
-
-#define MAIN_DEVSTAT_PRIMARY_BOOTMODE GENMASK(6, 3)
-#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG GENMASK(9, 7)
-#define MAIN_DEVSTAT_PRIMARY_USB_MODE BIT(1)
-#define MAIN_DEVSTAT_PRIMARY_MMC_PORT BIT(2)
-
-static void k3_get_primary_bootsource(u32 devstat, enum bootsource *src, int *instance)
-{
- u32 bootmode = FIELD_GET(MAIN_DEVSTAT_PRIMARY_BOOTMODE, devstat);
- u32 bootmode_cfg = FIELD_GET(MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG, devstat);
-
- switch (bootmode) {
- case BOOT_DEVICE_OSPI:
- case BOOT_DEVICE_QSPI:
- case BOOT_DEVICE_XSPI:
- case BOOT_DEVICE_SPI:
- *src = BOOTSOURCE_SPI;
- return;
- case BOOT_DEVICE_ETHERNET_RGMII:
- case BOOT_DEVICE_ETHERNET_RMII:
- *src = BOOTSOURCE_NET;
- return;
- case BOOT_DEVICE_EMMC:
- *src = BOOTSOURCE_MMC;
- *instance = 0;
- return;
- case BOOT_DEVICE_MMC:
- if (bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT) {
- *src = BOOTSOURCE_MMC;
- *instance = 1;
- } else {
- *src = BOOTSOURCE_MMC;
- *instance = 0;
- }
- return;
- case BOOT_DEVICE_USB:
- if (bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE)
- *src = BOOTSOURCE_USB;
- else
- *src = BOOTSOURCE_SERIAL;
- return;
- case BOOT_DEVICE_NOBOOT:
- *src = BOOTSOURCE_UNKNOWN;
- return;
- }
-}
-
-#define AM625_BOOT_PARAM_TABLE_INDEX_OCRAM IOMEM(0x43c3f290)
-
-static void k3_get_bootsource(u32 devstat, enum bootsource *src, int *instance)
-{
- u32 bootmode = readl(AM625_BOOT_PARAM_TABLE_INDEX_OCRAM);
-
- if (bootmode == K3_PRIMARY_BOOTMODE)
- k3_get_primary_bootsource(devstat, src, instance);
- else
- k3_get_backup_bootsource(devstat, src, instance);
-}
-
-#define AM625_WKUP_CTRL_MMR0_BASE IOMEM(0x43000000)
-#define AM625_CTRLMMR_MAIN_DEVSTAT (AM625_WKUP_CTRL_MMR0_BASE + 0x30)
-
-void am625_get_bootsource(enum bootsource *src, int *instance)
-{
- u32 devstat;
-
- devstat = readl(AM625_CTRLMMR_MAIN_DEVSTAT);
-
- k3_get_bootsource(devstat, src, instance);
-}
-
-bool k3_boot_is_emmc(void)
-{
- u32 bootmode = readl(AM625_BOOT_PARAM_TABLE_INDEX_OCRAM);
- u32 devstat = readl(AM625_CTRLMMR_MAIN_DEVSTAT);
-
- if (bootmode != K3_PRIMARY_BOOTMODE)
- return false;
- if (FIELD_GET(MAIN_DEVSTAT_PRIMARY_BOOTMODE, devstat) != BOOT_DEVICE_EMMC)
- return false;
-
- return true;
-}
-
-static void of_delete_node_path(struct device_node *root, const char *path)
-{
- struct device_node *np;
-
- np = of_find_node_by_path_from(root, path);
- of_delete_node(np);
-}
-
-#define MCU_CTRL_MMR0_BASE 0x04500000
-#define MCU_CTRL_LFXOSC_CTRL (MCU_CTRL_MMR0_BASE + 0x8038)
-#define MCU_CTRL_LFXOSC_32K_DISABLE_VAL BIT(7)
-#define MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL (0x3)
-#define MCU_CTRL_DEVICE_CLKOUT_32K_CTRL (MCU_CTRL_MMR0_BASE + 0x8058)
-
-void am625_enable_32k_crystal(void)
-{
- u32 val;
-
- /* Enable 32k crystal */
- val = readl(MCU_CTRL_LFXOSC_CTRL);
- val &= ~(MCU_CTRL_LFXOSC_32K_DISABLE_VAL);
- writel(val, MCU_CTRL_LFXOSC_CTRL);
-
- /* select 32k clock from LFOSC0 */
- writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL,
- MCU_CTRL_DEVICE_CLKOUT_32K_CTRL);
-}
-
-#define CTRLMMR_WKUP_JTAG_DEVICE_ID (AM625_WKUP_CTRL_MMR0_BASE + 0x18)
-
-#define JTAG_DEV_CORE_NR GENMASK(21, 19)
-#define JTAG_DEV_GPU BIT(18)
-#define JTAG_DEV_FEATURES GENMASK(17, 13)
-#define JTAG_DEV_FEATURE_NO_PRU 0x4
-
-static int am625_of_fixup(struct device_node *root, void *unused)
-{
- u32 full_devid = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
- u32 feature_mask = FIELD_GET(JTAG_DEV_FEATURES, full_devid);
- int num_cores = FIELD_GET(JTAG_DEV_CORE_NR, full_devid);
- bool has_gpu = full_devid & JTAG_DEV_GPU;
- bool has_pru = !(feature_mask & JTAG_DEV_FEATURE_NO_PRU);
- char path[32];
- int i;
-
- for (i = num_cores; i < 4; i++) {
- snprintf(path, sizeof(path), "/cpus/cpu@%d", i);
- of_delete_node_path(root, path);
-
- snprintf(path, sizeof(path), "/cpus/cpu-map/cluster0/core%d", i);
- of_delete_node_path(root, path);
-
- snprintf(path, sizeof(path), "/bus@f0000/watchdog@e0%d0000", i);
- of_delete_node_path(root, path);
- }
-
- if (!has_gpu) {
- of_delete_node_path(root, "/bus@f0000/gpu@fd00000");
- of_delete_node_path(root, "/bus@f0000/watchdog@e0f0000");
- }
-
- if (!has_pru)
- of_delete_node_path(root, "/bus@f0000/pruss@30040000");
-
- return 0;
-}
-
-#define CTRLMMR_MCU_RST_CTRL IOMEM(0x04518170)
-#define RST_CTRL_ESM_ERROR_RST_EN_Z_MASK BIT(17)
-
-static void am625_enable_mcu_esm_reset(void)
-{
- /* activate reset of main by ESMO */
- u32 stat = readl(CTRLMMR_MCU_RST_CTRL);
- stat &= ~RST_CTRL_ESM_ERROR_RST_EN_Z_MASK;
- writel(stat, CTRLMMR_MCU_RST_CTRL);
-}
-
-static int am625_init(void)
-{
- enum bootsource src = BOOTSOURCE_UNKNOWN;
- int instance = 0;
-
- if (!of_machine_is_compatible("ti,am625"))
- return 0;
-
- am625_get_bootsource(&src, &instance);
- bootsource_set(src, instance);
- am625_register_dram();
-
- genpd_activate();
-
- of_register_fixup(am625_of_fixup, NULL);
-
- am625_enable_mcu_esm_reset();
-
- return 0;
-}
-postcore_initcall(am625_init);
-
static int omap_env_init(void)
{
char *partname, *cdevname, *envpath;
--git a/arch/arm/mach-k3/ddrss.c b/arch/arm/mach-k3/ddrss.c
index 797b60c2d80b06aaa26cc14c0fb886d04bc48ec0..f60c47372b2988a176b7e5a847fbc717028c8ef4 100644
--- a/arch/arm/mach-k3/ddrss.c
+++ b/arch/arm/mach-k3/ddrss.c
@@ -34,7 +34,7 @@
#define DENALI_CTL_0_DRAM_CLASS_DDR4 0xa
#define DENALI_CTL_0_DRAM_CLASS_LPDDR4 0xb
-static unsigned int am625_get_banks_count(unsigned int regval)
+static unsigned int am62x_get_banks_count(unsigned int regval)
{
/*
* The BANK_DIFF_x are only described in the Reference Manual as:
@@ -55,7 +55,7 @@ static unsigned int am625_get_banks_count(unsigned int regval)
}
}
-u64 am625_sdram_size(void)
+u64 am62x_sdram_size(void)
{
void __iomem *base = IOMEM(AM625_DDRSS_BASE);
u32 ctl3 = readl(base + CTLPHY_CTL_CFG_CTLCFG_DENALI_CTL_3);
@@ -68,7 +68,7 @@ u64 am625_sdram_size(void)
if (ctl327 & BIT(0)) {
cols = FIELD_GET(MAX_COL, ctl3) - FIELD_GET(COL_DIFF_0, ctl317);
rows = FIELD_GET(MAX_ROW, ctl3) - FIELD_GET(ROW_DIFF_0, ctl317);
- banks = am625_get_banks_count(FIELD_GET(BANK_DIFF_0, ctl316));
+ banks = am62x_get_banks_count(FIELD_GET(BANK_DIFF_0, ctl316));
size += memory_sdram_size(cols, rows, banks, 2);
}
@@ -76,7 +76,7 @@ u64 am625_sdram_size(void)
if (ctl327 & BIT(1)) {
cols = FIELD_GET(MAX_COL, ctl3) - FIELD_GET(COL_DIFF_1, ctl317);
rows = FIELD_GET(MAX_ROW, ctl3) - FIELD_GET(ROW_DIFF_1, ctl317);
- banks = am625_get_banks_count(FIELD_GET(BANK_DIFF_1, ctl316));
+ banks = am62x_get_banks_count(FIELD_GET(BANK_DIFF_1, ctl316));
size += memory_sdram_size(cols, rows, banks, 2);
}
@@ -84,9 +84,9 @@ u64 am625_sdram_size(void)
return size;
}
-void am625_register_dram(void)
+void am62x_register_dram(void)
{
- u64 size = am625_sdram_size();
+ u64 size = am62x_sdram_size();
u64 lowmem = min_t(u64, size, SZ_2G);
arm_add_mem_device("ram0", 0x80000000, lowmem);
diff --git a/include/mach/k3/common.h b/include/mach/k3/common.h
index 94c5fba19d44a12c115604b3a22c1c6e78c61f30..d14b8b9cb891dd23dcc3a6277e79aa9f639f412a 100644
--- a/include/mach/k3/common.h
+++ b/include/mach/k3/common.h
@@ -8,11 +8,11 @@
#define UUID_TI_DM_FW \
UUID_INIT(0x9e8c2017, 0x8b94, 0x4e2b, 0xa7, 0xb3, 0xa0, 0xf8, 0x8e, 0xab, 0xb8, 0xae)
-void am625_get_bootsource(enum bootsource *src, int *instance);
+void am62x_get_bootsource(enum bootsource *src, int *instance);
bool k3_boot_is_emmc(void);
-u64 am625_sdram_size(void);
-void am625_register_dram(void);
-void am625_enable_32k_crystal(void);
+u64 am62x_sdram_size(void);
+void am62x_register_dram(void);
+void am62x_enable_32k_crystal(void);
int k3_authenticate_image(void **buf, size_t *size);
#define K3_EMMC_BOOTPART_TIBOOT3_BIN_SIZE SZ_1M
--
2.39.5
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 03/31] ARM: k3: make k3img destination addresses configurable
2025-05-28 11:45 [PATCH 00/31] ARM: K3: add support for AM62L Sascha Hauer
2025-05-28 11:45 ` [PATCH 01/31] scripts: k3img: remove duplicate case value Sascha Hauer
2025-05-28 11:45 ` [PATCH 02/31] ARM: K3: prepare support for other SoCs Sascha Hauer
@ 2025-05-28 11:45 ` Sascha Hauer
2025-05-28 11:45 ` [PATCH 04/31] ARM: dts: add k3-am62l dts(i) files Sascha Hauer
` (27 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Sascha Hauer @ 2025-05-28 11:45 UTC (permalink / raw)
To: BAREBOX
The destination addresses where the binaries in the image shall be
copied to varies across different K3 SoCs. Make the addresses
configurable. The options that previously took a filename now
additionally take the destination address separated by a double colon.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
images/Makefile.k3 | 51 +++++++++++++++++++++++++++------------------------
scripts/k3img | 20 ++++++++++++--------
2 files changed, 39 insertions(+), 32 deletions(-)
diff --git a/images/Makefile.k3 b/images/Makefile.k3
index d9b0af8d67b49569283d35ce0ec1792897654c57..e31a5cd2dcdd4fdbe62f3084092b641499e404ff 100644
--- a/images/Makefile.k3
+++ b/images/Makefile.k3
@@ -28,47 +28,50 @@ KEY_custmpk=$(srctree)/arch/arm/mach-k3/custMpk.pem
KEY_degenerate=$(srctree)/arch/arm/mach-k3/ti-degenerate-key.pem
## TI am625(sip)-SK ##
-SYSFW_start_am625_sk_r5.pblb.k3img=$(SYSFW_am625_hs_fs)
-SYSFWDATA_start_am625_sk_r5.pblb.k3img=$(SYSFWDATA_am625)
-DMDATA_start_am625_sk_r5.pblb.k3img=$(DMDATA_am625)
-INNERDATA_start_am625_sk_r5.pblb.k3img=$(INNERDATA_am625)
-KEY_start_am625_sk_r5.pblb.k3img=$(KEY_custmpk)
+SYSFW_start_am625_sk_r5.pblb.k3_am62x_img=$(SYSFW_am625_hs_fs)
+SYSFWDATA_start_am625_sk_r5.pblb.k3_am62x_img=$(SYSFWDATA_am625)
+DMDATA_start_am625_sk_r5.pblb.k3_am62x_img=$(DMDATA_am625)
+INNERDATA_start_am625_sk_r5.pblb.k3_am62x_img=$(INNERDATA_am625)
+KEY_start_am625_sk_r5.pblb.k3_am62x_img=$(KEY_custmpk)
pblb-$(CONFIG_MACH_AM625_SK) += start_am625_sk_r5
-FILE_barebox-am625-sk-r5.img = start_am625_sk_r5.pblb.k3img
+FILE_barebox-am625-sk-r5.img = start_am625_sk_r5.pblb.k3_am62x_img
image-$(CONFIG_MACH_AM625_SK) += barebox-am625-sk-r5.img
-SYSFW_start_am625sip_sk_r5.pblb.k3img=$(SYSFW_am625_hs_fs)
-SYSFWDATA_start_am625sip_sk_r5.pblb.k3img=$(SYSFWDATA_am625)
-DMDATA_start_am625sip_sk_r5.pblb.k3img=$(DMDATA_am625)
-INNERDATA_start_am625sip_sk_r5.pblb.k3img=$(INNERDATA_am625)
-KEY_start_am625sip_sk_r5.pblb.k3img=$(KEY_custmpk)
+SYSFW_start_am625sip_sk_r5.pblb.k3_am62x_img=$(SYSFW_am625_hs_fs)
+SYSFWDATA_start_am625sip_sk_r5.pblb.k3_am62x_img=$(SYSFWDATA_am625)
+DMDATA_start_am625sip_sk_r5.pblb.k3_am62x_img=$(DMDATA_am625)
+INNERDATA_start_am625sip_sk_r5.pblb.k3_am62x_img=$(INNERDATA_am625)
+KEY_start_am625sip_sk_r5.pblb.k3_am62x_img=$(KEY_custmpk)
pblb-$(CONFIG_MACH_AM625_SK) += start_am625sip_sk_r5
-FILE_barebox-am625sip-sk-r5.img = start_am625sip_sk_r5.pblb.k3img
+FILE_barebox-am625sip-sk-r5.img = start_am625sip_sk_r5.pblb.k3_am62x_img
image-$(CONFIG_MACH_AM625_SK) += barebox-am625sip-sk-r5.img
## BeaglePlay ##
-SYSFW_start_beagleplay_r5.pblb.k3img=$(SYSFW_am625_gp)
-SYSFWDATA_start_beagleplay_r5.pblb.k3img=$(SYSFWDATA_am625)
-DMDATA_start_beagleplay_r5.pblb.k3img=$(DMDATA_am625)
-KEY_start_beagleplay_r5.pblb.k3img=$(KEY_degenerate)
+SYSFW_start_beagleplay_r5.pblb.k3_am62x_img=$(SYSFW_am625_gp)
+SYSFWDATA_start_beagleplay_r5.pblb.k3_am62x_img=$(SYSFWDATA_am625)
+DMDATA_start_beagleplay_r5.pblb.k3_am62x_img=$(DMDATA_am625)
+KEY_start_beagleplay_r5.pblb.k3_am62x_img=$(KEY_degenerate)
pblb-$(CONFIG_MACH_BEAGLEPLAY) += start_beagleplay_r5
-FILE_barebox-beagleplay-r5.img = start_beagleplay_r5.pblb.k3img
+FILE_barebox-beagleplay-r5.img = start_beagleplay_r5.pblb.k3_am62x_img
image-$(CONFIG_MACH_BEAGLEPLAY) += barebox-beagleplay-r5.img
endif
-quiet_cmd_k3_image = K3IMG $@
- cmd_k3_image = \
+quiet_cmd_k3_am62x_image = K3_am62x_IMG $@
+ cmd_k3_am62x_image = \
if [ -n "$(INNERDATA_$(@F))" ]; then \
inner="--innerdata $(INNERDATA_$(@F))"; \
fi; \
\
- $(srctree)/scripts/k3img --sysfw $(SYSFW_$(@F)) \
- --sysfwdata $(SYSFWDATA_$(@F)) --dmdata $(DMDATA_$(@F)) \
- --key $(KEY_$(@F)) $$inner --sbl $< --out $@
+ $(srctree)/scripts/k3img \
+ --sysfw $(SYSFW_$(@F)):00040000 \
+ --sysfwdata $(SYSFWDATA_$(@F)):00067000 \
+ --dmdata $(DMDATA_$(@F)):43c3a800 \
+ --sbl $<:43c00000 \
+ --key $(KEY_$(@F)) $$inner --out $@
-$(obj)/%.k3img: $(obj)/% scripts/k3img FORCE
- $(call if_changed,k3_image)
+$(obj)/%.k3_am62x_img: $(obj)/% scripts/k3_am62x_img FORCE
+ $(call if_changed,k3_am62x_image)
diff --git a/scripts/k3img b/scripts/k3img
index f622f877cb89ce5604b8cb7651b3c23d3a5459be..a9f7e513723b251c3605e81a97093e23850a8f4d 100755
--- a/scripts/k3img
+++ b/scripts/k3img
@@ -16,17 +16,20 @@ unset TEMP
while true; do
case "$1" in
'--sysfw')
- sysfw="$2"
+ sysfw=$(echo "$2" | cut -d ":" -f 1)
+ sysfw_addr=$(echo "$2" | cut -d ":" -f 2)
shift 2
continue
;;
'--sysfwdata')
- sysfwdata="$2"
+ sysfwdata=$(echo "$2" | cut -d ":" -f 1)
+ sysfwdata_addr=$(echo "$2" | cut -d ":" -f 2)
shift 2
continue
;;
'--dmdata')
- dmdata="$2"
+ dmdata=$(echo "$2" | cut -d ":" -f 1)
+ dmdata_addr=$(echo "$2" | cut -d ":" -f 2)
shift 2
continue
;;
@@ -36,7 +39,8 @@ while true; do
continue
;;
'--sbl')
- sbl="$2"
+ sbl=$(echo "$2" | cut -d ":" -f 1)
+ sbl_addr=$(echo "$2" | cut -d ":" -f 2)
shift 2
continue
;;
@@ -140,7 +144,7 @@ dm_data=SEQUENCE:dm_data
compType = INTEGER:1
bootCore = INTEGER:16
compOpts = INTEGER:0
-destAddr = FORMAT:HEX,OCT:43c00000
+destAddr = FORMAT:HEX,OCT:$sbl_addr
compSize = INTEGER:$sblsize
shaType = OID:2.16.840.1.101.3.4.2.3
shaValue = FORMAT:HEX,OCT:$shasbl
@@ -149,7 +153,7 @@ shaValue = FORMAT:HEX,OCT:$shasbl
compType = INTEGER:2
bootCore = INTEGER:0
compOpts = INTEGER:0
-destAddr = FORMAT:HEX,OCT:00040000
+destAddr = FORMAT:HEX,OCT:$sysfw_addr
compSize = INTEGER:$sysfwsize
shaType = OID:2.16.840.1.101.3.4.2.3
shaValue = FORMAT:HEX,OCT:$shasysfw
@@ -158,7 +162,7 @@ shaValue = FORMAT:HEX,OCT:$shasysfw
compType = INTEGER:18
bootCore = INTEGER:0
compOpts = INTEGER:0
-destAddr = FORMAT:HEX,OCT:00067000
+destAddr = FORMAT:HEX,OCT:$sysfwdata_addr
compSize = INTEGER:$sysfwdatasize
shaType = OID:2.16.840.1.101.3.4.2.3
shaValue = FORMAT:HEX,OCT:$shasysfwdata
@@ -175,7 +179,7 @@ $innercert
compType = INTEGER:17
bootCore = INTEGER:16
compOpts = INTEGER:0
-destAddr = FORMAT:HEX,OCT:43c3a800
+destAddr = FORMAT:HEX,OCT:$dmdata_addr
compSize = INTEGER:$dmdatasize
shaType = OID:2.16.840.1.101.3.4.2.3
shaValue = FORMAT:HEX,OCT:$shadmdata
--
2.39.5
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 04/31] ARM: dts: add k3-am62l dts(i) files
2025-05-28 11:45 [PATCH 00/31] ARM: K3: add support for AM62L Sascha Hauer
` (2 preceding siblings ...)
2025-05-28 11:45 ` [PATCH 03/31] ARM: k3: make k3img destination addresses configurable Sascha Hauer
@ 2025-05-28 11:45 ` Sascha Hauer
2025-05-28 11:45 ` [PATCH 05/31] ARM: dts: am62l: Fix assigned-clock-parents Sascha Hauer
` (26 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Sascha Hauer @ 2025-05-28 11:45 UTC (permalink / raw)
To: BAREBOX
The device trees are taken from [1]. Until these are upstream we have to
live with a local copy.
[1] https://lore.kernel.org/all/20250507-am62lx-v5-0-4b57ea878e62@ti.com/
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/dts/k3-am62l-main.dtsi | 673 +++++++++++++++++++++++++++++++++++++
arch/arm/dts/k3-am62l-thermal.dtsi | 25 ++
arch/arm/dts/k3-am62l-wakeup.dtsi | 133 ++++++++
arch/arm/dts/k3-am62l.dtsi | 121 +++++++
arch/arm/dts/k3-am62l3-evm.dts | 294 ++++++++++++++++
arch/arm/dts/k3-am62l3.dtsi | 67 ++++
arch/arm/dts/k3-pinctrl.h | 7 +
7 files changed, 1320 insertions(+)
diff --git a/arch/arm/dts/k3-am62l-main.dtsi b/arch/arm/dts/k3-am62l-main.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..f6fbaaede8c36ac0aab92bef7763202bb0ab30dc
--- /dev/null
+++ b/arch/arm/dts/k3-am62l-main.dtsi
@@ -0,0 +1,673 @@
+// SPDX-License-Identifier: GPL-2.0-only or MIT
+/*
+ * Device Tree file for the AM62L main domain peripherals
+ * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4
+ */
+
+&cbass_main {
+ gic500: interrupt-controller@1800000 {
+ compatible = "arm,gic-v3";
+ reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
+ <0x00 0x01840000 0x00 0xc0000>, /* GICR */
+ <0x01 0x00000000 0x00 0x2000>, /* GICC */
+ <0x01 0x00010000 0x00 0x1000>, /* GICH */
+ <0x01 0x00020000 0x00 0x2000>; /* GICV */
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ /*
+ * vcpumntirq:
+ * virtual CPU interface maintenance interrupt
+ */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ gic_its: msi-controller@1820000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x00 0x01820000 0x00 0x10000>;
+ socionext,synquacer-pre-its = <0x1000000 0x400000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ };
+
+ gpio0: gpio@600000 {
+ compatible = "ti,am64-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x00600000 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 267 IRQ_TYPE_EDGE_RISING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ power-domains = <&scmi_pds 34>;
+ clocks = <&scmi_clk 140>;
+ clock-names = "gpio";
+ ti,ngpio = <126>;
+ ti,davinci-gpio-unbanked = <0>;
+ status = "disabled";
+ };
+
+ gpio2: gpio@610000 {
+ compatible = "ti,am64-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x00610000 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 281 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 284 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 285 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 287 IRQ_TYPE_EDGE_RISING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ power-domains = <&scmi_pds 35>;
+ clocks = <&scmi_clk 141>;
+ clock-names = "gpio";
+ ti,ngpio = <79>;
+ ti,davinci-gpio-unbanked = <0>;
+ status = "disabled";
+ };
+
+ timer0: timer@2400000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2400000 0x00 0x400>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk 47>;
+ clock-names = "fck";
+ power-domains = <&scmi_pds 15>;
+ ti,timer-pwm;
+ };
+
+ timer1: timer@2410000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2410000 0x00 0x400>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk 61>;
+ clock-names = "fck";
+ power-domains = <&scmi_pds 16>;
+ ti,timer-pwm;
+ };
+
+ timer2: timer@2420000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2420000 0x00 0x400>;
+ interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk 66>;
+ clock-names = "fck";
+ power-domains = <&scmi_pds 17>;
+ ti,timer-pwm;
+ };
+
+ timer3: timer@2430000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2430000 0x00 0x400>;
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk 80>;
+ clock-names = "fck";
+ power-domains = <&scmi_pds 18>;
+ ti,timer-pwm;
+ };
+
+ uart0: serial@2800000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02800000 0x00 0x100>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&scmi_pds 89>;
+ clocks = <&scmi_clk 358>;
+ clock-names = "fclk";
+ status = "disabled";
+ };
+
+ uart1: serial@2810000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02810000 0x00 0x100>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&scmi_pds 77>;
+ clocks = <&scmi_clk 312>;
+ clock-names = "fclk";
+ status = "disabled";
+ };
+
+ uart2: serial@2820000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02820000 0x00 0x100>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&scmi_pds 78>;
+ clocks = <&scmi_clk 314>;
+ clock-names = "fclk";
+ status = "disabled";
+ };
+
+ uart3: serial@2830000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02830000 0x00 0x100>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&scmi_pds 79>;
+ clocks = <&scmi_clk 316>;
+ clock-names = "fclk";
+ status = "disabled";
+ };
+
+ uart4: serial@2840000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02840000 0x00 0x100>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&scmi_pds 80>;
+ clocks = <&scmi_clk 318>;
+ clock-names = "fclk";
+ status = "disabled";
+ };
+
+ uart5: serial@2850000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02850000 0x00 0x100>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&scmi_pds 81>;
+ clocks = <&scmi_clk 320>;
+ clock-names = "fclk";
+ status = "disabled";
+ };
+
+ uart6: serial@2860000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02860000 0x00 0x100>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&scmi_pds 82>;
+ clocks = <&scmi_clk 322>;
+ clock-names = "fclk";
+ status = "disabled";
+ };
+
+ conf: syscon@9000000 {
+ compatible = "syscon", "simple-mfd";
+ ranges = <0x0 0x00 0x09000000 0x400000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ phy_gmii_sel: phy@1be000 {
+ compatible = "ti,am654-phy-gmii-sel";
+ reg = <0x1be000 0x8>;
+ #phy-cells = <1>;
+ };
+
+ epwm_tbclk: clock-controller@1e9100 {
+ compatible = "ti,am62-epwm-tbclk";
+ reg = <0x1e9100 0x4>;
+ #clock-cells = <1>;
+ };
+ };
+
+ rti0: watchdog@e000000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x0e000000 0x00 0x100>;
+ clocks = <&scmi_clk 273>;
+ power-domains = <&scmi_pds 60>;
+ assigned-clocks = <&scmi_clk 273>;
+ assigned-clock-parents = <&scmi_clk 1>;
+ };
+
+ rti1: watchdog@e010000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x0e010000 0x00 0x100>;
+ clocks = <&scmi_clk 279>;
+ power-domains = <&scmi_pds 61>;
+ assigned-clocks = <&scmi_clk 279>;
+ assigned-clock-parents = <&scmi_clk 1>;
+ };
+
+ fss: bus@fc00000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x0fc00000 0x00 0x100>, // FSS Control
+ <0x00 0x0fc40000 0x00 0x100>, // OSPI0 Control
+ <0x05 0x00000000 0x01 0x00000000>; // OSPI0 Memory
+
+ ospi0: spi@fc40000 {
+ compatible = "ti,am654-ospi", "cdns,qspi-nor";
+ reg = <0x00 0x0fc40000 0x00 0x100>,
+ <0x05 0x00000000 0x01 0x00000000>;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk 134>;
+ assigned-clocks = <&scmi_clk 134>;
+ assigned-clock-rates = <166666666>;
+ power-domains = <&scmi_pds 32>;
+ #size-cells = <0>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ cdns,phase-detect-selector = <2>;
+ status = "disabled";
+ };
+ };
+
+ usbss0: dwc3-usb@f900000 {
+ compatible = "ti,am62-usb";
+ reg = <0x00 0x0f900000 0x00 0x800>,
+ <0x00 0x0f908000 0x00 0x400>;
+ clocks = <&scmi_clk 329>;
+ clock-names = "ref";
+ power-domains = <&scmi_pds 95>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ ti,syscon-phy-pll-refclk = <&wkup_conf 0x45000>;
+ status = "disabled";
+
+ usb0: usb@31000000 {
+ compatible = "snps,dwc3";
+ reg = <0x00 0x31000000 0x00 0x50000>;
+ interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+ <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
+ interrupt-names = "host", "peripheral";
+ maximum-speed = "high-speed";
+ dr_mode = "otg";
+ snps,usb2-gadget-lpm-disable;
+ snps,usb2-lpm-disable;
+ bootph-all;
+ };
+ };
+
+ usbss1: dwc3-usb@f910000 {
+ compatible = "ti,am62-usb";
+ reg = <0x00 0x0f910000 0x00 0x800>,
+ <0x00 0x0f918000 0x00 0x400>;
+ clocks = <&scmi_clk 336>;
+ clock-names = "ref";
+ power-domains = <&scmi_pds 96>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ti,syscon-phy-pll-refclk = <&wkup_conf 0x45004>;
+ ranges;
+ status = "disabled";
+
+ usb1: usb@31100000 {
+ compatible = "snps,dwc3";
+ reg = <0x00 0x31100000 0x00 0x50000>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+ <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
+ interrupt-names = "host", "peripheral";
+ maximum-speed = "high-speed";
+ dr_mode = "otg";
+ snps,usb2-gadget-lpm-disable;
+ snps,usb2-lpm-disable;
+ };
+ };
+
+ sdhci0: mmc@fa10000 {
+ compatible = "ti,am62-sdhci";
+ reg = <0x00 0xfa10000 0x00 0x1000>,
+ <0x00 0xfa18000 0x00 0x400>;
+ interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&scmi_pds 28>;
+ clocks = <&scmi_clk 122>, <&scmi_clk 123>;
+ clock-names = "clk_ahb", "clk_xin";
+ assigned-clocks = <&scmi_clk 123>;
+ assigned-clock-parents = <&scmi_clk 0>;
+ bus-width = <8>;
+ ti,clkbuf-sel = <0x7>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,itap-del-sel-legacy = <0x0>;
+ status = "disabled";
+ };
+
+ sdhci1: mmc@fa00000 {
+ compatible = "ti,am62-sdhci";
+ reg = <0x00 0x0fa00000 0x00 0x1000>,
+ <0x00 0x0fa08000 0x00 0x400>;
+ interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&scmi_pds 26>;
+ clocks = <&scmi_clk 106>, <&scmi_clk 107>;
+ clock-names = "clk_ahb", "clk_xin";
+ assigned-clocks = <&scmi_clk 107>;
+ assigned-clock-parents = <&scmi_clk 0>;
+ bus-width = <4>;
+ ti,clkbuf-sel = <0x7>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,itap-del-sel-legacy = <0x0>;
+ status = "disabled";
+ };
+
+ sdhci2: mmc@fa20000 {
+ compatible = "ti,am62-sdhci";
+ reg = <0x00 0x0fa20000 0x00 0x1000>,
+ <0x00 0x0fa28000 0x00 0x400>;
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&scmi_pds 27>;
+ clocks = <&scmi_clk 114>, <&scmi_clk 115>;
+ clock-names = "clk_ahb", "clk_xin";
+ assigned-clocks = <&scmi_clk 115>;
+ assigned-clock-parents = <&scmi_clk 0>;
+ bus-width = <4>;
+ ti,clkbuf-sel = <0x7>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,itap-del-sel-legacy = <0x0>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@20000000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x20000000 0x00 0x100>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&scmi_pds 53>;
+ clocks = <&scmi_clk 246>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@20010000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x20010000 0x00 0x100>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&scmi_pds 54>;
+ clocks = <&scmi_clk 250>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@20020000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x20020000 0x00 0x100>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&scmi_pds 55>;
+ clocks = <&scmi_clk 254>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@20030000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x20030000 0x00 0x100>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&scmi_pds 56>;
+ clocks = <&scmi_clk 258>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ mcan0: can@20701000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x20701000 0x00 0x200>,
+ <0x00 0x20708000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&scmi_pds 47>;
+ clocks = <&scmi_clk 179>, <&scmi_clk 174>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ mcan1: can@20711000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x20711000 0x00 0x200>,
+ <0x00 0x20718000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&scmi_pds 48>;
+ clocks = <&scmi_clk 185>, <&scmi_clk 180>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ mcan2: can@20721000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x20721000 0x00 0x200>,
+ <0x00 0x20728000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&scmi_pds 49>;
+ clocks = <&scmi_clk 191>, <&scmi_clk 186>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ spi0: spi@20100000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x20100000 0x00 0x400>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&scmi_pds 72>;
+ clocks = <&scmi_clk 299>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi1: spi@20110000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x20110000 0x00 0x400>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&scmi_pds 73>;
+ clocks = <&scmi_clk 302>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi2: spi@20120000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x20120000 0x00 0x400>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&scmi_pds 74>;
+ clocks = <&scmi_clk 305>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi3: spi@20130000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x20130000 0x00 0x400>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&scmi_pds 75>;
+ clocks = <&scmi_clk 308>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ epwm0: pwm@23000000 {
+ compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x23000000 0x00 0x100>;
+ power-domains = <&scmi_pds 40>;
+ clocks = <&epwm_tbclk 0>, <&scmi_clk 164>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ epwm1: pwm@23010000 {
+ compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x23010000 0x00 0x100>;
+ power-domains = <&scmi_pds 41>;
+ clocks = <&epwm_tbclk 1>, <&scmi_clk 165>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ epwm2: pwm@23020000 {
+ compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x23020000 0x00 0x100>;
+ power-domains = <&scmi_pds 42>;
+ clocks = <&epwm_tbclk 2>, <&scmi_clk 166>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ ecap0: pwm@23100000 {
+ compatible = "ti,am3352-ecap";
+ reg = <0x00 0x23100000 0x00 0x100>;
+ power-domains = <&scmi_pds 22>;
+ clocks = <&scmi_clk 99>;
+ clock-names = "fck";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ ecap1: pwm@23110000 {
+ compatible = "ti,am3352-ecap";
+ reg = <0x00 0x23110000 0x00 0x100>;
+ power-domains = <&scmi_pds 23>;
+ clocks = <&scmi_clk 100>;
+ clock-names = "fck";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ ecap2: pwm@23120000 {
+ compatible = "ti,am3352-ecap";
+ reg = <0x00 0x23120000 0x00 0x100>;
+ power-domains = <&scmi_pds 24>;
+ clocks = <&scmi_clk 101>;
+ clock-names = "fck";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ eqep0: counter@23200000 {
+ compatible = "ti,am62-eqep";
+ reg = <0x00 0x23200000 0x00 0x100>;
+ power-domains = <&scmi_pds 29>;
+ clocks = <&scmi_clk 127>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
+ eqep1: counter@23210000 {
+ compatible = "ti,am62-eqep";
+ reg = <0x00 0x23210000 0x00 0x100>;
+ power-domains = <&scmi_pds 30>;
+ clocks = <&scmi_clk 128>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
+ eqep2: counter@23220000 {
+ compatible = "ti,am62-eqep";
+ reg = <0x00 0x23220000 0x00 0x100>;
+ power-domains = <&scmi_pds 31>;
+ clocks = <&scmi_clk 129>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
+ elm0: ecc@25010000 {
+ compatible = "ti,am64-elm";
+ reg = <0x00 0x25010000 0x00 0x2000>;
+ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&scmi_pds 25>;
+ clocks = <&scmi_clk 102>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ tscadc0: tscadc@28001000 {
+ compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
+ reg = <0x00 0x28001000 0x00 0x1000>;
+ interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&scmi_pds 0>;
+ clocks = <&scmi_clk 0>;
+ assigned-clocks = <&scmi_clk 0>;
+ assigned-clock-parents = <&scmi_clk 2>;
+ assigned-clock-rates = <60000000>;
+ clock-names = "fck";
+ status = "disabled";
+
+ adc {
+ compatible = "ti,am654-adc", "ti,am3359-adc";
+ #io-channel-cells = <1>;
+ };
+ };
+
+ dphy_tx0: phy@301c0000 {
+ compatible = "ti,j721e-dphy";
+ reg = <0x0 0x301c0000 0x0 0x1000>;
+ clocks = <&scmi_clk 348>, <&scmi_clk 341>;
+ clock-names = "psm", "pll_ref";
+ power-domains = <&scmi_pds 86>;
+ assigned-clocks = <&scmi_clk 341>;
+ assigned-clock-parents = <&scmi_clk 0>;
+ assigned-clock-rates = <25000000>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ dsi0: dsi@30500000 {
+ compatible = "ti,j721e-dsi";
+ reg = <0x0 0x30500000 0x0 0x100000>,
+ <0x0 0x30270000 0x0 0x100>;
+ clocks = <&scmi_clk 155>, <&scmi_clk 158>;
+ clock-names = "dsi_p_clk", "dsi_sys_clk";
+ power-domains = <&scmi_pds 38>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&dphy_tx0>;
+ phy-names = "dphy";
+ status = "disabled";
+ };
+
+ gpmc0: memory-controller@3b000000 {
+ compatible = "ti,am64-gpmc";
+ reg = <0x00 0x3b000000 0x00 0x400>,
+ <0x00 0x50000000 0x00 0x8000000>;
+ power-domains = <&scmi_pds 37>;
+ clocks = <&scmi_clk 147>;
+ clock-names = "fck";
+ reg-names = "cfg", "data";
+ interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
+ gpmc,num-cs = <3>;
+ gpmc,num-waitpins = <2>;
+ interrupt-controller;
+ gpio-controller;
+ #interrupt-cells = <2>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ oc_sram: sram@70800000 {
+ compatible = "mmio-sram";
+ reg = <0x00 0x70800000 0x00 0x10000>;
+ ranges = <0x0 0x00 0x70800000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ scmi_shmem: sram@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x100>;
+ };
+ };
+};
diff --git a/arch/arm/dts/k3-am62l-thermal.dtsi b/arch/arm/dts/k3-am62l-thermal.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..55a83eaa88c943deb767a26e8fbe2d7f88a7c04c
--- /dev/null
+++ b/arch/arm/dts/k3-am62l-thermal.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Thermal limits for the AM62L
+ * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4
+ */
+
+#include <dt-bindings/thermal/thermal.h>
+
+thermal_zones: thermal-zones {
+ main0_thermal: main0-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&wkup_vtm0 0>;
+
+ trips {
+ main0_crit: main0-crit {
+ temperature = <105000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/k3-am62l-wakeup.dtsi b/arch/arm/dts/k3-am62l-wakeup.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..1e4ca8ec7babe78ca60106f0d06e4d8e2953bac8
--- /dev/null
+++ b/arch/arm/dts/k3-am62l-wakeup.dtsi
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0-only or MIT
+/*
+ * Device Tree file for the AM62L wakeup domain peripherals
+ * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4
+ */
+
+#include <dt-bindings/bus/ti-sysc.h>
+
+&cbass_wakeup {
+ wkup_vtm0: temperature-sensor@b00000 {
+ compatible = "ti,j7200-vtm";
+ reg = <0x00 0xb00000 0x00 0x400>,
+ <0x00 0xb01000 0x00 0x400>;
+ power-domains = <&scmi_pds 46>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ pmx0: pinctrl@4084000 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0x4084000 0x00 0x8000>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ #pinctrl-cells = <1>;
+ bootph-all;
+ };
+
+ wkup_gpio0: gpio@4201000 {
+ compatible = "ti,am64-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x04201000 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 276 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 704 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 705 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 706 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 707 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 708 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 709 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 710 IRQ_TYPE_EDGE_RISING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ power-domains = <&scmi_pds 36>;
+ clocks = <&scmi_clk 142>;
+ clock-names = "gpio";
+ ti,ngpio = <7>;
+ ti,davinci-gpio-unbanked = <0>;
+ status = "disabled";
+ };
+
+ wkup_timer0: timer@2b100000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2b100000 0x00 0x400>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk 85>;
+ clock-names = "fck";
+ power-domains = <&scmi_pds 19>;
+ ti,timer-pwm;
+ };
+
+ wkup_timer1: timer@2b110000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2b110000 0x00 0x400>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk 96>;
+ clock-names = "fck";
+ power-domains = <&scmi_pds 20>;
+ ti,timer-pwm;
+ };
+
+ wkup_i2c0: i2c@2b200000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x2b200000 0x00 0x100>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&scmi_pds 57>;
+ clocks = <&scmi_clk 262>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ target-module@2b300050 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x00 0x2b300050 0x00 0x4>,
+ <0x00 0x2b300054 0x00 0x4>,
+ <0x00 0x2b300058 0x00 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ranges = <0x0 0x00 0x2b300000 0x100000>;
+ power-domains = <&scmi_pds 83>;
+ clocks = <&scmi_clk 324>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ ti,no-reset-on-init;
+ status = "disabled";
+
+ wkup_uart0: serial@0 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk 324>;
+ assigned-clocks = <&scmi_clk 324>;
+ assigned-clock-rates = <48000000>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+ };
+
+ wkup_conf: syscon@43000000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x00 0x43000000 0x00 0x20000>;
+ ranges = <0x0 0x00 0x43000000 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chipid: chipid@14 {
+ compatible = "ti,am654-chipid";
+ reg = <0x14 0x4>;
+ bootph-all;
+ };
+ };
+};
diff --git a/arch/arm/dts/k3-am62l.dtsi b/arch/arm/dts/k3-am62l.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..19e73a2267503caca1cc7969700931a5a594e3aa
--- /dev/null
+++ b/arch/arm/dts/k3-am62l.dtsi
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: GPL-2.0-only or MIT
+/*
+ * Device Tree Source for AM62L SoC Family
+ * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "k3-pinctrl.h"
+
+/ {
+ model = "Texas Instruments K3 AM62L3 SoC";
+ compatible = "ti,am62l3";
+ interrupt-parent = <&gic500>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+
+ psci: psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ scmi: scmi {
+ compatible = "arm,scmi-smc";
+ arm,smc-id = <0x82004000>;
+ shmem = <&scmi_shmem>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ bootph-all;
+ };
+
+ scmi_pds: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ bootph-all;
+ };
+ };
+ };
+
+ a53_timer0: timer-cl0-cpu0 {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ cbass_main: bus@f0000 {
+ compatible = "simple-bus";
+ ranges = <0x00 0x00600000 0x00 0x00600000 0x00 0x00010100>, /* GPIO */
+ <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First Peripheral Window */
+ <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000400>, /* Timesync Router */
+ <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* CPSW */
+ <0x00 0x09000000 0x00 0x09000000 0x00 0x00400000>, /* CTRL MMRs */
+ <0x00 0x0e000000 0x00 0x0e000000 0x00 0x1a001400>, /* Second Peripheral Window */
+ <0x00 0x301c0000 0x00 0x301c0000 0x00 0x00001000>, /* DPHY-TX */
+ <0x00 0x30200000 0x00 0x30200000 0x00 0x0000b000>, /* DSS */
+ <0x00 0x30270000 0x00 0x30270000 0x00 0x00390000>, /* DSI Wrapper */
+ <0x00 0x30500000 0x00 0x30500000 0x00 0x00100000>, /* DSI Config */
+ <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core Window */
+ <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core Window */
+ <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0 */
+ <0x00 0x45810000 0x00 0x45810000 0x00 0x03170000>, /* DMSS */
+ <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC DATA */
+ <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS DAT1 */
+ <0x00 0x70800000 0x00 0x70800000 0x00 0x00018000>, /* OCSRAM */
+ <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
+ <0x04 0x00000000 0x04 0x00000000 0x01 0x00000000>, /* FSS DAT0 */
+ <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS DAT3 */
+
+ /* Wakeup Domain Range */
+ <0x00 0x00a80000 0x00 0x00a80000 0x00 0x00034000>, /* GTC */
+ <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00001400>, /* VTM */
+ <0x00 0x04080000 0x00 0x04080000 0x00 0x00008000>, /* PDGCFG */
+ <0x00 0x04201000 0x00 0x04201000 0x00 0x00000100>, /* GPIO */
+ <0x00 0x2b100000 0x00 0x2b100000 0x00 0x00100100>, /* Wakeup Peripheral Window */
+ <0x00 0x40800000 0x00 0x40800000 0x00 0x00014000>, /* DMA */
+ <0x00 0x43000000 0x00 0x43000000 0x00 0x00080000>; /* CTRL MMRs */
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cbass_wakeup: bus@43000000 {
+ compatible = "simple-bus";
+ ranges = <0x00 0x00a80000 0x00 0x00a80000 0x00 0x00034000>, /* GTC */
+ <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00001400>, /* VTM */
+ <0x00 0x04080000 0x00 0x04080000 0x00 0x00008000>, /* PDGCFG */
+ <0x00 0x04201000 0x00 0x04201000 0x00 0x00000100>, /* GPIO */
+ <0x00 0x2b100000 0x00 0x2b100000 0x00 0x00100100>, /* Wakeup Peripheral Window */
+ <0x00 0x40800000 0x00 0x40800000 0x00 0x00014000>, /* DMA */
+ <0x00 0x43000000 0x00 0x43000000 0x00 0x00080000>; /* CTRL MMRs */
+ #address-cells = <2>;
+ #size-cells = <2>;
+ bootph-all;
+ };
+ };
+
+ #include "k3-am62l-thermal.dtsi"
+};
+
+/* Now include peripherals for each bus segment */
+#include "k3-am62l-main.dtsi"
+#include "k3-am62l-wakeup.dtsi"
diff --git a/arch/arm/dts/k3-am62l3-evm.dts b/arch/arm/dts/k3-am62l3-evm.dts
new file mode 100644
index 0000000000000000000000000000000000000000..16efb60bf326018cd483cdeae35ed9538d24d522
--- /dev/null
+++ b/arch/arm/dts/k3-am62l3-evm.dts
@@ -0,0 +1,294 @@
+// SPDX-License-Identifier: GPL-2.0-only or MIT
+/*
+ * Device Tree file for the AM62L3 Evaluation Module
+ * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4
+ * Data Sheet: https://www.ti.com/lit/pdf/sprspa1
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+#include "k3-am62l3.dtsi"
+#include "k3-pinctrl.h"
+
+/ {
+ compatible = "ti,am62l3-evm", "ti,am62l3";
+ model = "Texas Instruments AM62L3 Evaluation Module";
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ gpio_keys: gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usr_btn_pins_default>;
+
+ usr: button-usr {
+ label = "User Key";
+ linux,code = <BTN_0>;
+ gpios = <&gpio0 90 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usr_led_pins_default>;
+
+ led-0 {
+ label = "am62-sk:green:heartbeat";
+ gpios = <&gpio0 123 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ function = LED_FUNCTION_HEARTBEAT;
+ default-state = "on";
+ };
+ };
+
+ memory@80000000 {
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+ device_type = "memory";
+ bootph-all;
+ };
+
+ vcc_1v8: regulator-3 {
+ /* output of TPS6282518DMQ */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3_sys>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc_3v3_sys: regulator-1 {
+ /* output of LM61460-Q1 */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3_sys";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vmain_pd>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vmain_pd: regulator-0 {
+ /* TPS65988 PD CONTROLLER OUTPUT */
+ bootph-all;
+ compatible = "regulator-fixed";
+ regulator-name = "vmain_pd";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_default>;
+ clock-frequency = <400000>;
+ status = "okay";
+ bootph-all;
+
+ eeprom@51 {
+ /* AT24C512C-MAHM-T or M24512-DFMC6TG */
+ compatible = "atmel,24c512";
+ reg = <0x51>;
+ };
+};
+
+&i2c1 {
+ pinctrl-0 = <&i2c1_pins_default>;
+ pinctrl-names = "default";
+ clock-frequency = <100000>;
+ status = "okay";
+ bootph-all;
+
+ exp1: gpio@22 {
+ compatible = "ti,tca6424";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "", "",
+ "UART1_FET_SEL", "MMC1_SD_EN",
+ "VPP_EN", "EXP_PS_3V3_EN",
+ "UART1_FET_BUF_EN", "",
+ "DSI_GPIO0", "DSI_GPIO1",
+ "", "BT_UART_WAKE_SOC_3V3",
+ "USB_TYPEA_OC_INDICATION", "",
+ "", "WLAN_ALERTn",
+ "HDMI_INTn", "TEST_GPIO2",
+ "MCASP0_FET_EN", "MCASP0_BUF_BT_EN",
+ "MCASP0_FET_SEL", "DSI_EDID",
+ "PD_I2C_IRQ", "IO_EXP_TEST_LED";
+
+ interrupt-parent = <&gpio0>;
+ interrupts = <91 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ pinctrl-0 = <&gpio0_ioexp_intr_pins_default>;
+ pinctrl-names = "default";
+ bootph-all;
+ };
+
+ exp2: gpio@23 {
+ compatible = "ti,tca6424";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "BT_EN_SOC", "VOUT0_FET_SEL0",
+ "", "",
+ "", "",
+ "", "",
+ "WL_LT_EN", "EXP_PS_5V0_EN",
+ "TP45", "TP48",
+ "TP46", "TP49",
+ "TP47", "TP50",
+ "GPIO_QSPI_NAND_RSTn", "GPIO_HDMI_RSTn",
+ "GPIO_CPSW1_RST", "GPIO_CPSW2_RST",
+ "", "GPIO_AUD_RSTn",
+ "GPIO_eMMC_RSTn", "SoC_WLAN_SDIO_RST";
+
+ bootph-all;
+ };
+};
+
+&pmx0 {
+ gpio0_ioexp_intr_pins_default: gpio0-ioexp-intr-default-pins {
+ pinctrl-single,pins = <
+ AM62LX_IOPAD(0x01b0, PIN_INPUT, 7) /* (B12) SPI0_D1.GPIO0_91 */
+ >;
+ bootph-all;
+ };
+
+ i2c0_pins_default: i2c0-default-pins {
+ pinctrl-single,pins = <
+ AM62LX_IOPAD(0x01cc, PIN_INPUT_PULLUP, 0) /* (B7) I2C0_SCL */
+ AM62LX_IOPAD(0x01d0, PIN_INPUT_PULLUP, 0) /* (A7) I2C0_SDA */
+ >;
+ bootph-all;
+ };
+
+ i2c1_pins_default: i2c1-default-pins {
+ pinctrl-single,pins = <
+ AM62LX_IOPAD(0x01d4, PIN_INPUT_PULLUP, 0) /* (D7) I2C1_SCL */
+ AM62LX_IOPAD(0x01d8, PIN_INPUT_PULLUP, 0) /* (A6) I2C1_SDA */
+ >;
+ };
+
+ mmc0_pins_default: mmc0-default-pins {
+ pinctrl-single,pins = <
+ AM62LX_IOPAD(0x0214, PIN_INPUT_PULLUP, 0) /* (D2) MMC0_CMD */
+ AM62LX_IOPAD(0x020c, PIN_OUTPUT, 0) /* (B2) MMC0_CLK */
+ AM62LX_IOPAD(0x0208, PIN_INPUT_PULLUP, 0) /* (D3) MMC0_DAT0 */
+ AM62LX_IOPAD(0x0204, PIN_INPUT_PULLUP, 0) /* (D4) MMC0_DAT1 */
+ AM62LX_IOPAD(0x0200, PIN_INPUT_PULLUP, 0) /* (C1) MMC0_DAT2 */
+ AM62LX_IOPAD(0x01fc, PIN_INPUT_PULLUP, 0) /* (C2) MMC0_DAT3 */
+ AM62LX_IOPAD(0x01f8, PIN_INPUT_PULLUP, 0) /* (C4) MMC0_DAT4 */
+ AM62LX_IOPAD(0x01f4, PIN_INPUT_PULLUP, 0) /* (B3) MMC0_DAT5 */
+ AM62LX_IOPAD(0x01f0, PIN_INPUT_PULLUP, 0) /* (A3) MMC0_DAT6 */
+ AM62LX_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (B4) MMC0_DAT7 */
+ >;
+ bootph-all;
+ };
+
+ mmc1_pins_default: mmc1-default-pins {
+ pinctrl-single,pins = <
+ AM62LX_IOPAD(0x0230, PIN_INPUT, 0) /* (Y3) MMC1_CMD */
+ AM62LX_IOPAD(0x0228, PIN_OUTPUT, 0) /* (Y2) MMC1_CLK */
+ AM62LX_IOPAD(0x0224, PIN_INPUT, 0) /* (AA1) MMC1_DAT0 */
+ AM62LX_IOPAD(0x0220, PIN_INPUT_PULLUP, 0) /* (Y4) MMC1_DAT1 */
+ AM62LX_IOPAD(0x021c, PIN_INPUT_PULLUP, 0) /* (AA2) MMC1_DAT2 */
+ AM62LX_IOPAD(0x0218, PIN_INPUT_PULLUP, 0) /* (AB2) MMC1_DAT3 */
+ AM62LX_IOPAD(0x0234, PIN_INPUT, 0) /* (B6) MMC1_SDCD */
+ >;
+ bootph-all;
+ };
+
+ uart0_pins_default: uart0-default-pins {
+ pinctrl-single,pins = <
+ AM62LX_IOPAD(0x01b4, PIN_INPUT, 0) /* (D13) UART0_RXD */
+ AM62LX_IOPAD(0x01b8, PIN_OUTPUT, 0) /* (C13) UART0_TXD */
+ >;
+ bootph-all;
+ };
+
+ uart1_pins_default: uart1-default-pins {
+ pinctrl-single,pins = <
+ AM62LX_IOPAD(0x0180, PIN_INPUT, 2) /* (A8) MCASP0_AXR3.UART1_CTSn */
+ AM62LX_IOPAD(0x0184, PIN_OUTPUT, 2) /* (B10) MCASP0_AXR2.UART1_RTSn */
+ AM62LX_IOPAD(0x0198, PIN_INPUT, 2) /* (C11) MCASP0_AFSR.UART1_RXD */
+ AM62LX_IOPAD(0x019c, PIN_OUTPUT, 2) /* (A12) MCASP0_ACLKR.UART1_TXD */
+ >;
+ bootph-all;
+ };
+
+ usb1_default_pins: usb1-default-pins {
+ pinctrl-single,pins = <
+ AM62LX_IOPAD(0x0248, PIN_INPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP, 0) /* (A5) USB1_DRVVBUS */
+ >;
+ };
+
+ usr_btn_pins_default: usr-btn-default-pins {
+ pinctrl-single,pins = <
+ AM62LX_IOPAD(0x01ac, PIN_INPUT, 7) /* (E12) SPI0_D0.GPIO0_90 */
+ >;
+ };
+
+ usr_led_pins_default: usr-led-default-pins {
+ pinctrl-single,pins = <
+ AM62LX_IOPAD(0x0238, PIN_OUTPUT, 7) /* (D24) MMC1_SDWP.GPIO0_123 */
+ >;
+ };
+};
+
+&sdhci0 {
+ /* eMMC */
+ pinctrl-0 = <&mmc0_pins_default>;
+ pinctrl-names = "default";
+ non-removable;
+ status = "okay";
+ bootph-all;
+};
+
+&sdhci1 {
+ /* SD/MMC */
+ pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-names = "default";
+ status = "okay";
+ bootph-all;
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pins_default>;
+ pinctrl-names = "default";
+ status = "okay";
+ bootph-all;
+};
+
+&uart1 {
+ pinctrl-0 = <&uart1_pins_default>;
+ pinctrl-names = "default";
+ status = "okay";
+ bootph-all;
+};
+
+&usb1 {
+ pinctrl-0 = <&usb1_default_pins>;
+ pinctrl-names = "default";
+ dr_mode = "host";
+};
+
+&usbss1 {
+ ti,vbus-divider;
+ status = "okay";
+};
diff --git a/arch/arm/dts/k3-am62l3.dtsi b/arch/arm/dts/k3-am62l3.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..da220b85151227c63f59b2b8ec48ae2ebb37e7bf
--- /dev/null
+++ b/arch/arm/dts/k3-am62l3.dtsi
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0-only or MIT
+/*
+ * Device Tree file for the AM62L3 SoC family (Dual Core A53)
+ * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4
+ */
+
+/dts-v1/;
+
+#include "k3-am62l.dtsi"
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0: cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ reg = <0x000>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ reg = <0x001>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ };
+ };
+
+ l2_0: l2-cache0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ cache-size = <0x40000>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
+ };
+};
diff --git a/arch/arm/dts/k3-pinctrl.h b/arch/arm/dts/k3-pinctrl.h
new file mode 100644
index 0000000000000000000000000000000000000000..5f23f4d9c7f83bfa188da2056f28c7ddd06d7afe
--- /dev/null
+++ b/arch/arm/dts/k3-pinctrl.h
@@ -0,0 +1,7 @@
+#ifndef __DTS_TI_K3_PINCTRL_BAREBOX_H
+#define __DTS_TI_K3_PINCTRL_BAREBOX_H
+
+#include <arm64/ti/k3-pinctrl.h>
+#define AM62LX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+
+#endif /* __DTS_TI_K3_PINCTRL_BAREBOX_H */
--
2.39.5
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 05/31] ARM: dts: am62l: Fix assigned-clock-parents
2025-05-28 11:45 [PATCH 00/31] ARM: K3: add support for AM62L Sascha Hauer
` (3 preceding siblings ...)
2025-05-28 11:45 ` [PATCH 04/31] ARM: dts: add k3-am62l dts(i) files Sascha Hauer
@ 2025-05-28 11:45 ` Sascha Hauer
2025-05-28 11:45 ` [PATCH 06/31] ARM: K3: add am62lx base support Sascha Hauer
` (25 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Sascha Hauer @ 2025-05-28 11:45 UTC (permalink / raw)
To: BAREBOX
The AM62l device trees we imported to barebox have problems with the
clock parents which is described in [1] and [2].
There is no way the Kernel or barebox SCMI clk drivers can work with the
current way the clk parents are specified in the downstream TF-A. This
problem is acknowledged by TI and will hopefully be fixed.
This patch fixes the clk parents the way that I hope TI will do it as
well. Currently this only works with a patched downstream TF-A.
[1] https://lore.kernel.org/all/aCcSG5ah12N0yOwi@pengutronix.de/
[2] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/34834/1/plat/ti/k3/common/drivers/scmi/scmi_clock.c#165
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/dts/k3-am62l-main.dtsi | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm/dts/k3-am62l-main.dtsi b/arch/arm/dts/k3-am62l-main.dtsi
index f6fbaaede8c36ac0aab92bef7763202bb0ab30dc..d161df3215c35a2d3de67e8ca021b9a9a89edb80 100644
--- a/arch/arm/dts/k3-am62l-main.dtsi
+++ b/arch/arm/dts/k3-am62l-main.dtsi
@@ -217,7 +217,7 @@ rti0: watchdog@e000000 {
clocks = <&scmi_clk 273>;
power-domains = <&scmi_pds 60>;
assigned-clocks = <&scmi_clk 273>;
- assigned-clock-parents = <&scmi_clk 1>;
+ assigned-clock-parents = <&scmi_clk 275>;
};
rti1: watchdog@e010000 {
@@ -226,7 +226,7 @@ rti1: watchdog@e010000 {
clocks = <&scmi_clk 279>;
power-domains = <&scmi_pds 61>;
assigned-clocks = <&scmi_clk 279>;
- assigned-clock-parents = <&scmi_clk 1>;
+ assigned-clock-parents = <&scmi_clk 281>;
};
fss: bus@fc00000 {
@@ -317,7 +317,7 @@ sdhci0: mmc@fa10000 {
clocks = <&scmi_clk 122>, <&scmi_clk 123>;
clock-names = "clk_ahb", "clk_xin";
assigned-clocks = <&scmi_clk 123>;
- assigned-clock-parents = <&scmi_clk 0>;
+ assigned-clock-parents = <&scmi_clk 124>;
bus-width = <8>;
ti,clkbuf-sel = <0x7>;
ti,otap-del-sel-legacy = <0x0>;
@@ -334,7 +334,7 @@ sdhci1: mmc@fa00000 {
clocks = <&scmi_clk 106>, <&scmi_clk 107>;
clock-names = "clk_ahb", "clk_xin";
assigned-clocks = <&scmi_clk 107>;
- assigned-clock-parents = <&scmi_clk 0>;
+ assigned-clock-parents = <&scmi_clk 108>;
bus-width = <4>;
ti,clkbuf-sel = <0x7>;
ti,otap-del-sel-legacy = <0x0>;
@@ -351,7 +351,7 @@ sdhci2: mmc@fa20000 {
clocks = <&scmi_clk 114>, <&scmi_clk 115>;
clock-names = "clk_ahb", "clk_xin";
assigned-clocks = <&scmi_clk 115>;
- assigned-clock-parents = <&scmi_clk 0>;
+ assigned-clock-parents = <&scmi_clk 116>;
bus-width = <4>;
ti,clkbuf-sel = <0x7>;
ti,otap-del-sel-legacy = <0x0>;
@@ -600,7 +600,7 @@ tscadc0: tscadc@28001000 {
power-domains = <&scmi_pds 0>;
clocks = <&scmi_clk 0>;
assigned-clocks = <&scmi_clk 0>;
- assigned-clock-parents = <&scmi_clk 2>;
+ assigned-clock-parents = <&scmi_clk 3>;
assigned-clock-rates = <60000000>;
clock-names = "fck";
status = "disabled";
@@ -618,7 +618,7 @@ dphy_tx0: phy@301c0000 {
clock-names = "psm", "pll_ref";
power-domains = <&scmi_pds 86>;
assigned-clocks = <&scmi_clk 341>;
- assigned-clock-parents = <&scmi_clk 0>;
+ assigned-clock-parents = <&scmi_clk 342>;
assigned-clock-rates = <25000000>;
#phy-cells = <0>;
status = "disabled";
--
2.39.5
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 06/31] ARM: K3: add am62lx base support
2025-05-28 11:45 [PATCH 00/31] ARM: K3: add support for AM62L Sascha Hauer
` (4 preceding siblings ...)
2025-05-28 11:45 ` [PATCH 05/31] ARM: dts: am62l: Fix assigned-clock-parents Sascha Hauer
@ 2025-05-28 11:45 ` Sascha Hauer
2025-05-28 11:45 ` [PATCH 07/31] ARM: Makefile: descend into mach-* for cleaning Sascha Hauer
` (24 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Sascha Hauer @ 2025-05-28 11:45 UTC (permalink / raw)
To: BAREBOX
This adds the MACH_AM62LX Kconfig symbol to be selected by the boards
and the AM62l bootsource detection.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-k3/Kconfig | 3 +
arch/arm/mach-k3/Makefile | 1 +
arch/arm/mach-k3/am62lx.c | 155 ++++++++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-k3/common.c | 5 +-
include/mach/k3/common.h | 1 +
5 files changed, 164 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index 1c236ef7648869ff3605bfb379298f0e6e6f3305..cda44807e8a1db7c2f701309948c7bd1a863d365 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -6,6 +6,9 @@ menu "K3 boards"
config MACH_AM62X
bool
+config MACH_AM62LX
+ bool
+
config MACH_K3_CORTEX_R5
bool
select CPU_V7
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index b81088007426a1e2a43d84a0d09b49525370c4bf..050d12a32a6720170a007931fee8a621a0326dd2 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -1,5 +1,6 @@
obj-y += common.o
obj-$(CONFIG_MACH_AM62X) += am62x.o
+obj-$(CONFIG_MACH_AM62LX) += am62lx.o
obj-pbl-$(CONFIG_MACH_K3_CORTEX_R5) += r5.o
obj-pbl-y += ddrss.o
obj-$(CONFIG_BAREBOX_UPDATE) += bbu.o
diff --git a/arch/arm/mach-k3/am62lx.c b/arch/arm/mach-k3/am62lx.c
new file mode 100644
index 0000000000000000000000000000000000000000..38a88ea7cf95be110a4125807630db10d402534e
--- /dev/null
+++ b/arch/arm/mach-k3/am62lx.c
@@ -0,0 +1,155 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <io.h>
+#include <of.h>
+#include <init.h>
+#include <linux/bits.h>
+#include <linux/bitfield.h>
+#include <pm_domain.h>
+#include <bootsource.h>
+#include <mach/k3/common.h>
+
+/* Primary BootMode devices */
+#define BOOT_DEVICE_SPI_NAND 0x00
+#define BOOT_DEVICE_RAM 0xFF
+#define BOOT_DEVICE_OSPI 0x01
+#define BOOT_DEVICE_QSPI 0x02
+#define BOOT_DEVICE_SPI 0x03
+#define BOOT_DEVICE_UART 0x07
+#define BOOT_DEVICE_MMC 0x08
+#define BOOT_DEVICE_EMMC 0x09
+#define BOOT_DEVICE_USB 0x0A
+#define BOOT_DEVICE_DFU 0x0A
+#define BOOT_DEVICE_GPMC_NAND 0x0B
+#define BOOT_DEVICE_XSPI_FAST 0x0D
+#define BOOT_DEVICE_XSPI 0x0E
+#define BOOT_DEVICE_NOBOOT 0x0F
+
+/* U-Boot used aliases */
+#define BOOT_DEVICE_SPINAND 0x10
+#define BOOT_DEVICE_MMC2 BOOT_DEVICE_MMC
+#define BOOT_DEVICE_MMC1 BOOT_DEVICE_EMMC
+/* Invalid Choices for the AM62Lx */
+#define BOOT_DEVICE_MMC2_2 0x1F
+#define BOOT_DEVICE_ETHERNET 0x1F
+
+/* Backup BootMode devices */
+#define BACKUP_BOOT_DEVICE_USB 0x01
+#define BACKUP_BOOT_DEVICE_DFU 0x01
+#define BACKUP_BOOT_DEVICE_UART 0x03
+#define BACKUP_BOOT_DEVICE_MMC 0x05
+#define BACKUP_BOOT_DEVICE_SPI 0x06
+
+#define K3_PRIMARY_BOOTMODE 0x0
+
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE GENMASK(12, 10)
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG BIT(13)
+#define MAIN_DEVSTAT_BACKUP_USB_MODE BIT(0)
+
+static void am62lx_get_backup_bootsource(u32 devstat, enum bootsource *src, int *instance)
+{
+ u32 bkup_bootmode = FIELD_GET(MAIN_DEVSTAT_BACKUP_BOOTMODE, devstat);
+ u32 bkup_bootmode_cfg = FIELD_GET(MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG, devstat);
+
+ *src = BOOTSOURCE_UNKNOWN;
+
+ switch (bkup_bootmode) {
+ case BACKUP_BOOT_DEVICE_UART:
+ *src = BOOTSOURCE_SERIAL;
+ return;
+ case BACKUP_BOOT_DEVICE_MMC:
+ if (bkup_bootmode_cfg) {
+ *src = BOOTSOURCE_MMC;
+ *instance = 1;
+ } else {
+ *src = BOOTSOURCE_MMC;
+ *instance = 0;
+ }
+ return;
+ case BACKUP_BOOT_DEVICE_SPI:
+ *src = BOOTSOURCE_SPI;
+ return;
+ case BACKUP_BOOT_DEVICE_USB:
+ if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE)
+ *src = BOOTSOURCE_USB;
+ else
+ *src = BOOTSOURCE_SERIAL;
+ return;
+ };
+}
+
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE GENMASK(6, 3)
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG GENMASK(9, 7)
+#define MAIN_DEVSTAT_PRIMARY_USB_MODE BIT(1)
+#define MAIN_DEVSTAT_PRIMARY_MMC_PORT BIT(2)
+
+static void am62lx_get_primary_bootsource(u32 devstat, enum bootsource *src, int *instance)
+{
+ u32 bootmode = FIELD_GET(MAIN_DEVSTAT_PRIMARY_BOOTMODE, devstat);
+ u32 bootmode_cfg = FIELD_GET(MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG, devstat);
+
+ switch (bootmode) {
+ case BOOT_DEVICE_OSPI:
+ case BOOT_DEVICE_QSPI:
+ case BOOT_DEVICE_XSPI:
+ case BOOT_DEVICE_SPI:
+ *src = BOOTSOURCE_SPI;
+ return;
+ case BOOT_DEVICE_EMMC:
+ *src = BOOTSOURCE_MMC;
+ *instance = 0;
+ return;
+ case BOOT_DEVICE_MMC:
+ if (bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT) {
+ *src = BOOTSOURCE_MMC;
+ *instance = 1;
+ } else {
+ *src = BOOTSOURCE_MMC;
+ *instance = 0;
+ }
+ return;
+ case BOOT_DEVICE_USB:
+ if (bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE)
+ *src = BOOTSOURCE_USB;
+ else
+ *src = BOOTSOURCE_SERIAL;
+ return;
+ case BOOT_DEVICE_NOBOOT:
+ *src = BOOTSOURCE_UNKNOWN;
+ return;
+ }
+}
+
+#define AM62LX_BOOT_PARAM_TABLE_INDEX_OCRAM IOMEM(0x70816e70)
+
+#define AM62LX_WKUP_CTRL_MMR0_BASE IOMEM(0x43010000)
+#define AM62LX_CTRLMMR_MAIN_DEVSTAT (AM62LX_WKUP_CTRL_MMR0_BASE + 0x30)
+
+void am62lx_get_bootsource(enum bootsource *src, int *instance)
+{
+ u32 bootmode = readl(AM62LX_BOOT_PARAM_TABLE_INDEX_OCRAM);
+ u32 devstat;
+
+ devstat = readl(AM62LX_CTRLMMR_MAIN_DEVSTAT);
+
+ if (bootmode == K3_PRIMARY_BOOTMODE)
+ am62lx_get_primary_bootsource(devstat, src, instance);
+ else
+ am62lx_get_backup_bootsource(devstat, src, instance);
+}
+
+static int am62lx_init(void)
+{
+ enum bootsource src = BOOTSOURCE_UNKNOWN;
+ int instance = 0;
+
+ if (!of_machine_is_compatible("ti,am62l3"))
+ return 0;
+
+ am62lx_get_bootsource(&src, &instance);
+ bootsource_set(src, instance);
+
+ genpd_activate();
+
+ return 0;
+}
+postcore_initcall(am62lx_init);
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 7299355eecef1c38e0d53a8feda60d233d74e2cd..aafd22453b9c8393e75fad07a21712a5af6674ef 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -20,8 +20,11 @@
static const struct of_device_id k3_of_match[] = {
{
.compatible = "ti,am625",
+ }, {
+ .compatible = "ti,am62l3",
+ }, {
+ /* sentinel */
},
- { /* sentinel */ },
};
BAREBOX_DEEP_PROBE_ENABLE(k3_of_match);
diff --git a/include/mach/k3/common.h b/include/mach/k3/common.h
index d14b8b9cb891dd23dcc3a6277e79aa9f639f412a..5ce129f88cc8522954670d0ae34dda76445fcb75 100644
--- a/include/mach/k3/common.h
+++ b/include/mach/k3/common.h
@@ -9,6 +9,7 @@
UUID_INIT(0x9e8c2017, 0x8b94, 0x4e2b, 0xa7, 0xb3, 0xa0, 0xf8, 0x8e, 0xab, 0xb8, 0xae)
void am62x_get_bootsource(enum bootsource *src, int *instance);
+void am62lx_get_bootsource(enum bootsource *src, int *instance);
bool k3_boot_is_emmc(void);
u64 am62x_sdram_size(void);
void am62x_register_dram(void);
--
2.39.5
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 07/31] ARM: Makefile: descend into mach-* for cleaning
2025-05-28 11:45 [PATCH 00/31] ARM: K3: add support for AM62L Sascha Hauer
` (5 preceding siblings ...)
2025-05-28 11:45 ` [PATCH 06/31] ARM: K3: add am62lx base support Sascha Hauer
@ 2025-05-28 11:45 ` Sascha Hauer
2025-05-28 11:45 ` [PATCH 08/31] ARM: k3: rename yaml files from am625 to am62x Sascha Hauer
` (23 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Sascha Hauer @ 2025-05-28 11:45 UTC (permalink / raw)
To: BAREBOX
When you run "make clean" for arm, it never visits mach-* directories
because machine-y is just empty. With this files generated with extra-y
like the .k3cfg files are not cleaned.
When cleaning, all machine directories are accumulated to machine-, so
let's pass them to common- to clean up those directories.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/Makefile | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index e4041cf715c4b7f7c62e86941c94b9cd549573b7..eb71c84f587a583eb306483d3aa554273e827ddd 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -99,7 +99,6 @@ machine-$(CONFIG_ARCH_MVEBU) += mvebu
machine-$(CONFIG_ARCH_OMAP) += omap
machine-$(CONFIG_ARCH_PXA) += pxa
machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
-machine-$(CONFIG_ARCH_SAMSUNG) += samsung
machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
machine-$(CONFIG_ARCH_STM32MP) += stm32mp
machine-$(CONFIG_ARCH_SUNXI) += sunxi
@@ -139,6 +138,9 @@ common-y += arch/arm/boards/ $(MACH)
common-y += arch/arm/cpu/
common-y += arch/arm/crypto/
+# For cleaning
+common- += $(patsubst %,arch/arm/mach-%/,$(machine-))
+
ifeq ($(CONFIG_CPU_64), y)
common-y += arch/arm/lib64/
else
--
2.39.5
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 08/31] ARM: k3: rename yaml files from am625 to am62x
2025-05-28 11:45 [PATCH 00/31] ARM: K3: add support for AM62L Sascha Hauer
` (6 preceding siblings ...)
2025-05-28 11:45 ` [PATCH 07/31] ARM: Makefile: descend into mach-* for cleaning Sascha Hauer
@ 2025-05-28 11:45 ` Sascha Hauer
2025-05-28 11:45 ` [PATCH 09/31] scripts/ti-board-config.py: fix length Sascha Hauer
` (22 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Sascha Hauer @ 2025-05-28 11:45 UTC (permalink / raw)
To: BAREBOX
The yaml files for the board configuration are named 'am625', but they
seem to work on other am62x variants as well, so rename them.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-k3/Makefile | 18 +++++++++---------
.../{board-cfg-am625.yaml => board-cfg-am62x.yaml} | 0
.../mach-k3/{pm-cfg-am625.yaml => pm-cfg-am62x.yaml} | 0
.../mach-k3/{rm-cfg-am625.yaml => rm-cfg-am62x.yaml} | 0
.../mach-k3/{sec-cfg-am625.yaml => sec-cfg-am62x.yaml} | 0
images/Makefile.k3 | 4 ++--
6 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index 050d12a32a6720170a007931fee8a621a0326dd2..b05d90da4b3ad468cdfcdcb286c004f5e9e72925 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -5,18 +5,18 @@ obj-pbl-$(CONFIG_MACH_K3_CORTEX_R5) += r5.o
obj-pbl-y += ddrss.o
obj-$(CONFIG_BAREBOX_UPDATE) += bbu.o
-extra-$(CONFIG_MACH_K3_CORTEX_R5) += combined-dm-cfg-am625.k3cfg combined-sysfw-cfg-am625.k3cfg
+extra-$(CONFIG_MACH_K3_CORTEX_R5) += combined-dm-cfg-am62x.k3cfg combined-sysfw-cfg-am62x.k3cfg
-$(obj)/combined-dm-cfg-am625.k3cfg: $(srctree)/arch/arm/mach-k3/schema.yaml \
- $(obj)/pm-cfg-am625.yaml \
- $(obj)/rm-cfg-am625.yaml \
+$(obj)/combined-dm-cfg-am62x.k3cfg: $(srctree)/arch/arm/mach-k3/schema.yaml \
+ $(obj)/pm-cfg-am62x.yaml \
+ $(obj)/rm-cfg-am62x.yaml \
FORCE
$(call if_changed,k3_cfg)
-$(obj)/combined-sysfw-cfg-am625.k3cfg: $(srctree)/arch/arm/mach-k3/schema.yaml \
- $(obj)/board-cfg-am625.yaml \
- $(obj)/sec-cfg-am625.yaml \
- $(obj)/pm-cfg-am625.yaml \
- $(obj)/rm-cfg-am625.yaml \
+$(obj)/combined-sysfw-cfg-am62x.k3cfg: $(srctree)/arch/arm/mach-k3/schema.yaml \
+ $(obj)/board-cfg-am62x.yaml \
+ $(obj)/sec-cfg-am62x.yaml \
+ $(obj)/pm-cfg-am62x.yaml \
+ $(obj)/rm-cfg-am62x.yaml \
FORCE
$(call if_changed,k3_cfg)
diff --git a/arch/arm/mach-k3/board-cfg-am625.yaml b/arch/arm/mach-k3/board-cfg-am62x.yaml
similarity index 100%
rename from arch/arm/mach-k3/board-cfg-am625.yaml
rename to arch/arm/mach-k3/board-cfg-am62x.yaml
diff --git a/arch/arm/mach-k3/pm-cfg-am625.yaml b/arch/arm/mach-k3/pm-cfg-am62x.yaml
similarity index 100%
rename from arch/arm/mach-k3/pm-cfg-am625.yaml
rename to arch/arm/mach-k3/pm-cfg-am62x.yaml
diff --git a/arch/arm/mach-k3/rm-cfg-am625.yaml b/arch/arm/mach-k3/rm-cfg-am62x.yaml
similarity index 100%
rename from arch/arm/mach-k3/rm-cfg-am625.yaml
rename to arch/arm/mach-k3/rm-cfg-am62x.yaml
diff --git a/arch/arm/mach-k3/sec-cfg-am625.yaml b/arch/arm/mach-k3/sec-cfg-am62x.yaml
similarity index 100%
rename from arch/arm/mach-k3/sec-cfg-am625.yaml
rename to arch/arm/mach-k3/sec-cfg-am62x.yaml
diff --git a/images/Makefile.k3 b/images/Makefile.k3
index e31a5cd2dcdd4fdbe62f3084092b641499e404ff..801ffe42ca221b53ca0221e75eaa089bdf07b2b7 100644
--- a/images/Makefile.k3
+++ b/images/Makefile.k3
@@ -19,8 +19,8 @@ endif
ifdef CONFIG_MACH_K3_CORTEX_R5
-SYSFWDATA_am625=$(objtree)/arch/arm/mach-k3/combined-sysfw-cfg-am625.k3cfg
-DMDATA_am625=$(objtree)/arch/arm/mach-k3/combined-dm-cfg-am625.k3cfg
+SYSFWDATA_am625=$(objtree)/arch/arm/mach-k3/combined-sysfw-cfg-am62x.k3cfg
+DMDATA_am625=$(objtree)/arch/arm/mach-k3/combined-dm-cfg-am62x.k3cfg
SYSFW_am625_hs_fs=$(FIRMWARE_DIR)/ti-fs-firmware-am62x-hs-fs-enc.bin
SYSFW_am625_gp=$(FIRMWARE_DIR)/ti-fs-firmware-am62x-gp.bin
INNERDATA_am625=$(FIRMWARE_DIR)/ti-fs-firmware-am62x-hs-fs-cert.bin
--
2.39.5
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 09/31] scripts/ti-board-config.py: fix length
2025-05-28 11:45 [PATCH 00/31] ARM: K3: add support for AM62L Sascha Hauer
` (7 preceding siblings ...)
2025-05-28 11:45 ` [PATCH 08/31] ARM: k3: rename yaml files from am625 to am62x Sascha Hauer
@ 2025-05-28 11:45 ` Sascha Hauer
2025-05-28 11:45 ` [PATCH 10/31] ARM: k3: add yaml files for AM62l Sascha Hauer
` (21 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Sascha Hauer @ 2025-05-28 11:45 UTC (permalink / raw)
To: BAREBOX
The number of config files is encoded in the header. So far this was
hardcoded to 4. Fix this to include the actual number of config files
instead.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
scripts/ti-board-config.py | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/scripts/ti-board-config.py b/scripts/ti-board-config.py
index 4b6214c299d7bf000a56d90dcdf9120d438f58ff..24731c66d017837ab66a78faa41f7c310644e79d 100755
--- a/scripts/ti-board-config.py
+++ b/scripts/ti-board-config.py
@@ -36,8 +36,6 @@ class Entry_ti_board_config:
self._sw_rev = 1
self._devgrp = 0
self.cfgentries = []
- self.header = struct.pack('<BB', 4, 1)
- self._binary_offset = len(self.header)
self._schema_file = schema
def _convert_to_byte_chunk(self, val, data_type):
@@ -149,6 +147,9 @@ class Entry_ti_board_config:
return data
def save(self, filename):
+ print(len(self.cfgentries))
+ self.header = struct.pack('<BB', len(self.cfgentries), 1)
+ self._binary_offset = len(self.header)
with open(filename, "wb") as binary_file:
binary_file.write(self.header)
for i in self.cfgentries:
--
2.39.5
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 10/31] ARM: k3: add yaml files for AM62l
2025-05-28 11:45 [PATCH 00/31] ARM: K3: add support for AM62L Sascha Hauer
` (8 preceding siblings ...)
2025-05-28 11:45 ` [PATCH 09/31] scripts/ti-board-config.py: fix length Sascha Hauer
@ 2025-05-28 11:45 ` Sascha Hauer
2025-05-28 11:45 ` [PATCH 11/31] k3: ringacc: pass ringrt address in struct k3_ringacc_init_data Sascha Hauer
` (20 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Sascha Hauer @ 2025-05-28 11:45 UTC (permalink / raw)
To: BAREBOX
board-cfg-am62x.yaml can be re-used for AM62l, but we need a AM62l
specific sec-cfg-am62l.yaml. pm-cfg.yaml and rm-cfg.yaml are no longer
needed for AM62l, so create a new k3cfg file with only board-cfg.yaml
and sec-cfg.yaml.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-k3/Makefile | 7 +
arch/arm/mach-k3/sec-cfg-am62l.yaml | 379 ++++++++++++++++++++++++++++++++++++
2 files changed, 386 insertions(+)
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index b05d90da4b3ad468cdfcdcb286c004f5e9e72925..df77832887e992de934623d0a3384ab82454e2cc 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -6,6 +6,7 @@ obj-pbl-y += ddrss.o
obj-$(CONFIG_BAREBOX_UPDATE) += bbu.o
extra-$(CONFIG_MACH_K3_CORTEX_R5) += combined-dm-cfg-am62x.k3cfg combined-sysfw-cfg-am62x.k3cfg
+extra-$(CONFIG_MACH_AM62LX) += combined-sysfw-cfg-am62l.k3cfg
$(obj)/combined-dm-cfg-am62x.k3cfg: $(srctree)/arch/arm/mach-k3/schema.yaml \
$(obj)/pm-cfg-am62x.yaml \
@@ -20,3 +21,9 @@ $(obj)/combined-sysfw-cfg-am62x.k3cfg: $(srctree)/arch/arm/mach-k3/schema.yaml \
$(obj)/rm-cfg-am62x.yaml \
FORCE
$(call if_changed,k3_cfg)
+
+$(obj)/combined-sysfw-cfg-am62l.k3cfg: $(srctree)/arch/arm/mach-k3/schema.yaml \
+ $(obj)/board-cfg-am62x.yaml \
+ $(obj)/sec-cfg-am62l.yaml \
+ FORCE
+ $(call if_changed,k3_cfg)
diff --git a/arch/arm/mach-k3/sec-cfg-am62l.yaml b/arch/arm/mach-k3/sec-cfg-am62l.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..bea6891eda249e236b2057cc1e6758de2c47016d
--- /dev/null
+++ b/arch/arm/mach-k3/sec-cfg-am62l.yaml
@@ -0,0 +1,379 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Security management configuration for AM62Lx
+#
+---
+
+sec-cfg:
+ rev:
+ boardcfg_abi_maj: 0x0
+ boardcfg_abi_min: 0x1
+ processor_acl_list:
+ subhdr:
+ magic: 0xF1EA
+ size: 164
+
+ proc_acl_entries:
+ - # 1
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 2
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 3
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 4
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 5
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 6
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 7
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 8
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 9
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 10
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 11
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 12
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 13
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 14
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 15
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 16
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 17
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 18
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 19
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 20
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 21
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 22
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 23
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 24
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 25
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 26
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 27
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 28
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 29
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 30
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 31
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 32
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ host_hierarchy:
+ subhdr:
+ magic: 0x8D27
+ size: 68
+ host_hierarchy_entries:
+ - # 1
+ host_id: 0
+ supervisor_host_id: 0
+ - # 2
+ host_id: 0
+ supervisor_host_id: 0
+ - # 3
+ host_id: 0
+ supervisor_host_id: 0
+ - # 4
+ host_id: 0
+ supervisor_host_id: 0
+ - # 5
+ host_id: 0
+ supervisor_host_id: 0
+ - # 6
+ host_id: 0
+ supervisor_host_id: 0
+ - # 7
+ host_id: 0
+ supervisor_host_id: 0
+ - # 8
+ host_id: 0
+ supervisor_host_id: 0
+ - # 9
+ host_id: 0
+ supervisor_host_id: 0
+ - # 10
+ host_id: 0
+ supervisor_host_id: 0
+ - # 11
+ host_id: 0
+ supervisor_host_id: 0
+ - # 12
+ host_id: 0
+ supervisor_host_id: 0
+ - # 13
+ host_id: 0
+ supervisor_host_id: 0
+ - # 14
+ host_id: 0
+ supervisor_host_id: 0
+ - # 15
+ host_id: 0
+ supervisor_host_id: 0
+ - # 16
+ host_id: 0
+ supervisor_host_id: 0
+ - # 17
+ host_id: 0
+ supervisor_host_id: 0
+ - # 18
+ host_id: 0
+ supervisor_host_id: 0
+ - # 19
+ host_id: 0
+ supervisor_host_id: 0
+ - # 20
+ host_id: 0
+ supervisor_host_id: 0
+ - # 21
+ host_id: 0
+ supervisor_host_id: 0
+ - # 22
+ host_id: 0
+ supervisor_host_id: 0
+ - # 23
+ host_id: 0
+ supervisor_host_id: 0
+ - # 24
+ host_id: 0
+ supervisor_host_id: 0
+ - # 25
+ host_id: 0
+ supervisor_host_id: 0
+ - # 26
+ host_id: 0
+ supervisor_host_id: 0
+ - # 27
+ host_id: 0
+ supervisor_host_id: 0
+ - # 28
+ host_id: 0
+ supervisor_host_id: 0
+ - # 29
+ host_id: 0
+ supervisor_host_id: 0
+ - # 30
+ host_id: 0
+ supervisor_host_id: 0
+ - # 31
+ host_id: 0
+ supervisor_host_id: 0
+ - # 32
+ host_id: 0
+ supervisor_host_id: 0
+ otp_config:
+ subhdr:
+ magic: 0x4081
+ size: 69
+ otp_entry:
+ - # 1
+ host_id: 0
+ host_perms: 0
+ - # 2
+ host_id: 0
+ host_perms: 0
+ - # 3
+ host_id: 0
+ host_perms: 0
+ - # 4
+ host_id: 0
+ host_perms: 0
+ - # 5
+ host_id: 0
+ host_perms: 0
+ - # 6
+ host_id: 0
+ host_perms: 0
+ - # 7
+ host_id: 0
+ host_perms: 0
+ - # 8
+ host_id: 0
+ host_perms: 0
+ - # 9
+ host_id: 0
+ host_perms: 0
+ - # 10
+ host_id: 0
+ host_perms: 0
+ - # 11
+ host_id: 0
+ host_perms: 0
+ - # 12
+ host_id: 0
+ host_perms: 0
+ - # 13
+ host_id: 0
+ host_perms: 0
+ - # 14
+ host_id: 0
+ host_perms: 0
+ - # 15
+ host_id: 0
+ host_perms: 0
+ - # 16
+ host_id: 0
+ host_perms: 0
+ - # 17
+ host_id: 0
+ host_perms: 0
+ - # 18
+ host_id: 0
+ host_perms: 0
+ - # 19
+ host_id: 0
+ host_perms: 0
+ - # 20
+ host_id: 0
+ host_perms: 0
+ - # 21
+ host_id: 0
+ host_perms: 0
+ - # 22
+ host_id: 0
+ host_perms: 0
+ - # 23
+ host_id: 0
+ host_perms: 0
+ - # 24
+ host_id: 0
+ host_perms: 0
+ - # 25
+ host_id: 0
+ host_perms: 0
+ - # 26
+ host_id: 0
+ host_perms: 0
+ - # 27
+ host_id: 0
+ host_perms: 0
+ - # 28
+ host_id: 0
+ host_perms: 0
+ - # 29
+ host_id: 0
+ host_perms: 0
+ - # 30
+ host_id: 0
+ host_perms: 0
+ - # 31
+ host_id: 0
+ host_perms: 0
+ - # 32
+ host_id: 0
+ host_perms: 0
+ write_host_id: 0
+ dkek_config:
+ subhdr:
+ magic: 0x5170
+ size: 12
+ allowed_hosts: [128, 0, 0, 0]
+ allow_dkek_export_tisci: 0x5A
+ rsvd: [0, 0, 0]
+ sa2ul_cfg:
+ subhdr:
+ magic: 0x0
+ size: 0
+ auth_resource_owner: 0
+ enable_saul_psil_global_config_writes: 0x0
+ rsvd: [0, 0]
+ sec_dbg_config:
+ subhdr:
+ magic: 0x42AF
+ size: 16
+ allow_jtag_unlock: 0x5A
+ allow_wildcard_unlock: 0x5A
+ allowed_debug_level_rsvd: 0
+ rsvd: 0
+ min_cert_rev: 0x0
+ jtag_unlock_hosts: [0, 0, 0, 0]
+ sec_handover_cfg:
+ subhdr:
+ magic: 0x0
+ size: 10
+ handover_msg_sender: 0
+ handover_to_host_id: 0
+ rsvd: [0, 0, 0, 0]
--
2.39.5
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 11/31] k3: ringacc: pass ringrt address in struct k3_ringacc_init_data
2025-05-28 11:45 [PATCH 00/31] ARM: K3: add support for AM62L Sascha Hauer
` (9 preceding siblings ...)
2025-05-28 11:45 ` [PATCH 10/31] ARM: k3: add yaml files for AM62l Sascha Hauer
@ 2025-05-28 11:45 ` Sascha Hauer
2025-05-28 11:45 ` [PATCH 12/31] drivers: soc: ti: k3-ringacc: handle absence of tisci Sascha Hauer
` (19 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Sascha Hauer @ 2025-05-28 11:45 UTC (permalink / raw)
To: BAREBOX
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/soc/ti/k3-navss-ringacc.c | 9 ++++++---
include/soc/ti/k3-navss-ringacc.h | 1 +
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/ti/k3-navss-ringacc.c b/drivers/soc/ti/k3-navss-ringacc.c
index 2d61f63761fadf9c15419adb914a1307cdfe0904..4835aef2f3d2425bf45610cc9e5b9273bde30eb3 100644
--- a/drivers/soc/ti/k3-navss-ringacc.c
+++ b/drivers/soc/ti/k3-navss-ringacc.c
@@ -1405,9 +1405,12 @@ struct k3_ringacc *k3_ringacc_dmarings_init(struct device *dev,
mutex_init(&ringacc->req_lock);
- base_rt = dev_request_mem_region_by_name(dev, "ringrt");
- if (IS_ERR(base_rt))
- return ERR_CAST(base_rt);
+ base_rt = data->base_rt;
+ if (!base_rt) {
+ base_rt = dev_request_mem_region_by_name(dev, "ringrt");
+ if (IS_ERR(base_rt))
+ return ERR_CAST(base_rt);
+ }
ringacc->rings = devm_kzalloc(dev,
sizeof(*ringacc->rings) *
diff --git a/include/soc/ti/k3-navss-ringacc.h b/include/soc/ti/k3-navss-ringacc.h
index d9f2bd779595728f5103acf44c6f4ee58d90d408..80b14b98622480d5c6927afc6e5b5407eae5c7f5 100644
--- a/include/soc/ti/k3-navss-ringacc.h
+++ b/include/soc/ti/k3-navss-ringacc.h
@@ -262,6 +262,7 @@ struct k3_ringacc_init_data {
const struct ti_sci_handle *tisci;
u32 tisci_dev_id;
u32 num_rings;
+ void __iomem *base_rt;
};
struct k3_ringacc *k3_ringacc_dmarings_init(struct device *dev,
--
2.39.5
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 12/31] drivers: soc: ti: k3-ringacc: handle absence of tisci
2025-05-28 11:45 [PATCH 00/31] ARM: K3: add support for AM62L Sascha Hauer
` (10 preceding siblings ...)
2025-05-28 11:45 ` [PATCH 11/31] k3: ringacc: pass ringrt address in struct k3_ringacc_init_data Sascha Hauer
@ 2025-05-28 11:45 ` Sascha Hauer
2025-05-28 11:45 ` [PATCH 13/31] drivers: soc: ti: k3-ringacc: fix k3_ringacc_ring_reset_sci Sascha Hauer
` (18 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Sascha Hauer @ 2025-05-28 11:45 UTC (permalink / raw)
To: BAREBOX
Based on Linux downstream commit:
| commit a621a1075550f0e857adbadb4142fc1b3142136d
| Author: Sai Sree Kartheek Adivi <s-adivi@ti.com>
| Date: Thu Feb 20 21:56:48 2025 +0530
|
| PENDING: drivers: soc: ti: k3-ringacc: handle absence of tisci
|
| Handle absence of tisci with direct register writes. This will support
| platforms that do not have tisci firmware like AM62L.
|
| Signed-off-by: Sai Sree Kartheek Adivi <s-adivi@ti.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/soc/ti/k3-navss-ringacc.c | 127 ++++++++++++++++++++++++++++++++++----
include/soc/ti/k3-navss-ringacc.h | 3 +
2 files changed, 117 insertions(+), 13 deletions(-)
diff --git a/drivers/soc/ti/k3-navss-ringacc.c b/drivers/soc/ti/k3-navss-ringacc.c
index 4835aef2f3d2425bf45610cc9e5b9273bde30eb3..dfc397a1f5aca08a90ed773540bdeae9f50b8173 100644
--- a/drivers/soc/ti/k3-navss-ringacc.c
+++ b/drivers/soc/ti/k3-navss-ringacc.c
@@ -40,6 +40,38 @@ struct k3_ring_rt_regs {
u32 hwindx;
};
+#define K3_RINGACC_RT_CFG_REGS_OFS 0x40
+#define K3_DMARING_CFG_ADDR_HI_MASK GENMASK(3, 0)
+#define K3_DMARING_CFG_ASEL_SHIFT 16
+#define K3_DMARING_CFG_SIZE_MASK GENMASK(15, 0)
+
+/**
+ * struct k3_ring_cfg_regs - The RA Configuration Registers region
+ *
+ * @ba_lo: Ring Base Address Low Register
+ * @ba_hi: Ring Base Address High Register
+ * @size: Ring Size Register
+ */
+struct k3_ring_cfg_regs {
+ u32 ba_lo;
+ u32 ba_hi;
+ u32 size;
+};
+
+#define K3_RINGACC_RT_INT_REGS_OFS 0x140
+#define K3_RINGACC_RT_INT_ENABLE_SET_COMPLETE BIT(0)
+#define K3_RINGACC_RT_INT_ENABLE_SET_TR BIT(2)
+
+struct k3_ring_intr_regs {
+ u32 enable_set;
+ u32 resv_4;
+ u32 clr;
+ u32 resv_16;
+ u32 status_set;
+ u32 resv_8;
+ u32 status;
+};
+
#define K3_RINGACC_RT_REGS_STEP 0x1000
#define K3_DMARING_RT_REGS_STEP 0x2000
#define K3_DMARING_RT_REGS_REVERSE_OFS 0x1000
@@ -152,6 +184,8 @@ struct k3_ring_state {
*/
struct k3_ring {
struct k3_ring_rt_regs __iomem *rt;
+ struct k3_ring_cfg_regs __iomem *cfg;
+ struct k3_ring_intr_regs __iomem *intr;
struct k3_ring_fifo_regs __iomem *fifos;
struct k3_ringacc_proxy_target_regs __iomem *proxy;
dma_addr_t ring_mem_dma;
@@ -439,6 +473,10 @@ static void k3_ringacc_ring_reset_sci(struct k3_ring *ring)
struct k3_ringacc *ringacc = ring->parent;
int ret;
+ /* TODO: Implement ring reset without tisci */
+ if (!ringacc->tisci)
+ return;
+
ring_cfg.nav_id = ringacc->tisci_dev_id;
ring_cfg.index = ring->ring_id;
ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID;
@@ -467,16 +505,30 @@ static void k3_ringacc_ring_reconfig_qmode_sci(struct k3_ring *ring,
struct ti_sci_msg_rm_ring_cfg ring_cfg = { 0 };
struct k3_ringacc *ringacc = ring->parent;
int ret;
+ u32 reg;
ring_cfg.nav_id = ringacc->tisci_dev_id;
ring_cfg.index = ring->ring_id;
ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_RING_MODE_VALID;
ring_cfg.mode = mode;
- ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
- if (ret)
- dev_err(ringacc->dev, "TISCI reconf qmode fail (%d) ring_idx %d\n",
- ret, ring->ring_id);
+ if (!ringacc->tisci) {
+ writel(ring_cfg.addr_lo, &ring->cfg->ba_lo);
+ writel((ring_cfg.addr_hi & K3_DMARING_CFG_ADDR_HI_MASK) +
+ (ring_cfg.asel << K3_DMARING_CFG_ASEL_SHIFT),
+ &ring->cfg->ba_hi);
+
+ reg = readl(&ring->cfg->size);
+ reg &= ~K3_DMARING_CFG_SIZE_MASK;
+ reg |= ring_cfg.count & K3_DMARING_CFG_SIZE_MASK;
+
+ writel(reg, &ring->cfg->size);
+ } else {
+ ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
+ if (ret)
+ dev_err(ringacc->dev, "TISCI reconf qmode fail (%d) ring_idx %d\n",
+ ret, ring->ring_id);
+ }
}
void k3_ringacc_ring_reset_dma(struct k3_ring *ring, u32 occ)
@@ -543,15 +595,29 @@ static void k3_ringacc_ring_free_sci(struct k3_ring *ring)
struct ti_sci_msg_rm_ring_cfg ring_cfg = { 0 };
struct k3_ringacc *ringacc = ring->parent;
int ret;
+ u32 reg;
ring_cfg.nav_id = ringacc->tisci_dev_id;
ring_cfg.index = ring->ring_id;
ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER;
- ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
- if (ret)
- dev_err(ringacc->dev, "TISCI ring free fail (%d) ring_idx %d\n",
- ret, ring->ring_id);
+ if (!ringacc->tisci) {
+ writel(ring_cfg.addr_lo, &ring->cfg->ba_lo);
+ writel((ring_cfg.addr_hi & K3_DMARING_CFG_ADDR_HI_MASK) +
+ (ring_cfg.asel << K3_DMARING_CFG_ASEL_SHIFT),
+ &ring->cfg->ba_hi);
+
+ reg = readl(&ring->cfg->size);
+ reg &= ~K3_DMARING_CFG_SIZE_MASK;
+ reg |= ring_cfg.count & K3_DMARING_CFG_SIZE_MASK;
+
+ writel(reg, &ring->cfg->size);
+ } else {
+ ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
+ if (ret)
+ dev_err(ringacc->dev, "TISCI ring free fail (%d) ring_idx %d\n",
+ ret, ring->ring_id);
+ }
}
int k3_ringacc_ring_free(struct k3_ring *ring)
@@ -626,15 +692,31 @@ u32 k3_ringacc_get_tisci_dev_id(struct k3_ring *ring)
}
EXPORT_SYMBOL_GPL(k3_ringacc_get_tisci_dev_id);
+u32 k3_ringacc_ring_get_irq_status(struct k3_ring *ring)
+{
+ struct k3_ringacc *ringacc = ring->parent;
+ struct k3_ring *ring2 = &ringacc->rings[ring->ring_id];
+
+ return readl(&ring2->intr->status);
+}
+EXPORT_SYMBOL_GPL(k3_ringacc_ring_get_irq_status);
+
+void k3_ringacc_ring_clear_irq(struct k3_ring *ring)
+{
+ struct k3_ringacc *ringacc = ring->parent;
+ struct k3_ring *ring2 = &ringacc->rings[ring->ring_id];
+
+ writel(0xFF, &ring2->intr->status);
+}
+EXPORT_SYMBOL_GPL(k3_ringacc_ring_clear_irq);
+
static int k3_ringacc_ring_cfg_sci(struct k3_ring *ring)
{
struct ti_sci_msg_rm_ring_cfg ring_cfg = { 0 };
struct k3_ringacc *ringacc = ring->parent;
+ u32 reg;
int ret;
- if (!ringacc->tisci)
- return -EINVAL;
-
ring_cfg.nav_id = ringacc->tisci_dev_id;
ring_cfg.index = ring->ring_id;
ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER;
@@ -645,11 +727,26 @@ static int k3_ringacc_ring_cfg_sci(struct k3_ring *ring)
ring_cfg.size = ring->elm_size;
ring_cfg.asel = ring->asel;
+ if (!ringacc->tisci) {
+ writel(ring_cfg.addr_lo, &ring->cfg->ba_lo);
+ writel((ring_cfg.addr_hi & K3_DMARING_CFG_ADDR_HI_MASK) +
+ (ring_cfg.asel << K3_DMARING_CFG_ASEL_SHIFT),
+ &ring->cfg->ba_hi);
+
+ reg = readl(&ring->cfg->size);
+ reg &= ~K3_DMARING_CFG_SIZE_MASK;
+ reg |= ring_cfg.count & K3_DMARING_CFG_SIZE_MASK;
+
+ writel(reg, &ring->cfg->size);
+ writel(K3_RINGACC_RT_INT_ENABLE_SET_COMPLETE | K3_RINGACC_RT_INT_ENABLE_SET_TR,
+ &ring->intr->enable_set);
+ return 0;
+ }
+
ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
if (ret)
dev_err(ringacc->dev, "TISCI config ring fail (%d) ring_idx %d\n",
- ret, ring->ring_id);
-
+ ret, ring->ring_id);
return ret;
}
@@ -1426,6 +1523,10 @@ struct k3_ringacc *k3_ringacc_dmarings_init(struct device *dev,
struct k3_ring *ring = &ringacc->rings[i];
ring->rt = base_rt + K3_DMARING_RT_REGS_STEP * i;
+ ring->cfg = base_rt + K3_RINGACC_RT_CFG_REGS_OFS +
+ K3_DMARING_RT_REGS_STEP * i;
+ ring->intr = base_rt + K3_RINGACC_RT_INT_REGS_OFS +
+ K3_DMARING_RT_REGS_STEP * i;
ring->parent = ringacc;
ring->ring_id = i;
ring->proxy_id = K3_RINGACC_PROXY_NOT_USED;
diff --git a/include/soc/ti/k3-navss-ringacc.h b/include/soc/ti/k3-navss-ringacc.h
index 80b14b98622480d5c6927afc6e5b5407eae5c7f5..96a89113c100b409aef77bc0ee55c07597196223 100644
--- a/include/soc/ti/k3-navss-ringacc.h
+++ b/include/soc/ti/k3-navss-ringacc.h
@@ -158,6 +158,9 @@ u32 k3_ringacc_get_ring_id(struct k3_ring *ring);
*/
int k3_ringacc_get_ring_irq_num(struct k3_ring *ring);
+u32 k3_ringacc_ring_get_irq_status(struct k3_ring *ring);
+void k3_ringacc_ring_clear_irq(struct k3_ring *ring);
+
/**
* k3_ringacc_ring_cfg - ring configure
* @ring: pointer on ring
--
2.39.5
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 13/31] drivers: soc: ti: k3-ringacc: fix k3_ringacc_ring_reset_sci
2025-05-28 11:45 [PATCH 00/31] ARM: K3: add support for AM62L Sascha Hauer
` (11 preceding siblings ...)
2025-05-28 11:45 ` [PATCH 12/31] drivers: soc: ti: k3-ringacc: handle absence of tisci Sascha Hauer
@ 2025-05-28 11:45 ` Sascha Hauer
2025-05-28 11:45 ` [PATCH 14/31] dma: ti: k3-psil: Add PSIL data for AM62L Sascha Hauer
` (17 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Sascha Hauer @ 2025-05-28 11:45 UTC (permalink / raw)
To: BAREBOX
Based on Linux downstream commit:
| commit 5591c7f9a0fedc8dde70e6f2143165e296084249
| Author: Sai Sree Kartheek Adivi <s-adivi@ti.com>
| Date: Fri Mar 7 03:26:59 2025 +0530
|
| PENDING: drivers: soc: ti: k3-ringacc: fix k3_ringacc_ring_reset_sci
|
| Add non-tisci implementation for k3_ringacc_ring_reset_sci using direct
| register writes.
|
| Fixes: a621a1075550f ("PENDING: drivers: soc: ti: k3-ringacc: handle absence of tisci")
| Signed-off-by: Sai Sree Kartheek Adivi <s-adivi@ti.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/soc/ti/k3-navss-ringacc.c | 31 ++++++++++++++++++++-----------
1 file changed, 20 insertions(+), 11 deletions(-)
diff --git a/drivers/soc/ti/k3-navss-ringacc.c b/drivers/soc/ti/k3-navss-ringacc.c
index dfc397a1f5aca08a90ed773540bdeae9f50b8173..18fb9153caa467b3159e035448e16da65563b36e 100644
--- a/drivers/soc/ti/k3-navss-ringacc.c
+++ b/drivers/soc/ti/k3-navss-ringacc.c
@@ -472,20 +472,29 @@ static void k3_ringacc_ring_reset_sci(struct k3_ring *ring)
struct ti_sci_msg_rm_ring_cfg ring_cfg = { 0 };
struct k3_ringacc *ringacc = ring->parent;
int ret;
+ u32 reg;
- /* TODO: Implement ring reset without tisci */
- if (!ringacc->tisci)
- return;
+ if (!ringacc->tisci) {
+ if (ring->cfg == NULL)
+ return;
+ reg = readl(&ring->cfg->size);
+ reg &= ~K3_DMARING_CFG_SIZE_MASK;
- ring_cfg.nav_id = ringacc->tisci_dev_id;
- ring_cfg.index = ring->ring_id;
- ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID;
- ring_cfg.count = ring->size;
+ writel(reg, &ring->cfg->size);
+ reg |= ring->size;
- ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
- if (ret)
- dev_err(ringacc->dev, "TISCI reset ring fail (%d) ring_idx %d\n",
- ret, ring->ring_id);
+ writel(reg, &ring->cfg->size);
+ } else {
+ ring_cfg.nav_id = ringacc->tisci_dev_id;
+ ring_cfg.index = ring->ring_id;
+ ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID;
+ ring_cfg.count = ring->size;
+
+ ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
+ if (ret)
+ dev_err(ringacc->dev, "TISCI reset ring fail (%d) ring_idx %d\n",
+ ret, ring->ring_id);
+ }
}
void k3_ringacc_ring_reset(struct k3_ring *ring)
--
2.39.5
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 14/31] dma: ti: k3-psil: Add PSIL data for AM62L
2025-05-28 11:45 [PATCH 00/31] ARM: K3: add support for AM62L Sascha Hauer
` (12 preceding siblings ...)
2025-05-28 11:45 ` [PATCH 13/31] drivers: soc: ti: k3-ringacc: fix k3_ringacc_ring_reset_sci Sascha Hauer
@ 2025-05-28 11:45 ` Sascha Hauer
2025-05-28 11:45 ` [PATCH 15/31] dma: ti: k3-udma: Refactor common bits for AM62L support Sascha Hauer
` (16 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Sascha Hauer @ 2025-05-28 11:45 UTC (permalink / raw)
To: BAREBOX
This introduces PSIL data specific to AM62L SoC. Based on U-Boot
downstream commit:
| commit 3e91f4443a2b01e1a313ee3ecfe2a082c88402af
| Author: Vignesh Raghavendra <vigneshr@ti.com>
| Date: Wed Feb 26 19:55:43 2025 +0530
|
| PENDING: dma: ti: k3-psil: Add PSIL data for AM62L
|
| This introduces PSIL data specific to AM62L SoC
|
| Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/dma/ti/Makefile | 2 +-
drivers/dma/ti/k3-psil-am62l.c | 50 ++++++++++++++++++++++++++++++++++++++++++
drivers/dma/ti/k3-psil-priv.h | 1 +
drivers/dma/ti/k3-psil.c | 2 ++
4 files changed, 54 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile
index f449429e2a23633a7dadbda1470104d52d49e5e8..b7dfff07210537660965d235c10ea7345c22b0a6 100644
--- a/drivers/dma/ti/Makefile
+++ b/drivers/dma/ti/Makefile
@@ -1 +1 @@
-obj-$(CONFIG_TI_K3_UDMA) += k3-udma.o k3-psil.o
+obj-$(CONFIG_TI_K3_UDMA) += k3-udma.o k3-psil.o k3-psil-am62l.o
diff --git a/drivers/dma/ti/k3-psil-am62l.c b/drivers/dma/ti/k3-psil-am62l.c
new file mode 100644
index 0000000000000000000000000000000000000000..972895ec56fb4278e958ffa7ec88819e8fbf23ee
--- /dev/null
+++ b/drivers/dma/ti/k3-psil-am62l.c
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com
+ */
+
+#include <linux/kernel.h>
+
+#include "k3-psil-priv.h"
+
+#define PSIL_ETHERNET(x, ch, flow_base, flow_cnt) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_NATIVE, \
+ .pkt_mode = 1, \
+ .needs_epib = 1, \
+ .psd_size = 16, \
+ .mapped_channel_id = ch, \
+ .flow_start = flow_base, \
+ .flow_num = flow_cnt, \
+ .default_flow_id = flow_base, \
+ }, \
+ }
+
+/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
+static struct psil_ep am62l_src_ep_map[] = {
+ /* CPSW3G */
+ PSIL_ETHERNET(0x4600, 96, 96, 16),
+};
+
+/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
+static struct psil_ep am62l_dst_ep_map[] = {
+ /* CPSW3G */
+ PSIL_ETHERNET(0xc600, 64, 64, 2),
+ PSIL_ETHERNET(0xc601, 66, 66, 2),
+ PSIL_ETHERNET(0xc602, 68, 68, 2),
+ PSIL_ETHERNET(0xc603, 70, 70, 2),
+ PSIL_ETHERNET(0xc604, 72, 72, 2),
+ PSIL_ETHERNET(0xc605, 74, 74, 2),
+ PSIL_ETHERNET(0xc606, 76, 76, 2),
+ PSIL_ETHERNET(0xc607, 78, 78, 2),
+};
+
+struct psil_ep_map am62l_ep_map = {
+ .name = "am62l",
+ .src = am62l_src_ep_map,
+ .src_count = ARRAY_SIZE(am62l_src_ep_map),
+ .dst = am62l_dst_ep_map,
+ .dst_count = ARRAY_SIZE(am62l_dst_ep_map),
+};
diff --git a/drivers/dma/ti/k3-psil-priv.h b/drivers/dma/ti/k3-psil-priv.h
index b80916a7ff8fa728ca41f1dbabc1817bde69cf6e..d00ef99867a4f146621550c9eb308958ca8d182c 100644
--- a/drivers/dma/ti/k3-psil-priv.h
+++ b/drivers/dma/ti/k3-psil-priv.h
@@ -45,5 +45,6 @@ extern struct psil_ep_map am62_ep_map;
extern struct psil_ep_map am62a_ep_map;
extern struct psil_ep_map j784s4_ep_map;
extern struct psil_ep_map am62p_ep_map;
+extern struct psil_ep_map am62l_ep_map;
#endif /* K3_PSIL_PRIV_H_ */
diff --git a/drivers/dma/ti/k3-psil.c b/drivers/dma/ti/k3-psil.c
index 58f39c0453e9724ad28680fa375a031529687ed8..f517da7afcac17d502af3002494c2cd7cbf7322b 100644
--- a/drivers/dma/ti/k3-psil.c
+++ b/drivers/dma/ti/k3-psil.c
@@ -62,6 +62,8 @@ struct psil_endpoint_config *psil_get_ep_config(u32 thread_id)
if (!soc_ep_map) {
if (of_machine_is_compatible("ti,am625"))
soc_ep_map = &am62_ep_map;
+ else if (of_machine_is_compatible("ti,am62l3"))
+ soc_ep_map = &am62l_ep_map;
}
if (!soc_ep_map) {
--
2.39.5
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 15/31] dma: ti: k3-udma: Refactor common bits for AM62L support
2025-05-28 11:45 [PATCH 00/31] ARM: K3: add support for AM62L Sascha Hauer
` (13 preceding siblings ...)
2025-05-28 11:45 ` [PATCH 14/31] dma: ti: k3-psil: Add PSIL data for AM62L Sascha Hauer
@ 2025-05-28 11:45 ` Sascha Hauer
2025-05-28 11:45 ` [PATCH 16/31] dma: ti: k3-udma-common: Update common code for AM62L DMAs Sascha Hauer
` (15 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Sascha Hauer @ 2025-05-28 11:45 UTC (permalink / raw)
To: BAREBOX
Based on U-Boot downstream commit:
| commit c0b542d473986fbc9daef66d8a232b74bba89a30
| Author: Vignesh Raghavendra <vigneshr@ti.com>
| Date: Wed Feb 26 19:55:44 2025 +0530
|
| PENDING: dma: ti: k3-udma: Refactor common bits for AM62L support
|
| In anticipation of adding BCDMA_V2 and PKTDMA_V2 for upcoming AM62L
| SoCs, move the common bits in to k3-udma-common.c.
|
| No functional change intended.
|
| Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/dma/ti/Makefile | 2 +-
drivers/dma/ti/k3-udma-common.c | 1154 +++++++++++++++++++++++++++++++
drivers/dma/ti/k3-udma.c | 1434 +--------------------------------------
drivers/dma/ti/k3-udma.h | 355 ++++++++++
4 files changed, 1537 insertions(+), 1408 deletions(-)
diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile
index b7dfff07210537660965d235c10ea7345c22b0a6..f841ad0cffaf086ffbf3b5775bfad776fa5c3d73 100644
--- a/drivers/dma/ti/Makefile
+++ b/drivers/dma/ti/Makefile
@@ -1 +1 @@
-obj-$(CONFIG_TI_K3_UDMA) += k3-udma.o k3-psil.o k3-psil-am62l.o
+obj-$(CONFIG_TI_K3_UDMA) += k3-udma.o k3-udma-common.o k3-psil.o k3-psil-am62l.o
diff --git a/drivers/dma/ti/k3-udma-common.c b/drivers/dma/ti/k3-udma-common.c
new file mode 100644
index 0000000000000000000000000000000000000000..d2ef9cc7b83d7fe4c2845b78b05c3a0e640cc589
--- /dev/null
+++ b/drivers/dma/ti/k3-udma-common.c
@@ -0,0 +1,1154 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
+ * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
+ */
+#define pr_fmt(fmt) "udma: " fmt
+
+#include <io.h>
+#include <malloc.h>
+#include <stdio.h>
+#include <linux/bitops.h>
+#include <linux/sizes.h>
+#include <linux/printk.h>
+#include <dma.h>
+#include <soc/ti/ti-udma.h>
+#include <soc/ti/ti_sci_protocol.h>
+#include <dma-devices.h>
+#include <soc/ti/cppi5.h>
+#include <soc/ti/k3-navss-ringacc.h>
+#include <clock.h>
+#include <linux/bitmap.h>
+#include <driver.h>
+#include <linux/device.h>
+
+#include "k3-udma-hwdef.h"
+#include "k3-udma.h"
+#include "k3-psil-priv.h"
+
+#define K3_ADDRESS_ASEL_SHIFT 48
+
+char *udma_get_dir_text(enum dma_transfer_direction dir)
+{
+ switch (dir) {
+ case DMA_DEV_TO_MEM:
+ return "DEV_TO_MEM";
+ case DMA_MEM_TO_DEV:
+ return "MEM_TO_DEV";
+ case DMA_MEM_TO_MEM:
+ return "MEM_TO_MEM";
+ case DMA_DEV_TO_DEV:
+ return "DEV_TO_DEV";
+ default:
+ break;
+ }
+
+ return "invalid";
+}
+
+void udma_reset_uchan(struct udma_chan *uc)
+{
+ memset(&uc->config, 0, sizeof(uc->config));
+ uc->config.remote_thread_id = -1;
+ uc->config.mapped_channel_id = -1;
+ uc->config.default_flow_id = -1;
+}
+
+bool udma_is_chan_running(struct udma_chan *uc)
+{
+ u32 trt_ctl = 0;
+ u32 rrt_ctl = 0;
+
+ switch (uc->config.dir) {
+ case DMA_DEV_TO_MEM:
+ rrt_ctl = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_CTL_REG);
+ dev_dbg(uc->ud->dev, "rrt_ctl: 0x%08x (peer: 0x%08x)\n",
+ rrt_ctl,
+ udma_rchanrt_read(uc->rchan,
+ UDMA_RCHAN_RT_PEER_RT_EN_REG));
+ break;
+ case DMA_MEM_TO_DEV:
+ trt_ctl = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_CTL_REG);
+ dev_dbg(uc->ud->dev, "trt_ctl: 0x%08x (peer: 0x%08x)\n",
+ trt_ctl,
+ udma_tchanrt_read(uc->tchan,
+ UDMA_TCHAN_RT_PEER_RT_EN_REG));
+ break;
+ case DMA_MEM_TO_MEM:
+ trt_ctl = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_CTL_REG);
+ rrt_ctl = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_CTL_REG);
+ break;
+ default:
+ break;
+ }
+
+ if (trt_ctl & UDMA_CHAN_RT_CTL_EN || rrt_ctl & UDMA_CHAN_RT_CTL_EN)
+ return true;
+
+ return false;
+}
+
+static int udma_pop_from_ring(struct udma_chan *uc, dma_addr_t *addr)
+{
+ struct k3_ring *ring = NULL;
+ int ret = -ENOENT;
+
+ switch (uc->config.dir) {
+ case DMA_DEV_TO_MEM:
+ ring = uc->rflow->r_ring;
+ break;
+ case DMA_MEM_TO_DEV:
+ ring = uc->tchan->tc_ring;
+ break;
+ case DMA_MEM_TO_MEM:
+ ring = uc->tchan->tc_ring;
+ break;
+ default:
+ break;
+ }
+
+ if (ring && k3_ringacc_ring_get_occ(ring))
+ ret = k3_ringacc_ring_pop(ring, addr);
+
+ return ret;
+}
+
+void udma_reset_rings(struct udma_chan *uc)
+{
+ struct k3_ring *ring1 = NULL;
+ struct k3_ring *ring2 = NULL;
+
+ switch (uc->config.dir) {
+ case DMA_DEV_TO_MEM:
+ ring1 = uc->rflow->fd_ring;
+ ring2 = uc->rflow->r_ring;
+ break;
+ case DMA_MEM_TO_DEV:
+ ring1 = uc->tchan->t_ring;
+ ring2 = uc->tchan->tc_ring;
+ break;
+ case DMA_MEM_TO_MEM:
+ ring1 = uc->tchan->t_ring;
+ ring2 = uc->tchan->tc_ring;
+ break;
+ default:
+ break;
+ }
+
+ if (ring1)
+ k3_ringacc_ring_reset_dma(ring1, k3_ringacc_ring_get_occ(ring1));
+ if (ring2)
+ k3_ringacc_ring_reset(ring2);
+}
+
+void udma_reset_counters(struct udma_chan *uc)
+{
+ u32 val;
+
+ if (uc->tchan) {
+ val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_BCNT_REG);
+ udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_BCNT_REG, val);
+
+ val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_SBCNT_REG);
+ udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_SBCNT_REG, val);
+
+ val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PCNT_REG);
+ udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PCNT_REG, val);
+
+ if (!uc->bchan) {
+ val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PEER_BCNT_REG);
+ udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PEER_BCNT_REG, val);
+ }
+ }
+
+ if (uc->rchan) {
+ val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_BCNT_REG);
+ udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_BCNT_REG, val);
+
+ val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_SBCNT_REG);
+ udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_SBCNT_REG, val);
+
+ val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_PCNT_REG);
+ udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PCNT_REG, val);
+
+ val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_PEER_BCNT_REG);
+ udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_BCNT_REG, val);
+ }
+
+ uc->bcnt = 0;
+}
+
+int udma_stop_hard(struct udma_chan *uc)
+{
+ dev_dbg(uc->ud->dev, "%s: ENTER (chan%d)\n", __func__, uc->id);
+
+ switch (uc->config.dir) {
+ case DMA_DEV_TO_MEM:
+ udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG, 0);
+ udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG, 0);
+ break;
+ case DMA_MEM_TO_DEV:
+ udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG, 0);
+ udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PEER_RT_EN_REG, 0);
+ break;
+ case DMA_MEM_TO_MEM:
+ udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG, 0);
+ udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG, 0);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+int udma_start(struct udma_chan *uc)
+{
+ /* Channel is already running, no need to proceed further */
+ if (udma_is_chan_running(uc))
+ goto out;
+
+ dev_dbg(uc->ud->dev, "%s: chan:%d dir:%s\n",
+ __func__, uc->id, udma_get_dir_text(uc->config.dir));
+
+ /* Make sure that we clear the teardown bit, if it is set */
+ udma_stop_hard(uc);
+
+ /* Reset all counters */
+ udma_reset_counters(uc);
+
+ switch (uc->config.dir) {
+ case DMA_DEV_TO_MEM:
+ udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN);
+
+ /* Enable remote */
+ udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG,
+ UDMA_PEER_RT_EN_ENABLE);
+
+ dev_dbg(uc->ud->dev, "%s(rx): RT_CTL:0x%08x PEER RT_ENABLE:0x%08x\n",
+ __func__,
+ udma_rchanrt_read(uc->rchan,
+ UDMA_RCHAN_RT_CTL_REG),
+ udma_rchanrt_read(uc->rchan,
+ UDMA_RCHAN_RT_PEER_RT_EN_REG));
+ break;
+ case DMA_MEM_TO_DEV:
+ /* Enable remote */
+ udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PEER_RT_EN_REG,
+ UDMA_PEER_RT_EN_ENABLE);
+
+ udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN);
+
+ dev_dbg(uc->ud->dev, "%s(tx): RT_CTL:0x%08x PEER RT_ENABLE:0x%08x\n",
+ __func__,
+ udma_tchanrt_read(uc->tchan,
+ UDMA_TCHAN_RT_CTL_REG),
+ udma_tchanrt_read(uc->tchan,
+ UDMA_TCHAN_RT_PEER_RT_EN_REG));
+ break;
+ case DMA_MEM_TO_MEM:
+ udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN);
+ udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN);
+
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ dev_dbg(uc->ud->dev, "%s: DONE chan:%d\n", __func__, uc->id);
+out:
+ return 0;
+}
+
+void udma_stop_mem2dev(struct udma_chan *uc, bool sync)
+{
+ int i = 0;
+ u32 val;
+
+ udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN |
+ UDMA_CHAN_RT_CTL_TDOWN);
+
+ val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_CTL_REG);
+
+ while (sync && (val & UDMA_CHAN_RT_CTL_EN)) {
+ val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_CTL_REG);
+ udelay(1);
+ if (i > 1000) {
+ dev_dbg(uc->ud->dev, "%s TIMEOUT !\n", __func__);
+ break;
+ }
+ i++;
+ }
+
+ val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PEER_RT_EN_REG);
+ if (val & UDMA_PEER_RT_EN_ENABLE)
+ dev_dbg(uc->ud->dev, "%s: peer not stopped TIMEOUT !\n", __func__);
+}
+
+void udma_stop_dev2mem(struct udma_chan *uc, bool sync)
+{
+ int i = 0;
+ u32 val;
+
+ udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG,
+ UDMA_PEER_RT_EN_ENABLE |
+ UDMA_PEER_RT_EN_TEARDOWN);
+
+ val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_CTL_REG);
+
+ while (sync && (val & UDMA_CHAN_RT_CTL_EN)) {
+ val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_CTL_REG);
+ udelay(1);
+ if (i > 1000) {
+ dev_dbg(uc->ud->dev, "%s TIMEOUT !\n", __func__);
+ break;
+ }
+ i++;
+ }
+
+ val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG);
+ if (val & UDMA_PEER_RT_EN_ENABLE)
+ dev_dbg(uc->ud->dev, "%s: peer not stopped TIMEOUT !\n", __func__);
+}
+
+int udma_stop(struct udma_chan *uc)
+{
+ dev_dbg(uc->ud->dev, "%s: chan:%d dir:%s\n",
+ __func__, uc->id, udma_get_dir_text(uc->config.dir));
+
+ udma_reset_counters(uc);
+ switch (uc->config.dir) {
+ case DMA_DEV_TO_MEM:
+ udma_stop_dev2mem(uc, true);
+ break;
+ case DMA_MEM_TO_DEV:
+ udma_stop_mem2dev(uc, true);
+ break;
+ case DMA_MEM_TO_MEM:
+ udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG, 0);
+ udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG, 0);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int udma_poll_completion(struct udma_chan *uc, dma_addr_t *paddr)
+{
+ u64 start = get_time_ns();
+ int ret;
+
+ while (!is_timeout(start, SECOND)) {
+ ret = udma_pop_from_ring(uc, paddr);
+ if (!ret)
+ return 0;
+ }
+
+ return -ETIMEDOUT;
+}
+
+static struct udma_rflow *__udma_reserve_rflow(struct udma_dev *ud, int id)
+{
+ DECLARE_BITMAP(tmp, K3_UDMA_MAX_RFLOWS);
+
+ if (id >= 0) {
+ if (test_bit(id, ud->rflow_map)) {
+ dev_err(ud->dev, "rflow%d is in use\n", id);
+ return ERR_PTR(-ENOENT);
+ }
+ } else {
+ bitmap_or(tmp, ud->rflow_map, ud->rflow_map_reserved,
+ ud->rflow_cnt);
+
+ id = find_next_zero_bit(tmp, ud->rflow_cnt, ud->rchan_cnt);
+ if (id >= ud->rflow_cnt)
+ return ERR_PTR(-ENOENT);
+ }
+
+ __set_bit(id, ud->rflow_map);
+ return &ud->rflows[id];
+}
+
+#define UDMA_RESERVE_RESOURCE(res) \
+static struct udma_##res *__udma_reserve_##res(struct udma_dev *ud, \
+ int id) \
+{ \
+ if (id >= 0) { \
+ if (test_bit(id, ud->res##_map)) { \
+ dev_err(ud->dev, "res##%d is in use\n", id); \
+ return ERR_PTR(-ENOENT); \
+ } \
+ } else { \
+ id = find_first_zero_bit(ud->res##_map, ud->res##_cnt); \
+ if (id == ud->res##_cnt) { \
+ return ERR_PTR(-ENOENT); \
+ } \
+ } \
+ \
+ __set_bit(id, ud->res##_map); \
+ return &ud->res##s[id]; \
+}
+
+UDMA_RESERVE_RESOURCE(tchan);
+UDMA_RESERVE_RESOURCE(rchan);
+
+static int udma_get_tchan(struct udma_chan *uc)
+{
+ struct udma_dev *ud = uc->ud;
+
+ if (uc->tchan) {
+ dev_dbg(ud->dev, "chan%d: already have tchan%d allocated\n",
+ uc->id, uc->tchan->id);
+ return 0;
+ }
+
+ uc->tchan = __udma_reserve_tchan(ud, uc->config.mapped_channel_id);
+ if (IS_ERR(uc->tchan))
+ return PTR_ERR(uc->tchan);
+
+ if (ud->tflow_cnt) {
+ int tflow_id;
+
+ /* Only PKTDMA have support for tx flows */
+ if (uc->config.default_flow_id >= 0)
+ tflow_id = uc->config.default_flow_id;
+ else
+ tflow_id = uc->tchan->id;
+
+ if (test_bit(tflow_id, ud->tflow_map)) {
+ dev_err(ud->dev, "tflow%d is in use\n", tflow_id);
+ __clear_bit(uc->tchan->id, ud->tchan_map);
+ uc->tchan = NULL;
+ return -ENOENT;
+ }
+
+ uc->tchan->tflow_id = tflow_id;
+ __set_bit(tflow_id, ud->tflow_map);
+ } else {
+ uc->tchan->tflow_id = -1;
+ }
+
+ dev_dbg(ud->dev, "chan%d: got tchan%d\n", uc->id, uc->tchan->id);
+
+ return 0;
+}
+
+static int udma_get_rchan(struct udma_chan *uc)
+{
+ struct udma_dev *ud = uc->ud;
+
+ if (uc->rchan) {
+ dev_dbg(ud->dev, "chan%d: already have rchan%d allocated\n",
+ uc->id, uc->rchan->id);
+ return 0;
+ }
+
+ uc->rchan = __udma_reserve_rchan(ud, uc->config.mapped_channel_id);
+ if (IS_ERR(uc->rchan))
+ return PTR_ERR(uc->rchan);
+
+ dev_dbg(uc->ud->dev, "chan%d: got rchan%d\n", uc->id, uc->rchan->id);
+
+ return 0;
+}
+
+static int udma_get_rflow(struct udma_chan *uc, int flow_id)
+{
+ struct udma_dev *ud = uc->ud;
+
+ if (uc->rflow) {
+ dev_dbg(ud->dev, "chan%d: already have rflow%d allocated\n",
+ uc->id, uc->rflow->id);
+ return 0;
+ }
+
+ if (!uc->rchan)
+ dev_warn(ud->dev, "chan%d: does not have rchan??\n", uc->id);
+
+ uc->rflow = __udma_reserve_rflow(ud, flow_id);
+ if (IS_ERR(uc->rflow))
+ return PTR_ERR(uc->rflow);
+
+ pr_debug("chan%d: got rflow%d\n", uc->id, uc->rflow->id);
+ return 0;
+}
+
+static void udma_put_rchan(struct udma_chan *uc)
+{
+ struct udma_dev *ud = uc->ud;
+
+ if (uc->rchan) {
+ dev_dbg(ud->dev, "chan%d: put rchan%d\n", uc->id,
+ uc->rchan->id);
+ __clear_bit(uc->rchan->id, ud->rchan_map);
+ uc->rchan = NULL;
+ }
+}
+
+static void udma_put_tchan(struct udma_chan *uc)
+{
+ struct udma_dev *ud = uc->ud;
+
+ if (uc->tchan) {
+ dev_dbg(ud->dev, "chan%d: put tchan%d\n", uc->id,
+ uc->tchan->id);
+ __clear_bit(uc->tchan->id, ud->tchan_map);
+ if (uc->tchan->tflow_id >= 0)
+ __clear_bit(uc->tchan->tflow_id, ud->tflow_map);
+ uc->tchan = NULL;
+ }
+}
+
+static void udma_put_rflow(struct udma_chan *uc)
+{
+ struct udma_dev *ud = uc->ud;
+
+ if (uc->rflow) {
+ dev_dbg(ud->dev, "chan%d: put rflow%d\n", uc->id,
+ uc->rflow->id);
+ __clear_bit(uc->rflow->id, ud->rflow_map);
+ uc->rflow = NULL;
+ }
+}
+
+void udma_free_tx_resources(struct udma_chan *uc)
+{
+ if (!uc->tchan)
+ return;
+
+ k3_ringacc_ring_free(uc->tchan->t_ring);
+ k3_ringacc_ring_free(uc->tchan->tc_ring);
+ uc->tchan->t_ring = NULL;
+ uc->tchan->tc_ring = NULL;
+
+ udma_put_tchan(uc);
+}
+
+int udma_alloc_tx_resources(struct udma_chan *uc)
+{
+ struct k3_ring_cfg ring_cfg;
+ struct udma_dev *ud = uc->ud;
+ struct udma_tchan *tchan;
+ int ring_idx, ret;
+
+ ret = udma_get_tchan(uc);
+ if (ret)
+ return ret;
+
+ tchan = uc->tchan;
+ if (tchan->tflow_id > 0)
+ ring_idx = tchan->tflow_id;
+ else
+ ring_idx = tchan->id;
+
+ ret = k3_ringacc_request_rings_pair(ud->ringacc, ring_idx, -1,
+ &uc->tchan->t_ring,
+ &uc->tchan->tc_ring);
+ if (ret) {
+ ret = -EBUSY;
+ goto err_tx_ring;
+ }
+
+ memset(&ring_cfg, 0, sizeof(ring_cfg));
+ ring_cfg.size = 16;
+ ring_cfg.asel = uc->config.asel;
+ ring_cfg.elm_size = K3_RINGACC_RING_ELSIZE_8;
+ ring_cfg.mode = K3_RINGACC_RING_MODE_RING;
+
+ ret = k3_ringacc_ring_cfg(uc->tchan->t_ring, &ring_cfg);
+ ret |= k3_ringacc_ring_cfg(uc->tchan->tc_ring, &ring_cfg);
+
+ if (ret)
+ goto err_ringcfg;
+
+ return 0;
+
+err_ringcfg:
+ k3_ringacc_ring_free(uc->tchan->tc_ring);
+ uc->tchan->tc_ring = NULL;
+ k3_ringacc_ring_free(uc->tchan->t_ring);
+ uc->tchan->t_ring = NULL;
+err_tx_ring:
+ udma_put_tchan(uc);
+
+ return ret;
+}
+
+void udma_free_rx_resources(struct udma_chan *uc)
+{
+ if (!uc->rchan)
+ return;
+
+ if (uc->rflow) {
+ k3_ringacc_ring_free(uc->rflow->fd_ring);
+ k3_ringacc_ring_free(uc->rflow->r_ring);
+ uc->rflow->fd_ring = NULL;
+ uc->rflow->r_ring = NULL;
+
+ udma_put_rflow(uc);
+ }
+
+ udma_put_rchan(uc);
+}
+
+int udma_alloc_rx_resources(struct udma_chan *uc)
+{
+ struct k3_ring_cfg ring_cfg;
+ struct udma_dev *ud = uc->ud;
+ struct udma_rflow *rflow;
+ int fd_ring_id;
+ int ret;
+
+ ret = udma_get_rchan(uc);
+ if (ret)
+ return ret;
+
+ /* For MEM_TO_MEM we don't need rflow or rings */
+ if (uc->config.dir == DMA_MEM_TO_MEM)
+ return 0;
+
+ if (uc->config.default_flow_id >= 0)
+ ret = udma_get_rflow(uc, uc->config.default_flow_id);
+ else
+ ret = udma_get_rflow(uc, uc->rchan->id);
+
+ if (ret) {
+ ret = -EBUSY;
+ goto err_rflow;
+ }
+
+ rflow = uc->rflow;
+ if (ud->tflow_cnt) {
+ fd_ring_id = ud->tflow_cnt + rflow->id;
+ } else {
+ fd_ring_id = ud->bchan_cnt + ud->tchan_cnt + ud->echan_cnt +
+ uc->rchan->id;
+ }
+
+ ret = k3_ringacc_request_rings_pair(ud->ringacc, fd_ring_id, -1,
+ &rflow->fd_ring, &rflow->r_ring);
+ if (ret) {
+ ret = -EBUSY;
+ goto err_rx_ring;
+ }
+
+ memset(&ring_cfg, 0, sizeof(ring_cfg));
+ ring_cfg.size = 16;
+ ring_cfg.elm_size = K3_RINGACC_RING_ELSIZE_8;
+ ring_cfg.mode = K3_RINGACC_RING_MODE_RING;
+ ring_cfg.asel = uc->config.asel;
+
+ ret = k3_ringacc_ring_cfg(rflow->fd_ring, &ring_cfg);
+ ret |= k3_ringacc_ring_cfg(rflow->r_ring, &ring_cfg);
+ if (ret)
+ goto err_ringcfg;
+
+ return 0;
+
+err_ringcfg:
+ k3_ringacc_ring_free(rflow->r_ring);
+ rflow->r_ring = NULL;
+ k3_ringacc_ring_free(rflow->fd_ring);
+ rflow->fd_ring = NULL;
+err_rx_ring:
+ udma_put_rflow(uc);
+err_rflow:
+ udma_put_rchan(uc);
+
+ return ret;
+}
+
+static int udma_push_to_ring(struct k3_ring *ring, void *elem)
+{
+ u64 addr = 0;
+
+ memcpy(&addr, &elem, sizeof(elem));
+ return k3_ringacc_ring_push(ring, &addr);
+}
+
+static int *udma_prep_dma_memcpy(struct udma_chan *uc, dma_addr_t dest,
+ dma_addr_t src, size_t len)
+{
+ u32 tc_ring_id = k3_ringacc_get_ring_id(uc->tchan->tc_ring);
+ struct cppi5_tr_type15_t *tr_req;
+ int num_tr;
+ size_t tr_size = sizeof(struct cppi5_tr_type15_t);
+ u16 tr0_cnt0, tr0_cnt1, tr1_cnt0;
+ void *tr_desc;
+ size_t desc_size;
+ u64 asel = (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT;
+
+ if (len < SZ_64K) {
+ num_tr = 1;
+ tr0_cnt0 = len;
+ tr0_cnt1 = 1;
+ } else {
+ unsigned long align_to = __ffs(src | dest);
+
+ if (align_to > 3)
+ align_to = 3;
+ /*
+ * Keep simple: tr0: SZ_64K-alignment blocks,
+ * tr1: the remaining
+ */
+ num_tr = 2;
+ tr0_cnt0 = (SZ_64K - BIT(align_to));
+ if (len / tr0_cnt0 >= SZ_64K) {
+ dev_err(uc->ud->dev, "size %zu is not supported\n",
+ len);
+ return NULL;
+ }
+
+ tr0_cnt1 = len / tr0_cnt0;
+ tr1_cnt0 = len % tr0_cnt0;
+ }
+
+ desc_size = cppi5_trdesc_calc_size(num_tr, tr_size);
+ tr_desc = dma_alloc_coherent(DMA_DEVICE_BROKEN, desc_size, DMA_ADDRESS_BROKEN);
+ if (!tr_desc)
+ return NULL;
+
+ cppi5_trdesc_init(tr_desc, num_tr, tr_size, 0, 0);
+ cppi5_desc_set_pktids(tr_desc, uc->id, 0x3fff);
+ cppi5_desc_set_retpolicy(tr_desc, 0, tc_ring_id);
+
+ tr_req = tr_desc + tr_size;
+
+ cppi5_tr_init(&tr_req[0].flags, CPPI5_TR_TYPE15, false, true,
+ CPPI5_TR_EVENT_SIZE_COMPLETION, 1);
+ cppi5_tr_csf_set(&tr_req[0].flags, CPPI5_TR_CSF_SUPR_EVT);
+
+ src |= asel;
+ dest |= asel;
+
+ tr_req[0].addr = src;
+ tr_req[0].icnt0 = tr0_cnt0;
+ tr_req[0].icnt1 = tr0_cnt1;
+ tr_req[0].icnt2 = 1;
+ tr_req[0].icnt3 = 1;
+ tr_req[0].dim1 = tr0_cnt0;
+
+ tr_req[0].daddr = dest;
+ tr_req[0].dicnt0 = tr0_cnt0;
+ tr_req[0].dicnt1 = tr0_cnt1;
+ tr_req[0].dicnt2 = 1;
+ tr_req[0].dicnt3 = 1;
+ tr_req[0].ddim1 = tr0_cnt0;
+
+ if (num_tr == 2) {
+ cppi5_tr_init(&tr_req[1].flags, CPPI5_TR_TYPE15, false, true,
+ CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
+ cppi5_tr_csf_set(&tr_req[1].flags, CPPI5_TR_CSF_SUPR_EVT);
+
+ tr_req[1].addr = src + tr0_cnt1 * tr0_cnt0;
+ tr_req[1].icnt0 = tr1_cnt0;
+ tr_req[1].icnt1 = 1;
+ tr_req[1].icnt2 = 1;
+ tr_req[1].icnt3 = 1;
+
+ tr_req[1].daddr = dest + tr0_cnt1 * tr0_cnt0;
+ tr_req[1].dicnt0 = tr1_cnt0;
+ tr_req[1].dicnt1 = 1;
+ tr_req[1].dicnt2 = 1;
+ tr_req[1].dicnt3 = 1;
+ }
+
+ cppi5_tr_csf_set(&tr_req[num_tr - 1].flags, CPPI5_TR_CSF_EOP);
+
+ udma_push_to_ring(uc->tchan->t_ring, tr_desc);
+
+ return 0;
+}
+
+static struct udma_bchan *__bcdma_reserve_bchan(struct udma_dev *ud, int id)
+{
+ if (id >= 0) {
+ if (test_bit(id, ud->bchan_map)) {
+ dev_err(ud->dev, "bchan%d is in use\n", id);
+ return ERR_PTR(-ENOENT);
+ }
+ } else {
+ id = find_next_zero_bit(ud->bchan_map, ud->bchan_cnt, 0);
+ if (id == ud->bchan_cnt)
+ return ERR_PTR(-ENOENT);
+ }
+ __set_bit(id, ud->bchan_map);
+ return &ud->bchans[id];
+}
+
+static int bcdma_get_bchan(struct udma_chan *uc)
+{
+ struct udma_dev *ud = uc->ud;
+
+ if (uc->bchan) {
+ dev_err(ud->dev, "chan%d: already have bchan%d allocated\n",
+ uc->id, uc->bchan->id);
+ return 0;
+ }
+
+ uc->bchan = __bcdma_reserve_bchan(ud, -1);
+ if (IS_ERR(uc->bchan))
+ return PTR_ERR(uc->bchan);
+
+ uc->tchan = uc->bchan;
+
+ return 0;
+}
+
+static void bcdma_put_bchan(struct udma_chan *uc)
+{
+ struct udma_dev *ud = uc->ud;
+
+ if (uc->bchan) {
+ dev_dbg(ud->dev, "chan%d: put bchan%d\n", uc->id,
+ uc->bchan->id);
+ __clear_bit(uc->bchan->id, ud->bchan_map);
+ uc->bchan = NULL;
+ uc->tchan = NULL;
+ }
+}
+
+void bcdma_free_bchan_resources(struct udma_chan *uc)
+{
+ if (!uc->bchan)
+ return;
+
+ k3_ringacc_ring_free(uc->bchan->tc_ring);
+ k3_ringacc_ring_free(uc->bchan->t_ring);
+ uc->bchan->tc_ring = NULL;
+ uc->bchan->t_ring = NULL;
+
+ bcdma_put_bchan(uc);
+}
+
+int bcdma_alloc_bchan_resources(struct udma_chan *uc)
+{
+ struct k3_ring_cfg ring_cfg;
+ struct udma_dev *ud = uc->ud;
+ int ret;
+
+ ret = bcdma_get_bchan(uc);
+ if (ret)
+ return ret;
+
+ ret = k3_ringacc_request_rings_pair(ud->ringacc, uc->bchan->id, -1,
+ &uc->bchan->t_ring,
+ &uc->bchan->tc_ring);
+ if (ret) {
+ ret = -EBUSY;
+ goto err_ring;
+ }
+
+ memset(&ring_cfg, 0, sizeof(ring_cfg));
+ ring_cfg.size = 16;
+ ring_cfg.elm_size = K3_RINGACC_RING_ELSIZE_8;
+ ring_cfg.mode = K3_RINGACC_RING_MODE_RING;
+
+ ret = k3_ringacc_ring_cfg(uc->bchan->t_ring, &ring_cfg);
+ if (ret)
+ goto err_ringcfg;
+
+ return 0;
+
+err_ringcfg:
+ k3_ringacc_ring_free(uc->bchan->tc_ring);
+ uc->bchan->tc_ring = NULL;
+ k3_ringacc_ring_free(uc->bchan->t_ring);
+ uc->bchan->t_ring = NULL;
+err_ring:
+ bcdma_put_bchan(uc);
+
+ return ret;
+}
+
+int udma_transfer(struct device *dev, int direction,
+ dma_addr_t dst, dma_addr_t src, size_t len)
+{
+ struct udma_dev *ud = dev_get_priv(dev);
+ /* Channel0 is reserved for memcpy */
+ struct udma_chan *uc = &ud->channels[0];
+ dma_addr_t paddr = 0;
+ int ret;
+
+ udma_prep_dma_memcpy(uc, dst, src, len);
+ udma_start(uc);
+ ret = udma_poll_completion(uc, &paddr);
+ udma_stop(uc);
+
+ return ret;
+}
+
+int udma_enable(struct dma *dma)
+{
+ struct udma_dev *ud = dev_get_priv(dma->dev);
+ struct udma_chan *uc;
+ int ret;
+
+ if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
+ dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
+ return -EINVAL;
+ }
+ uc = &ud->channels[dma->id];
+
+ ret = udma_start(uc);
+
+ return ret;
+}
+
+int udma_disable(struct dma *dma)
+{
+ struct udma_dev *ud = dev_get_priv(dma->dev);
+ struct udma_chan *uc;
+ int ret = 0;
+
+ if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
+ dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
+ return -EINVAL;
+ }
+ uc = &ud->channels[dma->id];
+
+ if (udma_is_chan_running(uc))
+ ret = udma_stop(uc);
+ else
+ dev_err(dma->dev, "%s not running\n", __func__);
+
+ return ret;
+}
+
+int udma_send(struct dma *dma, dma_addr_t src, size_t len, void *metadata)
+{
+ struct udma_dev *ud = dev_get_priv(dma->dev);
+ struct cppi5_host_desc_t *desc_tx;
+ struct ti_udma_drv_packet_data packet_data = { 0 };
+ dma_addr_t paddr;
+ struct udma_chan *uc;
+ u32 tc_ring_id;
+ int ret;
+ u64 asel;
+
+ if (metadata)
+ packet_data = *((struct ti_udma_drv_packet_data *)metadata);
+
+ if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
+ dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
+ return -EINVAL;
+ }
+ uc = &ud->channels[dma->id];
+
+ asel = (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT;
+
+ if (uc->config.dir != DMA_MEM_TO_DEV)
+ return -EINVAL;
+
+ tc_ring_id = k3_ringacc_get_ring_id(uc->tchan->tc_ring);
+
+ desc_tx = uc->desc_tx;
+
+ cppi5_hdesc_reset_hbdesc(desc_tx);
+
+ src |= asel;
+
+ cppi5_hdesc_init(desc_tx,
+ uc->config.needs_epib ? CPPI5_INFO0_HDESC_EPIB_PRESENT : 0,
+ uc->config.psd_size);
+ cppi5_hdesc_set_pktlen(desc_tx, len);
+ cppi5_hdesc_attach_buf(desc_tx, src, len, src, len);
+ cppi5_desc_set_pktids(&desc_tx->hdr, uc->id, 0x3fff);
+ cppi5_desc_set_retpolicy(&desc_tx->hdr, 0, tc_ring_id);
+ /* pass below information from caller */
+ cppi5_hdesc_set_pkttype(desc_tx, packet_data.pkt_type);
+ cppi5_desc_set_tags_ids(&desc_tx->hdr, 0, packet_data.dest_tag);
+
+ ret = udma_push_to_ring(uc->tchan->t_ring, uc->desc_tx);
+ if (ret) {
+ dev_err(dma->dev, "TX dma push fail ch_id %lu %d\n",
+ dma->id, ret);
+ return ret;
+ }
+
+ return udma_poll_completion(uc, &paddr);
+}
+
+int udma_receive(struct dma *dma, dma_addr_t *dst, void *metadata)
+{
+ struct udma_dev *ud = dev_get_priv(dma->dev);
+ struct udma_chan_config *ucc;
+ struct cppi5_host_desc_t *desc_rx;
+ dma_addr_t buf_dma;
+ struct udma_chan *uc;
+ u32 buf_dma_len, pkt_len;
+ u32 port_id = 0;
+ int ret;
+
+ if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
+ dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
+ return -EINVAL;
+ }
+ uc = &ud->channels[dma->id];
+ ucc = &uc->config;
+
+ if (uc->config.dir != DMA_DEV_TO_MEM)
+ return -EINVAL;
+ if (!uc->num_rx_bufs)
+ return -EINVAL;
+
+ ret = k3_ringacc_ring_pop(uc->rflow->r_ring, &desc_rx);
+ if (ret && ret != -ENODATA) {
+ dev_err(dma->dev, "rx dma fail ch_id:%lu %d\n", dma->id, ret);
+ return ret;
+ } else if (ret == -ENODATA) {
+ return 0;
+ }
+
+ cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len);
+ pkt_len = cppi5_hdesc_get_pktlen(desc_rx);
+
+ cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL);
+
+ if (metadata) {
+ struct ti_udma_drv_packet_data *packet_data = metadata;
+
+ packet_data->src_tag = port_id;
+ }
+
+ *dst = buf_dma & GENMASK_ULL(K3_ADDRESS_ASEL_SHIFT - 1, 0);
+
+ uc->num_rx_bufs--;
+
+ return pkt_len;
+}
+
+int udma_of_xlate(struct dma *dma, struct of_phandle_args *args)
+{
+ struct udma_chan_config *ucc;
+ struct udma_dev *ud = dev_get_priv(dma->dev);
+ struct udma_chan *uc = &ud->channels[0];
+ struct psil_endpoint_config *ep_config;
+ u32 val;
+
+ for (val = 0; val < ud->ch_count; val++) {
+ uc = &ud->channels[val];
+ if (!uc->in_use)
+ break;
+ }
+
+ if (val == ud->ch_count)
+ return -EBUSY;
+
+ ucc = &uc->config;
+ ucc->remote_thread_id = args->args[0];
+ if (ucc->remote_thread_id & K3_PSIL_DST_THREAD_ID_OFFSET)
+ ucc->dir = DMA_MEM_TO_DEV;
+ else
+ ucc->dir = DMA_DEV_TO_MEM;
+
+ ep_config = psil_get_ep_config(ucc->remote_thread_id);
+
+ if (IS_ERR(ep_config)) {
+ dev_err(ud->dev, "No configuration for psi-l thread 0x%04x\n",
+ uc->config.remote_thread_id);
+ ucc->dir = DMA_MEM_TO_MEM;
+ ucc->remote_thread_id = -1;
+ return false;
+ }
+
+ ucc->pkt_mode = ep_config->pkt_mode;
+ ucc->channel_tpl = ep_config->channel_tpl;
+ ucc->notdpkt = ep_config->notdpkt;
+ ucc->ep_type = ep_config->ep_type;
+
+ if (ud->match_data->type == DMA_TYPE_PKTDMA &&
+ ep_config->mapped_channel_id >= 0) {
+ ucc->mapped_channel_id = ep_config->mapped_channel_id;
+ ucc->default_flow_id = ep_config->default_flow_id;
+ if (args->args_count == 2)
+ ucc->asel = args->args[1];
+ } else {
+ ucc->mapped_channel_id = -1;
+ ucc->default_flow_id = -1;
+ }
+
+ ucc->needs_epib = ep_config->needs_epib;
+ ucc->psd_size = ep_config->psd_size;
+ ucc->metadata_size = (ucc->needs_epib ? CPPI5_INFO0_HDESC_EPIB_SIZE : 0) + ucc->psd_size;
+
+ ucc->hdesc_size = cppi5_hdesc_calc_size(ucc->needs_epib,
+ ucc->psd_size, 0);
+ ucc->hdesc_size = ALIGN(ucc->hdesc_size, DMA_ALIGNMENT);
+
+ dma->id = uc->id;
+ dev_dbg(ud->dev, "Allocated dma chn:%lu epib:%d psdata:%u meta:%u thread_id:%x\n",
+ dma->id, ucc->needs_epib,
+ ucc->psd_size, ucc->metadata_size,
+ ucc->remote_thread_id);
+
+ return 0;
+}
+
+int udma_prepare_rcv_buf(struct dma *dma, dma_addr_t dst, size_t size)
+{
+ struct udma_dev *ud = dev_get_priv(dma->dev);
+ struct cppi5_host_desc_t *desc_rx;
+ struct udma_chan *uc;
+ u32 desc_num;
+ u64 asel;
+
+ if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
+ dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
+ return -EINVAL;
+ }
+ uc = &ud->channels[dma->id];
+
+ if (uc->config.dir != DMA_DEV_TO_MEM)
+ return -EINVAL;
+
+ if (uc->num_rx_bufs >= UDMA_RX_DESC_NUM)
+ return -EINVAL;
+
+ asel = (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT;
+ desc_num = uc->desc_rx_cur % UDMA_RX_DESC_NUM;
+ desc_rx = uc->desc_rx + (desc_num * uc->config.hdesc_size);
+
+ cppi5_hdesc_reset_hbdesc(desc_rx);
+
+ cppi5_hdesc_init(desc_rx,
+ uc->config.needs_epib ? CPPI5_INFO0_HDESC_EPIB_PRESENT : 0,
+ uc->config.psd_size);
+ cppi5_hdesc_set_pktlen(desc_rx, size);
+ dst |= asel;
+ cppi5_hdesc_attach_buf(desc_rx, dst, size, dst, size);
+
+ udma_push_to_ring(uc->rflow->fd_ring, desc_rx);
+
+ uc->num_rx_bufs++;
+ uc->desc_rx_cur++;
+
+ return 0;
+}
+
+int udma_get_cfg(struct dma *dma, u32 id, void **data)
+{
+ struct udma_dev *ud = dev_get_priv(dma->dev);
+ struct udma_chan *uc;
+
+ if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
+ dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
+ return -EINVAL;
+ }
+
+ switch (id) {
+ case TI_UDMA_CHAN_PRIV_INFO:
+ uc = &ud->channels[dma->id];
+ *data = &uc->cfg_data;
+ return 0;
+ }
+
+ return -EINVAL;
+}
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index b9af13dcc0d2da47231b3f8751c66ac10e25973d..fb0fe62c53a9f298966ce64e0d34cac71230e5da 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -24,29 +24,10 @@
#include "k3-udma-hwdef.h"
#include "k3-psil-priv.h"
-
-#define K3_UDMA_MAX_RFLOWS 1024
-#define K3_ADDRESS_ASEL_SHIFT 48
+#include "k3-udma.h"
struct udma_chan;
-enum k3_dma_type {
- DMA_TYPE_UDMA = 0,
- DMA_TYPE_BCDMA,
- DMA_TYPE_PKTDMA,
-};
-
-enum udma_mmr {
- MMR_GCFG = 0,
- MMR_BCHANRT,
- MMR_RCHANRT,
- MMR_TCHANRT,
- MMR_RCHAN,
- MMR_TCHAN,
- MMR_RFLOW,
- MMR_LAST,
-};
-
static const char * const mmr_names[] = {
[MMR_GCFG] = "gcfg",
[MMR_BCHANRT] = "bchanrt",
@@ -57,240 +38,6 @@ static const char * const mmr_names[] = {
[MMR_RFLOW] = "rflow",
};
-struct udma_tchan {
- void __iomem *reg_chan;
- void __iomem *reg_rt;
-
- int id;
- struct k3_ring *t_ring; /* Transmit ring */
- struct k3_ring *tc_ring; /* Transmit Completion ring */
- int tflow_id; /* applicable only for PKTDMA */
-};
-
-#define udma_bchan udma_tchan
-
-struct udma_rflow {
- void __iomem *reg_rflow;
- int id;
- struct k3_ring *fd_ring; /* Free Descriptor ring */
- struct k3_ring *r_ring; /* Receive ring */
-};
-
-struct udma_rchan {
- void __iomem *reg_chan;
- void __iomem *reg_rt;
-
- int id;
-};
-
-struct udma_oes_offsets {
- /* K3 UDMA Output Event Offset */
- u32 udma_rchan;
-
- /* BCDMA Output Event Offsets */
- u32 bcdma_bchan_data;
- u32 bcdma_bchan_ring;
- u32 bcdma_tchan_data;
- u32 bcdma_tchan_ring;
- u32 bcdma_rchan_data;
- u32 bcdma_rchan_ring;
-
- /* PKTDMA Output Event Offsets */
- u32 pktdma_tchan_flow;
- u32 pktdma_rchan_flow;
-};
-
-#define UDMA_FLAG_PDMA_ACC32 BIT(0)
-#define UDMA_FLAG_PDMA_BURST BIT(1)
-#define UDMA_FLAG_TDTYPE BIT(2)
-
-struct udma_match_data {
- enum k3_dma_type type;
- u32 psil_base;
- bool enable_memcpy_support;
- u32 flags;
- u32 statictr_z_mask;
- struct udma_oes_offsets oes;
-
- u8 tpl_levels;
- u32 level_start_idx[];
-};
-
-enum udma_rm_range {
- RM_RANGE_BCHAN = 0,
- RM_RANGE_TCHAN,
- RM_RANGE_RCHAN,
- RM_RANGE_RFLOW,
- RM_RANGE_TFLOW,
- RM_RANGE_LAST,
-};
-
-struct udma_tisci_rm {
- const struct ti_sci_handle *tisci;
- const struct ti_sci_rm_udmap_ops *tisci_udmap_ops;
- u32 tisci_dev_id;
-
- /* tisci information for PSI-L thread pairing/unpairing */
- const struct ti_sci_rm_psil_ops *tisci_psil_ops;
- u32 tisci_navss_dev_id;
-
- struct ti_sci_resource *rm_ranges[RM_RANGE_LAST];
-};
-
-struct udma_dev {
- struct dma_device dmad;
- struct device *dev;
- void __iomem *mmrs[MMR_LAST];
-
- struct udma_tisci_rm tisci_rm;
- struct k3_ringacc *ringacc;
-
- u32 features;
-
- int bchan_cnt;
- int tchan_cnt;
- int echan_cnt;
- int rchan_cnt;
- int rflow_cnt;
- int tflow_cnt;
- unsigned long *bchan_map;
- unsigned long *tchan_map;
- unsigned long *rchan_map;
- unsigned long *rflow_map;
- unsigned long *rflow_map_reserved;
- unsigned long *tflow_map;
-
- struct udma_bchan *bchans;
- struct udma_tchan *tchans;
- struct udma_rchan *rchans;
- struct udma_rflow *rflows;
-
- const struct udma_match_data *match_data;
-
- struct udma_chan *channels;
- u32 psil_base;
-
- u32 ch_count;
-};
-
-struct udma_chan_config {
- u32 psd_size; /* size of Protocol Specific Data */
- u32 metadata_size; /* (needs_epib ? 16:0) + psd_size */
- u32 hdesc_size; /* Size of a packet descriptor in packet mode */
- int remote_thread_id;
- u32 atype;
- u32 src_thread;
- u32 dst_thread;
- enum psil_endpoint_type ep_type;
- enum udma_tp_level channel_tpl; /* Channel Throughput Level */
-
- /* PKTDMA mapped channel */
- int mapped_channel_id;
- /* PKTDMA default tflow or rflow for mapped channel */
- int default_flow_id;
-
- enum dma_transfer_direction dir;
-
- unsigned int pkt_mode:1; /* TR or packet */
- unsigned int needs_epib:1; /* EPIB is needed for the communication or not */
- unsigned int enable_acc32:1;
- unsigned int enable_burst:1;
- unsigned int notdpkt:1; /* Suppress sending TDC packet */
-
- u8 asel;
-};
-
-struct udma_chan {
- struct udma_dev *ud;
- char name[20];
-
- struct udma_bchan *bchan;
- struct udma_tchan *tchan;
- struct udma_rchan *rchan;
- struct udma_rflow *rflow;
-
- struct ti_udma_drv_chan_cfg_data cfg_data;
-
- u32 bcnt; /* number of bytes completed since the start of the channel */
-
- struct udma_chan_config config;
-
- u32 id;
-
- struct cppi5_host_desc_t *desc_tx;
- bool in_use;
- void *desc_rx;
- u32 num_rx_bufs;
- u32 desc_rx_cur;
-
-};
-
-#define UDMA_CH_1000(ch) (ch * 0x1000)
-#define UDMA_CH_100(ch) (ch * 0x100)
-#define UDMA_CH_40(ch) (ch * 0x40)
-
-#define UDMA_RX_DESC_NUM 128
-
-/* Generic register access functions */
-static inline u32 udma_read(void __iomem *base, int reg)
-{
- u32 v;
-
- v = readl(base + reg);
-
- return v;
-}
-
-static inline void udma_write(void __iomem *base, int reg, u32 val)
-{
- writel(val, base + reg);
-}
-
-static inline void udma_update_bits(void __iomem *base, int reg,
- u32 mask, u32 val)
-{
- u32 tmp, orig;
-
- orig = udma_read(base, reg);
- tmp = orig & ~mask;
- tmp |= (val & mask);
-
- if (tmp != orig)
- udma_write(base, reg, tmp);
-}
-
-/* TCHANRT */
-static inline u32 udma_tchanrt_read(struct udma_tchan *tchan, int reg)
-{
- if (!tchan)
- return 0;
- return udma_read(tchan->reg_rt, reg);
-}
-
-static inline void udma_tchanrt_write(struct udma_tchan *tchan,
- int reg, u32 val)
-{
- if (!tchan)
- return;
- udma_write(tchan->reg_rt, reg, val);
-}
-
-/* RCHANRT */
-static inline u32 udma_rchanrt_read(struct udma_rchan *rchan, int reg)
-{
- if (!rchan)
- return 0;
- return udma_read(rchan->reg_rt, reg);
-}
-
-static inline void udma_rchanrt_write(struct udma_rchan *rchan,
- int reg, u32 val)
-{
- if (!rchan)
- return;
- udma_write(rchan->reg_rt, reg, val);
-}
-
static inline int udma_navss_psil_pair(struct udma_dev *ud, u32 src_thread,
u32 dst_thread)
{
@@ -315,24 +62,6 @@ static inline int udma_navss_psil_unpair(struct udma_dev *ud, u32 src_thread,
src_thread, dst_thread);
}
-static inline char *udma_get_dir_text(enum dma_transfer_direction dir)
-{
- switch (dir) {
- case DMA_DEV_TO_MEM:
- return "DEV_TO_MEM";
- case DMA_MEM_TO_DEV:
- return "MEM_TO_DEV";
- case DMA_MEM_TO_MEM:
- return "MEM_TO_MEM";
- case DMA_DEV_TO_DEV:
- return "DEV_TO_DEV";
- default:
- break;
- }
-
- return "invalid";
-}
-
#define UDMA_RCHAN_RFLOW_RNG_FLOWID_CNT_SHIFT (16)
/* How SRC/DST tag should be updated by UDMA in the descriptor's Word 3 */
@@ -406,666 +135,45 @@ static inline void udma_rflow_update_bits(struct udma_rflow *rflow, int reg,
udma_update_bits(rflow->reg_rflow, reg, mask, val);
}
-static void udma_reset_uchan(struct udma_chan *uc)
-{
- memset(&uc->config, 0, sizeof(uc->config));
- uc->config.remote_thread_id = -1;
- uc->config.mapped_channel_id = -1;
- uc->config.default_flow_id = -1;
-}
-
-static inline bool udma_is_chan_running(struct udma_chan *uc)
-{
- u32 trt_ctl = 0;
- u32 rrt_ctl = 0;
-
- switch (uc->config.dir) {
- case DMA_DEV_TO_MEM:
- rrt_ctl = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_CTL_REG);
- dev_dbg(uc->ud->dev, "rrt_ctl: 0x%08x (peer: 0x%08x)\n",
- rrt_ctl,
- udma_rchanrt_read(uc->rchan,
- UDMA_RCHAN_RT_PEER_RT_EN_REG));
- break;
- case DMA_MEM_TO_DEV:
- trt_ctl = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_CTL_REG);
- dev_dbg(uc->ud->dev, "trt_ctl: 0x%08x (peer: 0x%08x)\n",
- trt_ctl,
- udma_tchanrt_read(uc->tchan,
- UDMA_TCHAN_RT_PEER_RT_EN_REG));
- break;
- case DMA_MEM_TO_MEM:
- trt_ctl = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_CTL_REG);
- rrt_ctl = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_CTL_REG);
- break;
- default:
- break;
- }
-
- if (trt_ctl & UDMA_CHAN_RT_CTL_EN || rrt_ctl & UDMA_CHAN_RT_CTL_EN)
- return true;
-
- return false;
-}
-
-static int udma_pop_from_ring(struct udma_chan *uc, dma_addr_t *addr)
-{
- struct k3_ring *ring = NULL;
- int ret = -ENOENT;
-
- switch (uc->config.dir) {
- case DMA_DEV_TO_MEM:
- ring = uc->rflow->r_ring;
- break;
- case DMA_MEM_TO_DEV:
- ring = uc->tchan->tc_ring;
- break;
- case DMA_MEM_TO_MEM:
- ring = uc->tchan->tc_ring;
- break;
- default:
- break;
- }
-
- if (ring && k3_ringacc_ring_get_occ(ring))
- ret = k3_ringacc_ring_pop(ring, addr);
-
- return ret;
-}
-
-static void udma_reset_rings(struct udma_chan *uc)
-{
- struct k3_ring *ring1 = NULL;
- struct k3_ring *ring2 = NULL;
-
- switch (uc->config.dir) {
- case DMA_DEV_TO_MEM:
- ring1 = uc->rflow->fd_ring;
- ring2 = uc->rflow->r_ring;
- break;
- case DMA_MEM_TO_DEV:
- ring1 = uc->tchan->t_ring;
- ring2 = uc->tchan->tc_ring;
- break;
- case DMA_MEM_TO_MEM:
- ring1 = uc->tchan->t_ring;
- ring2 = uc->tchan->tc_ring;
- break;
- default:
- break;
- }
-
- if (ring1)
- k3_ringacc_ring_reset_dma(ring1, k3_ringacc_ring_get_occ(ring1));
- if (ring2)
- k3_ringacc_ring_reset(ring2);
-}
-
-static void udma_reset_counters(struct udma_chan *uc)
-{
- u32 val;
-
- if (uc->tchan) {
- val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_BCNT_REG);
- udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_BCNT_REG, val);
-
- val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_SBCNT_REG);
- udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_SBCNT_REG, val);
-
- val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PCNT_REG);
- udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PCNT_REG, val);
-
- if (!uc->bchan) {
- val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PEER_BCNT_REG);
- udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PEER_BCNT_REG, val);
- }
- }
-
- if (uc->rchan) {
- val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_BCNT_REG);
- udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_BCNT_REG, val);
-
- val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_SBCNT_REG);
- udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_SBCNT_REG, val);
-
- val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_PCNT_REG);
- udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PCNT_REG, val);
-
- val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_PEER_BCNT_REG);
- udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_BCNT_REG, val);
- }
-
- uc->bcnt = 0;
-}
-
-static inline int udma_stop_hard(struct udma_chan *uc)
-{
- dev_dbg(uc->ud->dev, "%s: ENTER (chan%d)\n", __func__, uc->id);
-
- switch (uc->config.dir) {
- case DMA_DEV_TO_MEM:
- udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG, 0);
- udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG, 0);
- break;
- case DMA_MEM_TO_DEV:
- udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG, 0);
- udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PEER_RT_EN_REG, 0);
- break;
- case DMA_MEM_TO_MEM:
- udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG, 0);
- udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG, 0);
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int udma_start(struct udma_chan *uc)
-{
- /* Channel is already running, no need to proceed further */
- if (udma_is_chan_running(uc))
- goto out;
-
- dev_dbg(uc->ud->dev, "%s: chan:%d dir:%s\n",
- __func__, uc->id, udma_get_dir_text(uc->config.dir));
-
- /* Make sure that we clear the teardown bit, if it is set */
- udma_stop_hard(uc);
-
- /* Reset all counters */
- udma_reset_counters(uc);
-
- switch (uc->config.dir) {
- case DMA_DEV_TO_MEM:
- udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG,
- UDMA_CHAN_RT_CTL_EN);
-
- /* Enable remote */
- udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG,
- UDMA_PEER_RT_EN_ENABLE);
-
- dev_dbg(uc->ud->dev, "%s(rx): RT_CTL:0x%08x PEER RT_ENABLE:0x%08x\n",
- __func__,
- udma_rchanrt_read(uc->rchan,
- UDMA_RCHAN_RT_CTL_REG),
- udma_rchanrt_read(uc->rchan,
- UDMA_RCHAN_RT_PEER_RT_EN_REG));
- break;
- case DMA_MEM_TO_DEV:
- /* Enable remote */
- udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PEER_RT_EN_REG,
- UDMA_PEER_RT_EN_ENABLE);
-
- udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG,
- UDMA_CHAN_RT_CTL_EN);
-
- dev_dbg(uc->ud->dev, "%s(tx): RT_CTL:0x%08x PEER RT_ENABLE:0x%08x\n",
- __func__,
- udma_tchanrt_read(uc->tchan,
- UDMA_TCHAN_RT_CTL_REG),
- udma_tchanrt_read(uc->tchan,
- UDMA_TCHAN_RT_PEER_RT_EN_REG));
- break;
- case DMA_MEM_TO_MEM:
- udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG,
- UDMA_CHAN_RT_CTL_EN);
- udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG,
- UDMA_CHAN_RT_CTL_EN);
-
- break;
- default:
- return -EINVAL;
- }
-
- dev_dbg(uc->ud->dev, "%s: DONE chan:%d\n", __func__, uc->id);
-out:
- return 0;
-}
-
-static inline void udma_stop_mem2dev(struct udma_chan *uc, bool sync)
-{
- int i = 0;
- u32 val;
-
- udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG,
- UDMA_CHAN_RT_CTL_EN |
- UDMA_CHAN_RT_CTL_TDOWN);
-
- val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_CTL_REG);
-
- while (sync && (val & UDMA_CHAN_RT_CTL_EN)) {
- val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_CTL_REG);
- udelay(1);
- if (i > 1000) {
- dev_dbg(uc->ud->dev, "%s TIMEOUT !\n", __func__);
- break;
- }
- i++;
- }
-
- val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PEER_RT_EN_REG);
- if (val & UDMA_PEER_RT_EN_ENABLE)
- dev_dbg(uc->ud->dev, "%s: peer not stopped TIMEOUT !\n", __func__);
-}
-
-static inline void udma_stop_dev2mem(struct udma_chan *uc, bool sync)
-{
- int i = 0;
- u32 val;
-
- udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG,
- UDMA_PEER_RT_EN_ENABLE |
- UDMA_PEER_RT_EN_TEARDOWN);
-
- val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_CTL_REG);
-
- while (sync && (val & UDMA_CHAN_RT_CTL_EN)) {
- val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_CTL_REG);
- udelay(1);
- if (i > 1000) {
- dev_dbg(uc->ud->dev, "%s TIMEOUT !\n", __func__);
- break;
- }
- i++;
- }
-
- val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG);
- if (val & UDMA_PEER_RT_EN_ENABLE)
- dev_dbg(uc->ud->dev, "%s: peer not stopped TIMEOUT !\n", __func__);
-}
-
-static inline int udma_stop(struct udma_chan *uc)
-{
- dev_dbg(uc->ud->dev, "%s: chan:%d dir:%s\n",
- __func__, uc->id, udma_get_dir_text(uc->config.dir));
-
- udma_reset_counters(uc);
- switch (uc->config.dir) {
- case DMA_DEV_TO_MEM:
- udma_stop_dev2mem(uc, true);
- break;
- case DMA_MEM_TO_DEV:
- udma_stop_mem2dev(uc, true);
- break;
- case DMA_MEM_TO_MEM:
- udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG, 0);
- udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG, 0);
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int udma_poll_completion(struct udma_chan *uc, dma_addr_t *paddr)
-{
- u64 start = get_time_ns();
- int ret;
-
- while (!is_timeout(start, SECOND)) {
- ret = udma_pop_from_ring(uc, paddr);
- if (!ret)
- return 0;
- }
-
- return -ETIMEDOUT;
-}
-
-static struct udma_rflow *__udma_reserve_rflow(struct udma_dev *ud, int id)
-{
- DECLARE_BITMAP(tmp, K3_UDMA_MAX_RFLOWS);
-
- if (id >= 0) {
- if (test_bit(id, ud->rflow_map)) {
- dev_err(ud->dev, "rflow%d is in use\n", id);
- return ERR_PTR(-ENOENT);
- }
- } else {
- bitmap_or(tmp, ud->rflow_map, ud->rflow_map_reserved,
- ud->rflow_cnt);
-
- id = find_next_zero_bit(tmp, ud->rflow_cnt, ud->rchan_cnt);
- if (id >= ud->rflow_cnt)
- return ERR_PTR(-ENOENT);
- }
-
- __set_bit(id, ud->rflow_map);
- return &ud->rflows[id];
-}
-
-#define UDMA_RESERVE_RESOURCE(res) \
-static struct udma_##res *__udma_reserve_##res(struct udma_dev *ud, \
- int id) \
-{ \
- if (id >= 0) { \
- if (test_bit(id, ud->res##_map)) { \
- dev_err(ud->dev, "res##%d is in use\n", id); \
- return ERR_PTR(-ENOENT); \
- } \
- } else { \
- id = find_first_zero_bit(ud->res##_map, ud->res##_cnt); \
- if (id == ud->res##_cnt) { \
- return ERR_PTR(-ENOENT); \
- } \
- } \
- \
- __set_bit(id, ud->res##_map); \
- return &ud->res##s[id]; \
-}
-
-UDMA_RESERVE_RESOURCE(tchan);
-UDMA_RESERVE_RESOURCE(rchan);
-
-static int udma_get_tchan(struct udma_chan *uc)
-{
- struct udma_dev *ud = uc->ud;
-
- if (uc->tchan) {
- dev_dbg(ud->dev, "chan%d: already have tchan%d allocated\n",
- uc->id, uc->tchan->id);
- return 0;
- }
-
- uc->tchan = __udma_reserve_tchan(ud, uc->config.mapped_channel_id);
- if (IS_ERR(uc->tchan))
- return PTR_ERR(uc->tchan);
-
- if (ud->tflow_cnt) {
- int tflow_id;
-
- /* Only PKTDMA have support for tx flows */
- if (uc->config.default_flow_id >= 0)
- tflow_id = uc->config.default_flow_id;
- else
- tflow_id = uc->tchan->id;
-
- if (test_bit(tflow_id, ud->tflow_map)) {
- dev_err(ud->dev, "tflow%d is in use\n", tflow_id);
- __clear_bit(uc->tchan->id, ud->tchan_map);
- uc->tchan = NULL;
- return -ENOENT;
- }
-
- uc->tchan->tflow_id = tflow_id;
- __set_bit(tflow_id, ud->tflow_map);
- } else {
- uc->tchan->tflow_id = -1;
- }
-
- dev_dbg(ud->dev, "chan%d: got tchan%d\n", uc->id, uc->tchan->id);
-
- return 0;
-}
-
-static int udma_get_rchan(struct udma_chan *uc)
-{
- struct udma_dev *ud = uc->ud;
-
- if (uc->rchan) {
- dev_dbg(ud->dev, "chan%d: already have rchan%d allocated\n",
- uc->id, uc->rchan->id);
- return 0;
- }
-
- uc->rchan = __udma_reserve_rchan(ud, uc->config.mapped_channel_id);
- if (IS_ERR(uc->rchan))
- return PTR_ERR(uc->rchan);
-
- dev_dbg(uc->ud->dev, "chan%d: got rchan%d\n", uc->id, uc->rchan->id);
-
- return 0;
-}
-
static int udma_get_chan_pair(struct udma_chan *uc)
{
struct udma_dev *ud = uc->ud;
int chan_id, end;
- if ((uc->tchan && uc->rchan) && uc->tchan->id == uc->rchan->id) {
- dev_info(ud->dev, "chan%d: already have %d pair allocated\n",
- uc->id, uc->tchan->id);
- return 0;
- }
-
- if (uc->tchan) {
- dev_err(ud->dev, "chan%d: already have tchan%d allocated\n",
- uc->id, uc->tchan->id);
- return -EBUSY;
- } else if (uc->rchan) {
- dev_err(ud->dev, "chan%d: already have rchan%d allocated\n",
- uc->id, uc->rchan->id);
- return -EBUSY;
- }
-
- /* Can be optimized, but let's have it like this for now */
- end = min(ud->tchan_cnt, ud->rchan_cnt);
- for (chan_id = 0; chan_id < end; chan_id++) {
- if (!test_bit(chan_id, ud->tchan_map) &&
- !test_bit(chan_id, ud->rchan_map))
- break;
- }
-
- if (chan_id == end)
- return -ENOENT;
-
- __set_bit(chan_id, ud->tchan_map);
- __set_bit(chan_id, ud->rchan_map);
- uc->tchan = &ud->tchans[chan_id];
- uc->rchan = &ud->rchans[chan_id];
-
- dev_dbg(ud->dev, "chan%d: got t/rchan%d pair\n", uc->id, chan_id);
-
- return 0;
-}
-
-static int udma_get_rflow(struct udma_chan *uc, int flow_id)
-{
- struct udma_dev *ud = uc->ud;
-
- if (uc->rflow) {
- dev_dbg(ud->dev, "chan%d: already have rflow%d allocated\n",
- uc->id, uc->rflow->id);
- return 0;
- }
-
- if (!uc->rchan)
- dev_warn(ud->dev, "chan%d: does not have rchan??\n", uc->id);
-
- uc->rflow = __udma_reserve_rflow(ud, flow_id);
- if (IS_ERR(uc->rflow))
- return PTR_ERR(uc->rflow);
-
- dev_dbg(uc->ud->dev, "chan%d: got rflow%d\n", uc->id, uc->rflow->id);
-
- return 0;
-}
-
-static void udma_put_rchan(struct udma_chan *uc)
-{
- struct udma_dev *ud = uc->ud;
-
- if (uc->rchan) {
- dev_dbg(ud->dev, "chan%d: put rchan%d\n", uc->id,
- uc->rchan->id);
- __clear_bit(uc->rchan->id, ud->rchan_map);
- uc->rchan = NULL;
- }
-}
-
-static void udma_put_tchan(struct udma_chan *uc)
-{
- struct udma_dev *ud = uc->ud;
-
- if (uc->tchan) {
- dev_dbg(ud->dev, "chan%d: put tchan%d\n", uc->id,
- uc->tchan->id);
- __clear_bit(uc->tchan->id, ud->tchan_map);
- if (uc->tchan->tflow_id >= 0)
- __clear_bit(uc->tchan->tflow_id, ud->tflow_map);
- uc->tchan = NULL;
- }
-}
-
-static void udma_put_rflow(struct udma_chan *uc)
-{
- struct udma_dev *ud = uc->ud;
-
- if (uc->rflow) {
- dev_dbg(ud->dev, "chan%d: put rflow%d\n", uc->id,
- uc->rflow->id);
- __clear_bit(uc->rflow->id, ud->rflow_map);
- uc->rflow = NULL;
- }
-}
-
-static void udma_free_tx_resources(struct udma_chan *uc)
-{
- if (!uc->tchan)
- return;
-
- k3_ringacc_ring_free(uc->tchan->t_ring);
- k3_ringacc_ring_free(uc->tchan->tc_ring);
- uc->tchan->t_ring = NULL;
- uc->tchan->tc_ring = NULL;
-
- udma_put_tchan(uc);
-}
-
-static int udma_alloc_tx_resources(struct udma_chan *uc)
-{
- struct k3_ring_cfg ring_cfg;
- struct udma_dev *ud = uc->ud;
- struct udma_tchan *tchan;
- int ring_idx, ret;
-
- ret = udma_get_tchan(uc);
- if (ret)
- return ret;
-
- tchan = uc->tchan;
- if (tchan->tflow_id > 0)
- ring_idx = tchan->tflow_id;
- else
- ring_idx = tchan->id;
-
- ret = k3_ringacc_request_rings_pair(ud->ringacc, ring_idx, -1,
- &uc->tchan->t_ring,
- &uc->tchan->tc_ring);
- if (ret) {
- ret = -EBUSY;
- goto err_tx_ring;
- }
-
- memset(&ring_cfg, 0, sizeof(ring_cfg));
- ring_cfg.size = 16;
- ring_cfg.asel = uc->config.asel;
- ring_cfg.elm_size = K3_RINGACC_RING_ELSIZE_8;
- ring_cfg.mode = K3_RINGACC_RING_MODE_RING;
-
- ret = k3_ringacc_ring_cfg(uc->tchan->t_ring, &ring_cfg);
- ret |= k3_ringacc_ring_cfg(uc->tchan->tc_ring, &ring_cfg);
-
- if (ret)
- goto err_ringcfg;
-
- return 0;
-
-err_ringcfg:
- k3_ringacc_ring_free(uc->tchan->tc_ring);
- uc->tchan->tc_ring = NULL;
- k3_ringacc_ring_free(uc->tchan->t_ring);
- uc->tchan->t_ring = NULL;
-err_tx_ring:
- udma_put_tchan(uc);
-
- return ret;
-}
-
-static void udma_free_rx_resources(struct udma_chan *uc)
-{
- if (!uc->rchan)
- return;
-
- if (uc->rflow) {
- k3_ringacc_ring_free(uc->rflow->fd_ring);
- k3_ringacc_ring_free(uc->rflow->r_ring);
- uc->rflow->fd_ring = NULL;
- uc->rflow->r_ring = NULL;
-
- udma_put_rflow(uc);
- }
-
- udma_put_rchan(uc);
-}
-
-static int udma_alloc_rx_resources(struct udma_chan *uc)
-{
- struct k3_ring_cfg ring_cfg;
- struct udma_dev *ud = uc->ud;
- struct udma_rflow *rflow;
- int fd_ring_id;
- int ret;
-
- ret = udma_get_rchan(uc);
- if (ret)
- return ret;
-
- /* For MEM_TO_MEM we don't need rflow or rings */
- if (uc->config.dir == DMA_MEM_TO_MEM)
- return 0;
-
- if (uc->config.default_flow_id >= 0)
- ret = udma_get_rflow(uc, uc->config.default_flow_id);
- else
- ret = udma_get_rflow(uc, uc->rchan->id);
-
- if (ret) {
- ret = -EBUSY;
- goto err_rflow;
+ if ((uc->tchan && uc->rchan) && uc->tchan->id == uc->rchan->id) {
+ dev_info(ud->dev, "chan%d: already have %d pair allocated\n",
+ uc->id, uc->tchan->id);
+ return 0;
}
- rflow = uc->rflow;
- if (ud->tflow_cnt) {
- fd_ring_id = ud->tflow_cnt + rflow->id;
- } else {
- fd_ring_id = ud->bchan_cnt + ud->tchan_cnt + ud->echan_cnt +
- uc->rchan->id;
+ if (uc->tchan) {
+ dev_err(ud->dev, "chan%d: already have tchan%d allocated\n",
+ uc->id, uc->tchan->id);
+ return -EBUSY;
+ } else if (uc->rchan) {
+ dev_err(ud->dev, "chan%d: already have rchan%d allocated\n",
+ uc->id, uc->rchan->id);
+ return -EBUSY;
}
- ret = k3_ringacc_request_rings_pair(ud->ringacc, fd_ring_id, -1,
- &rflow->fd_ring, &rflow->r_ring);
- if (ret) {
- ret = -EBUSY;
- goto err_rx_ring;
+ /* Can be optimized, but let's have it like this for now */
+ end = min(ud->tchan_cnt, ud->rchan_cnt);
+ for (chan_id = 0; chan_id < end; chan_id++) {
+ if (!test_bit(chan_id, ud->tchan_map) &&
+ !test_bit(chan_id, ud->rchan_map))
+ break;
}
- memset(&ring_cfg, 0, sizeof(ring_cfg));
- ring_cfg.size = 16;
- ring_cfg.elm_size = K3_RINGACC_RING_ELSIZE_8;
- ring_cfg.mode = K3_RINGACC_RING_MODE_RING;
- ring_cfg.asel = uc->config.asel;
-
- ret = k3_ringacc_ring_cfg(rflow->fd_ring, &ring_cfg);
- ret |= k3_ringacc_ring_cfg(rflow->r_ring, &ring_cfg);
- if (ret)
- goto err_ringcfg;
+ if (chan_id == end)
+ return -ENOENT;
+ __set_bit(chan_id, ud->tchan_map);
+ __set_bit(chan_id, ud->rchan_map);
+ uc->tchan = &ud->tchans[chan_id];
+ uc->rchan = &ud->rchans[chan_id];
+
+ pr_debug("chan%d: got t/rchan%d pair\n", uc->id, chan_id);
return 0;
-
-err_ringcfg:
- k3_ringacc_ring_free(rflow->r_ring);
- rflow->r_ring = NULL;
- k3_ringacc_ring_free(rflow->fd_ring);
- rflow->fd_ring = NULL;
-err_rx_ring:
- udma_put_rflow(uc);
-err_rflow:
- udma_put_rchan(uc);
-
- return ret;
}
static int udma_alloc_tchan_sci_req(struct udma_chan *uc)
@@ -1738,108 +846,6 @@ static int setup_resources(struct udma_dev *ud)
return ch_count;
}
-static int udma_push_to_ring(struct k3_ring *ring, void *elem)
-{
- u64 addr = 0;
-
- memcpy(&addr, &elem, sizeof(elem));
- return k3_ringacc_ring_push(ring, &addr);
-}
-
-static int *udma_prep_dma_memcpy(struct udma_chan *uc, dma_addr_t dest,
- dma_addr_t src, size_t len)
-{
- u32 tc_ring_id = k3_ringacc_get_ring_id(uc->tchan->tc_ring);
- struct cppi5_tr_type15_t *tr_req;
- int num_tr;
- size_t tr_size = sizeof(struct cppi5_tr_type15_t);
- u16 tr0_cnt0, tr0_cnt1, tr1_cnt0;
- void *tr_desc;
- size_t desc_size;
- u64 asel = (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT;
-
- if (len < SZ_64K) {
- num_tr = 1;
- tr0_cnt0 = len;
- tr0_cnt1 = 1;
- } else {
- unsigned long align_to = __ffs(src | dest);
-
- if (align_to > 3)
- align_to = 3;
- /*
- * Keep simple: tr0: SZ_64K-alignment blocks,
- * tr1: the remaining
- */
- num_tr = 2;
- tr0_cnt0 = (SZ_64K - BIT(align_to));
- if (len / tr0_cnt0 >= SZ_64K) {
- dev_err(uc->ud->dev, "size %zu is not supported\n",
- len);
- return NULL;
- }
-
- tr0_cnt1 = len / tr0_cnt0;
- tr1_cnt0 = len % tr0_cnt0;
- }
-
- desc_size = cppi5_trdesc_calc_size(num_tr, tr_size);
- tr_desc = dma_alloc_coherent(DMA_DEVICE_BROKEN, desc_size, DMA_ADDRESS_BROKEN);
- if (!tr_desc)
- return NULL;
-
- cppi5_trdesc_init(tr_desc, num_tr, tr_size, 0, 0);
- cppi5_desc_set_pktids(tr_desc, uc->id, 0x3fff);
- cppi5_desc_set_retpolicy(tr_desc, 0, tc_ring_id);
-
- tr_req = tr_desc + tr_size;
-
- cppi5_tr_init(&tr_req[0].flags, CPPI5_TR_TYPE15, false, true,
- CPPI5_TR_EVENT_SIZE_COMPLETION, 1);
- cppi5_tr_csf_set(&tr_req[0].flags, CPPI5_TR_CSF_SUPR_EVT);
-
- src |= asel;
- dest |= asel;
-
- tr_req[0].addr = src;
- tr_req[0].icnt0 = tr0_cnt0;
- tr_req[0].icnt1 = tr0_cnt1;
- tr_req[0].icnt2 = 1;
- tr_req[0].icnt3 = 1;
- tr_req[0].dim1 = tr0_cnt0;
-
- tr_req[0].daddr = dest;
- tr_req[0].dicnt0 = tr0_cnt0;
- tr_req[0].dicnt1 = tr0_cnt1;
- tr_req[0].dicnt2 = 1;
- tr_req[0].dicnt3 = 1;
- tr_req[0].ddim1 = tr0_cnt0;
-
- if (num_tr == 2) {
- cppi5_tr_init(&tr_req[1].flags, CPPI5_TR_TYPE15, false, true,
- CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
- cppi5_tr_csf_set(&tr_req[1].flags, CPPI5_TR_CSF_SUPR_EVT);
-
- tr_req[1].addr = src + tr0_cnt1 * tr0_cnt0;
- tr_req[1].icnt0 = tr1_cnt0;
- tr_req[1].icnt1 = 1;
- tr_req[1].icnt2 = 1;
- tr_req[1].icnt3 = 1;
-
- tr_req[1].daddr = dest + tr0_cnt1 * tr0_cnt0;
- tr_req[1].dicnt0 = tr1_cnt0;
- tr_req[1].dicnt1 = 1;
- tr_req[1].dicnt2 = 1;
- tr_req[1].dicnt3 = 1;
- }
-
- cppi5_tr_csf_set(&tr_req[num_tr - 1].flags, CPPI5_TR_CSF_EOP);
-
- udma_push_to_ring(uc->tchan->t_ring, tr_desc);
-
- return 0;
-}
-
#define TISCI_BCDMA_BCHAN_VALID_PARAMS ( \
TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \
TI_SCI_MSG_VALUE_RM_UDMAP_CH_EXTENDED_CH_TYPE_VALID)
@@ -1893,107 +899,6 @@ static int bcdma_tisci_m2m_channel_config(struct udma_chan *uc)
return ret;
}
-static struct udma_bchan *__bcdma_reserve_bchan(struct udma_dev *ud, int id)
-{
- if (id >= 0) {
- if (test_bit(id, ud->bchan_map)) {
- dev_err(ud->dev, "bchan%d is in use\n", id);
- return ERR_PTR(-ENOENT);
- }
- } else {
- id = find_next_zero_bit(ud->bchan_map, ud->bchan_cnt, 0);
- if (id == ud->bchan_cnt)
- return ERR_PTR(-ENOENT);
- }
- __set_bit(id, ud->bchan_map);
- return &ud->bchans[id];
-}
-
-static int bcdma_get_bchan(struct udma_chan *uc)
-{
- struct udma_dev *ud = uc->ud;
-
- if (uc->bchan) {
- dev_err(ud->dev, "chan%d: already have bchan%d allocated\n",
- uc->id, uc->bchan->id);
- return 0;
- }
-
- uc->bchan = __bcdma_reserve_bchan(ud, -1);
- if (IS_ERR(uc->bchan))
- return PTR_ERR(uc->bchan);
-
- uc->tchan = uc->bchan;
-
- return 0;
-}
-
-static void bcdma_put_bchan(struct udma_chan *uc)
-{
- struct udma_dev *ud = uc->ud;
-
- if (uc->bchan) {
- dev_dbg(ud->dev, "chan%d: put bchan%d\n", uc->id,
- uc->bchan->id);
- __clear_bit(uc->bchan->id, ud->bchan_map);
- uc->bchan = NULL;
- uc->tchan = NULL;
- }
-}
-
-static void bcdma_free_bchan_resources(struct udma_chan *uc)
-{
- if (!uc->bchan)
- return;
-
- k3_ringacc_ring_free(uc->bchan->tc_ring);
- k3_ringacc_ring_free(uc->bchan->t_ring);
- uc->bchan->tc_ring = NULL;
- uc->bchan->t_ring = NULL;
-
- bcdma_put_bchan(uc);
-}
-
-static int bcdma_alloc_bchan_resources(struct udma_chan *uc)
-{
- struct k3_ring_cfg ring_cfg;
- struct udma_dev *ud = uc->ud;
- int ret;
-
- ret = bcdma_get_bchan(uc);
- if (ret)
- return ret;
-
- ret = k3_ringacc_request_rings_pair(ud->ringacc, uc->bchan->id, -1,
- &uc->bchan->t_ring,
- &uc->bchan->tc_ring);
- if (ret) {
- ret = -EBUSY;
- goto err_ring;
- }
-
- memset(&ring_cfg, 0, sizeof(ring_cfg));
- ring_cfg.size = 16;
- ring_cfg.elm_size = K3_RINGACC_RING_ELSIZE_8;
- ring_cfg.mode = K3_RINGACC_RING_MODE_RING;
-
- ret = k3_ringacc_ring_cfg(uc->bchan->t_ring, &ring_cfg);
- if (ret)
- goto err_ringcfg;
-
- return 0;
-
-err_ringcfg:
- k3_ringacc_ring_free(uc->bchan->tc_ring);
- uc->bchan->tc_ring = NULL;
- k3_ringacc_ring_free(uc->bchan->t_ring);
- uc->bchan->t_ring = NULL;
-err_ring:
- bcdma_put_bchan(uc);
-
- return ret;
-}
-
static int bcdma_tisci_tx_channel_config(struct udma_chan *uc)
{
struct udma_dev *ud = uc->ud;
@@ -2207,23 +1112,6 @@ static int pktdma_alloc_chan_resources(struct udma_chan *uc)
return ret;
}
-static int udma_transfer(struct device *dev, int direction,
- dma_addr_t dst, dma_addr_t src, size_t len)
-{
- struct udma_dev *ud = dev_get_priv(dev);
- /* Channel0 is reserved for memcpy */
- struct udma_chan *uc = &ud->channels[0];
- dma_addr_t paddr = 0;
- int ret;
-
- udma_prep_dma_memcpy(uc, dst, src, len);
- udma_start(uc);
- ret = udma_poll_completion(uc, &paddr);
- udma_stop(uc);
-
- return ret;
-}
-
static int udma_request(struct dma *dma)
{
struct udma_dev *ud = dev_get_priv(dma->dev);
@@ -2302,274 +1190,6 @@ static int udma_rfree(struct dma *dma)
return 0;
}
-static int udma_enable(struct dma *dma)
-{
- struct udma_dev *ud = dev_get_priv(dma->dev);
- struct udma_chan *uc;
- int ret;
-
- if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
- dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
- return -EINVAL;
- }
- uc = &ud->channels[dma->id];
-
- ret = udma_start(uc);
-
- return ret;
-}
-
-static int udma_disable(struct dma *dma)
-{
- struct udma_dev *ud = dev_get_priv(dma->dev);
- struct udma_chan *uc;
- int ret = 0;
-
- if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
- dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
- return -EINVAL;
- }
- uc = &ud->channels[dma->id];
-
- if (udma_is_chan_running(uc))
- ret = udma_stop(uc);
- else
- dev_err(dma->dev, "%s not running\n", __func__);
-
- return ret;
-}
-
-static int udma_send(struct dma *dma, dma_addr_t src, size_t len, void *metadata)
-{
- struct udma_dev *ud = dev_get_priv(dma->dev);
- struct cppi5_host_desc_t *desc_tx;
- struct ti_udma_drv_packet_data packet_data = { 0 };
- dma_addr_t paddr;
- struct udma_chan *uc;
- u32 tc_ring_id;
- int ret;
- u64 asel;
-
- if (metadata)
- packet_data = *((struct ti_udma_drv_packet_data *)metadata);
-
- if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
- dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
- return -EINVAL;
- }
- uc = &ud->channels[dma->id];
-
- asel = (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT;
-
- if (uc->config.dir != DMA_MEM_TO_DEV)
- return -EINVAL;
-
- tc_ring_id = k3_ringacc_get_ring_id(uc->tchan->tc_ring);
-
- desc_tx = uc->desc_tx;
-
- cppi5_hdesc_reset_hbdesc(desc_tx);
-
- src |= asel;
-
- cppi5_hdesc_init(desc_tx,
- uc->config.needs_epib ? CPPI5_INFO0_HDESC_EPIB_PRESENT : 0,
- uc->config.psd_size);
- cppi5_hdesc_set_pktlen(desc_tx, len);
- cppi5_hdesc_attach_buf(desc_tx, src, len, src, len);
- cppi5_desc_set_pktids(&desc_tx->hdr, uc->id, 0x3fff);
- cppi5_desc_set_retpolicy(&desc_tx->hdr, 0, tc_ring_id);
- /* pass below information from caller */
- cppi5_hdesc_set_pkttype(desc_tx, packet_data.pkt_type);
- cppi5_desc_set_tags_ids(&desc_tx->hdr, 0, packet_data.dest_tag);
-
- ret = udma_push_to_ring(uc->tchan->t_ring, uc->desc_tx);
- if (ret) {
- dev_err(dma->dev, "TX dma push fail ch_id %lu %d\n",
- dma->id, ret);
- return ret;
- }
-
- return udma_poll_completion(uc, &paddr);
-}
-
-static int udma_receive(struct dma *dma, dma_addr_t *dst, void *metadata)
-{
- struct udma_dev *ud = dev_get_priv(dma->dev);
- struct udma_chan_config *ucc;
- struct cppi5_host_desc_t *desc_rx;
- dma_addr_t buf_dma;
- struct udma_chan *uc;
- u32 buf_dma_len, pkt_len;
- u32 port_id = 0;
- int ret;
-
- if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
- dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
- return -EINVAL;
- }
- uc = &ud->channels[dma->id];
- ucc = &uc->config;
-
- if (uc->config.dir != DMA_DEV_TO_MEM)
- return -EINVAL;
- if (!uc->num_rx_bufs)
- return -EINVAL;
-
- ret = k3_ringacc_ring_pop(uc->rflow->r_ring, &desc_rx);
- if (ret && ret != -ENODATA) {
- dev_err(dma->dev, "rx dma fail ch_id:%lu %d\n", dma->id, ret);
- return ret;
- } else if (ret == -ENODATA) {
- return 0;
- }
-
- cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len);
- pkt_len = cppi5_hdesc_get_pktlen(desc_rx);
-
- cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL);
-
- if (metadata) {
- struct ti_udma_drv_packet_data *packet_data = metadata;
-
- packet_data->src_tag = port_id;
- }
-
- *dst = buf_dma & GENMASK_ULL(K3_ADDRESS_ASEL_SHIFT - 1, 0);
-
- uc->num_rx_bufs--;
-
- return pkt_len;
-}
-
-static int udma_of_xlate(struct dma *dma, struct of_phandle_args *args)
-{
- struct udma_chan_config *ucc;
- struct udma_dev *ud = dev_get_priv(dma->dev);
- struct udma_chan *uc = &ud->channels[0];
- struct psil_endpoint_config *ep_config;
- u32 val;
-
- for (val = 0; val < ud->ch_count; val++) {
- uc = &ud->channels[val];
- if (!uc->in_use)
- break;
- }
-
- if (val == ud->ch_count)
- return -EBUSY;
-
- ucc = &uc->config;
- ucc->remote_thread_id = args->args[0];
- if (ucc->remote_thread_id & K3_PSIL_DST_THREAD_ID_OFFSET)
- ucc->dir = DMA_MEM_TO_DEV;
- else
- ucc->dir = DMA_DEV_TO_MEM;
-
- ep_config = psil_get_ep_config(ucc->remote_thread_id);
-
- if (IS_ERR(ep_config)) {
- dev_err(ud->dev, "No configuration for psi-l thread 0x%04x\n",
- uc->config.remote_thread_id);
- ucc->dir = DMA_MEM_TO_MEM;
- ucc->remote_thread_id = -1;
- return false;
- }
-
- ucc->pkt_mode = ep_config->pkt_mode;
- ucc->channel_tpl = ep_config->channel_tpl;
- ucc->notdpkt = ep_config->notdpkt;
- ucc->ep_type = ep_config->ep_type;
-
- if (ud->match_data->type == DMA_TYPE_PKTDMA &&
- ep_config->mapped_channel_id >= 0) {
- ucc->mapped_channel_id = ep_config->mapped_channel_id;
- ucc->default_flow_id = ep_config->default_flow_id;
- if (args->args_count == 2)
- ucc->asel = args->args[1];
- } else {
- ucc->mapped_channel_id = -1;
- ucc->default_flow_id = -1;
- }
-
- ucc->needs_epib = ep_config->needs_epib;
- ucc->psd_size = ep_config->psd_size;
- ucc->metadata_size = (ucc->needs_epib ? CPPI5_INFO0_HDESC_EPIB_SIZE : 0) + ucc->psd_size;
-
- ucc->hdesc_size = cppi5_hdesc_calc_size(ucc->needs_epib,
- ucc->psd_size, 0);
- ucc->hdesc_size = ALIGN(ucc->hdesc_size, DMA_ALIGNMENT);
-
- dma->id = uc->id;
- dev_dbg(ud->dev, "Allocated dma chn:%lu epib:%d psdata:%u meta:%u thread_id:%x\n",
- dma->id, ucc->needs_epib,
- ucc->psd_size, ucc->metadata_size,
- ucc->remote_thread_id);
-
- return 0;
-}
-
-static int udma_prepare_rcv_buf(struct dma *dma, dma_addr_t dst, size_t size)
-{
- struct udma_dev *ud = dev_get_priv(dma->dev);
- struct cppi5_host_desc_t *desc_rx;
- struct udma_chan *uc;
- u32 desc_num;
- u64 asel;
-
- if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
- dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
- return -EINVAL;
- }
- uc = &ud->channels[dma->id];
-
- if (uc->config.dir != DMA_DEV_TO_MEM)
- return -EINVAL;
-
- if (uc->num_rx_bufs >= UDMA_RX_DESC_NUM)
- return -EINVAL;
-
- asel = (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT;
- desc_num = uc->desc_rx_cur % UDMA_RX_DESC_NUM;
- desc_rx = uc->desc_rx + (desc_num * uc->config.hdesc_size);
-
- cppi5_hdesc_reset_hbdesc(desc_rx);
-
- cppi5_hdesc_init(desc_rx,
- uc->config.needs_epib ? CPPI5_INFO0_HDESC_EPIB_PRESENT : 0,
- uc->config.psd_size);
- cppi5_hdesc_set_pktlen(desc_rx, size);
- dst |= asel;
- cppi5_hdesc_attach_buf(desc_rx, dst, size, dst, size);
-
- udma_push_to_ring(uc->rflow->fd_ring, desc_rx);
-
- uc->num_rx_bufs++;
- uc->desc_rx_cur++;
-
- return 0;
-}
-
-static int udma_get_cfg(struct dma *dma, u32 id, void **data)
-{
- struct udma_dev *ud = dev_get_priv(dma->dev);
- struct udma_chan *uc;
-
- if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
- dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
- return -EINVAL;
- }
-
- switch (id) {
- case TI_UDMA_CHAN_PRIV_INFO:
- uc = &ud->channels[dma->id];
- *data = &uc->cfg_data;
- return 0;
- }
-
- return -EINVAL;
-}
-
static const struct dma_ops udma_ops = {
.transfer = udma_transfer,
.of_xlate = udma_of_xlate,
diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h
new file mode 100644
index 0000000000000000000000000000000000000000..88325160841886af5514ae2385400e2b4156bb07
--- /dev/null
+++ b/drivers/dma/ti/k3-udma.h
@@ -0,0 +1,355 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com
+ *
+ */
+
+#ifndef K3_UDMA_H
+#define K3_UDMA_H
+
+#include <linux/types.h>
+#include <soc/ti/k3-navss-ringacc.h>
+#include <soc/ti/cppi5.h>
+#include <soc/ti/ti-udma.h>
+#include <soc/ti/ti_sci_protocol.h>
+#include <soc/ti/cppi5.h>
+#include <dma-devices.h>
+
+#include "k3-udma-hwdef.h"
+#include "k3-udma.h"
+#include "k3-psil-priv.h"
+
+enum k3_dma_type {
+ DMA_TYPE_UDMA = 0,
+ DMA_TYPE_BCDMA,
+ DMA_TYPE_PKTDMA,
+ DMA_TYPE_BCDMA_V2,
+ DMA_TYPE_PKTDMA_V2,
+};
+
+enum udma_mmr {
+ MMR_GCFG = 0,
+ MMR_BCHANRT,
+ MMR_RCHANRT,
+ MMR_TCHANRT,
+ MMR_RCHAN,
+ MMR_TCHAN,
+ MMR_RFLOW,
+ MMR_LAST,
+};
+
+enum udma_rm_range {
+ RM_RANGE_BCHAN = 0,
+ RM_RANGE_TCHAN,
+ RM_RANGE_RCHAN,
+ RM_RANGE_RFLOW,
+ RM_RANGE_TFLOW,
+ RM_RANGE_LAST,
+};
+
+struct udma_tisci_rm {
+ const struct ti_sci_handle *tisci;
+ const struct ti_sci_rm_udmap_ops *tisci_udmap_ops;
+ u32 tisci_dev_id;
+
+ /* tisci information for PSI-L thread pairing/unpairing */
+ const struct ti_sci_rm_psil_ops *tisci_psil_ops;
+ u32 tisci_navss_dev_id;
+
+ struct ti_sci_resource *rm_ranges[RM_RANGE_LAST];
+};
+
+// Structure definitions
+struct udma_tchan {
+ void __iomem *reg_chan;
+ void __iomem *reg_rt;
+
+ int id;
+ struct k3_ring *t_ring; /* Transmit ring */
+ struct k3_ring *tc_ring; /* Transmit Completion ring */
+ int tflow_id; /* applicable only for PKTDMA */
+};
+
+#define udma_bchan udma_tchan
+
+struct udma_rflow {
+ void __iomem *reg_rflow;
+ void __iomem *reg_rt;
+ int id;
+ struct k3_ring *fd_ring; /* Free Descriptor ring */
+ struct k3_ring *r_ring; /* Receive ring */
+};
+
+struct udma_rchan {
+ void __iomem *reg_chan;
+ void __iomem *reg_rt;
+
+ int id;
+};
+
+struct udma_oes_offsets {
+ /* K3 UDMA Output Event Offset */
+ u32 udma_rchan;
+
+ /* BCDMA Output Event Offsets */
+ u32 bcdma_bchan_data;
+ u32 bcdma_bchan_ring;
+ u32 bcdma_tchan_data;
+ u32 bcdma_tchan_ring;
+ u32 bcdma_rchan_data;
+ u32 bcdma_rchan_ring;
+
+ /* PKTDMA Output Event Offsets */
+ u32 pktdma_tchan_flow;
+ u32 pktdma_rchan_flow;
+};
+
+#define UDMA_FLAG_PDMA_ACC32 BIT(0)
+#define UDMA_FLAG_PDMA_BURST BIT(1)
+#define UDMA_FLAG_TDTYPE BIT(2)
+
+struct udma_match_data {
+ u32 type;
+ u32 psil_base;
+ bool enable_memcpy_support;
+ u32 flags;
+ u32 statictr_z_mask;
+ struct udma_oes_offsets oes;
+
+ u8 tpl_levels;
+ u32 bchan_cnt;
+ u32 tchan_cnt;
+ u32 rchan_cnt;
+ u32 tflow_cnt;
+ u32 rflow_cnt;
+ u32 chan_cnt;
+
+ u32 level_start_idx[];
+};
+
+struct udma_dev {
+ struct dma_device dmad;
+ struct device *dev;
+ void __iomem *mmrs[MMR_LAST];
+
+ struct udma_tisci_rm tisci_rm;
+ struct k3_ringacc *ringacc;
+
+ u32 features;
+
+ int bchan_cnt;
+ int tchan_cnt;
+ int echan_cnt;
+ int rchan_cnt;
+ int rflow_cnt;
+ int tflow_cnt;
+ unsigned long *bchan_map;
+ unsigned long *tchan_map;
+ unsigned long *rchan_map;
+ unsigned long *rflow_map;
+ unsigned long *rflow_map_reserved;
+ unsigned long *tflow_map;
+
+ struct udma_bchan *bchans;
+ struct udma_tchan *tchans;
+ struct udma_rchan *rchans;
+ struct udma_rflow *rflows;
+
+ const struct udma_match_data *match_data;
+
+ struct udma_chan *channels;
+ u32 psil_base;
+
+ u32 ch_count;
+};
+
+struct udma_chan_config {
+ u32 psd_size; /* size of Protocol Specific Data */
+ u32 metadata_size; /* (needs_epib ? 16:0) + psd_size */
+ u32 hdesc_size; /* Size of a packet descriptor in packet mode */
+ int remote_thread_id;
+ u32 atype;
+ u32 src_thread;
+ u32 dst_thread;
+ enum psil_endpoint_type ep_type;
+ enum udma_tp_level channel_tpl; /* Channel Throughput Level */
+
+ /* PKTDMA mapped channel */
+ int mapped_channel_id;
+ /* PKTDMA default tflow or rflow for mapped channel */
+ int default_flow_id;
+
+ enum dma_transfer_direction dir;
+
+ unsigned int pkt_mode:1; /* TR or packet */
+ unsigned int needs_epib:1; /* EPIB is needed for the communication or not */
+ unsigned int enable_acc32:1;
+ unsigned int enable_burst:1;
+ unsigned int notdpkt:1; /* Suppress sending TDC packet */
+
+ u8 asel;
+};
+
+struct udma_chan {
+ struct udma_dev *ud;
+ char name[20];
+
+ struct udma_bchan *bchan;
+ struct udma_tchan *tchan;
+ struct udma_rchan *rchan;
+ struct udma_rflow *rflow;
+
+ struct ti_udma_drv_chan_cfg_data cfg_data;
+
+ u32 bcnt; /* number of bytes completed since the start of the channel */
+
+ struct udma_chan_config config;
+
+ u32 id;
+
+ struct cppi5_host_desc_t *desc_tx;
+ bool in_use;
+ void *desc_rx;
+ u32 num_rx_bufs;
+ u32 desc_rx_cur;
+
+};
+
+#define UDMA_CH_1000(ch) (ch * 0x1000)
+#define UDMA_CH_100(ch) (ch * 0x100)
+#define UDMA_CH_40(ch) (ch * 0x40)
+
+#define UDMA_RX_DESC_NUM 128
+
+#define K3_UDMA_MAX_RFLOWS 1024
+#define K3_UDMA_MAX_TR 2
+
+/* Generic register access functions */
+static inline u32 udma_read(void __iomem *base, int reg)
+{
+ u32 v;
+
+ v = readl(base + reg);
+
+ return v;
+}
+
+static inline void udma_write(void __iomem *base, int reg, u32 val)
+{
+ writel(val, base + reg);
+}
+
+static inline void udma_update_bits(void __iomem *base, int reg,
+ u32 mask, u32 val)
+{
+ u32 tmp, orig;
+
+ orig = udma_read(base, reg);
+ tmp = orig & ~mask;
+ tmp |= (val & mask);
+
+ if (tmp != orig)
+ udma_write(base, reg, tmp);
+}
+
+/* TCHANRT */
+static inline u32 udma_tchanrt_read(struct udma_tchan *tchan, int reg)
+{
+ if (!tchan)
+ return 0;
+ return udma_read(tchan->reg_rt, reg);
+}
+
+static inline void udma_tchanrt_write(struct udma_tchan *tchan,
+ int reg, u32 val)
+{
+ if (!tchan)
+ return;
+ udma_write(tchan->reg_rt, reg, val);
+}
+
+static inline void udma_tchanrt_update_bits(struct udma_tchan *tchan, int reg,
+ u32 mask, u32 val)
+{
+ if (!tchan)
+ return;
+ udma_update_bits(tchan->reg_rt, reg, mask, val);
+}
+
+/* RCHANRT */
+static inline u32 udma_rchanrt_read(struct udma_rchan *rchan, int reg)
+{
+ if (!rchan)
+ return 0;
+ return udma_read(rchan->reg_rt, reg);
+}
+
+static inline void udma_rchanrt_write(struct udma_rchan *rchan,
+ int reg, u32 val)
+{
+ if (!rchan)
+ return;
+ udma_write(rchan->reg_rt, reg, val);
+}
+
+static inline void udma_rflowrt_write(struct udma_rflow *rflow,
+ int reg, u32 val)
+{
+ if (!rflow)
+ return;
+ udma_write(rflow->reg_rflow, reg, val);
+}
+
+static inline void udma_rchanrt_update_bits(struct udma_rchan *rchan, int reg,
+ u32 mask, u32 val)
+{
+ if (!rchan)
+ return;
+ udma_update_bits(rchan->reg_rt, reg, mask, val);
+}
+
+static inline void udma_rflowrt_update_bits(struct udma_rflow *rflow, int reg,
+ u32 mask, u32 val)
+{
+ if (!rflow)
+ return;
+ udma_update_bits(rflow->reg_rflow, reg, mask, val);
+}
+
+// Function headers
+int udma_alloc_rx_resources(struct udma_chan *uc);
+int udma_alloc_tx_resources(struct udma_chan *uc);
+void udma_free_rx_resources(struct udma_chan *uc);
+void udma_free_tx_resources(struct udma_chan *uc);
+int udma_transfer(struct device *dev, int direction, dma_addr_t dst,
+ dma_addr_t src, size_t len);
+int udma_enable(struct dma *dma);
+int udma_disable(struct dma *dma);
+int udma_send(struct dma *dma, dma_addr_t src, size_t len, void *metadata);
+int udma_receive(struct dma *dma, dma_addr_t *dst, void *metadata);
+int udma_get_cfg(struct dma *dma, u32 id, void **data);
+int udma_prepare_rcv_buf(struct dma *dma, dma_addr_t dst, size_t size);
+int udma_of_xlate(struct dma *dma, struct of_phandle_args *args);
+
+int udma_alloc_tx_resources(struct udma_chan *uc);
+int udma_alloc_rx_resources(struct udma_chan *uc);
+void bcdma_free_bchan_resources(struct udma_chan *uc);
+int bcdma_alloc_bchan_resources(struct udma_chan *uc);
+
+void udma_stop_mem2dev(struct udma_chan *uc, bool sync);
+int udma_start(struct udma_chan *uc);
+void udma_reset_counters(struct udma_chan *uc);
+int udma_stop_hard(struct udma_chan *uc);
+int udma_stop(struct udma_chan *uc);
+bool udma_is_chan_running(struct udma_chan *uc);
+void udma_stop_dev2mem(struct udma_chan *uc, bool sync);
+void udma_reset_uchan(struct udma_chan *uc);
+void udma_reset_rings(struct udma_chan *uc);
+
+char *udma_get_dir_text(enum dma_transfer_direction dir);
+
+// Common macros
+#define K3_UDMA_MAX_RFLOWS 1024
+#define K3_UDMA_MAX_TR 2
+
+#endif // K3_UDMA_H
--
2.39.5
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 16/31] dma: ti: k3-udma-common: Update common code for AM62L DMAs
2025-05-28 11:45 [PATCH 00/31] ARM: K3: add support for AM62L Sascha Hauer
` (14 preceding siblings ...)
2025-05-28 11:45 ` [PATCH 15/31] dma: ti: k3-udma: Refactor common bits for AM62L support Sascha Hauer
@ 2025-05-28 11:45 ` Sascha Hauer
2025-05-28 11:45 ` [PATCH 17/31] dma: ti: k3-udma-am62l: Add AM62L support DMA drivers Sascha Hauer
` (14 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Sascha Hauer @ 2025-05-28 11:45 UTC (permalink / raw)
To: BAREBOX
Based on U-Boot downstream commit:
| commit 8679e1f2f3cb8de0b71e72e7538f5404f7abbd2b
| Author: Vignesh Raghavendra <vigneshr@ti.com>
| Date: Wed Feb 26 19:55:45 2025 +0530
|
| PENDING: dma: ti: k3-udma-common: Update common code for AM62L DMAs
|
| AM62L has a autopair mechanism to pair DMA and remote endpoints, and
| setup all the peer registers. So avoid accessing or setting up PEER
| registers for AM62L DMAs.
|
| Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/dma/ti/k3-udma-common.c | 80 +++++++++++++++++++++++++++++------------
drivers/dma/ti/k3-udma-hwdef.h | 7 ++++
2 files changed, 64 insertions(+), 23 deletions(-)
diff --git a/drivers/dma/ti/k3-udma-common.c b/drivers/dma/ti/k3-udma-common.c
index d2ef9cc7b83d7fe4c2845b78b05c3a0e640cc589..8661d148aa1324828a168edb5caa496bb7e6da45 100644
--- a/drivers/dma/ti/k3-udma-common.c
+++ b/drivers/dma/ti/k3-udma-common.c
@@ -211,20 +211,24 @@ int udma_start(struct udma_chan *uc)
dev_dbg(uc->ud->dev, "%s: chan:%d dir:%s\n",
__func__, uc->id, udma_get_dir_text(uc->config.dir));
- /* Make sure that we clear the teardown bit, if it is set */
- udma_stop_hard(uc);
- /* Reset all counters */
- udma_reset_counters(uc);
+ if (uc->ud->match_data->type < DMA_TYPE_BCDMA_V2) {
+ /* Make sure that we clear the teardown bit, if it is set */
+ udma_stop_hard(uc);
+ /* Reset all counters */
+ udma_reset_counters(uc);
+ }
switch (uc->config.dir) {
case DMA_DEV_TO_MEM:
- udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG,
- UDMA_CHAN_RT_CTL_EN);
+ udma_rchanrt_update_bits(uc->rchan, UDMA_RCHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN,
+ UDMA_CHAN_RT_CTL_EN);
/* Enable remote */
- udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG,
- UDMA_PEER_RT_EN_ENABLE);
+ if (uc->ud->match_data->type < DMA_TYPE_BCDMA_V2)
+ udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG,
+ UDMA_PEER_RT_EN_ENABLE);
dev_dbg(uc->ud->dev, "%s(rx): RT_CTL:0x%08x PEER RT_ENABLE:0x%08x\n",
__func__,
@@ -235,11 +239,13 @@ int udma_start(struct udma_chan *uc)
break;
case DMA_MEM_TO_DEV:
/* Enable remote */
- udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PEER_RT_EN_REG,
- UDMA_PEER_RT_EN_ENABLE);
+ if (uc->ud->match_data->type < DMA_TYPE_BCDMA_V2)
+ udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PEER_RT_EN_REG,
+ UDMA_PEER_RT_EN_ENABLE);
- udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG,
- UDMA_CHAN_RT_CTL_EN);
+ udma_tchanrt_update_bits(uc->tchan, UDMA_TCHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN,
+ UDMA_CHAN_RT_CTL_EN);
dev_dbg(uc->ud->dev, "%s(tx): RT_CTL:0x%08x PEER RT_ENABLE:0x%08x\n",
__func__,
@@ -269,9 +275,17 @@ void udma_stop_mem2dev(struct udma_chan *uc, bool sync)
int i = 0;
u32 val;
- udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG,
- UDMA_CHAN_RT_CTL_EN |
- UDMA_CHAN_RT_CTL_TDOWN);
+ if (uc->ud->match_data->type == DMA_TYPE_BCDMA_V2 ||
+ uc->ud->match_data->type == DMA_TYPE_PKTDMA_V2) {
+ udma_tchanrt_update_bits(uc->tchan, UDMA_TCHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN |
+ UDMA_CHAN_RT_CTL_TDOWN,
+ UDMA_CHAN_RT_CTL_TDOWN);
+ } else {
+ udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN |
+ UDMA_CHAN_RT_CTL_TDOWN);
+ }
val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_CTL_REG);
@@ -285,6 +299,12 @@ void udma_stop_mem2dev(struct udma_chan *uc, bool sync)
i++;
}
+ if (uc->ud->match_data->type == DMA_TYPE_BCDMA_V2 ||
+ uc->ud->match_data->type == DMA_TYPE_PKTDMA_V2) {
+ udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG, UDMA_CHAN_RT_CTL_PAIR_COMPLETE);
+ return;
+ }
+
val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PEER_RT_EN_REG);
if (val & UDMA_PEER_RT_EN_ENABLE)
dev_dbg(uc->ud->dev, "%s: peer not stopped TIMEOUT !\n", __func__);
@@ -295,9 +315,15 @@ void udma_stop_dev2mem(struct udma_chan *uc, bool sync)
int i = 0;
u32 val;
- udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG,
- UDMA_PEER_RT_EN_ENABLE |
- UDMA_PEER_RT_EN_TEARDOWN);
+ if (uc->ud->match_data->type == DMA_TYPE_BCDMA_V2 ||
+ uc->ud->match_data->type == DMA_TYPE_PKTDMA_V2)
+ udma_rchanrt_update_bits(uc->rchan, UDMA_RCHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN,
+ UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN);
+ else
+ udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG,
+ UDMA_PEER_RT_EN_ENABLE |
+ UDMA_PEER_RT_EN_TEARDOWN);
val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_CTL_REG);
@@ -311,6 +337,10 @@ void udma_stop_dev2mem(struct udma_chan *uc, bool sync)
i++;
}
+ if (uc->ud->match_data->type == DMA_TYPE_BCDMA_V2 ||
+ uc->ud->match_data->type == DMA_TYPE_PKTDMA_V2)
+ return;
+
val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG);
if (val & UDMA_PEER_RT_EN_ENABLE)
dev_dbg(uc->ud->dev, "%s: peer not stopped TIMEOUT !\n", __func__);
@@ -625,7 +655,10 @@ int udma_alloc_rx_resources(struct udma_chan *uc)
}
rflow = uc->rflow;
- if (ud->tflow_cnt) {
+
+ if (ud->match_data->type >= DMA_TYPE_BCDMA_V2) {
+ fd_ring_id = rflow->id;
+ } else if (ud->tflow_cnt) {
fd_ring_id = ud->tflow_cnt + rflow->id;
} else {
fd_ring_id = ud->bchan_cnt + ud->tchan_cnt + ud->echan_cnt +
@@ -838,9 +871,10 @@ int bcdma_alloc_bchan_resources(struct udma_chan *uc)
if (ret)
return ret;
- ret = k3_ringacc_request_rings_pair(ud->ringacc, uc->bchan->id, -1,
- &uc->bchan->t_ring,
- &uc->bchan->tc_ring);
+ ret = k3_ringacc_request_rings_pair(ud->ringacc,
+ ud->match_data->chan_cnt + uc->bchan->id,
+ -1, &uc->bchan->t_ring,
+ &uc->bchan->tc_ring);
if (ret) {
ret = -EBUSY;
goto err_ring;
@@ -1064,7 +1098,7 @@ int udma_of_xlate(struct dma *dma, struct of_phandle_args *args)
ucc->notdpkt = ep_config->notdpkt;
ucc->ep_type = ep_config->ep_type;
- if (ud->match_data->type == DMA_TYPE_PKTDMA &&
+ if (ud->match_data->type >= DMA_TYPE_PKTDMA &&
ep_config->mapped_channel_id >= 0) {
ucc->mapped_channel_id = ep_config->mapped_channel_id;
ucc->default_flow_id = ep_config->default_flow_id;
diff --git a/drivers/dma/ti/k3-udma-hwdef.h b/drivers/dma/ti/k3-udma-hwdef.h
index 3d6b4d10fff1156f5d0a0a8ae8d0c940b8060236..6fbbd88e75fc8ee737a36c9f573d99a4e0c77392 100644
--- a/drivers/dma/ti/k3-udma-hwdef.h
+++ b/drivers/dma/ti/k3-udma-hwdef.h
@@ -37,6 +37,8 @@
#define UDMA_RFLOW_REG(x) (UDMA_RFLOW_RF##x##_REG)
+#define UDMA_RX_FLOWRT_RFA 0x8
+
/* TX chan regs */
#define UDMA_TCHAN_TCFG_REG 0x0
#define UDMA_TCHAN_TCREDIT_REG 0x4
@@ -60,6 +62,7 @@
/* TX chan RT regs */
#define UDMA_TCHAN_RT_CTL_REG 0x0
+#define UDMA_TCHAN_RT_CFG_REG 0x4
#define UDMA_TCHAN_RT_SWTRIG_REG 0x8
#define UDMA_TCHAN_RT_STDATA_REG 0x80
@@ -79,6 +82,7 @@
/* RX chan RT regs */
#define UDMA_RCHAN_RT_CTL_REG 0x0
+#define UDMA_RCHAN_RT_CFG_REG 0x4
#define UDMA_RCHAN_RT_SWTRIG_REG 0x8
#define UDMA_RCHAN_RT_STDATA_REG 0x80
@@ -132,6 +136,9 @@
#define UDMA_CHAN_RT_CTL_TDOWN BIT(30)
#define UDMA_CHAN_RT_CTL_PAUSE BIT(29)
#define UDMA_CHAN_RT_CTL_FTDOWN BIT(28)
+#define UDMA_CHAN_RT_CTL_AUTOPAIR BIT(23)
+#define UDMA_CHAN_RT_CTL_PAIR_TIMEOUT BIT(17)
+#define UDMA_CHAN_RT_CTL_PAIR_COMPLETE BIT(16)
#define UDMA_CHAN_RT_CTL_ERROR BIT(0)
/* UDMA_TCHAN_RT_PEER_RT_EN_REG/UDMA_RCHAN_RT_PEER_RT_EN_REG (PSI-L: 0x408) */
--
2.39.5
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 17/31] dma: ti: k3-udma-am62l: Add AM62L support DMA drivers
2025-05-28 11:45 [PATCH 00/31] ARM: K3: add support for AM62L Sascha Hauer
` (15 preceding siblings ...)
2025-05-28 11:45 ` [PATCH 16/31] dma: ti: k3-udma-common: Update common code for AM62L DMAs Sascha Hauer
@ 2025-05-28 11:45 ` Sascha Hauer
2025-05-28 11:45 ` [PATCH 18/31] ARM: dts: am62l: Add ethernet ports Sascha Hauer
` (13 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Sascha Hauer @ 2025-05-28 11:45 UTC (permalink / raw)
To: BAREBOX
Based on U-Boot downstream commit:
| commit 63633a3ebdce1d0e6eba47a0af70779b773fd45b
| Author: Vignesh Raghavendra <vigneshr@ti.com>
| Date: Wed Feb 26 19:55:46 2025 +0530
|
| PENDING: dma: ti: k3-udma-am62l: Add AM62L support DMA drivers
|
| AM62L has newer version of AM62x DMA with few changes:
| - Has a flat 1:1 channel mapping
| - No dependency on DM firmware, with autopairing support for PSIL
| pairing
| - Aliased registers in RT region to configure channel / rings
|
| Add support for the same.
|
| Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/dma/ti/Makefile | 2 +-
drivers/dma/ti/k3-udma-am62l.c | 593 +++++++++++++++++++++++++++++++++++++++++
drivers/dma/ti/k3-udma.h | 2 +
3 files changed, 596 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile
index f841ad0cffaf086ffbf3b5775bfad776fa5c3d73..37e6e56bd17befbbb86da5f2a6cc4492d6dea205 100644
--- a/drivers/dma/ti/Makefile
+++ b/drivers/dma/ti/Makefile
@@ -1 +1 @@
-obj-$(CONFIG_TI_K3_UDMA) += k3-udma.o k3-udma-common.o k3-psil.o k3-psil-am62l.o
+obj-$(CONFIG_TI_K3_UDMA) += k3-udma.o k3-udma-common.o k3-psil.o k3-psil-am62l.o k3-udma-am62l.o
diff --git a/drivers/dma/ti/k3-udma-am62l.c b/drivers/dma/ti/k3-udma-am62l.c
new file mode 100644
index 0000000000000000000000000000000000000000..cd4a4cdf032fc377befac2de129e4b4c5a18e9b2
--- /dev/null
+++ b/drivers/dma/ti/k3-udma-am62l.c
@@ -0,0 +1,593 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com
+ */
+
+#include <io.h>
+#include <malloc.h>
+#include <stdio.h>
+#include <linux/bitops.h>
+#include <linux/sizes.h>
+#include <linux/printk.h>
+#include <dma.h>
+#include <soc/ti/ti-udma.h>
+#include <soc/ti/ti_sci_protocol.h>
+#include <dma-devices.h>
+#include <soc/ti/cppi5.h>
+#include <soc/ti/k3-navss-ringacc.h>
+#include <clock.h>
+#include <linux/bitmap.h>
+#include <driver.h>
+#include <linux/device.h>
+
+#include "k3-udma-hwdef.h"
+#include "k3-psil-priv.h"
+#include "k3-udma.h"
+
+enum am62l_udma_mmr {
+ AM62L_MMR_GCFG = 0,
+ AM62L_MMR_BCHANRT,
+ AM62L_MMR_CHANRT,
+ AM62L_MMR_RFLOWRT,
+ AM62L_MMR_LAST,
+};
+
+static const char * const am62l_mmr_names[] = {
+ [AM62L_MMR_GCFG] = "gcfg",
+ [AM62L_MMR_BCHANRT] = "bchanrt",
+ [AM62L_MMR_CHANRT] = "chanrt",
+ [AM62L_MMR_RFLOWRT] = "ringrt",
+};
+
+static int pktdma_v2_rx_channel_config(struct udma_chan *uc)
+{
+ u32 val = 0;
+
+ if (uc->config.needs_epib)
+ val |= UDMA_RFLOW_RFA_EINFO;
+ if (uc->config.psd_size)
+ val |= UDMA_RFLOW_RFA_PSINFO;
+
+ udma_rflowrt_write(uc->rflow, UDMA_RX_FLOWRT_RFA, val);
+
+ return 0;
+}
+
+static int bcdma_v2_alloc_chan_resources(struct udma_chan *uc)
+{
+ int ret;
+
+ uc->config.pkt_mode = false;
+
+ switch (uc->config.dir) {
+ case DMA_MEM_TO_MEM:
+ /* Non synchronized - mem to mem type of transfer */
+ dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-MEM\n", __func__,
+ uc->id);
+
+ ret = bcdma_alloc_bchan_resources(uc);
+ if (ret)
+ return ret;
+
+ break;
+ default:
+ /* Can not happen */
+ dev_err(uc->ud->dev, "%s: chan%d invalid direction (%u)\n",
+ __func__, uc->id, uc->config.dir);
+ return -EINVAL;
+ }
+
+ /* check if the channel configuration was successful */
+ if (ret)
+ goto err_res_free;
+
+ if (udma_is_chan_running(uc)) {
+ dev_warn(uc->ud->dev, "chan%d: is running!\n", uc->id);
+ udma_stop(uc);
+ if (udma_is_chan_running(uc)) {
+ dev_err(uc->ud->dev, "chan%d: won't stop!\n", uc->id);
+ goto err_res_free;
+ }
+ }
+
+ udma_reset_rings(uc);
+
+ return 0;
+
+err_res_free:
+ bcdma_free_bchan_resources(uc);
+ udma_free_tx_resources(uc);
+ udma_free_rx_resources(uc);
+
+ udma_reset_uchan(uc);
+
+ return ret;
+}
+
+static int pktdma_v2_alloc_chan_resources(struct udma_chan *uc)
+{
+ struct udma_dev *ud = uc->ud;
+ int ret;
+
+ switch (uc->config.dir) {
+ case DMA_MEM_TO_DEV:
+ /* Slave transfer synchronized - mem to dev (TX) trasnfer */
+ dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-DEV\n", __func__,
+ uc->id);
+
+ ret = udma_alloc_tx_resources(uc);
+ if (ret) {
+ uc->config.remote_thread_id = -1;
+ return ret;
+ }
+ break;
+ case DMA_DEV_TO_MEM:
+ /* Slave transfer synchronized - dev to mem (RX) trasnfer */
+ dev_dbg(uc->ud->dev, "%s: chan%d as DEV-to-MEM\n", __func__,
+ uc->id);
+
+ ret = udma_alloc_rx_resources(uc);
+ if (ret) {
+ uc->config.remote_thread_id = -1;
+ return ret;
+ }
+
+ ret = pktdma_v2_rx_channel_config(uc);
+ break;
+ default:
+ /* Can not happen */
+ dev_err(uc->ud->dev, "%s: chan%d invalid direction (%u)\n",
+ __func__, uc->id, uc->config.dir);
+ return -EINVAL;
+ }
+
+ /* check if the channel configuration was successful */
+ if (ret)
+ goto err_res_free;
+
+ if (uc->config.dir == DMA_DEV_TO_MEM)
+ udma_rchanrt_update_bits(uc->rchan, UDMA_RCHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_TDOWN | UDMA_CHAN_RT_CTL_AUTOPAIR,
+ UDMA_CHAN_RT_CTL_AUTOPAIR);
+ else if (uc->config.dir == DMA_MEM_TO_DEV)
+ udma_tchanrt_update_bits(uc->tchan, UDMA_TCHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_TDOWN | UDMA_CHAN_RT_CTL_AUTOPAIR,
+ UDMA_CHAN_RT_CTL_AUTOPAIR);
+
+ if (udma_is_chan_running(uc)) {
+ dev_warn(ud->dev, "chan%d: is running!\n", uc->id);
+ udma_stop(uc);
+ if (udma_is_chan_running(uc)) {
+ dev_err(ud->dev, "chan%d: won't stop!\n", uc->id);
+ goto err_res_free;
+ }
+ }
+
+ if (uc->tchan)
+ dev_dbg(ud->dev,
+ "chan%d: tchan%d, tflow%d, Remote thread: 0x%04x\n",
+ uc->id, uc->tchan->id, uc->tchan->tflow_id,
+ uc->config.remote_thread_id);
+ else if (uc->rchan)
+ dev_dbg(ud->dev,
+ "chan%d: rchan%d, rflow%d, Remote thread: 0x%04x\n",
+ uc->id, uc->rchan->id, uc->rflow->id,
+ uc->config.remote_thread_id);
+ return 0;
+
+err_res_free:
+ udma_free_tx_resources(uc);
+ udma_free_rx_resources(uc);
+
+ udma_reset_uchan(uc);
+
+ return ret;
+}
+
+static int am62l_udma_request(struct dma *dma)
+{
+ struct udma_dev *ud = dev_get_priv(dma->dev);
+ struct udma_chan_config *ucc;
+ struct udma_chan *uc;
+ int ret;
+
+ if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
+ dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
+ return -EINVAL;
+ }
+
+ uc = &ud->channels[dma->id];
+ ucc = &uc->config;
+ switch (ud->match_data->type) {
+ case DMA_TYPE_BCDMA_V2:
+ ret = bcdma_v2_alloc_chan_resources(uc);
+ break;
+ case DMA_TYPE_PKTDMA_V2:
+ ret = pktdma_v2_alloc_chan_resources(uc);
+ break;
+ default:
+ return -EINVAL;
+ }
+ if (ret) {
+ dev_err(dma->dev, "alloc dma res failed %d\n", ret);
+ return -EINVAL;
+ }
+
+ if (uc->config.dir == DMA_MEM_TO_DEV) {
+ uc->desc_tx = dma_alloc_coherent(DMA_DEVICE_BROKEN, ucc->hdesc_size, DMA_ADDRESS_BROKEN);
+ } else {
+ uc->desc_rx = dma_alloc_coherent(DMA_DEVICE_BROKEN,
+ ucc->hdesc_size * UDMA_RX_DESC_NUM, DMA_ADDRESS_BROKEN);
+ }
+
+ uc->in_use = true;
+ uc->desc_rx_cur = 0;
+ uc->num_rx_bufs = 0;
+
+ if (uc->config.dir == DMA_DEV_TO_MEM) {
+ uc->cfg_data.flow_id_base = uc->rflow->id;
+ uc->cfg_data.flow_id_cnt = 1;
+ }
+
+ return 0;
+}
+
+static int bcdma_v2_setup_resources(struct udma_dev *ud)
+{
+ struct device *dev = ud->dev;
+ size_t desc_size;
+
+ ud->bchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->bchan_cnt),
+ sizeof(unsigned long), GFP_KERNEL);
+ ud->bchans = devm_kcalloc(dev, ud->bchan_cnt, sizeof(*ud->bchans),
+ GFP_KERNEL);
+ ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
+ sizeof(unsigned long), GFP_KERNEL);
+ ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans),
+ GFP_KERNEL);
+ ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt),
+ sizeof(unsigned long), GFP_KERNEL);
+ ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans),
+ GFP_KERNEL);
+ ud->rflows = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rflows),
+ GFP_KERNEL);
+
+ desc_size = cppi5_trdesc_calc_size(K3_UDMA_MAX_TR,
+ sizeof(struct cppi5_tr_type15_t));
+ ud->bc_desc = devm_kzalloc(dev, ALIGN(desc_size, ARCH_DMA_MINALIGN), GFP_KERNEL);
+
+ if (!ud->bchan_map || !ud->tchan_map || !ud->rchan_map ||
+ !ud->bchans || !ud->tchans || !ud->rchans ||
+ !ud->rflows || !ud->bc_desc)
+ return -ENOMEM;
+
+ bitmap_zero(ud->bchan_map, ud->bchan_cnt);
+ bitmap_zero(ud->tchan_map, ud->tchan_cnt);
+ bitmap_zero(ud->rchan_map, ud->rchan_cnt);
+
+ return 0;
+}
+
+static int pktdma_v2_setup_resources(struct udma_dev *ud)
+{
+ struct device *dev = ud->dev;
+
+ ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
+ sizeof(unsigned long), GFP_KERNEL);
+ ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans),
+ GFP_KERNEL);
+ ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt),
+ sizeof(unsigned long), GFP_KERNEL);
+ ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans),
+ GFP_KERNEL);
+ ud->rflow_map = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt),
+ sizeof(unsigned long),
+ GFP_KERNEL);
+ ud->rflows = devm_kcalloc(dev, ud->rflow_cnt, sizeof(*ud->rflows),
+ GFP_KERNEL);
+ ud->tflow_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tflow_cnt),
+ sizeof(unsigned long), GFP_KERNEL);
+
+ if (!ud->tchan_map || !ud->rchan_map || !ud->tflow_map || !ud->tchans ||
+ !ud->rchans || !ud->rflows || !ud->rflow_map)
+ return -ENOMEM;
+
+ bitmap_zero(ud->bchan_map, ud->bchan_cnt);
+ bitmap_zero(ud->tchan_map, ud->tchan_cnt);
+ bitmap_zero(ud->rchan_map, ud->rchan_cnt);
+
+ return 0;
+}
+
+static int am62l_udma_setup_resources(struct udma_dev *ud)
+{
+ struct device *dev = ud->dev;
+ int ch_count, ret;
+
+ switch (ud->match_data->type) {
+ case DMA_TYPE_BCDMA_V2:
+ ret = bcdma_v2_setup_resources(ud);
+ break;
+ case DMA_TYPE_PKTDMA_V2:
+ ret = pktdma_v2_setup_resources(ud);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (ret)
+ return ret;
+
+ ch_count = ud->bchan_cnt + ud->tchan_cnt + ud->rchan_cnt;
+
+ ud->channels = devm_kcalloc(dev, ch_count, sizeof(*ud->channels),
+ GFP_KERNEL);
+ if (!ud->channels)
+ return -ENOMEM;
+
+ switch (ud->match_data->type) {
+ case DMA_TYPE_UDMA:
+ dev_dbg(dev,
+ "Channels: %d (tchan: %u, rchan: %u, gp-rflow: %u)\n",
+ ch_count, ud->tchan_cnt, ud->rchan_cnt, ud->rflow_cnt);
+ break;
+ case DMA_TYPE_BCDMA:
+ case DMA_TYPE_BCDMA_V2:
+ dev_dbg(dev,
+ "Channels: %d (bchan: %u, tchan: %u, rchan: %u)\n",
+ ch_count, ud->bchan_cnt, ud->tchan_cnt, ud->rchan_cnt);
+ break;
+ case DMA_TYPE_PKTDMA_V2:
+ dev_dbg(dev,
+ "Channels: %d (tchan: %u, rchan: %u)\n",
+ ch_count, ud->tchan_cnt, ud->rchan_cnt);
+ break;
+ default:
+ break;
+ }
+
+ return ch_count;
+}
+
+static int am62l_udma_get_mmrs(struct device *dev, struct udma_dev *ud)
+{
+ int i;
+
+ /* There are no tchan and rchan in BCDMA_V2 and PKTDMA_V2.
+ * Duplicate chan as tchan and rchan to keep the common code
+ * in k3-udma-common.c functional.
+ */
+ if (ud->match_data->type == DMA_TYPE_BCDMA_V2) {
+ ud->bchan_cnt = ud->match_data->bchan_cnt;
+ ud->chan_cnt = ud->match_data->chan_cnt;
+ ud->tchan_cnt = ud->match_data->chan_cnt;
+ ud->rchan_cnt = ud->match_data->chan_cnt;
+ ud->rflow_cnt = ud->chan_cnt;
+ } else if (ud->match_data->type == DMA_TYPE_PKTDMA_V2) {
+ ud->chan_cnt = ud->match_data->chan_cnt;
+ ud->tchan_cnt = ud->match_data->tchan_cnt;
+ ud->rchan_cnt = ud->match_data->rchan_cnt;
+ ud->rflow_cnt = ud->match_data->rflow_cnt;
+ }
+
+ for (i = 1; i < AM62L_MMR_LAST; i++) {
+ if (i == AM62L_MMR_BCHANRT && ud->bchan_cnt == 0)
+ continue;
+ if (i == AM62L_MMR_CHANRT && ud->chan_cnt == 0)
+ continue;
+
+ ud->mmrs[i] = dev_request_mem_region_by_name(ud->dev, am62l_mmr_names[i]);
+ if (IS_ERR(ud->mmrs[i]))
+ return PTR_ERR(ud->mmrs[i]);
+ }
+
+ return 0;
+}
+
+static int am62l_udma_rfree(struct dma *dma)
+{
+ struct udma_dev *ud = dev_get_priv(dma->dev);
+ struct udma_chan *uc;
+
+ if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
+ dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
+ return -EINVAL;
+ }
+ uc = &ud->channels[dma->id];
+
+ if (udma_is_chan_running(uc))
+ udma_stop(uc);
+
+ bcdma_free_bchan_resources(uc);
+ udma_free_tx_resources(uc);
+ udma_free_rx_resources(uc);
+ udma_reset_uchan(uc);
+
+ uc->in_use = false;
+
+ return 0;
+}
+
+static const struct dma_ops am62l_udma_ops = {
+ .transfer = udma_transfer,
+ .of_xlate = udma_of_xlate,
+ .request = am62l_udma_request,
+ .rfree = am62l_udma_rfree,
+ .enable = udma_enable,
+ .disable = udma_disable,
+ .send = udma_send,
+ .receive = udma_receive,
+ .prepare_rcv_buf = udma_prepare_rcv_buf,
+ .get_cfg = udma_get_cfg,
+};
+
+static int k3_udma_am62l_probe(struct device *dev)
+{
+ struct udma_dev *ud;
+ struct udma_chan *uc;
+ int i, ret;
+ struct k3_ringacc_init_data ring_init_data = { 0 };
+ const struct udma_match_data *match_data;
+ struct dma_device *dmad;
+
+ match_data = device_get_match_data(dev);
+
+ ud = xzalloc(sizeof(*ud));
+ ud->match_data = match_data;
+ ud->dev = dev;
+
+ dev->priv = ud;
+
+ ret = am62l_udma_get_mmrs(dev, ud);
+ if (ret)
+ return ret;
+
+ if (ud->match_data->type == DMA_TYPE_BCDMA_V2)
+ ring_init_data.num_rings = ud->bchan_cnt + ud->chan_cnt;
+ else if (ud->match_data->type == DMA_TYPE_PKTDMA_V2)
+ ring_init_data.num_rings = ud->rflow_cnt;
+
+ ring_init_data.base_rt = ud->mmrs[AM62L_MMR_RFLOWRT];
+
+ ud->ringacc = k3_ringacc_dmarings_init(dev, &ring_init_data);
+ if (IS_ERR(ud->ringacc))
+ return PTR_ERR(ud->ringacc);
+
+ ret = am62l_udma_setup_resources(ud);
+ if (ret < 0)
+ return ret;
+
+ ud->ch_count = ret;
+
+ for (i = 0; i < ud->bchan_cnt; i++) {
+ struct udma_bchan *bchan = &ud->bchans[i];
+
+ bchan->id = i;
+ bchan->reg_rt = ud->mmrs[AM62L_MMR_BCHANRT] + i * 0x1000;
+ }
+
+ for (i = 0; i < ud->tchan_cnt; i++) {
+ struct udma_tchan *tchan = &ud->tchans[i];
+
+ tchan->id = i;
+ tchan->reg_rt = ud->mmrs[AM62L_MMR_CHANRT] + UDMA_CH_1000(i);
+ tchan->reg_chan = tchan->reg_rt + 0x4;
+ }
+
+ for (i = 0; i < ud->rchan_cnt; i++) {
+ struct udma_rchan *rchan = &ud->rchans[i];
+
+ rchan->id = i;
+ rchan->reg_rt = ud->mmrs[AM62L_MMR_CHANRT] + UDMA_CH_1000(i);
+ rchan->reg_chan = rchan->reg_rt + 0x4;
+ }
+
+ for (i = 0; i < ud->rflow_cnt; i++) {
+ struct udma_rflow *rflow = &ud->rflows[i];
+
+ rflow->id = i;
+ rflow->reg_rt = ud->mmrs[AM62L_MMR_RFLOWRT] + UDMA_CH_1000(2 * i);
+ rflow->reg_rflow = rflow->reg_rt;
+ }
+
+ for (i = 0; i < ud->ch_count; i++) {
+ struct udma_chan *uc = &ud->channels[i];
+
+ uc->ud = ud;
+ uc->id = i;
+ uc->config.remote_thread_id = -1;
+ uc->bchan = NULL;
+ uc->tchan = NULL;
+ uc->rchan = NULL;
+ uc->config.mapped_channel_id = -1;
+ uc->config.default_flow_id = -1;
+ uc->config.dir = DMA_MEM_TO_MEM;
+ sprintf(uc->name, "UDMA chan%d\n", i);
+ if (!i)
+ uc->in_use = true;
+ }
+
+ uc = &ud->channels[0];
+ ret = 0;
+ switch (ud->match_data->type) {
+ case DMA_TYPE_BCDMA_V2:
+ ret = bcdma_v2_alloc_chan_resources(uc);
+ break;
+ default:
+ break; /* Do nothing in any other case */
+ };
+
+ if (ret) {
+ dev_err(dev, " Channel 0 allocation failure %d\n", ret);
+ return ret;
+ }
+
+ dmad = &ud->dmad;
+
+ dmad->dev = dev;
+ dmad->ops = &am62l_udma_ops;
+
+ ret = dma_device_register(dmad);
+
+ return ret;
+}
+
+static void am62l_udma_remove(struct device *dev)
+{
+ struct udma_dev *ud = dev_get_priv(dev);
+ struct udma_chan *uc = &ud->channels[0];
+
+ switch (ud->match_data->type) {
+ case DMA_TYPE_BCDMA_V2:
+ bcdma_free_bchan_resources(uc);
+ break;
+ default:
+ break;
+ };
+}
+
+static struct udma_match_data am62l_bcdma_data = {
+ .type = DMA_TYPE_BCDMA_V2,
+ .psil_base = 0x2000, /* for tchan and rchan, not applicable to bchan */
+ .enable_memcpy_support = true, /* Supported via bchan */
+ .flags = UDMA_FLAG_PDMA_ACC32 | UDMA_FLAG_PDMA_BURST | UDMA_FLAG_TDTYPE,
+ .statictr_z_mask = GENMASK(23, 0),
+ .bchan_cnt = 16,
+ .chan_cnt = 128,
+ .tchan_cnt = 128,
+ .rchan_cnt = 128,
+};
+
+static struct udma_match_data am62l_pktdma_data = {
+ .type = DMA_TYPE_PKTDMA_V2,
+ .psil_base = 0x1000,
+ .enable_memcpy_support = false,
+ .flags = UDMA_FLAG_PDMA_ACC32 | UDMA_FLAG_PDMA_BURST | UDMA_FLAG_TDTYPE,
+ .statictr_z_mask = GENMASK(23, 0),
+ .tchan_cnt = 97,
+ .rchan_cnt = 97,
+ .chan_cnt = 97,
+ .tflow_cnt = 112,
+ .rflow_cnt = 112,
+};
+
+static struct of_device_id k3_udma_am62l_dt_ids[] = {
+ {
+ .compatible = "ti,am62l-dmss-bcdma",
+ .data = &am62l_bcdma_data,
+ }, {
+ .compatible = "ti,am62l-dmss-pktdma",
+ .data = &am62l_pktdma_data,
+ }, {
+ /* Sentinel */
+ },
+};
+
+static struct driver k3_udma_am62l_driver = {
+ .probe = k3_udma_am62l_probe,
+ .remove = am62l_udma_remove,
+ .name = "k3-udma-am62l",
+ .of_compatible = k3_udma_am62l_dt_ids,
+};
+
+core_platform_driver(k3_udma_am62l_driver);
diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h
index 88325160841886af5514ae2385400e2b4156bb07..0abbb478ddb4d999cfdfc317924c4a9f2116a11d 100644
--- a/drivers/dma/ti/k3-udma.h
+++ b/drivers/dma/ti/k3-udma.h
@@ -143,6 +143,7 @@ struct udma_dev {
int rchan_cnt;
int rflow_cnt;
int tflow_cnt;
+ int chan_cnt;
unsigned long *bchan_map;
unsigned long *tchan_map;
unsigned long *rchan_map;
@@ -156,6 +157,7 @@ struct udma_dev {
struct udma_rflow *rflows;
const struct udma_match_data *match_data;
+ void *bc_desc;
struct udma_chan *channels;
u32 psil_base;
--
2.39.5
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 18/31] ARM: dts: am62l: Add ethernet ports
2025-05-28 11:45 [PATCH 00/31] ARM: K3: add support for AM62L Sascha Hauer
` (16 preceding siblings ...)
2025-05-28 11:45 ` [PATCH 17/31] dma: ti: k3-udma-am62l: Add AM62L support DMA drivers Sascha Hauer
@ 2025-05-28 11:45 ` Sascha Hauer
2025-05-28 11:45 ` [PATCH 19/31] ARM: dts: am62l evm: " Sascha Hauer
` (12 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Sascha Hauer @ 2025-05-28 11:45 UTC (permalink / raw)
To: BAREBOX
The AM62l device trees are based on the upstream submission which
currently lack the ethernet ports. Add them from the downstream Linux
repository.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/dts/k3-am62l-main.dtsi | 95 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 95 insertions(+)
diff --git a/arch/arm/dts/k3-am62l-main.dtsi b/arch/arm/dts/k3-am62l-main.dtsi
index d161df3215c35a2d3de67e8ca021b9a9a89edb80..95d387afd14e4f85df022673b8100830cbc6c410 100644
--- a/arch/arm/dts/k3-am62l-main.dtsi
+++ b/arch/arm/dts/k3-am62l-main.dtsi
@@ -670,4 +670,99 @@ scmi_shmem: sram@0 {
reg = <0x0 0x100>;
};
};
+
+ main_pktdma: dma-controller@485c0000 {
+ compatible = "ti,am62l-dmss-pktdma";
+ reg = <0x00 0x485c0000 0x00 0x4000>,
+ <0x00 0x48900000 0x00 0x80000>,
+ <0x00 0x47200000 0x00 0x100000>;
+ reg-names = "gcfg", "chanrt", "ringrt";
+ #address-cells = <2>;
+ #dma-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map = <0 0 0 &gic500 0 0 GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 1 &gic500 0 0 GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 2 &gic500 0 0 GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 3 &gic500 0 0 GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 4 &gic500 0 0 GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 5 &gic500 0 0 GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 6 &gic500 0 0 GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 7 &gic500 0 0 GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 8 &gic500 0 0 GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 9 &gic500 0 0 GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 10 &gic500 0 0 GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 11 &gic500 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 12 &gic500 0 0 GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 13 &gic500 0 0 GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 64 &gic500 0 0 GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 65 &gic500 0 0 GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 66 &gic500 0 0 GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 67 &gic500 0 0 GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 68 &gic500 0 0 GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 69 &gic500 0 0 GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 70 &gic500 0 0 GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 71 &gic500 0 0 GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 72 &gic500 0 0 GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 73 &gic500 0 0 GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 74 &gic500 0 0 GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 75 &gic500 0 0 GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 76 &gic500 0 0 GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 77 &gic500 0 0 GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 78 &gic500 0 0 GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 79 &gic500 0 0 GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 96 &gic500 0 0 GIC_SPI 484 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ cpsw3g: ethernet@8000000 {
+ compatible = "ti,am642-cpsw-nuss";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x00 0x08000000 0x00 0x200000>;
+ reg-names = "cpsw_nuss";
+ ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>;
+ clocks = <&scmi_clk 9>;
+ clock-names = "fck";
+ power-domains = <&scmi_pds 3>;
+ dmas = <&main_pktdma 0xc600 15>,
+ <&main_pktdma 0xc601 15>,
+ <&main_pktdma 0xc602 15>,
+ <&main_pktdma 0xc603 15>,
+ <&main_pktdma 0xc604 15>,
+ <&main_pktdma 0xc605 15>,
+ <&main_pktdma 0xc606 15>,
+ <&main_pktdma 0xc607 15>,
+ <&main_pktdma 0x4600 15>;
+ dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
+ "tx7", "rx";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpsw_port1: port@1 {
+ reg = <1>;
+ ti,mac-only;
+ label = "port1";
+ phys = <&phy_gmii_sel 1>;
+ };
+
+ cpsw_port2: port@2 {
+ reg = <2>;
+ ti,mac-only;
+ label = "port2";
+ phys = <&phy_gmii_sel 2>;
+ };
+ };
+
+ cpsw3g_mdio: mdio@f00 {
+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+ reg = <0x00 0xf00 0x00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&scmi_clk 13 0>;
+ clock-names = "fck";
+ bus_freq = <1000000>;
+ status = "disabled";
+ };
+ };
};
--
2.39.5
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 19/31] ARM: dts: am62l evm: Add ethernet ports
2025-05-28 11:45 [PATCH 00/31] ARM: K3: add support for AM62L Sascha Hauer
` (17 preceding siblings ...)
2025-05-28 11:45 ` [PATCH 18/31] ARM: dts: am62l: Add ethernet ports Sascha Hauer
@ 2025-05-28 11:45 ` Sascha Hauer
2025-05-28 11:45 ` [PATCH 20/31] ARM: k3: am62l: add barebox specific am62l.dtsi Sascha Hauer
` (11 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Sascha Hauer @ 2025-05-28 11:45 UTC (permalink / raw)
To: BAREBOX
The AM62l device trees are based on the upstream submission which
currently lack the ethernet ports. Add them from the downstream Linux
repository.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/dts/k3-am62l3-evm.dts | 78 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 78 insertions(+)
diff --git a/arch/arm/dts/k3-am62l3-evm.dts b/arch/arm/dts/k3-am62l3-evm.dts
index 16efb60bf326018cd483cdeae35ed9538d24d522..4484279e8fcc0361fe73bf42b63a0663b71725b7 100644
--- a/arch/arm/dts/k3-am62l3-evm.dts
+++ b/arch/arm/dts/k3-am62l3-evm.dts
@@ -12,6 +12,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
+#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am62l3.dtsi"
#include "k3-pinctrl.h"
@@ -105,6 +106,42 @@ eeprom@51 {
};
};
+&cpsw3g {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii1_pins_default>,
+ <&rgmii2_pins_default>;
+};
+
+&cpsw_port1 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&cpsw3g_phy0>;
+};
+
+&cpsw_port2 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&cpsw3g_phy1>;
+};
+
+&cpsw3g_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio1_pins_default>;
+ status = "okay";
+
+ cpsw3g_phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,min-output-impedance;
+ };
+
+ cpsw3g_phy1: ethernet-phy@1 {
+ reg = <1>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,min-output-impedance;
+ };
+};
+
&i2c1 {
pinctrl-0 = <&i2c1_pins_default>;
pinctrl-names = "default";
@@ -201,6 +238,47 @@ AM62LX_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (B4) MMC0_DAT7 */
bootph-all;
};
+ rgmii1_pins_default: rgmii1-default-pins {
+ pinctrl-single,pins = <
+ AM62LX_IOPAD(0x0138, PIN_INPUT, 0) /* (Y8) RGMII1_RD0 */
+ AM62LX_IOPAD(0x013c, PIN_INPUT, 0) /* (AA6) RGMII1_RD1 */
+ AM62LX_IOPAD(0x0140, PIN_INPUT, 0) /* (AA8) RGMII1_RD2 */
+ AM62LX_IOPAD(0x0144, PIN_INPUT, 0) /* (W8) RGMII1_RD3 */
+ AM62LX_IOPAD(0x0134, PIN_INPUT, 0) /* (Y7) RGMII1_RXC */
+ AM62LX_IOPAD(0x0130, PIN_INPUT, 0) /* (Y6) RGMII1_RX_CTL */
+ AM62LX_IOPAD(0x0120, PIN_OUTPUT, 0) /* (AC10) RGMII1_TD0 */
+ AM62LX_IOPAD(0x0124, PIN_OUTPUT, 0) /* (W13) RGMII1_TD1 */
+ AM62LX_IOPAD(0x0128, PIN_OUTPUT, 0) /* (Y11) RGMII1_TD2 */
+ AM62LX_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AA11) RGMII1_TD3 */
+ AM62LX_IOPAD(0x011c, PIN_OUTPUT, 0) /* (W11) RGMII1_TXC */
+ AM62LX_IOPAD(0x0118, PIN_OUTPUT, 0) /* (AB11) RGMII1_TX_CTL */
+ >;
+ };
+
+ rgmii2_pins_default: rgmii2-default-pins {
+ pinctrl-single,pins = <
+ AM62LX_IOPAD(0x0170, PIN_INPUT, 0) /* (AB9) RGMII2_RD0 */
+ AM62LX_IOPAD(0x0174, PIN_INPUT, 0) /* (AC9) RGMII2_RD1 */
+ AM62LX_IOPAD(0x0178, PIN_INPUT, 0) /* (AB10) RGMII2_RD2 */
+ AM62LX_IOPAD(0x017c, PIN_INPUT, 0) /* (AB8) RGMII2_RD3 */
+ AM62LX_IOPAD(0x016c, PIN_INPUT, 0) /* (AC7) RGMII2_RXC */
+ AM62LX_IOPAD(0x0168, PIN_INPUT, 0) /* (AC8) RGMII2_RX_CTL */
+ AM62LX_IOPAD(0x0158, PIN_OUTPUT, 0) /* (AC12) RGMII2_TD0 */
+ AM62LX_IOPAD(0x015c, PIN_OUTPUT, 0) /* (AB13) RGMII2_TD1 */
+ AM62LX_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AA12) RGMII2_TD2 */
+ AM62LX_IOPAD(0x0164, PIN_OUTPUT, 0) /* (AA13) RGMII2_TD3 */
+ AM62LX_IOPAD(0x0154, PIN_OUTPUT, 0) /* (Y13) RGMII2_TXC */
+ AM62LX_IOPAD(0x0150, PIN_OUTPUT, 0) /* (AB12) RGMII2_TX_CTL */
+ >;
+ };
+
+ mdio1_pins_default: mdio1-default-pins {
+ pinctrl-single,pins = <
+ AM62LX_IOPAD(0x014c, PIN_OUTPUT, 0) /* (AC15) MDIO0_MDC */
+ AM62LX_IOPAD(0x0148, PIN_INPUT, 0) /* (AC13) MDIO0_MDIO */
+ >;
+ };
+
mmc1_pins_default: mmc1-default-pins {
pinctrl-single,pins = <
AM62LX_IOPAD(0x0230, PIN_INPUT, 0) /* (Y3) MMC1_CMD */
--
2.39.5
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 20/31] ARM: k3: am62l: add barebox specific am62l.dtsi
2025-05-28 11:45 [PATCH 00/31] ARM: K3: add support for AM62L Sascha Hauer
` (18 preceding siblings ...)
2025-05-28 11:45 ` [PATCH 19/31] ARM: dts: am62l evm: " Sascha Hauer
@ 2025-05-28 11:45 ` Sascha Hauer
2025-05-28 11:45 ` [PATCH 21/31] net: davinci_mdio: Use fallback clock rate Sascha Hauer
` (10 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Sascha Hauer @ 2025-05-28 11:45 UTC (permalink / raw)
To: BAREBOX
Some adjustments to the AM62l dtsi files: Enable gpio ports by default
and add a syscon compatible to the phy_gmii_sel node which is needed for
the ethernet driver to access it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/dts/k3-am62l-barebox.dtsi | 16 ++++++++++++++++
arch/arm/dts/k3-am62l3-evm.dts | 1 +
2 files changed, 17 insertions(+)
diff --git a/arch/arm/dts/k3-am62l-barebox.dtsi b/arch/arm/dts/k3-am62l-barebox.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..9fe44a67ee7374e6c6d9052dc8ea0f31d2e8f4a1
--- /dev/null
+++ b/arch/arm/dts/k3-am62l-barebox.dtsi
@@ -0,0 +1,16 @@
+
+&phy_gmii_sel {
+ compatible = "ti,am654-phy-gmii-sel", "syscon";
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
+&wkup_gpio0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/k3-am62l3-evm.dts b/arch/arm/dts/k3-am62l3-evm.dts
index 4484279e8fcc0361fe73bf42b63a0663b71725b7..7b528ae1e41e92bc9aa1428e86d5141d30fe7cd7 100644
--- a/arch/arm/dts/k3-am62l3-evm.dts
+++ b/arch/arm/dts/k3-am62l3-evm.dts
@@ -15,6 +15,7 @@
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am62l3.dtsi"
+#include "k3-am62l-barebox.dtsi"
#include "k3-pinctrl.h"
/ {
--
2.39.5
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 21/31] net: davinci_mdio: Use fallback clock rate
2025-05-28 11:45 [PATCH 00/31] ARM: K3: add support for AM62L Sascha Hauer
` (19 preceding siblings ...)
2025-05-28 11:45 ` [PATCH 20/31] ARM: k3: am62l: add barebox specific am62l.dtsi Sascha Hauer
@ 2025-05-28 11:45 ` Sascha Hauer
2025-05-28 11:45 ` [PATCH 22/31] firmware: arm_scmi: Add support for clock parents Sascha Hauer
` (9 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Sascha Hauer @ 2025-05-28 11:45 UTC (permalink / raw)
To: BAREBOX
On AM62L There is a clock attached to the mdio block, but the TF-A
returns 0 for its rate. Use 256MHz as fallback rate when we don't find a
valid clock rate.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/net/davinci_mdio.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/net/davinci_mdio.c b/drivers/net/davinci_mdio.c
index 1186642e1337b603f541f6bdf19ac2d2792f4994..ca7cecd2c08488cfa7a12d9cf8947e27722b916c 100644
--- a/drivers/net/davinci_mdio.c
+++ b/drivers/net/davinci_mdio.c
@@ -112,17 +112,18 @@ static int cpsw_mdio_write(struct mii_bus *bus, int phy_id, int phy_reg, u16 val
static void cpsw_mdio_init_clk(struct cpsw_mdio_priv *priv)
{
- u32 mdio_in, clk_div;
+ u32 mdio_in = 0, clk_div;
u32 bus_freq = 1000000;
of_property_read_u32(priv->dev->of_node, "bus_freq", &bus_freq);
priv->clk = clk_get_enabled(priv->dev, "fck");
- if (IS_ERR(priv->clk))
- mdio_in = 256000000;
- else
+ if (!IS_ERR(priv->clk))
mdio_in = clk_get_rate(priv->clk);
+ if (mdio_in == 0)
+ mdio_in = 256000000;
+
clk_div = (mdio_in / bus_freq) - 1;
if (clk_div > CONTROL_MAX_DIV)
clk_div = CONTROL_MAX_DIV;
--
2.39.5
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 22/31] firmware: arm_scmi: Add support for clock parents
2025-05-28 11:45 [PATCH 00/31] ARM: K3: add support for AM62L Sascha Hauer
` (20 preceding siblings ...)
2025-05-28 11:45 ` [PATCH 21/31] net: davinci_mdio: Use fallback clock rate Sascha Hauer
@ 2025-05-28 11:45 ` Sascha Hauer
2025-05-28 11:45 ` [PATCH 23/31] clk: add struct clk_parent_data Sascha Hauer
` (8 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Sascha Hauer @ 2025-05-28 11:45 UTC (permalink / raw)
To: BAREBOX
Based on Linux commit:
| commit 77bbfe607b1d306c88bf96fed00c030f6bf462f1
| Author: Peng Fan <peng.fan@nxp.com>
| Date: Wed Oct 4 07:42:23 2023 +0800
|
| firmware: arm_scmi: Add support for clock parents
|
| SCMI v3.2 spec introduces CLOCK_POSSIBLE_PARENTS_GET, CLOCK_PARENT_SET
| and CLOCK_PARENT_GET. Add support for these to enable clock parents
| and use them in the clock driver.
|
| Reviewed-by: Cristian Marussi <cristian.marussi@arm.com>
| Signed-off-by: Peng Fan <peng.fan@nxp.com>
| Link: https://lore.kernel.org/r/20231004-scmi-clock-v3-v5-1-1b8a1435673e@nxp.com
| Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/firmware/arm_scmi/clock.c | 179 ++++++++++++++++++++++++++++++++++++--
include/linux/scmi_protocol.h | 6 ++
2 files changed, 179 insertions(+), 6 deletions(-)
diff --git a/drivers/firmware/arm_scmi/clock.c b/drivers/firmware/arm_scmi/clock.c
index 2c902835a0ecbfdf5513fd188f7f2b84ddb65cfc..6b8ef9321db6f799f2c47c3748fe64e0781f6396 100644
--- a/drivers/firmware/arm_scmi/clock.c
+++ b/drivers/firmware/arm_scmi/clock.c
@@ -17,6 +17,9 @@ enum scmi_clock_protocol_cmd {
CLOCK_RATE_GET = 0x6,
CLOCK_CONFIG_SET = 0x7,
CLOCK_NAME_GET = 0x8,
+ CLOCK_POSSIBLE_PARENTS_GET = 0xC,
+ CLOCK_PARENT_SET = 0xD,
+ CLOCK_PARENT_GET = 0xE,
};
struct scmi_msg_resp_clock_protocol_attributes {
@@ -29,10 +32,28 @@ struct scmi_msg_resp_clock_attributes {
__le32 attributes;
#define CLOCK_ENABLE BIT(0)
#define SUPPORTS_EXTENDED_NAMES(x) ((x) & BIT(29))
+#define SUPPORTS_PARENT_CLOCK(x) ((x) & BIT(28))
u8 name[SCMI_SHORT_NAME_MAX_SIZE];
__le32 clock_enable_latency;
};
+struct scmi_msg_clock_possible_parents {
+ __le32 id;
+ __le32 skip_parents;
+};
+
+struct scmi_msg_resp_clock_possible_parents {
+ __le32 num_parent_flags;
+#define NUM_PARENTS_RETURNED(x) ((x) & 0xff)
+#define NUM_PARENTS_REMAINING(x) ((x) >> 24)
+ __le32 possible_parents[];
+};
+
+struct scmi_msg_clock_set_parent {
+ __le32 id;
+ __le32 parent_id;
+};
+
struct scmi_clock_set_config {
__le32 id;
__le32 attributes;
@@ -105,6 +126,98 @@ scmi_clock_protocol_attributes_get(const struct scmi_protocol_handle *ph,
return ret;
}
+struct scmi_clk_ipriv {
+ struct device *dev;
+ u32 clk_id;
+ struct scmi_clock_info *clk;
+};
+
+static void iter_clk_possible_parents_prepare_message(void *message, unsigned int desc_index,
+ const void *priv)
+{
+ struct scmi_msg_clock_possible_parents *msg = message;
+ const struct scmi_clk_ipriv *p = priv;
+
+ msg->id = cpu_to_le32(p->clk_id);
+ /* Set the number of OPPs to be skipped/already read */
+ msg->skip_parents = cpu_to_le32(desc_index);
+}
+
+static int iter_clk_possible_parents_update_state(struct scmi_iterator_state *st,
+ const void *response, void *priv)
+{
+ const struct scmi_msg_resp_clock_possible_parents *r = response;
+ struct scmi_clk_ipriv *p = priv;
+ struct device *dev = ((struct scmi_clk_ipriv *)p)->dev;
+ u32 flags;
+
+ flags = le32_to_cpu(r->num_parent_flags);
+ st->num_returned = NUM_PARENTS_RETURNED(flags);
+ st->num_remaining = NUM_PARENTS_REMAINING(flags);
+
+ /*
+ * num parents is not declared previously anywhere so we
+ * assume it's returned+remaining on first call.
+ */
+ if (!st->max_resources) {
+ p->clk->num_parents = st->num_returned + st->num_remaining;
+ p->clk->parents = devm_kcalloc(dev, p->clk->num_parents,
+ sizeof(*p->clk->parents),
+ GFP_KERNEL);
+ if (!p->clk->parents) {
+ p->clk->num_parents = 0;
+ return -ENOMEM;
+ }
+ st->max_resources = st->num_returned + st->num_remaining;
+ }
+
+ return 0;
+}
+
+static int iter_clk_possible_parents_process_response(const struct scmi_protocol_handle *ph,
+ const void *response,
+ struct scmi_iterator_state *st,
+ void *priv)
+{
+ const struct scmi_msg_resp_clock_possible_parents *r = response;
+ struct scmi_clk_ipriv *p = priv;
+
+ u32 *parent = &p->clk->parents[st->desc_index + st->loop_idx];
+
+ *parent = le32_to_cpu(r->possible_parents[st->loop_idx]);
+
+ return 0;
+}
+
+static int scmi_clock_possible_parents(const struct scmi_protocol_handle *ph, u32 clk_id,
+ struct scmi_clock_info *clk)
+{
+ struct scmi_iterator_ops ops = {
+ .prepare_message = iter_clk_possible_parents_prepare_message,
+ .update_state = iter_clk_possible_parents_update_state,
+ .process_response = iter_clk_possible_parents_process_response,
+ };
+
+ struct scmi_clk_ipriv ppriv = {
+ .clk_id = clk_id,
+ .clk = clk,
+ .dev = ph->dev,
+ };
+ void *iter;
+ int ret;
+
+ iter = ph->hops->iter_response_init(ph, &ops, 0,
+ CLOCK_POSSIBLE_PARENTS_GET,
+ sizeof(struct scmi_msg_clock_possible_parents),
+ &ppriv);
+ if (IS_ERR(iter))
+ return PTR_ERR(iter);
+
+ ret = ph->hops->iter_response_run(iter);
+
+ return ret;
+}
+
static int scmi_clock_attributes_get(const struct scmi_protocol_handle *ph,
u32 clk_id, struct scmi_clock_info *clk,
u32 version)
@@ -145,6 +258,8 @@ static int scmi_clock_attributes_get(const struct scmi_protocol_handle *ph,
clk->name,
SCMI_MAX_STR_SIZE);
+ if (SUPPORTS_PARENT_CLOCK(attributes))
+ scmi_clock_possible_parents(ph, clk_id, clk);
}
return ret;
@@ -162,12 +277,6 @@ static int rate_cmp_func(const void *_r1, const void *_r2)
return 1;
}
-struct scmi_clk_ipriv {
- struct device *dev;
- u32 clk_id;
- struct scmi_clock_info *clk;
-};
-
static void iter_clk_describe_prepare_message(void *message,
const unsigned int desc_index,
const void *priv)
@@ -406,6 +515,62 @@ scmi_clock_info_get(const struct scmi_protocol_handle *ph, u32 clk_id)
return clk;
}
+static int
+scmi_clock_set_parent(const struct scmi_protocol_handle *ph, u32 clk_id,
+ u32 parent_id)
+{
+ int ret;
+ struct scmi_xfer *t;
+ struct scmi_msg_clock_set_parent *cfg;
+ struct clock_info *ci = ph->get_priv(ph);
+ struct scmi_clock_info *clk;
+
+ if (clk_id >= ci->num_clocks)
+ return -EINVAL;
+
+ clk = ci->clk + clk_id;
+
+ if (parent_id >= clk->num_parents)
+ return -EINVAL;
+
+ ret = ph->xops->xfer_get_init(ph, CLOCK_PARENT_SET,
+ sizeof(*cfg), 0, &t);
+ if (ret)
+ return ret;
+
+ cfg = t->tx.buf;
+ cfg->id = cpu_to_le32(clk_id);
+ cfg->parent_id = cpu_to_le32(clk->parents[parent_id]);
+
+ ret = ph->xops->do_xfer(ph, t);
+
+ ph->xops->xfer_put(ph, t);
+
+ return ret;
+}
+
+static int
+scmi_clock_get_parent(const struct scmi_protocol_handle *ph, u32 clk_id,
+ u32 *parent_id)
+{
+ int ret;
+ struct scmi_xfer *t;
+
+ ret = ph->xops->xfer_get_init(ph, CLOCK_PARENT_GET,
+ sizeof(__le32), sizeof(u32), &t);
+ if (ret)
+ return ret;
+
+ put_unaligned_le32(clk_id, t->tx.buf);
+
+ ret = ph->xops->do_xfer(ph, t);
+ if (!ret)
+ *parent_id = get_unaligned_le32(t->rx.buf);
+
+ ph->xops->xfer_put(ph, t);
+ return ret;
+}
+
static const struct scmi_clk_proto_ops clk_proto_ops = {
.count_get = scmi_clock_count_get,
.info_get = scmi_clock_info_get,
@@ -415,6 +580,8 @@ static const struct scmi_clk_proto_ops clk_proto_ops = {
.disable = scmi_clock_disable,
.enable_atomic = scmi_clock_enable_atomic,
.disable_atomic = scmi_clock_disable_atomic,
+ .parent_set = scmi_clock_set_parent,
+ .parent_get = scmi_clock_get_parent,
};
static int scmi_clock_protocol_init(const struct scmi_protocol_handle *ph)
diff --git a/include/linux/scmi_protocol.h b/include/linux/scmi_protocol.h
index a33cb497a12b0e08209b2a1d22e319c7849ced2e..c9cacb7f617a90b6f280c60787eb010a6edbefbc 100644
--- a/include/linux/scmi_protocol.h
+++ b/include/linux/scmi_protocol.h
@@ -59,6 +59,8 @@ struct scmi_clock_info {
u64 step_size;
} range;
};
+ int num_parents;
+ u32 *parents;
};
enum scmi_power_scale {
@@ -81,6 +83,8 @@ struct scmi_protocol_handle;
* @rate_set: set the clock rate of a clock
* @enable: enables the specified clock
* @disable: disables the specified clock
+ * @parent_get: get the parent id of a clk
+ * @parent_set: set the parent of a clock
*/
struct scmi_clk_proto_ops {
int (*count_get)(const struct scmi_protocol_handle *ph);
@@ -96,6 +100,8 @@ struct scmi_clk_proto_ops {
int (*enable_atomic)(const struct scmi_protocol_handle *ph, u32 clk_id);
int (*disable_atomic)(const struct scmi_protocol_handle *ph,
u32 clk_id);
+ int (*parent_get)(const struct scmi_protocol_handle *ph, u32 clk_id, u32 *parent_id);
+ int (*parent_set)(const struct scmi_protocol_handle *ph, u32 clk_id, u32 parent_id);
};
/**
--
2.39.5
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 23/31] clk: add struct clk_parent_data
2025-05-28 11:45 [PATCH 00/31] ARM: K3: add support for AM62L Sascha Hauer
` (21 preceding siblings ...)
2025-05-28 11:45 ` [PATCH 22/31] firmware: arm_scmi: Add support for clock parents Sascha Hauer
@ 2025-05-28 11:45 ` Sascha Hauer
2025-05-28 11:45 ` [PATCH 24/31] clk: arm_scmi: implement clock parent setting Sascha Hauer
` (7 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Sascha Hauer @ 2025-05-28 11:45 UTC (permalink / raw)
To: BAREBOX
This will become in handy for the upcoming SCMI clk parent support.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
include/linux/clk.h | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 7ae4c48ca27ffbe4597eede01fca27ddee9772d1..f2c02c9eec8fca9702176d0265eecc3620e74fdb 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -349,6 +349,18 @@ struct clk_ops {
int (*get_phase)(struct clk_hw *hw);
};
+/**
+ * struct clk_parent_data - clk parent information
+ * @hw: parent clk_hw pointer (used for clk providers with internal clks)
+ * @name: globally unique parent name (used as a fallback)
+ * @index: parent index local to provider registering clk (if @fw_name absent)
+ */
+struct clk_parent_data {
+ const struct clk_hw *hw;
+ const char *name;
+ int index;
+};
+
/**
* struct clk_init_data - holds init data that's common to all clocks and is
* shared between the clock provider and the common clock framework.
@@ -365,6 +377,7 @@ struct clk_init_data {
const char *name;
const struct clk_ops *ops;
const char * const *parent_names;
+ const struct clk_parent_data *parent_data;
const struct clk_hw **parent_hws;
unsigned int num_parents;
unsigned long flags;
--
2.39.5
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 24/31] clk: arm_scmi: implement clock parent setting
2025-05-28 11:45 [PATCH 00/31] ARM: K3: add support for AM62L Sascha Hauer
` (22 preceding siblings ...)
2025-05-28 11:45 ` [PATCH 23/31] clk: add struct clk_parent_data Sascha Hauer
@ 2025-05-28 11:45 ` Sascha Hauer
2025-05-28 11:45 ` [PATCH 25/31] ARM: dts: am62l3-evm: add MMC aliases Sascha Hauer
` (6 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Sascha Hauer @ 2025-05-28 11:45 UTC (permalink / raw)
To: BAREBOX
This adds support for getting/setting the clk parents in the SCMI clk
driver.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/clk/clk-scmi.c | 80 +++++++++++++++++++++++++++++++++++++++++++++-----
1 file changed, 72 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/clk-scmi.c b/drivers/clk/clk-scmi.c
index 5c9f61ae0b6f94da104cda682e8b399fc4f9c84e..62228d7ba2c12b6bf4ae41dff4aa4553fd3e325e 100644
--- a/drivers/clk/clk-scmi.c
+++ b/drivers/clk/clk-scmi.c
@@ -20,6 +20,7 @@ struct scmi_clk {
struct clk_hw hw;
const struct scmi_clock_info *info;
const struct scmi_protocol_handle *ph;
+ struct clk_parent_data *parent_data;
};
#define to_scmi_clk(clk) container_of(clk, struct scmi_clk, hw)
@@ -74,6 +75,34 @@ static int scmi_clk_set_rate(struct clk_hw *hw, unsigned long rate,
return scmi_proto_clk_ops->rate_set(clk->ph, clk->id, rate);
}
+static int scmi_clk_set_parent(struct clk_hw *hw, u8 parent_index)
+{
+ struct scmi_clk *clk = to_scmi_clk(hw);
+
+ return scmi_proto_clk_ops->parent_set(clk->ph, clk->id, parent_index);
+}
+
+static int scmi_clk_get_parent(struct clk_hw *hw)
+{
+ struct scmi_clk *clk = to_scmi_clk(hw);
+ u32 parent_id, p_idx;
+ int ret;
+
+ ret = scmi_proto_clk_ops->parent_get(clk->ph, clk->id, &parent_id);
+ if (ret)
+ return 0;
+
+ for (p_idx = 0; p_idx < clk->info->num_parents; p_idx++) {
+ if (clk->parent_data[p_idx].index == parent_id)
+ break;
+ }
+
+ if (p_idx == clk->info->num_parents)
+ return 0;
+
+ return p_idx;
+}
+
static int scmi_clk_enable(struct clk_hw *hw)
{
struct scmi_clk *clk = to_scmi_clk(hw);
@@ -121,6 +150,8 @@ static const struct clk_ops scmi_clk_ops = {
.set_rate = scmi_clk_set_rate,
.enable = scmi_clk_enable,
.disable = scmi_clk_disable,
+ .set_parent = scmi_clk_set_parent,
+ .get_parent = scmi_clk_get_parent,
};
static const struct clk_ops scmi_atomic_clk_ops = {
@@ -129,6 +160,8 @@ static const struct clk_ops scmi_atomic_clk_ops = {
.set_rate = scmi_clk_set_rate,
.enable = scmi_clk_atomic_enable,
.disable = scmi_clk_atomic_disable,
+ .set_parent = scmi_clk_set_parent,
+ .get_parent = scmi_clk_get_parent,
};
static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk,
@@ -136,12 +169,22 @@ static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk,
{
struct clk_init_data init = {
.flags = CLK_GET_RATE_NOCACHE,
-
- .num_parents = 0,
+ .num_parents = sclk->info->num_parents,
.ops = scmi_ops,
.name = sclk->info->name,
};
+ if (sclk->info->num_parents > 0) {
+ init.parent_hws = devm_kcalloc(dev, sclk->info->num_parents,
+ sizeof(void *), GFP_KERNEL);
+ if (!init.parent_hws)
+ return -ENOMEM;
+
+ for (int i = 0; i < sclk->info->num_parents; i++) {
+ init.parent_hws[i] = sclk->parent_data[i].hw;
+ }
+ }
+
sclk->hw.init = &init;
return clk_hw_register(dev, &sclk->hw);
}
@@ -157,6 +200,8 @@ static int scmi_clocks_probe(struct scmi_device *sdev)
struct device_node *np = dev->of_node;
const struct scmi_handle *handle = sdev->handle;
struct scmi_protocol_handle *ph;
+ struct scmi_clk *sclks;
+ int ret;
if (!handle)
return -ENODEV;
@@ -182,13 +227,17 @@ static int scmi_clocks_probe(struct scmi_device *sdev)
is_atomic = handle->is_transport_atomic(handle, &atomic_threshold);
+ sclks = devm_kzalloc(dev, sizeof(*sclks) * count, GFP_KERNEL);
+
for (idx = 0; idx < count; idx++) {
- struct scmi_clk *sclk;
- const struct clk_ops *scmi_ops;
+ struct scmi_clk *sclk = &sclks[idx];
- sclk = devm_kzalloc(dev, sizeof(*sclk), GFP_KERNEL);
- if (!sclk)
- return -ENOMEM;
+ hws[idx] = &sclk->hw;
+ }
+
+ for (idx = 0; idx < count; idx++) {
+ struct scmi_clk *sclk = &sclks[idx];
+ const struct clk_ops *scmi_ops;
sclk->info = scmi_proto_clk_ops->info_get(ph, idx);
if (!sclk->info) {
@@ -210,9 +259,25 @@ static int scmi_clocks_probe(struct scmi_device *sdev)
else
scmi_ops = &scmi_clk_ops;
+ /* Initialize clock parent data. */
+ if (sclk->info->num_parents > 0) {
+ u32 parent_id;
+
+ sclk->parent_data = devm_kcalloc(dev, sclk->info->num_parents,
+ sizeof(*sclk->parent_data), GFP_KERNEL);
+ if (!sclk->parent_data)
+ return -ENOMEM;
+
+ for (int i = 0; i < sclk->info->num_parents; i++) {
+ sclk->parent_data[i].index = sclk->info->parents[i];
+ sclk->parent_data[i].hw = hws[sclk->info->parents[i]];
+ }
+ }
+
err = scmi_clk_ops_init(dev, sclk, scmi_ops);
if (err) {
dev_err(dev, "failed to register clock %d\n", idx);
+ devm_kfree(dev, sclk->parent_data);
devm_kfree(dev, sclk);
hws[idx] = NULL;
} else {
@@ -220,7 +285,6 @@ static int scmi_clocks_probe(struct scmi_device *sdev)
sclk->info->name,
scmi_ops == &scmi_atomic_clk_ops ?
" (atomic ops)" : "");
- hws[idx] = &sclk->hw;
}
}
--
2.39.5
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 25/31] ARM: dts: am62l3-evm: add MMC aliases
2025-05-28 11:45 [PATCH 00/31] ARM: K3: add support for AM62L Sascha Hauer
` (23 preceding siblings ...)
2025-05-28 11:45 ` [PATCH 24/31] clk: arm_scmi: implement clock parent setting Sascha Hauer
@ 2025-05-28 11:45 ` Sascha Hauer
2025-05-28 11:45 ` [PATCH 26/31] dma: ti: k3-udma: limit asel to am625 Sascha Hauer
` (5 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Sascha Hauer @ 2025-05-28 11:45 UTC (permalink / raw)
To: BAREBOX
Set the MMC aliases to get device names in barebox that match the
bootsource detection.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/dts/k3-am62l3-evm.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/k3-am62l3-evm.dts b/arch/arm/dts/k3-am62l3-evm.dts
index 7b528ae1e41e92bc9aa1428e86d5141d30fe7cd7..bb1e3a891c3847cb6cbb458810a8decca779c845 100644
--- a/arch/arm/dts/k3-am62l3-evm.dts
+++ b/arch/arm/dts/k3-am62l3-evm.dts
@@ -22,6 +22,11 @@ / {
compatible = "ti,am62l3-evm", "ti,am62l3";
model = "Texas Instruments AM62L3 Evaluation Module";
+ aliases {
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ };
+
chosen {
stdout-path = &uart0;
};
--
2.39.5
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 26/31] dma: ti: k3-udma: limit asel to am625
2025-05-28 11:45 [PATCH 00/31] ARM: K3: add support for AM62L Sascha Hauer
` (24 preceding siblings ...)
2025-05-28 11:45 ` [PATCH 25/31] ARM: dts: am62l3-evm: add MMC aliases Sascha Hauer
@ 2025-05-28 11:45 ` Sascha Hauer
2025-05-28 11:45 ` [PATCH 27/31] gpio: increase ARCH_NR_GPIOS to 512 Sascha Hauer
` (4 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Sascha Hauer @ 2025-05-28 11:45 UTC (permalink / raw)
To: BAREBOX
For reasons currently unknown the asel setting is only needed and
required on am625. It doesn't work on AM62l though.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/dma/ti/k3-udma-common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/ti/k3-udma-common.c b/drivers/dma/ti/k3-udma-common.c
index 8661d148aa1324828a168edb5caa496bb7e6da45..49e2396e9b52145fdf325c2e07efe0869f844a1d 100644
--- a/drivers/dma/ti/k3-udma-common.c
+++ b/drivers/dma/ti/k3-udma-common.c
@@ -1102,7 +1102,7 @@ int udma_of_xlate(struct dma *dma, struct of_phandle_args *args)
ep_config->mapped_channel_id >= 0) {
ucc->mapped_channel_id = ep_config->mapped_channel_id;
ucc->default_flow_id = ep_config->default_flow_id;
- if (args->args_count == 2)
+ if (of_machine_is_compatible("ti,am625") && args->args_count == 2)
ucc->asel = args->args[1];
} else {
ucc->mapped_channel_id = -1;
--
2.39.5
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 27/31] gpio: increase ARCH_NR_GPIOS to 512
2025-05-28 11:45 [PATCH 00/31] ARM: K3: add support for AM62L Sascha Hauer
` (25 preceding siblings ...)
2025-05-28 11:45 ` [PATCH 26/31] dma: ti: k3-udma: limit asel to am625 Sascha Hauer
@ 2025-05-28 11:45 ` Sascha Hauer
2025-05-28 11:45 ` [PATCH 28/31] ARM: dts: k3-am62l: reserve memory for TF-A Sascha Hauer
` (3 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Sascha Hauer @ 2025-05-28 11:45 UTC (permalink / raw)
To: BAREBOX
The TI AM62l EVM board has 259 GPIOs which is more than the current
maximum of 256. We could increase it locally for the K3 arch, but others
are likely to follow, so increase it globally.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
include/gpio.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/gpio.h b/include/gpio.h
index beda10efde0815aa89a8b064b4c9d515c16ae97d..92fd27b2b996eed8777e9321b4f34e245ceca480 100644
--- a/include/gpio.h
+++ b/include/gpio.h
@@ -84,7 +84,7 @@ static inline struct gpio_chip *of_gpio_get_chip_by_alias(const char *alias)
#if defined(CONFIG_ARCH_NR_GPIO) && CONFIG_ARCH_NR_GPIO > 0
#define ARCH_NR_GPIOS CONFIG_ARCH_NR_GPIO
#else
-#define ARCH_NR_GPIOS 256
+#define ARCH_NR_GPIOS 512
#endif
static inline int gpio_is_valid(int gpio)
--
2.39.5
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 28/31] ARM: dts: k3-am62l: reserve memory for TF-A
2025-05-28 11:45 [PATCH 00/31] ARM: K3: add support for AM62L Sascha Hauer
` (26 preceding siblings ...)
2025-05-28 11:45 ` [PATCH 27/31] gpio: increase ARCH_NR_GPIOS to 512 Sascha Hauer
@ 2025-05-28 11:45 ` Sascha Hauer
2025-05-28 11:45 ` [PATCH 29/31] scripts: k3img: make dmdata optional Sascha Hauer
` (2 subsequent siblings)
30 siblings, 0 replies; 32+ messages in thread
From: Sascha Hauer @ 2025-05-28 11:45 UTC (permalink / raw)
To: BAREBOX
On the AM62l the TF-A is placed at the start of the DRAM. Reserve space
for it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/dts/k3-am62l-barebox.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/dts/k3-am62l-barebox.dtsi b/arch/arm/dts/k3-am62l-barebox.dtsi
index 9fe44a67ee7374e6c6d9052dc8ea0f31d2e8f4a1..93f2dbb8c86cd4f8321bfa544b4888b66a2d4309 100644
--- a/arch/arm/dts/k3-am62l-barebox.dtsi
+++ b/arch/arm/dts/k3-am62l-barebox.dtsi
@@ -14,3 +14,17 @@ &gpio2 {
&wkup_gpio0 {
status = "okay";
};
+
+/ {
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ tfa@80000000 {
+ reg = <0x0 0x80000000 0x0 0x80000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+};
--
2.39.5
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 29/31] scripts: k3img: make dmdata optional
2025-05-28 11:45 [PATCH 00/31] ARM: K3: add support for AM62L Sascha Hauer
` (27 preceding siblings ...)
2025-05-28 11:45 ` [PATCH 28/31] ARM: dts: k3-am62l: reserve memory for TF-A Sascha Hauer
@ 2025-05-28 11:45 ` Sascha Hauer
2025-05-28 11:45 ` [PATCH 30/31] scripts: k3img: handle bootcore_opts Sascha Hauer
2025-05-28 11:45 ` [PATCH 31/31] ARM: k3: add AM62l3 EVM board support Sascha Hauer
30 siblings, 0 replies; 32+ messages in thread
From: Sascha Hauer @ 2025-05-28 11:45 UTC (permalink / raw)
To: BAREBOX
dmdata will not be needed for AM62L support, so make it optional.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
scripts/k3img | 39 +++++++++++++++++++++++++--------------
1 file changed, 25 insertions(+), 14 deletions(-)
diff --git a/scripts/k3img b/scripts/k3img
index a9f7e513723b251c3605e81a97093e23850a8f4d..2cb2a6b33bbdf6bcf2dedcd067dcc2ffd2d17d04 100755
--- a/scripts/k3img
+++ b/scripts/k3img
@@ -68,14 +68,12 @@ done
shasbl=$(sha512sum $sbl | sed 's/ .*//')
shasysfw=$(sha512sum $sysfw | sed 's/ .*//')
shasysfwdata=$(sha512sum $sysfwdata | sed 's/ .*//')
-shadmdata=$(sha512sum $dmdata | sed 's/ .*//')
sblsize=$(stat -c%s $sbl)
sysfwsize=$(stat -c%s $sysfw)
sysfwdatasize=$(stat -c%s $sysfwdata)
-dmdatasize=$(stat -c%s $dmdata)
-total=$(($sblsize + $sysfwsize + $sysfwdatasize + $dmdatasize))
+total=$(($sblsize + $sysfwsize + $sysfwdatasize))
TMPDIR="$(mktemp -d)"
trap 'rm -rf -- "$TMPDIR"' EXIT
@@ -83,7 +81,7 @@ trap 'rm -rf -- "$TMPDIR"' EXIT
certcfg=${TMPDIR}/certcfg
cert=${TMPDIR}/cert
-num_comp=4
+num_comp=3
if [ -n "${innerdata}" ]; then
shainnerdata=$(sha512sum $innerdata | sed 's/ .*//')
@@ -100,12 +98,32 @@ shaType = OID:2.16.840.1.101.3.4.2.3
shaValue = FORMAT:HEX,OCT:$shainnerdata
EOF
)
-
num_comp=$((num_comp + 1))
total=$((total + innerdatasize))
sysfw_inner_cert="sysfw_inner_cert=SEQUENCE:sysfw_inner_cert"
fi
+if [ -n "${dmdata}" ]; then
+ shadmdata=$(sha512sum $dmdata | sed 's/ .*//')
+ dmdatasize=$(stat -c%s $dmdata)
+
+ dmdata_sect=$(cat <<EOF
+[dm_data]
+compType = INTEGER:17
+bootCore = INTEGER:16
+compOpts = INTEGER:0
+destAddr = FORMAT:HEX,OCT:$dmdata_addr
+compSize = INTEGER:$dmdatasize
+shaType = OID:2.16.840.1.101.3.4.2.3
+shaValue = FORMAT:HEX,OCT:$shadmdata
+EOF
+)
+
+ num_comp=$((num_comp + 1))
+ total=$((total + dmdatasize))
+ dm_data="dm_data=SEQUENCE:dm_data"
+fi
+
cat > $certcfg <<EndOfHereDocument
[ req ]
distinguished_name = req_distinguished_name
@@ -138,7 +156,7 @@ sbl=SEQUENCE:sbl
sysfw=SEQUENCE:sysfw
sysfw_data=SEQUENCE:sysfw_data
$sysfw_inner_cert
-dm_data=SEQUENCE:dm_data
+$dm_data
[sbl]
compType = INTEGER:1
@@ -175,14 +193,7 @@ coreDbgSecEn = INTEGER:0
$innercert
-[dm_data]
-compType = INTEGER:17
-bootCore = INTEGER:16
-compOpts = INTEGER:0
-destAddr = FORMAT:HEX,OCT:$dmdata_addr
-compSize = INTEGER:$dmdatasize
-shaType = OID:2.16.840.1.101.3.4.2.3
-shaValue = FORMAT:HEX,OCT:$shadmdata
+$dmdata_sect
EndOfHereDocument
--
2.39.5
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 30/31] scripts: k3img: handle bootcore_opts
2025-05-28 11:45 [PATCH 00/31] ARM: K3: add support for AM62L Sascha Hauer
` (28 preceding siblings ...)
2025-05-28 11:45 ` [PATCH 29/31] scripts: k3img: make dmdata optional Sascha Hauer
@ 2025-05-28 11:45 ` Sascha Hauer
2025-05-28 11:45 ` [PATCH 31/31] ARM: k3: add AM62l3 EVM board support Sascha Hauer
30 siblings, 0 replies; 32+ messages in thread
From: Sascha Hauer @ 2025-05-28 11:45 UTC (permalink / raw)
To: BAREBOX
bootcore_opts needs another setting for AM62L. Make it configurable.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
scripts/k3img | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/scripts/k3img b/scripts/k3img
index 2cb2a6b33bbdf6bcf2dedcd067dcc2ffd2d17d04..93bcfaea7688d038b2b95189fac764884dec4a72 100755
--- a/scripts/k3img
+++ b/scripts/k3img
@@ -2,7 +2,9 @@
set -e
-TEMP=$(getopt -o '' --long 'sysfw:,sysfwdata:,dmdata:,out:,sbl:,key:,innerdata:' -n 'k3img' -- "$@")
+bootcore_opts=0
+
+TEMP=$(getopt -o '' --long 'sysfw:,sysfwdata:,dmdata:,out:,sbl:,key:,innerdata:,bootcore_opts:' -n 'k3img' -- "$@")
if [ $? -ne 0 ]; then
echo 'Terminating...' >&2
@@ -54,6 +56,11 @@ while true; do
shift 2
continue
;;
+ '--bootcore_opts')
+ bootcore_opts="$2"
+ shift 2
+ continue
+ ;;
'--')
shift
break
@@ -161,7 +168,7 @@ $dm_data
[sbl]
compType = INTEGER:1
bootCore = INTEGER:16
-compOpts = INTEGER:0
+compOpts = INTEGER:$bootcore_opts
destAddr = FORMAT:HEX,OCT:$sbl_addr
compSize = INTEGER:$sblsize
shaType = OID:2.16.840.1.101.3.4.2.3
--
2.39.5
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 31/31] ARM: k3: add AM62l3 EVM board support
2025-05-28 11:45 [PATCH 00/31] ARM: K3: add support for AM62L Sascha Hauer
` (29 preceding siblings ...)
2025-05-28 11:45 ` [PATCH 30/31] scripts: k3img: handle bootcore_opts Sascha Hauer
@ 2025-05-28 11:45 ` Sascha Hauer
30 siblings, 0 replies; 32+ messages in thread
From: Sascha Hauer @ 2025-05-28 11:45 UTC (permalink / raw)
To: BAREBOX
Add support for the AM62l3 EVM board [1]. Currently supported are:
- DRAM
- eMMC
- SD card
- Ethernet
- USB
[1] https://www.ti.com/tool/TMDS62LEVM
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/Makefile | 1 +
arch/arm/boards/am62lx-evm/Makefile | 1 +
arch/arm/boards/am62lx-evm/lowlevel.c | 35 ++++++++++++++++++++
arch/arm/dts/Makefile | 1 +
arch/arm/mach-k3/Kconfig | 6 ++++
images/Makefile.k3 | 60 +++++++++++++++++++++++++++++++++--
6 files changed, 101 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index 908497cd8b0509bdca01c9ccfbb1501654051bda..ac1fa74d4c03de7a462746cb93a061017cd2b64d 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_MACH_ADVANTECH_ROM_742X) += advantech-mx6/
obj-$(CONFIG_MACH_AFI_GF) += afi-gf/
obj-$(CONFIG_MACH_ANIMEO_IP) += animeo_ip/
obj-$(CONFIG_MACH_AM625_SK) += am625-sk/
+obj-$(CONFIG_MACH_AM62LX_EVM) += am62lx-evm/
obj-$(CONFIG_MACH_AT91RM9200EK) += at91rm9200ek/
obj-$(CONFIG_MACH_AT91SAM9260EK) += at91sam9260ek/
obj-$(CONFIG_MACH_AT91SAM9261EK) += at91sam9261ek/
diff --git a/arch/arm/boards/am62lx-evm/Makefile b/arch/arm/boards/am62lx-evm/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..562535d391d66ae2068377967c4c84844cddd380
--- /dev/null
+++ b/arch/arm/boards/am62lx-evm/Makefile
@@ -0,0 +1 @@
+pbl-y += lowlevel.o
diff --git a/arch/arm/boards/am62lx-evm/lowlevel.c b/arch/arm/boards/am62lx-evm/lowlevel.c
new file mode 100644
index 0000000000000000000000000000000000000000..1b57641bee71a7e83a2ac5cbe64bf6714343f468
--- /dev/null
+++ b/arch/arm/boards/am62lx-evm/lowlevel.c
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <common.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <mach/k3/debug_ll.h>
+#include <debug_ll.h>
+#include <pbl.h>
+#include <cache.h>
+#include <pbl/handoff-data.h>
+#include <compressed-dtb.h>
+#include <mach/k3/common.h>
+
+static noinline void am62lx_evm_continue(void)
+{
+ extern char __dtb_z_k3_am62l3_evm_start[];
+
+ pbl_set_putc((void *)debug_ll_ns16550_putc, IOMEM(AM62X_UART_UART0_BASE));
+
+ putc_ll('>');
+
+ barebox_arm_entry(0x80000000 + SZ_512K, SZ_2G - SZ_512K, __dtb_z_k3_am62l3_evm_start);
+}
+
+ENTRY_FUNCTION_WITHSTACK(start_am62lx_evm, 0x80800000, r0, r1, r2)
+{
+ writel(0x00000000, 0x040841b8);
+
+ k3_debug_ll_init(IOMEM(AM62X_UART_UART0_BASE));
+
+ relocate_to_current_adr();
+ setup_c();
+
+ am62lx_evm_continue();
+}
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3044c9bf120f9ece9564164b3fa569f4b7be1881..6612a514523103fdaaae026527f3441ebc57d228 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -7,6 +7,7 @@ obj- += dummy.o
lwl-$(CONFIG_MACH_ADVANTECH_ROM_742X) += imx6dl-advantech-rom-7421.dtb.o
lwl-$(CONFIG_MACH_AFI_GF) += am335x-afi-gf.dtb.o
lwl-$(CONFIG_MACH_AM625_SK) += k3-am625-sk.dtb.o k3-am625-r5-sk.dtb.o k3-am625sip-r5-sk.dtb.o
+lwl-$(CONFIG_MACH_AM62LX_EVM) += k3-am62l3-evm.dtb.o
lwl-$(CONFIG_MACH_BEAGLEBONE) += am335x-bone.dtb.o am335x-boneblack.dtb.o am335x-bone-common.dtb.o
lwl-$(CONFIG_MACH_BEAGLEPLAY) += k3-am625-beagleplay.dtb.o k3-am625-r5-beagleplay.dtb.o
lwl-$(CONFIG_MACH_CLEP7212) += ep7212-clep7212.dtb.o
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index cda44807e8a1db7c2f701309948c7bd1a863d365..338421a8af1715c72a23adc41fb7a21d69091585 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -46,6 +46,12 @@ config MACH_BEAGLEPLAY
help
Say Y here if you are using a TI AM62x based BeaglePlay board
+config MACH_AM62LX_EVM
+ bool "TI AM62Lx EVM"
+ select MACH_AM62LX
+ help
+ Say Y here if you are using a TI AM62Lx EVM board
+
config ARCH_K3_AUTHENTICATE_IMAGE
bool "Force authentication of FIP image against ROM API"
help
diff --git a/images/Makefile.k3 b/images/Makefile.k3
index 801ffe42ca221b53ca0221e75eaa089bdf07b2b7..61ea75191910cefcc95e101559fa2717a1ae0117 100644
--- a/images/Makefile.k3
+++ b/images/Makefile.k3
@@ -17,6 +17,9 @@ image-$(CONFIG_MACH_BEAGLEPLAY) += barebox-beagleplay.img
endif
+KEY_custmpk=$(srctree)/arch/arm/mach-k3/custMpk.pem
+KEY_degenerate=$(srctree)/arch/arm/mach-k3/ti-degenerate-key.pem
+
ifdef CONFIG_MACH_K3_CORTEX_R5
SYSFWDATA_am625=$(objtree)/arch/arm/mach-k3/combined-sysfw-cfg-am62x.k3cfg
@@ -24,8 +27,6 @@ DMDATA_am625=$(objtree)/arch/arm/mach-k3/combined-dm-cfg-am62x.k3cfg
SYSFW_am625_hs_fs=$(FIRMWARE_DIR)/ti-fs-firmware-am62x-hs-fs-enc.bin
SYSFW_am625_gp=$(FIRMWARE_DIR)/ti-fs-firmware-am62x-gp.bin
INNERDATA_am625=$(FIRMWARE_DIR)/ti-fs-firmware-am62x-hs-fs-cert.bin
-KEY_custmpk=$(srctree)/arch/arm/mach-k3/custMpk.pem
-KEY_degenerate=$(srctree)/arch/arm/mach-k3/ti-degenerate-key.pem
## TI am625(sip)-SK ##
SYSFW_start_am625_sk_r5.pblb.k3_am62x_img=$(SYSFW_am625_hs_fs)
@@ -60,6 +61,29 @@ image-$(CONFIG_MACH_BEAGLEPLAY) += barebox-beagleplay-r5.img
endif
+SYSFWDATA_am62lx=$(objtree)/arch/arm/mach-k3/combined-sysfw-cfg-am62l.k3cfg
+SYSFW_am62lx_hs_fs=$(FIRMWARE_DIR)/ti-fs-firmware-am62lx-hs-fs-enc.bin
+INNERDATA_am62lx=$(FIRMWARE_DIR)/ti-fs-firmware-am62lx-hs-fs-cert.bin
+
+## TI am62lx-EVM ##
+SYSFW_start_am62lx_evm.pblb.k3_am62lx_img=$(SYSFW_am62lx_hs_fs)
+SYSFWDATA_start_am62lx_evm.pblb.k3_am62lx_img=$(SYSFWDATA_am62lx)
+TFA_start_am62lx_evm.pblb.k3_am62lx_img=$(FIRMWARE_DIR)/am62lx-bl31.bin
+INNERDATA_start_am62lx_evm.pblb.k3_am62lx_img=$(INNERDATA_am62lx)
+KEY_start_am62lx_evm.pblb.k3_am62lx_img=$(KEY_custmpk)
+
+SYSFW_start_am62lx_evm.pblb.k3_am62lx_tiboot3_img=$(SYSFW_am62lx_hs_fs)
+SYSFWDATA_start_am62lx_evm.pblb.k3_am62lx_tiboot3_img=$(SYSFWDATA_am62lx)
+INNERDATA_start_am62lx_evm.pblb.k3_am62lx_tiboot3_img=$(INNERDATA_am62lx)
+TFA_BL1_start_am62lx_evm.pblb.k3_am62lx_tiboot3_img=$(FIRMWARE_DIR)/am62lx-bl1.bin
+KEY_start_am62lx_evm.pblb.k3_am62lx_tiboot3_img=$(KEY_custmpk)
+
+pblb-$(CONFIG_MACH_AM62LX_EVM) += start_am62lx_evm
+FILE_barebox-am62lx-evm.img = start_am62lx_evm.pblb.k3_am62lx_img
+image-$(CONFIG_MACH_AM62LX_EVM) += barebox-am62lx-evm.img barebox-am62lx-evm-tiboot3.img
+
+FILE_barebox-am62lx-evm-tiboot3.img = start_am62lx_evm.pblb.k3_am62lx_tiboot3_img
+
quiet_cmd_k3_am62x_image = K3_am62x_IMG $@
cmd_k3_am62x_image = \
if [ -n "$(INNERDATA_$(@F))" ]; then \
@@ -73,5 +97,35 @@ quiet_cmd_k3_am62x_image = K3_am62x_IMG $@
--sbl $<:43c00000 \
--key $(KEY_$(@F)) $$inner --out $@
-$(obj)/%.k3_am62x_img: $(obj)/% scripts/k3_am62x_img FORCE
+quiet_cmd_k3_am62lx_image = K3_am62lx_IMG $@
+ cmd_k3_am62lx_image = \
+ if [ -n "$(INNERDATA_$(@F))" ]; then \
+ inner="--innerdata $(INNERDATA_$(@F))"; \
+ fi; \
+ \
+ $(srctree)/scripts/k3img \
+ --sysfw $(SYSFW_$(@F)):00040000 \
+ --sysfwdata $(SYSFWDATA_$(@F)):0006c000 \
+ --dmdata $<:82000000 \
+ --sbl $(TFA_$(@F)):80000000 \
+ --key $(KEY_$(@F)) $$inner --out $@
+
+quiet_cmd_k3_am62lx_tiboot3_image = K3_am62lx_tiboot3_IMG $@
+ cmd_k3_am62lx_tiboot3_image = \
+ $(srctree)/scripts/k3img \
+ --sysfw $(SYSFW_$(@F)):00040000 \
+ --sysfwdata $(SYSFWDATA_$(@F)):0006c000 \
+ --sbl $(TFA_BL1_$(@F)):70800000 \
+ --key $(KEY_$(@F)) \
+ --innerdata $(INNERDATA_$(@F)) \
+ --bootcore_opts 160 \
+ --out $@
+
+$(obj)/%.k3_am62x_img: $(obj)/% scripts/k3img FORCE
$(call if_changed,k3_am62x_image)
+
+$(obj)/%.k3_am62lx_img: $(obj)/% scripts/k3img FORCE
+ $(call if_changed,k3_am62lx_image)
+
+$(obj)/%.k3_am62lx_tiboot3_img: $(obj)/% scripts/k3img FORCE
+ $(call if_changed,k3_am62lx_tiboot3_image)
--
2.39.5
^ permalink raw reply [flat|nested] 32+ messages in thread
end of thread, other threads:[~2025-05-28 12:05 UTC | newest]
Thread overview: 32+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2025-05-28 11:45 [PATCH 00/31] ARM: K3: add support for AM62L Sascha Hauer
2025-05-28 11:45 ` [PATCH 01/31] scripts: k3img: remove duplicate case value Sascha Hauer
2025-05-28 11:45 ` [PATCH 02/31] ARM: K3: prepare support for other SoCs Sascha Hauer
2025-05-28 11:45 ` [PATCH 03/31] ARM: k3: make k3img destination addresses configurable Sascha Hauer
2025-05-28 11:45 ` [PATCH 04/31] ARM: dts: add k3-am62l dts(i) files Sascha Hauer
2025-05-28 11:45 ` [PATCH 05/31] ARM: dts: am62l: Fix assigned-clock-parents Sascha Hauer
2025-05-28 11:45 ` [PATCH 06/31] ARM: K3: add am62lx base support Sascha Hauer
2025-05-28 11:45 ` [PATCH 07/31] ARM: Makefile: descend into mach-* for cleaning Sascha Hauer
2025-05-28 11:45 ` [PATCH 08/31] ARM: k3: rename yaml files from am625 to am62x Sascha Hauer
2025-05-28 11:45 ` [PATCH 09/31] scripts/ti-board-config.py: fix length Sascha Hauer
2025-05-28 11:45 ` [PATCH 10/31] ARM: k3: add yaml files for AM62l Sascha Hauer
2025-05-28 11:45 ` [PATCH 11/31] k3: ringacc: pass ringrt address in struct k3_ringacc_init_data Sascha Hauer
2025-05-28 11:45 ` [PATCH 12/31] drivers: soc: ti: k3-ringacc: handle absence of tisci Sascha Hauer
2025-05-28 11:45 ` [PATCH 13/31] drivers: soc: ti: k3-ringacc: fix k3_ringacc_ring_reset_sci Sascha Hauer
2025-05-28 11:45 ` [PATCH 14/31] dma: ti: k3-psil: Add PSIL data for AM62L Sascha Hauer
2025-05-28 11:45 ` [PATCH 15/31] dma: ti: k3-udma: Refactor common bits for AM62L support Sascha Hauer
2025-05-28 11:45 ` [PATCH 16/31] dma: ti: k3-udma-common: Update common code for AM62L DMAs Sascha Hauer
2025-05-28 11:45 ` [PATCH 17/31] dma: ti: k3-udma-am62l: Add AM62L support DMA drivers Sascha Hauer
2025-05-28 11:45 ` [PATCH 18/31] ARM: dts: am62l: Add ethernet ports Sascha Hauer
2025-05-28 11:45 ` [PATCH 19/31] ARM: dts: am62l evm: " Sascha Hauer
2025-05-28 11:45 ` [PATCH 20/31] ARM: k3: am62l: add barebox specific am62l.dtsi Sascha Hauer
2025-05-28 11:45 ` [PATCH 21/31] net: davinci_mdio: Use fallback clock rate Sascha Hauer
2025-05-28 11:45 ` [PATCH 22/31] firmware: arm_scmi: Add support for clock parents Sascha Hauer
2025-05-28 11:45 ` [PATCH 23/31] clk: add struct clk_parent_data Sascha Hauer
2025-05-28 11:45 ` [PATCH 24/31] clk: arm_scmi: implement clock parent setting Sascha Hauer
2025-05-28 11:45 ` [PATCH 25/31] ARM: dts: am62l3-evm: add MMC aliases Sascha Hauer
2025-05-28 11:45 ` [PATCH 26/31] dma: ti: k3-udma: limit asel to am625 Sascha Hauer
2025-05-28 11:45 ` [PATCH 27/31] gpio: increase ARCH_NR_GPIOS to 512 Sascha Hauer
2025-05-28 11:45 ` [PATCH 28/31] ARM: dts: k3-am62l: reserve memory for TF-A Sascha Hauer
2025-05-28 11:45 ` [PATCH 29/31] scripts: k3img: make dmdata optional Sascha Hauer
2025-05-28 11:45 ` [PATCH 30/31] scripts: k3img: handle bootcore_opts Sascha Hauer
2025-05-28 11:45 ` [PATCH 31/31] ARM: k3: add AM62l3 EVM board support Sascha Hauer
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