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Fri, 13 Jun 2025 09:58:51 +0200 Received: from localhost ([::1] helo=dude02.red.stw.pengutronix.de) by dude02.red.stw.pengutronix.de with esmtp (Exim 4.96) (envelope-from ) id 1uPzJL-00CPUK-0j; Fri, 13 Jun 2025 09:58:51 +0200 From: Sascha Hauer Date: Fri, 13 Jun 2025 09:58:51 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250613-arm-mmu-xn-ro-v1-3-60f05c6e7b4b@pengutronix.de> References: <20250613-arm-mmu-xn-ro-v1-0-60f05c6e7b4b@pengutronix.de> In-Reply-To: <20250613-arm-mmu-xn-ro-v1-0-60f05c6e7b4b@pengutronix.de> To: BAREBOX X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1749801531; l=1634; i=s.hauer@pengutronix.de; s=20230412; h=from:subject:message-id; bh=dAYE9A02RC+ERb27/+ziNOfZTly2kW/Hw43IP47vhN4=; b=8/ACu+ldhJhYZSnZld7MABGb2m3fI2+2ZaTnzL6bPAOV7vQFY/msgNOpMFnJ1uc3LM0F/rnc4 3o6hWyDM84WDgH93V70vfVVBZE5SKztQZ1IZzQG5XjWwFIyyvXGVntX X-Developer-Key: i=s.hauer@pengutronix.de; a=ed25519; pk=4kuc9ocmECiBJKWxYgqyhtZOHj5AWi7+d0n/UjhkwTg= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250613_085909_083816_0FD3F06A X-CRM114-Status: GOOD ( 10.84 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.whiteo.stw.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-5.2 required=4.0 tests=AWL,BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: [PATCH 3/7] ARM: mmu: move ARCH_MAP_WRITECOMBINE to header X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.whiteo.stw.pengutronix.de) ARCH_MAP_WRITECOMBINE is defined equally for both mmu_32 and mmu_64 and we'll add more mapping types later, so move it to a header file to be shared by both mmu implementations. Signed-off-by: Sascha Hauer --- arch/arm/cpu/mmu-common.h | 2 ++ arch/arm/cpu/mmu_32.c | 1 - arch/arm/cpu/mmu_64.c | 2 -- 3 files changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/mmu-common.h b/arch/arm/cpu/mmu-common.h index d0b50662570a48fafd47edac9fbc12fe2a62458a..0f11a4b73d1199ec2400f64a2f057cf940d4ff2d 100644 --- a/arch/arm/cpu/mmu-common.h +++ b/arch/arm/cpu/mmu-common.h @@ -9,6 +9,8 @@ #include #include +#define ARCH_MAP_WRITECOMBINE ((unsigned)-1) + struct device; void dma_inv_range(void *ptr, size_t size); diff --git a/arch/arm/cpu/mmu_32.c b/arch/arm/cpu/mmu_32.c index 2754bea88a514c2886e43ffc4dbf310d75055fca..3e0c761cd43486d3193b80b5f79097bdd5cd333c 100644 --- a/arch/arm/cpu/mmu_32.c +++ b/arch/arm/cpu/mmu_32.c @@ -23,7 +23,6 @@ #include "mmu_32.h" #define PTRS_PER_PTE (PGDIR_SIZE / PAGE_SIZE) -#define ARCH_MAP_WRITECOMBINE ((unsigned)-1) static inline uint32_t *get_ttb(void) { diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c index 65c6f1bb9f8ac2f4b55baf46c2af3d3714060088..440258fa767735a4537abd71030a5540813fc443 100644 --- a/arch/arm/cpu/mmu_64.c +++ b/arch/arm/cpu/mmu_64.c @@ -24,8 +24,6 @@ #include "mmu_64.h" -#define ARCH_MAP_WRITECOMBINE ((unsigned)-1) - static uint64_t *get_ttb(void) { return (uint64_t *)get_ttbr(current_el()); -- 2.39.5