[PATCH 1/6] resource: mark normal memory as supporting being uncacheable

[Ahmad Fatoum <a.fatoum@barebox.org>]

The attributes report what the underlying memory is capable of,
so if we can configure it as WT/WC/WB, it's likely we can configure it
as uncached as well. This doesn't hold true for all architectures, but
it does for ARM, so add it to the MEMATTRS_NORMAL bitfield for now.

Signed-off-by: Ahmad Fatoum <a.fatoum@barebox.org>
---
 include/linux/ioport.h | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/include/linux/ioport.h b/include/linux/ioport.h
index 425928df3bfe..ceff1bb7e5ac 100644
--- a/include/linux/ioport.h
+++ b/include/linux/ioport.h
@@ -133,11 +133,11 @@ enum resource_memtype {
 #define MEMATTR_RO	0x00020000	/* read-only */
 #define MEMATTR_SP	0x00040000	/* specific-purpose */
 
-#define MEMATTRS_CACHEABLE	(MEMATTR_WT | MEMATTR_WC | MEMATTR_WB)
-#define MEMATTRS_RW		(MEMATTRS_CACHEABLE | MEMATTR_XP)
-#define MEMATTRS_RO		(MEMATTRS_CACHEABLE | MEMATTR_XP | MEMATTR_RO)
-#define MEMATTRS_RX		(MEMATTRS_CACHEABLE | MEMATTR_RO)
-#define MEMATTRS_RWX		(MEMATTRS_CACHEABLE)	/* TODO: remove all */
+#define MEMATTRS_NORMAL		(MEMATTR_UC | MEMATTR_WT | MEMATTR_WC | MEMATTR_WB)
+#define MEMATTRS_RW		(MEMATTRS_NORMAL | MEMATTR_XP)
+#define MEMATTRS_RO		(MEMATTRS_NORMAL | MEMATTR_XP | MEMATTR_RO)
+#define MEMATTRS_RX		(MEMATTRS_NORMAL | MEMATTR_RO)
+#define MEMATTRS_RWX		(MEMATTRS_NORMAL)	/* TODO: remove all */
 #define MEMATTRS_RW_DEVICE	(MEMATTR_UC | MEMATTR_XP)
 #define MEMATTRS_FAULT		(MEMATTR_UC | MEMATTR_XP | MEMATTR_RP | MEMATTR_RO)
 
-- 
2.39.5