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Tue, 17 Jun 2025 23:36:07 -0700 (PDT) Received: from localhost.localdomain ([188.243.23.53]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-32b3c7decb8sm19038121fa.49.2025.06.17.23.36.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jun 2025 23:36:06 -0700 (PDT) From: Alexander Shiyan To: barebox@lists.infradead.org Cc: Alexander Shiyan Date: Wed, 18 Jun 2025 09:35:48 +0300 Message-Id: <20250618063552.23777-1-eagle.alexander923@gmail.com> X-Mailer: git-send-email 2.39.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250617_233610_278387_83A82D9B X-CRM114-Status: GOOD ( 13.19 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.whiteo.stw.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-4.6 required=4.0 tests=AWL,BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: [PATCH] ARM: at91: clock: remove unused SAMA5D2/SAMA5D3 support from legacy clock driver X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.whiteo.stw.pengutronix.de) This driver is not used for DT-based boards and only affects legacy non-DT platforms. Remove support for SAMA5D2/SAMA5D3 SoCs as they are exclusively supported through DT-based boot in current configurations. Signed-off-by: Alexander Shiyan --- arch/arm/mach-at91/clock.c | 32 ++++---------------------------- 1 file changed, 4 insertions(+), 28 deletions(-) diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index 6482aa93c0..7ffd549dc4 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c @@ -40,14 +40,10 @@ #define cpu_has_utmi() ( cpu_is_at91sam9rl() \ || cpu_is_at91sam9g45() \ || cpu_is_at91sam9x5() \ - || cpu_is_sama5d2() \ - || cpu_is_sama5d3() \ || cpu_is_sama5d4()) #define cpu_has_1200M_plla() (cpu_is_sama5d4()) -#define cpu_has_1056M_plla() (cpu_is_sama5d3()) - #define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \ || cpu_is_at91sam9g45() \ || cpu_is_at91sam9x5() \ @@ -64,14 +60,10 @@ #define cpu_has_pllb() (!(cpu_is_at91sam9rl() \ || cpu_is_at91sam9g45() \ || cpu_is_at91sam9x5() \ - || cpu_is_sama5d2() \ - || cpu_is_sama5d3() \ || cpu_is_sama5d4())) #define cpu_has_upll() (cpu_is_at91sam9g45() \ || cpu_is_at91sam9x5() \ - || cpu_is_sama5d2() \ - || cpu_is_sama5d3() \ || cpu_is_sama5d4()) /* USB host HS & FS */ @@ -81,36 +73,25 @@ #define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \ || cpu_is_at91sam9g45() \ || cpu_is_at91sam9x5() \ - || cpu_is_sama5d2() \ - || cpu_is_sama5d3() \ || cpu_is_sama5d4())) #define cpu_has_plladiv2() (cpu_is_at91sam9g45() \ || cpu_is_at91sam9x5() \ || cpu_is_at91sam9n12() \ - || cpu_is_sama5d2() \ - || cpu_is_sama5d3() \ || cpu_is_sama5d4()) #define cpu_has_mdiv3() (cpu_is_at91sam9g45() \ || cpu_is_at91sam9x5() \ || cpu_is_at91sam9n12() \ - || cpu_is_sama5d2() \ - || cpu_is_sama5d3() \ || cpu_is_sama5d4()) #define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \ || cpu_is_at91sam9n12() \ - || cpu_is_sama5d2() \ - || cpu_is_sama5d3() \ || cpu_is_sama5d4()) -#define cpu_has_pcr() (cpu_is_sama5d2() \ - || cpu_is_sama5d3() \ - || cpu_is_sama5d4()) +#define cpu_has_pcr() (cpu_is_sama5d4()) -#define cpu_has_dual_matrix() (cpu_is_sama5d2() \ - || cpu_is_sama5d4()) +#define cpu_has_dual_matrix() (cpu_is_sama5d4()) static void *pmc; @@ -253,7 +234,7 @@ static void pmc_periph_mode(struct clk *clk, int is_on) u32 regval = 0; /* - * With sama5d3 chips, you have more than 32 peripherals so only one + * With sama5d4 chips, you have more than 32 peripherals so only one * register is not enough to manage their clocks. A peripheral * control register has been introduced to solve this issue. */ @@ -517,7 +498,7 @@ static u32 at91_pll_rate(struct clk *pll, u32 freq, u32 reg) unsigned mul, div; div = reg & 0xff; - if (cpu_is_sama5d3() || cpu_is_sama5d4()) + if (cpu_is_sama5d4()) mul = (reg >> 18) & 0x7ff; else mul = (reg >> 16) & 0x7ff; @@ -666,8 +647,6 @@ int at91_clock_init(void) if (cpu_is_sama5d4()) pmc = IOMEM(0xf0018000); - else if (cpu_is_sama5d2()) - pmc = IOMEM(0xf0014000); else pmc = IOMEM(0xfffffc00); /* * All other supported SoCs use this @@ -696,9 +675,6 @@ int at91_clock_init(void) if (cpu_has_1200M_plla()) { if (plla.rate_hz > 1200000000) pll_overclock = 1; - } else if (cpu_has_1056M_plla()) { - if (plla.rate_hz > 1056000000) - pll_overclock = 1; } else if (cpu_has_300M_plla()) { if (plla.rate_hz > 300000000) pll_overclock = 1; -- 2.39.1