From mboxrd@z Thu Jan 1 00:00:00 1970 Delivery-date: Thu, 26 Jun 2025 20:24:27 +0200 Received: from metis.whiteo.stw.pengutronix.de ([2a0a:edc0:2:b01:1d::104]) by lore.white.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1uUrGt-00BM7F-2i for lore@lore.pengutronix.de; Thu, 26 Jun 2025 20:24:27 +0200 Received: from bombadil.infradead.org ([2607:7c80:54:3::133]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1uUrGt-0005KD-7O for lore@pengutronix.de; Thu, 26 Jun 2025 20:24:27 +0200 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:Message-Id:Date:Subject:To:From:Reply-To:Cc:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=2l5wjObHl2sufs8xqQ8bNtKJUSVxUtT5rXGDLRhRGqM=; b=RAimCHQf6LAPeV2/yEPwltx/Z2 XlcWq54fMAR0lU16sfPEXaoTIadFg3XWNKeYJHjc3hY60eIy+NuN7Mq5Lxf7EwM9waxMwLV8WL5+N sc9HBERhntuhcc77I+RY5EW5C23b4Zitfdf9e2Q2jxntpFhsCmhqMhW05gxNY9Ou0G9MmHdk+VYzp qyQ4wuiEozu1vUgPTwY/66U8cY2iwc+o5URooFhAayUgY2xf03mPELoj/UjwVA7xsmc1gPxdpbf7X 0mowU7tITsX2CVo00rM8y8NkGRGQDAqlQa/XNTlf6im04LZBXLLrqs+2wwbaoHTkhYeM/+z5of32x 1RHmeimQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1uUrGU-0000000CS6Y-2IHu; Thu, 26 Jun 2025 18:24:02 +0000 Received: from metis.whiteo.stw.pengutronix.de ([2a0a:edc0:2:b01:1d::104]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1uUo6P-0000000C2Lz-2lCY for barebox@lists.infradead.org; Thu, 26 Jun 2025 15:01:26 +0000 Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1uUo6O-0007nU-Cc; Thu, 26 Jun 2025 17:01:24 +0200 Received: from dude02.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::28]) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1uUo6O-005Spk-0f; Thu, 26 Jun 2025 17:01:24 +0200 Received: from localhost ([::1] helo=dude02.red.stw.pengutronix.de) by dude02.red.stw.pengutronix.de with esmtp (Exim 4.96) (envelope-from ) id 1uUo6O-001rub-0J; Thu, 26 Jun 2025 17:01:24 +0200 From: Sascha Hauer To: Barebox List Date: Thu, 26 Jun 2025 17:01:22 +0200 Message-Id: <20250626150122.445558-1-s.hauer@pengutronix.de> X-Mailer: git-send-email 2.39.5 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250626_080125_693892_B03691C8 X-CRM114-Status: GOOD ( 13.57 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.whiteo.stw.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-5.3 required=4.0 tests=AWL,BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: [PATCH] ARM: i.MX: tzasc: configure region 1 X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.whiteo.stw.pengutronix.de) Configuring TZASC region0 for non secure access has the effect that the OP-TEE memory can be accessed via aliases in the SDRAM memory space, see https://lore.kernel.org/20250626144527.416697-1-m.felsch@pengutronix.de. This patch fixes the issue for i.MX6ul boards. Signed-off-by: Sascha Hauer --- arch/arm/boards/tqma6ulx/lowlevel.c | 5 +++-- arch/arm/boards/webasto-ccbv2/lowlevel.c | 5 +++-- arch/arm/mach-imx/tzasc.c | 12 ++++++++++++ include/mach/imx/tzasc.h | 2 ++ 4 files changed, 20 insertions(+), 4 deletions(-) diff --git a/arch/arm/boards/tqma6ulx/lowlevel.c b/arch/arm/boards/tqma6ulx/lowlevel.c index ce330c37af..14553fa1aa 100644 --- a/arch/arm/boards/tqma6ulx/lowlevel.c +++ b/arch/arm/boards/tqma6ulx/lowlevel.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "tqma6ulx.h" @@ -82,8 +83,8 @@ static void noinline start_mba6ulx(u32 r2) */ if (IS_ENABLED(CONFIG_FIRMWARE_TQMA6UL_OPTEE) && !(r2 > MX6_MMDC_PORT0_BASE_ADDR && r2 < MX6_MMDC_PORT0_BASE_ADDR + SZ_256M)) { - /* Enable normal/secure r/w for TZC380 region0 */ - writel(0xf0000000, 0x021D0108); + + imx6ul_tzc380_early_ns_region1(); get_builtin_firmware(mba6ul_optee_bin, &tee, &tee_size); diff --git a/arch/arm/boards/webasto-ccbv2/lowlevel.c b/arch/arm/boards/webasto-ccbv2/lowlevel.c index 17264479c2..23d053863a 100644 --- a/arch/arm/boards/webasto-ccbv2/lowlevel.c +++ b/arch/arm/boards/webasto-ccbv2/lowlevel.c @@ -13,6 +13,7 @@ #include #include #include +#include #include "ccbv2.h" @@ -44,8 +45,8 @@ static void noinline start_ccbv2(u32 r2, unsigned long mem_size, char *fdt) */ if(IS_ENABLED(CONFIG_FIRMWARE_CCBV2_OPTEE) && !(r2 > MX6_MMDC_PORT0_BASE_ADDR && r2 < MX6_MMDC_PORT0_BASE_ADDR + mem_size)) { - /* Enable normal/secure r/w for TZC380 region0 */ - writel(0xf0000000, 0x021D0108); + imx6ul_tzc380_early_ns_region1(); + get_builtin_firmware(ccbv2_optee_bin, &tee, &tee_size); memset((void *)OPTEE_OVERLAY_LOCATION, 0, 0x1000); diff --git a/arch/arm/mach-imx/tzasc.c b/arch/arm/mach-imx/tzasc.c index c2603c2b43..77601d8d14 100644 --- a/arch/arm/mach-imx/tzasc.c +++ b/arch/arm/mach-imx/tzasc.c @@ -296,6 +296,18 @@ void imx6q_tzc380_early_ns_region1(void) TZC380_REGION_SP_NS_RW); } +void imx6ul_tzc380_early_ns_region1(void) +{ + resource_size_t ram_sz = imx6_get_mmdc_sdram_size(); + + imx_tzc380_init_and_setup(IOMEM(MX6_TZASC1_BASE), 1, + MX6_MMDC_PORT0_BASE_ADDR, ram_sz, + TZC380_REGION_SP_NS_RW); +} + +void imx6sx_tzc380_early_ns_region1(void) + __alias(imx6ul_tzc380_early_ns_region1); + bool imx6q_tzc380_is_enabled(void) { u32 __iomem *gpr = IOMEM(MX6_IOMUXC_BASE_ADDR); diff --git a/include/mach/imx/tzasc.h b/include/mach/imx/tzasc.h index 59ec56a5ec..75bb7b1393 100644 --- a/include/mach/imx/tzasc.h +++ b/include/mach/imx/tzasc.h @@ -7,6 +7,8 @@ #include void imx6q_tzc380_early_ns_region1(void); +void imx6ul_tzc380_early_ns_region1(void); +void imx6sx_tzc380_early_ns_region1(void); bool imx6q_tzc380_is_enabled(void); void imx8m_tzc380_init(void); bool imx8m_tzc380_is_enabled(void); -- 2.39.5