Re: [PATCH 08/14] ARM: mach-imx: tzasc: add imx6[q|ul]_tzc380_is_bypassed()

[Marco Felsch <m.felsch@pengutronix.de>]

On 25-06-27, Sascha Hauer wrote:
> From: Marco Felsch <m.felsch@pengutronix.de>
> 
> The TZASC_BYP bits in the IOMUX GPR offer a great way to shoot yourself
> in the foot. These bits are cleared by default and with these bits
> cleared the TZASC will never check DDR transactions. The TZASC can be
> configured normally with the bits cleared, it just doesn't work and all
> secure regions can be accessed by the normal worls. These
> bits can only be set in the DCD table, trying to set them in code will
> make the system hang. As the DCD tables are board specific it's easy to

I think this is not entirely true. At least the i.MX6 TRM says, that any
DDR access must be done before the TZASC is turned on.

Since most i.MX6/7 boards do use the DCD RAM setup and tell the BootROM
to load the barebox(-pbl) directly into RAM, we can enable it only from
DCD. But it should still be possible to enable it within the code, like
we do for i.MX8M. This only requires that the barebox-pbl is loaded into
internal OCRAM which is the rare case for i.MX6/7 boards.

Keep in mind, I did not test the later case.

> forget setting them. This patch adds a function that checks if the bits
> are set as desired which will be called by the optee-early helper later.
> 
> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  arch/arm/mach-imx/tzasc.c | 26 ++++++++++++++++++++++++++
>  include/mach/imx/tzasc.h  |  2 ++
>  2 files changed, 28 insertions(+)
> 
> diff --git a/arch/arm/mach-imx/tzasc.c b/arch/arm/mach-imx/tzasc.c
> index 169c4b9801e5fdd01edd3c5661418a945cf21c55..ed20ad8803a2e91b67b5d8c3ab1a4265c4228ec7 100644
> --- a/arch/arm/mach-imx/tzasc.c
> +++ b/arch/arm/mach-imx/tzasc.c
> @@ -76,6 +76,9 @@
>  #define MX6_TZASC1_BASE			0x21d0000
>  #define MX6_TZASC2_BASE			0x21d4000
>  
> +#define MX6_GPR_TZASC1_EN		BIT(0)
> +#define MX6_GPR_TZASC2_EN		BIT(1)
> +
>  #define GPR_TZASC_EN					BIT(0)
>  #define GPR_TZASC_ID_SWAP_BYPASS		BIT(1)
>  #define GPR_TZASC_EN_LOCK				BIT(16)
> @@ -303,6 +306,29 @@ void imx6ul_tzc380_early_ns_region1(void)
>  				  TZC380_REGION_SP_NS_RW);
>  }
>  
> +bool imx6q_tzc380_is_bypassed(void)
> +{
> +	u32 __iomem *gpr = IOMEM(MX6_IOMUXC_BASE_ADDR);
> +
> +	/*
> +	 * MX6_GPR_TZASC1_EN and MX6_GPR_TZASC2_EN are sticky bits which
> +	 * preserve their values once set until the next power-up cycle.
> +	 */
> +	return (readl(&gpr[9]) & (MX6_GPR_TZASC1_EN | MX6_GPR_TZASC2_EN)) !=
> +	       (MX6_GPR_TZASC1_EN | MX6_GPR_TZASC2_EN);
> +}
> +
> +bool imx6ul_tzc380_is_bypassed(void)
> +{
> +	u32 __iomem *gpr = IOMEM(MX6_IOMUXC_BASE_ADDR + 0x4000);
> +
> +	/*
> +	 * MX6_GPR_TZASC1_EN is a sticky bit which preserves its value
> +	 * once set until the next power-up cycle.
> +	 */
> +	return !(readl(&gpr[9]) & MX6_GPR_TZASC1_EN);
> +}
> +
>  void imx8m_tzc380_init(void)
>  {
>  	u32 __iomem *gpr = IOMEM(MX8M_IOMUXC_GPR_BASE_ADDR);
> diff --git a/include/mach/imx/tzasc.h b/include/mach/imx/tzasc.h
> index eb479ad55c9c101a5fb47fc4a7178b3669b9e44f..0fbcdc2150e63864366a8dddeed2d1b97685903d 100644
> --- a/include/mach/imx/tzasc.h
> +++ b/include/mach/imx/tzasc.h
> @@ -8,6 +8,8 @@
>  
>  void imx6q_tzc380_early_ns_region1(void);
>  void imx6ul_tzc380_early_ns_region1(void);
> +bool imx6q_tzc380_is_bypassed(void);
> +bool imx6ul_tzc380_is_bypassed(void);
>  void imx8m_tzc380_init(void);
>  bool imx8m_tzc380_is_enabled(void);
>  
> 
> -- 
> 2.39.5
> 
>