From: Ahmad Fatoum <a.fatoum@barebox.org>
To: barebox@lists.infradead.org
Cc: Ahmad Fatoum <a.fatoum@barebox.org>
Subject: [PATCH 2/8] RISC-V: virt: riscvemu: set better hostname/model
Date: Thu, 14 Aug 2025 22:27:59 +0200 [thread overview]
Message-ID: <20250814202805.354827-2-a.fatoum@barebox.org> (raw)
In-Reply-To: <20250814202805.354827-1-a.fatoum@barebox.org>
The hostname and model currently come from the device tree:
"riscvemu-bar_dev" and "ucbbar,riscvemu-bare", respectively.
The former is now warned about, because it contains an underscore and
the latter is not that descriptive.
As the device tree is supplied by the emulator, add an override to board
code. We differntiate between riscv32 and riscv64 in the hostname string
as that information can be relevant for choosing the correct kernel.
Signed-off-by: Ahmad Fatoum <a.fatoum@barebox.org>
---
arch/riscv/boards/riscvemu/board.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/riscv/boards/riscvemu/board.c b/arch/riscv/boards/riscvemu/board.c
index bf5a05dd6a4d..be1d0c162961 100644
--- a/arch/riscv/boards/riscvemu/board.c
+++ b/arch/riscv/boards/riscvemu/board.c
@@ -42,6 +42,13 @@ static int riscvemu_probe(struct device *dev)
struct riscvemu_priv *priv;
u64 start;
+ if (IS_ENABLED(CONFIG_ARCH_RV32I))
+ barebox_set_hostname("riscvemu32");
+ else
+ barebox_set_hostname("riscvemu64");
+
+ barebox_set_model("RISC-V Emulator");
+
of_overlay_apply_dtbo(dev->of_node, __dtbo_riscvemu_sram_start);
/* of_probe() will happen later at of_populate_initcall */
--
2.39.5
next prev parent reply other threads:[~2025-08-14 20:28 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-14 20:27 [PATCH 1/8] common: fix outdated barebox_set_hostname comment Ahmad Fatoum
2025-08-14 20:27 ` Ahmad Fatoum [this message]
2025-08-14 20:28 ` [PATCH 3/8] netconsole: bump down ip/port not set messages to info Ahmad Fatoum
2025-08-14 20:28 ` [PATCH 4/8] RISC-V: cpuinfo: enable structured I/O Ahmad Fatoum
2025-08-14 20:28 ` [PATCH 5/8] commands: bfetch: add RISC-V cpu/firmware info Ahmad Fatoum
2025-08-14 20:28 ` [PATCH 6/8] RISC-V: riscvemu: update configs for web demo Ahmad Fatoum
2025-08-14 20:28 ` [PATCH 7/8] RISC-V: rv64i_defconfig: enable Virt I/O Ahmad Fatoum
2025-08-14 20:28 ` [PATCH 8/8] poller: allow suppressing overtime warnings Ahmad Fatoum
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