[PATCH 1/4] ARM: i.MX8M: initialize SNVS

[Sascha Hauer <s.hauer@pengutronix.de>]

The Secure Non Volatile Storage (SNVS) needs some initialization on
i.MX8M. Add that into the startup path. The code is based on the
corresponding U-Boot code. This also adds the necessary code for i.MX7,
but this is untested and thus not enabled currently.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-imx/Kconfig     |  5 +++++
 arch/arm/mach-imx/Makefile    |  1 +
 arch/arm/mach-imx/atf.c       |  5 +++++
 arch/arm/mach-imx/snvs.c      | 44 +++++++++++++++++++++++++++++++++++++++++++
 include/mach/imx/imx8m-regs.h |  1 +
 include/mach/imx/snvs.h       |  9 +++++++++
 6 files changed, 65 insertions(+)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 0d745ce2315834ec5d0c366d227b40f2adff5e83..2c10b8ffdc4f8c67fc5a0ace9e5e0f385a676e1d 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -52,6 +52,11 @@ config ARCH_IMX_TZASC
 	default y if PBL_OPTEE
 	select ARM_EXCEPTIONS_PBL
 
+config ARCH_IMX_SNVS
+	bool
+	depends on ARCH_IMX7 || ARCH_IMX8M
+	default y
+
 #
 # PMIC configuration found on i.MX51 Babbadge board
 #
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index f81fa18e9214d7c3b60d04454bfb73eda0a6b5f4..a7d60068b954d7845f6a702c20733eec63e2b658 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -40,3 +40,4 @@ pbl-y += xload-spi.o xload-common.o xload-imx-nand.o xload-gpmi-nand.o
 pbl-y += xload-qspi.o
 obj-pbl-$(CONFIG_ARCH_IMX9) += ele.o
 obj-pbl-$(CONFIG_ARCH_IMX9) += imx93-trdc.o
+lwl-$(CONFIG_ARCH_IMX_SNVS) += snvs.o
diff --git a/arch/arm/mach-imx/atf.c b/arch/arm/mach-imx/atf.c
index 11fe0334059d104a003ee084c618ff6f0d66ea3c..94536d346d57e7926c1ab89a9a4c53439f7649f3 100644
--- a/arch/arm/mach-imx/atf.c
+++ b/arch/arm/mach-imx/atf.c
@@ -17,6 +17,7 @@
 #include <tee/optee.h>
 #include <mach/imx/ele.h>
 #include <mach/imx/xload.h>
+#include <mach/imx/snvs.h>
 
 /**
  * imx8m_atf_load_bl31 - Load ATF BL31 blob and transfer control to it
@@ -155,6 +156,7 @@ __noreturn void __imx8mm_load_and_start_image_via_tfa(void *bl33)
 	imx_set_cpu_type(IMX_CPU_IMX8MM);
 	imx8mm_init_scratch_space();
 	imx8m_save_bootrom_log();
+	imx8m_setup_snvs();
 	imx8mm_load_bl33(bl33);
 
 	if (IS_ENABLED(CONFIG_FIRMWARE_IMX8MM_OPTEE)) {
@@ -229,6 +231,7 @@ __noreturn void __imx8mp_load_and_start_image_via_tfa(void *bl33)
 	imx_set_cpu_type(IMX_CPU_IMX8MP);
 	imx8mp_init_scratch_space();
 	imx8m_save_bootrom_log();
+	imx8m_setup_snvs();
 	imx8mp_load_bl33(bl33);
 
 	if (IS_ENABLED(CONFIG_FIRMWARE_IMX8MP_OPTEE)) {
@@ -304,6 +307,7 @@ __noreturn void __imx8mn_load_and_start_image_via_tfa(void *bl33)
 	imx_set_cpu_type(IMX_CPU_IMX8MN);
 	imx8mn_init_scratch_space();
 	imx8m_save_bootrom_log();
+	imx8m_setup_snvs();
 	imx8mn_load_bl33(bl33);
 
 	if (IS_ENABLED(CONFIG_FIRMWARE_IMX8MN_OPTEE)) {
@@ -372,6 +376,7 @@ __noreturn void __imx8mq_load_and_start_image_via_tfa(void *bl33)
 	imx_set_cpu_type(IMX_CPU_IMX8MQ);
 	imx8mq_init_scratch_space();
 	imx8m_save_bootrom_log();
+	imx8m_setup_snvs();
 	imx8mq_load_bl33(bl33);
 
 	if (IS_ENABLED(CONFIG_FIRMWARE_IMX8MQ_OPTEE)) {
diff --git a/arch/arm/mach-imx/snvs.c b/arch/arm/mach-imx/snvs.c
new file mode 100644
index 0000000000000000000000000000000000000000..80df62ad966b7edd4843eb480df2a097db499d8f
--- /dev/null
+++ b/arch/arm/mach-imx/snvs.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <io.h>
+#include <linux/bits.h>
+#include <mach/imx/snvs.h>
+#include <mach/imx/imx7-regs.h>
+#include <mach/imx/imx8m-regs.h>
+
+#define SNVS_HPCOMR	0x04
+#define SNVS_HPCOMR_NPSWA_EN	BIT(31)
+
+#define SNVS_LPSR	0x4c
+
+#define SNVS_LPLVDR	0x64
+#define SNVS_LPPGDR_INIT	0x41736166
+
+static void snvs_init(void __iomem *snvs)
+{
+	u32 val;
+
+	/* Ensure SNVS HPCOMR sets NPSWA_EN to allow unpriv access to SNVS LP */
+	val = readl(snvs + SNVS_HPCOMR);
+	val |= SNVS_HPCOMR_NPSWA_EN;
+	writel(val, snvs + SNVS_HPCOMR);
+}
+
+void imx7_snvs_init(void)
+{
+	void __iomem *snvs = IOMEM(MX7_SNVS_BASE_ADDR);
+
+	snvs_init(snvs);
+}
+
+void imx8m_setup_snvs(void)
+{
+	void __iomem *snvs = IOMEM(MX8M_SNVS_BASE_ADDR);
+
+        /* Initialize glitch detect */
+        writel(SNVS_LPPGDR_INIT, snvs + SNVS_LPLVDR);
+        /* Clear interrupt status */
+        writel(0xffffffff, snvs + SNVS_LPSR);
+
+        snvs_init(snvs);
+}
diff --git a/include/mach/imx/imx8m-regs.h b/include/mach/imx/imx8m-regs.h
index d101b88cc4a67fed706dde157a86dc1bda217ca1..a69ca4c27e211224fffd1736dd9b76d7dbc163a1 100644
--- a/include/mach/imx/imx8m-regs.h
+++ b/include/mach/imx/imx8m-regs.h
@@ -25,6 +25,7 @@
 #define MX8M_IOMUXC_GPR_BASE_ADDR	0x30340000
 #define MX8M_OCOTP_BASE_ADDR		0x30350000
 #define MX8M_ANATOP_BASE_ADDR		0x30360000
+#define MX8M_SNVS_BASE_ADDR		0x30370000
 #define MX8M_CCM_BASE_ADDR		0x30380000
 #define MX8M_SRC_BASE_ADDR		0x30390000
 #define MX8M_SRC_DDRC_RCR_ADDR		0x30391000
diff --git a/include/mach/imx/snvs.h b/include/mach/imx/snvs.h
new file mode 100644
index 0000000000000000000000000000000000000000..01154d57d9bd8d6804f2b7f3d634fae1121b9fb7
--- /dev/null
+++ b/include/mach/imx/snvs.h
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#ifndef __MACH_IMX_SNVS_H
+#define __MACH_IMX_SNVS_H
+
+void imx7_snvs_init(void);
+void imx8m_setup_snvs(void);
+
+#endif /* __MACH_IMX_SNVS_H */

-- 
2.47.3