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From: Sascha Hauer <s.hauer@pengutronix.de>
To: BAREBOX <barebox@lists.infradead.org>
Subject: [PATCH 2/4] nvmem: snvs_lpgpr: Add i.MX7/8 support
Date: Mon, 08 Sep 2025 10:31:56 +0200	[thread overview]
Message-ID: <20250908-imx8-snvs-v1-2-1049458a0286@pengutronix.de> (raw)
In-Reply-To: <20250908-imx8-snvs-v1-0-1049458a0286@pengutronix.de>

This adds i.MX7/8 support to the snvs_lpgpr driver. This is based on
Linux commit 80b820cae421a ("nvmem: add i.MX7 support to snvs-lpgpr")

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/nvmem/snvs_lpgpr.c | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/nvmem/snvs_lpgpr.c b/drivers/nvmem/snvs_lpgpr.c
index 9bbee6d587a437716cba2189fed839497fb6f3c7..e29fa2bf3aec1e9b5b19beee4ac5440b6b18e018 100644
--- a/drivers/nvmem/snvs_lpgpr.c
+++ b/drivers/nvmem/snvs_lpgpr.c
@@ -20,10 +20,18 @@
 #define IMX6Q_GPR_HL		BIT(5)
 #define IMX6Q_SNVS_LPGPR	0x68
 
+#define IMX7D_SNVS_HPLR		0x00
+#define IMX7D_SNVS_LPLR		0x34
+#define IMX7D_SNVS_LPGPR	0x90
+
+#define IMX_GPR_SL		BIT(5)
+#define IMX_GPR_HL		BIT(5)
+
 struct snvs_lpgpr_cfg {
 	int offset;
 	int offset_hplr;
 	int offset_lplr;
+	int size;
 };
 
 struct snvs_lpgpr_priv {
@@ -37,6 +45,14 @@ static const struct snvs_lpgpr_cfg snvs_lpgpr_cfg_imx6q = {
 	.offset		= IMX6Q_SNVS_LPGPR,
 	.offset_hplr	= IMX6Q_SNVS_HPLR,
 	.offset_lplr	= IMX6Q_SNVS_LPLR,
+	.size		= 4,
+};
+
+static const struct snvs_lpgpr_cfg snvs_lpgpr_cfg_imx7d = {
+	.offset		= IMX7D_SNVS_LPGPR,
+	.offset_hplr	= IMX7D_SNVS_HPLR,
+	.offset_lplr	= IMX7D_SNVS_LPLR,
+	.size		= 16,
 };
 
 static int snvs_lpgpr_write(void *ctx, unsigned offset, const void *val, size_t bytes)
@@ -106,7 +122,7 @@ static int snvs_lpgpr_probe(struct device *dev)
 	cfg->priv = priv;
 	cfg->stride = 4;
 	cfg->word_size = 4;
-	cfg->size = 4;
+	cfg->size = priv->dcfg->size;
 	cfg->reg_write = snvs_lpgpr_write;
 	cfg->reg_read  = snvs_lpgpr_read;
 
@@ -122,6 +138,7 @@ static int snvs_lpgpr_probe(struct device *dev)
 static __maybe_unused struct of_device_id snvs_lpgpr_dt_ids[] = {
 	{ .compatible = "fsl,imx6q-snvs-lpgpr", .data = &snvs_lpgpr_cfg_imx6q },
 	{ .compatible = "fsl,imx6ul-snvs-lpgpr", .data = &snvs_lpgpr_cfg_imx6q },
+	{ .compatible = "fsl,imx7d-snvs-lpgpr", .data = &snvs_lpgpr_cfg_imx7d },
 	{ },
 };
 MODULE_DEVICE_TABLE(of, snvs_lpgpr_dt_ids);

-- 
2.47.3




  parent reply	other threads:[~2025-09-08  9:30 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-08  8:31 [PATCH 0/4] i.MX8M: Add SNVS support Sascha Hauer
2025-09-08  8:31 ` [PATCH 1/4] ARM: i.MX8M: initialize SNVS Sascha Hauer
2025-09-08  8:31 ` Sascha Hauer [this message]
2025-09-08  8:31 ` [PATCH 3/4] nvmem: snvs_lpgpr: set nvmem config name to snvs Sascha Hauer
2025-09-08  8:31 ` [PATCH 4/4] ARM: defconfigs: enable SNVS driver in i.MX8 configs Sascha Hauer

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