* [PATCH 1/4] ARM: i.MX8M: initialize SNVS
2025-09-08 8:31 [PATCH 0/4] i.MX8M: Add SNVS support Sascha Hauer
@ 2025-09-08 8:31 ` Sascha Hauer
2025-09-08 8:31 ` [PATCH 2/4] nvmem: snvs_lpgpr: Add i.MX7/8 support Sascha Hauer
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Sascha Hauer @ 2025-09-08 8:31 UTC (permalink / raw)
To: BAREBOX
The Secure Non Volatile Storage (SNVS) needs some initialization on
i.MX8M. Add that into the startup path. The code is based on the
corresponding U-Boot code. This also adds the necessary code for i.MX7,
but this is untested and thus not enabled currently.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/Kconfig | 5 +++++
arch/arm/mach-imx/Makefile | 1 +
arch/arm/mach-imx/atf.c | 5 +++++
arch/arm/mach-imx/snvs.c | 44 +++++++++++++++++++++++++++++++++++++++++++
include/mach/imx/imx8m-regs.h | 1 +
include/mach/imx/snvs.h | 9 +++++++++
6 files changed, 65 insertions(+)
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 0d745ce2315834ec5d0c366d227b40f2adff5e83..2c10b8ffdc4f8c67fc5a0ace9e5e0f385a676e1d 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -52,6 +52,11 @@ config ARCH_IMX_TZASC
default y if PBL_OPTEE
select ARM_EXCEPTIONS_PBL
+config ARCH_IMX_SNVS
+ bool
+ depends on ARCH_IMX7 || ARCH_IMX8M
+ default y
+
#
# PMIC configuration found on i.MX51 Babbadge board
#
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index f81fa18e9214d7c3b60d04454bfb73eda0a6b5f4..a7d60068b954d7845f6a702c20733eec63e2b658 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -40,3 +40,4 @@ pbl-y += xload-spi.o xload-common.o xload-imx-nand.o xload-gpmi-nand.o
pbl-y += xload-qspi.o
obj-pbl-$(CONFIG_ARCH_IMX9) += ele.o
obj-pbl-$(CONFIG_ARCH_IMX9) += imx93-trdc.o
+lwl-$(CONFIG_ARCH_IMX_SNVS) += snvs.o
diff --git a/arch/arm/mach-imx/atf.c b/arch/arm/mach-imx/atf.c
index 11fe0334059d104a003ee084c618ff6f0d66ea3c..94536d346d57e7926c1ab89a9a4c53439f7649f3 100644
--- a/arch/arm/mach-imx/atf.c
+++ b/arch/arm/mach-imx/atf.c
@@ -17,6 +17,7 @@
#include <tee/optee.h>
#include <mach/imx/ele.h>
#include <mach/imx/xload.h>
+#include <mach/imx/snvs.h>
/**
* imx8m_atf_load_bl31 - Load ATF BL31 blob and transfer control to it
@@ -155,6 +156,7 @@ __noreturn void __imx8mm_load_and_start_image_via_tfa(void *bl33)
imx_set_cpu_type(IMX_CPU_IMX8MM);
imx8mm_init_scratch_space();
imx8m_save_bootrom_log();
+ imx8m_setup_snvs();
imx8mm_load_bl33(bl33);
if (IS_ENABLED(CONFIG_FIRMWARE_IMX8MM_OPTEE)) {
@@ -229,6 +231,7 @@ __noreturn void __imx8mp_load_and_start_image_via_tfa(void *bl33)
imx_set_cpu_type(IMX_CPU_IMX8MP);
imx8mp_init_scratch_space();
imx8m_save_bootrom_log();
+ imx8m_setup_snvs();
imx8mp_load_bl33(bl33);
if (IS_ENABLED(CONFIG_FIRMWARE_IMX8MP_OPTEE)) {
@@ -304,6 +307,7 @@ __noreturn void __imx8mn_load_and_start_image_via_tfa(void *bl33)
imx_set_cpu_type(IMX_CPU_IMX8MN);
imx8mn_init_scratch_space();
imx8m_save_bootrom_log();
+ imx8m_setup_snvs();
imx8mn_load_bl33(bl33);
if (IS_ENABLED(CONFIG_FIRMWARE_IMX8MN_OPTEE)) {
@@ -372,6 +376,7 @@ __noreturn void __imx8mq_load_and_start_image_via_tfa(void *bl33)
imx_set_cpu_type(IMX_CPU_IMX8MQ);
imx8mq_init_scratch_space();
imx8m_save_bootrom_log();
+ imx8m_setup_snvs();
imx8mq_load_bl33(bl33);
if (IS_ENABLED(CONFIG_FIRMWARE_IMX8MQ_OPTEE)) {
diff --git a/arch/arm/mach-imx/snvs.c b/arch/arm/mach-imx/snvs.c
new file mode 100644
index 0000000000000000000000000000000000000000..80df62ad966b7edd4843eb480df2a097db499d8f
--- /dev/null
+++ b/arch/arm/mach-imx/snvs.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <io.h>
+#include <linux/bits.h>
+#include <mach/imx/snvs.h>
+#include <mach/imx/imx7-regs.h>
+#include <mach/imx/imx8m-regs.h>
+
+#define SNVS_HPCOMR 0x04
+#define SNVS_HPCOMR_NPSWA_EN BIT(31)
+
+#define SNVS_LPSR 0x4c
+
+#define SNVS_LPLVDR 0x64
+#define SNVS_LPPGDR_INIT 0x41736166
+
+static void snvs_init(void __iomem *snvs)
+{
+ u32 val;
+
+ /* Ensure SNVS HPCOMR sets NPSWA_EN to allow unpriv access to SNVS LP */
+ val = readl(snvs + SNVS_HPCOMR);
+ val |= SNVS_HPCOMR_NPSWA_EN;
+ writel(val, snvs + SNVS_HPCOMR);
+}
+
+void imx7_snvs_init(void)
+{
+ void __iomem *snvs = IOMEM(MX7_SNVS_BASE_ADDR);
+
+ snvs_init(snvs);
+}
+
+void imx8m_setup_snvs(void)
+{
+ void __iomem *snvs = IOMEM(MX8M_SNVS_BASE_ADDR);
+
+ /* Initialize glitch detect */
+ writel(SNVS_LPPGDR_INIT, snvs + SNVS_LPLVDR);
+ /* Clear interrupt status */
+ writel(0xffffffff, snvs + SNVS_LPSR);
+
+ snvs_init(snvs);
+}
diff --git a/include/mach/imx/imx8m-regs.h b/include/mach/imx/imx8m-regs.h
index d101b88cc4a67fed706dde157a86dc1bda217ca1..a69ca4c27e211224fffd1736dd9b76d7dbc163a1 100644
--- a/include/mach/imx/imx8m-regs.h
+++ b/include/mach/imx/imx8m-regs.h
@@ -25,6 +25,7 @@
#define MX8M_IOMUXC_GPR_BASE_ADDR 0x30340000
#define MX8M_OCOTP_BASE_ADDR 0x30350000
#define MX8M_ANATOP_BASE_ADDR 0x30360000
+#define MX8M_SNVS_BASE_ADDR 0x30370000
#define MX8M_CCM_BASE_ADDR 0x30380000
#define MX8M_SRC_BASE_ADDR 0x30390000
#define MX8M_SRC_DDRC_RCR_ADDR 0x30391000
diff --git a/include/mach/imx/snvs.h b/include/mach/imx/snvs.h
new file mode 100644
index 0000000000000000000000000000000000000000..01154d57d9bd8d6804f2b7f3d634fae1121b9fb7
--- /dev/null
+++ b/include/mach/imx/snvs.h
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#ifndef __MACH_IMX_SNVS_H
+#define __MACH_IMX_SNVS_H
+
+void imx7_snvs_init(void);
+void imx8m_setup_snvs(void);
+
+#endif /* __MACH_IMX_SNVS_H */
--
2.47.3
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH 2/4] nvmem: snvs_lpgpr: Add i.MX7/8 support
2025-09-08 8:31 [PATCH 0/4] i.MX8M: Add SNVS support Sascha Hauer
2025-09-08 8:31 ` [PATCH 1/4] ARM: i.MX8M: initialize SNVS Sascha Hauer
@ 2025-09-08 8:31 ` Sascha Hauer
2025-09-08 8:31 ` [PATCH 3/4] nvmem: snvs_lpgpr: set nvmem config name to snvs Sascha Hauer
2025-09-08 8:31 ` [PATCH 4/4] ARM: defconfigs: enable SNVS driver in i.MX8 configs Sascha Hauer
3 siblings, 0 replies; 5+ messages in thread
From: Sascha Hauer @ 2025-09-08 8:31 UTC (permalink / raw)
To: BAREBOX
This adds i.MX7/8 support to the snvs_lpgpr driver. This is based on
Linux commit 80b820cae421a ("nvmem: add i.MX7 support to snvs-lpgpr")
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/nvmem/snvs_lpgpr.c | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/nvmem/snvs_lpgpr.c b/drivers/nvmem/snvs_lpgpr.c
index 9bbee6d587a437716cba2189fed839497fb6f3c7..e29fa2bf3aec1e9b5b19beee4ac5440b6b18e018 100644
--- a/drivers/nvmem/snvs_lpgpr.c
+++ b/drivers/nvmem/snvs_lpgpr.c
@@ -20,10 +20,18 @@
#define IMX6Q_GPR_HL BIT(5)
#define IMX6Q_SNVS_LPGPR 0x68
+#define IMX7D_SNVS_HPLR 0x00
+#define IMX7D_SNVS_LPLR 0x34
+#define IMX7D_SNVS_LPGPR 0x90
+
+#define IMX_GPR_SL BIT(5)
+#define IMX_GPR_HL BIT(5)
+
struct snvs_lpgpr_cfg {
int offset;
int offset_hplr;
int offset_lplr;
+ int size;
};
struct snvs_lpgpr_priv {
@@ -37,6 +45,14 @@ static const struct snvs_lpgpr_cfg snvs_lpgpr_cfg_imx6q = {
.offset = IMX6Q_SNVS_LPGPR,
.offset_hplr = IMX6Q_SNVS_HPLR,
.offset_lplr = IMX6Q_SNVS_LPLR,
+ .size = 4,
+};
+
+static const struct snvs_lpgpr_cfg snvs_lpgpr_cfg_imx7d = {
+ .offset = IMX7D_SNVS_LPGPR,
+ .offset_hplr = IMX7D_SNVS_HPLR,
+ .offset_lplr = IMX7D_SNVS_LPLR,
+ .size = 16,
};
static int snvs_lpgpr_write(void *ctx, unsigned offset, const void *val, size_t bytes)
@@ -106,7 +122,7 @@ static int snvs_lpgpr_probe(struct device *dev)
cfg->priv = priv;
cfg->stride = 4;
cfg->word_size = 4;
- cfg->size = 4;
+ cfg->size = priv->dcfg->size;
cfg->reg_write = snvs_lpgpr_write;
cfg->reg_read = snvs_lpgpr_read;
@@ -122,6 +138,7 @@ static int snvs_lpgpr_probe(struct device *dev)
static __maybe_unused struct of_device_id snvs_lpgpr_dt_ids[] = {
{ .compatible = "fsl,imx6q-snvs-lpgpr", .data = &snvs_lpgpr_cfg_imx6q },
{ .compatible = "fsl,imx6ul-snvs-lpgpr", .data = &snvs_lpgpr_cfg_imx6q },
+ { .compatible = "fsl,imx7d-snvs-lpgpr", .data = &snvs_lpgpr_cfg_imx7d },
{ },
};
MODULE_DEVICE_TABLE(of, snvs_lpgpr_dt_ids);
--
2.47.3
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH 3/4] nvmem: snvs_lpgpr: set nvmem config name to snvs
2025-09-08 8:31 [PATCH 0/4] i.MX8M: Add SNVS support Sascha Hauer
2025-09-08 8:31 ` [PATCH 1/4] ARM: i.MX8M: initialize SNVS Sascha Hauer
2025-09-08 8:31 ` [PATCH 2/4] nvmem: snvs_lpgpr: Add i.MX7/8 support Sascha Hauer
@ 2025-09-08 8:31 ` Sascha Hauer
2025-09-08 8:31 ` [PATCH 4/4] ARM: defconfigs: enable SNVS driver in i.MX8 configs Sascha Hauer
3 siblings, 0 replies; 5+ messages in thread
From: Sascha Hauer @ 2025-09-08 8:31 UTC (permalink / raw)
To: BAREBOX
Set the nvmem config name to "snvs". Without it the cdev shows up as
/dev/30370000.snvs@30370000:snvs-lpgpr.of0.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/nvmem/snvs_lpgpr.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/nvmem/snvs_lpgpr.c b/drivers/nvmem/snvs_lpgpr.c
index e29fa2bf3aec1e9b5b19beee4ac5440b6b18e018..95ce023a14c4b79934fcfc15d7d5b82fa7f85e24 100644
--- a/drivers/nvmem/snvs_lpgpr.c
+++ b/drivers/nvmem/snvs_lpgpr.c
@@ -125,6 +125,8 @@ static int snvs_lpgpr_probe(struct device *dev)
cfg->size = priv->dcfg->size;
cfg->reg_write = snvs_lpgpr_write;
cfg->reg_read = snvs_lpgpr_read;
+ cfg->name = "snvs";
+ cfg->id = NVMEM_DEVID_NONE;
nvmem = nvmem_register(cfg);
if (IS_ERR(nvmem)) {
--
2.47.3
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH 4/4] ARM: defconfigs: enable SNVS driver in i.MX8 configs
2025-09-08 8:31 [PATCH 0/4] i.MX8M: Add SNVS support Sascha Hauer
` (2 preceding siblings ...)
2025-09-08 8:31 ` [PATCH 3/4] nvmem: snvs_lpgpr: set nvmem config name to snvs Sascha Hauer
@ 2025-09-08 8:31 ` Sascha Hauer
3 siblings, 0 replies; 5+ messages in thread
From: Sascha Hauer @ 2025-09-08 8:31 UTC (permalink / raw)
To: BAREBOX
i.MX8M now supports Secure Non Volatile Storage (SNVS). Enable the
driver in the i.MX8 defconfigs to give some more exposure.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/configs/imx_v8_defconfig | 1 +
arch/arm/configs/multi_v8_defconfig | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm/configs/imx_v8_defconfig b/arch/arm/configs/imx_v8_defconfig
index 19beacdefd0e9586de1327d84f792d43d2f37df9..5d93177a14b2940f114b1f69906518d988e6a08d 100644
--- a/arch/arm/configs/imx_v8_defconfig
+++ b/arch/arm/configs/imx_v8_defconfig
@@ -144,6 +144,7 @@ CONFIG_WATCHDOG_IMX=y
CONFIG_WATCHDOG_IMXULP=y
CONFIG_RAVE_SP_WATCHDOG=y
CONFIG_GPIO_PCA953X=y
+CONFIG_NVMEM_SNVS_LPGPR=y
CONFIG_IMX_OCOTP_ELE=y
CONFIG_RAVE_SP_EEPROM=y
CONFIG_REGULATOR=y
diff --git a/arch/arm/configs/multi_v8_defconfig b/arch/arm/configs/multi_v8_defconfig
index 73f43c1e31967310867b774360fe8f7fda00aacb..bd6fceb9416c474e2822b58c1b33dee86abdfffd 100644
--- a/arch/arm/configs/multi_v8_defconfig
+++ b/arch/arm/configs/multi_v8_defconfig
@@ -250,6 +250,7 @@ CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_ZYNQ=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_NVMEM_RMEM=y
+CONFIG_NVMEM_SNVS_LPGPR=y
CONFIG_IMX_OCOTP_ELE=y
CONFIG_RAVE_SP_EEPROM=y
CONFIG_REGULATOR=y
--
2.47.3
^ permalink raw reply [flat|nested] 5+ messages in thread