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From: Sascha Hauer <s.hauer@pengutronix.de>
To: BAREBOX <barebox@lists.infradead.org>
Subject: [PATCH v2 6/9] nvmem: ocotp: Fix SoC ID reading for i.MX8MP
Date: Mon, 17 Nov 2025 09:35:39 +0100	[thread overview]
Message-ID: <20251117-soc-uid-v2-6-a2415bf9133d@pengutronix.de> (raw)
In-Reply-To: <20251117-soc-uid-v2-0-a2415bf9133d@pengutronix.de>

On i.MX8MP the SoC ID is stored at 0x420/0x430, not on 0x410/0x420 as on
other i.MX8M SoCs. Also on i.MX8MP the SoC ID is 128bit and not 64bit
with the upper bits stored at 0xe00/0xe10.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/nvmem/ocotp.c | 33 +++++++++++++++++++++++++++------
 1 file changed, 27 insertions(+), 6 deletions(-)

diff --git a/drivers/nvmem/ocotp.c b/drivers/nvmem/ocotp.c
index 7bca27540417ad9ba0ce5c5f8ec43ad1c63638b9..affca938849d0d1a8dc347e3a0e1f3a380f1aab7 100644
--- a/drivers/nvmem/ocotp.c
+++ b/drivers/nvmem/ocotp.c
@@ -853,17 +853,38 @@ static int imx_ocotp_init_dt(struct ocotp_priv *priv)
 	return imx8m_feat_ctrl_init(priv->dev.parent, tester3, tester4, priv->data->feat);
 }
 
+#define IMX8MP_OCOTP_UID(n)	\
+	(OCOTP_WORD(0x420 + 0x10 * (n)) | OCOTP_BIT(0) | OCOTP_WIDTH(32))
+#define IMX8MP_OCOTP_UID_2(n)	\
+	(OCOTP_WORD(0xe00 + 0x10 * (n)) | OCOTP_BIT(0) | OCOTP_WIDTH(32))
+
 static void imx_ocotp_set_unique_machine_id(void)
 {
-	uint32_t unique_id_parts[UNIQUE_ID_NUM];
-	int i;
+	bool is_imx8mp = of_machine_is_compatible("fsl,imx8mp");
+	uint32_t uid[4];
+	int len;
 
-	for (i = 0; i < UNIQUE_ID_NUM; i++)
-		if (imx_ocotp_read_field(OCOTP_UNIQUE_ID(i),
-					 &unique_id_parts[i]))
+	if (is_imx8mp) {
+		if (imx_ocotp_read_field(IMX8MP_OCOTP_UID(0), &uid[0]))
+			return;
+		if (imx_ocotp_read_field(IMX8MP_OCOTP_UID(1), &uid[1]))
+			return;
+
+		if (imx_ocotp_read_field(IMX8MP_OCOTP_UID_2(0), &uid[2]))
+			return;
+		if (imx_ocotp_read_field(IMX8MP_OCOTP_UID_2(1), &uid[3]))
 			return;
+		len = sizeof(uid);
+	} else {
+		if (imx_ocotp_read_field(OCOTP_UNIQUE_ID(0), &uid[0]))
+			return;
+		if (imx_ocotp_read_field(OCOTP_UNIQUE_ID(1), &uid[1]))
+			return;
+
+		len = sizeof(uid) / 2;
+	}
 
-	machine_id_set_hashable(unique_id_parts, sizeof(unique_id_parts));
+	machine_id_set_hashable(uid, len);
 }
 
 static int imx_ocotp_probe(struct device *dev)

-- 
2.47.3




  parent reply	other threads:[~2025-11-17  8:36 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-17  8:35 [PATCH v2 0/9] Unify SoC UID and machine hashable data Sascha Hauer
2025-11-17  8:35 ` [PATCH v2 1/9] introduce SoC UID Sascha Hauer
2025-11-17 10:16   ` Jonas Rebmann
2025-11-17 11:28     ` Sascha Hauer
2025-11-17  8:35 ` [PATCH v2 2/9] soc: imx8mp: Soc ID is 128bit Sascha Hauer
2025-11-17  9:59   ` Jonas Rebmann
2025-11-17 11:02     ` Sascha Hauer
2025-11-17  8:35 ` [PATCH v2 3/9] ARM: i.MX6: print leading zero for SoC ID Sascha Hauer
2025-11-17  8:35 ` [PATCH v2 4/9] nvmem: bsec: call barebox_set_soc_uid() Sascha Hauer
2025-11-17  8:35 ` [PATCH v2 5/9] nvmem: imx-ocotp-ele: " Sascha Hauer
2025-11-17  8:35 ` Sascha Hauer [this message]
2025-11-17  8:35 ` [PATCH v2 7/9] nvmem: imx-ocotp: " Sascha Hauer
2025-11-17  8:35 ` [PATCH v2 8/9] soc: imx8m: register SoC UID Sascha Hauer
2025-11-17  8:35 ` [PATCH v2 9/9] Documentation: migration: add i.MX8MP SoC UID change note Sascha Hauer

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