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Tue, 20 Jan 2026 13:24:54 +0100 Received: from localhost ([::1] helo=dude05.red.stw.pengutronix.de) by dude05.red.stw.pengutronix.de with esmtp (Exim 4.98.2) (envelope-from ) id 1viAn0-00000002dE4-2Wmt; Tue, 20 Jan 2026 13:24:53 +0100 From: Ahmad Fatoum To: barebox@lists.infradead.org Cc: Ahmad Fatoum Date: Tue, 20 Jan 2026 13:24:45 +0100 Message-ID: <20260120122453.627239-3-a.fatoum@pengutronix.de> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260120122453.627239-1-a.fatoum@pengutronix.de> References: <20260120122453.627239-1-a.fatoum@pengutronix.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260120_122454_927154_4C375866 X-CRM114-Status: GOOD ( 10.97 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.whiteo.stw.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-4.0 required=4.0 tests=AWL,BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: [PATCH master 2/3] ARMv7: hyp: allow disabling support for invoking barebox in HYP mode X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.whiteo.stw.pengutronix.de) Older SoCs like the Cortex-A9 don't need this handling and disabling it allows us to save about 500 bytes. Signed-off-by: Ahmad Fatoum --- arch/arm/cpu/Kconfig | 10 ++++++++++ arch/arm/cpu/lowlevel_32.S | 2 +- arch/arm/cpu/start.c | 2 +- arch/arm/cpu/uncompress.c | 2 +- 4 files changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/Kconfig b/arch/arm/cpu/Kconfig index 04b1585679f3..47c116ea98c5 100644 --- a/arch/arm/cpu/Kconfig +++ b/arch/arm/cpu/Kconfig @@ -83,6 +83,16 @@ config CPU_V7 depends on 32BIT select CPU_32v7 +config CPU_V7VE + bool "ARMv7 Virtualization Extensions Support" + depends on CPU_V7 + default y + help + Say y here if it's possible for your CPU to be in HYP (hypervisor) + mode when entering barebox. + + If unsure, say y. + # ARMv8 config CPU_V8 bool "Generic ARMv8 support" diff --git a/arch/arm/cpu/lowlevel_32.S b/arch/arm/cpu/lowlevel_32.S index 5d524faf9cff..3b1dea5c67c0 100644 --- a/arch/arm/cpu/lowlevel_32.S +++ b/arch/arm/cpu/lowlevel_32.S @@ -12,7 +12,7 @@ ENTRY(arm_cpu_lowlevel_init) /* save sp, because possible HYP -> SVC transition below clobbers it */ mov r3, sp -#ifdef CONFIG_CPU_32v7 +#ifdef CONFIG_CPU_V7VE /* careful: the hyp install corrupts r0 and r1 */ bl __hyp_install #endif diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c index c2f14736dac5..bbcf465be4db 100644 --- a/arch/arm/cpu/start.c +++ b/arch/arm/cpu/start.c @@ -137,7 +137,7 @@ __noreturn void barebox_non_pbl_start(unsigned long membase, barebox_image_size, hd); - if (IS_ENABLED(CONFIG_CPU_V7)) + if (IS_ENABLED(CONFIG_CPU_V7VE)) armv7_hyp_install(); pbl_barebox_break(); diff --git a/arch/arm/cpu/uncompress.c b/arch/arm/cpu/uncompress.c index 9a9f391022c1..dffdd2c81232 100644 --- a/arch/arm/cpu/uncompress.c +++ b/arch/arm/cpu/uncompress.c @@ -121,7 +121,7 @@ void __noreturn barebox_pbl_start(unsigned long membase, unsigned long memsize, pr_debug("jumping to ELF entry point at 0x%p\n", barebox); - if (IS_ENABLED(CONFIG_CPU_V7) && boot_cpu_mode() == HYP_MODE) + if (IS_ENABLED(CONFIG_CPU_V7VE) && boot_cpu_mode() == HYP_MODE) armv7_switch_to_hyp(); barebox(membase, memsize, handoff_data); -- 2.47.3