* [PATCH v2 00/14] ARM: rockchip: Add initial RK3562 SoC support
@ 2026-01-30 5:16 Sohaib Mohamed
2026-01-30 5:16 ` [PATCH v2 01/14] " Sohaib Mohamed
` (13 more replies)
0 siblings, 14 replies; 23+ messages in thread
From: Sohaib Mohamed @ 2026-01-30 5:16 UTC (permalink / raw)
To: Sascha Hauer, BAREBOX; +Cc: Sohaib Mohamed, Ahmad Fatoum
All essential changes and additions required to boot the RK3562.
Includes board support for the RK3562-EVB2 and KickPi K3.
The GMAC driver is still missing from the upstream Linux device tree
and can be added in a future update. The rest is straightforward port from
the mainline Linux kernel.
---
Changes in v2:
- Remove unused header includes (globalvar.h and deep-probe.h) from board.c
- Fix "serial0:1500000n8" (squashed into the original commit)
- Link to v1: https://lore.barebox.org/r/20260116-barebox-kickpi-v1-0-eb253c439421@gmail.com/
---
To: Sascha Hauer <s.hauer@pengutronix.de>
To: open list:BAREBOX <barebox@lists.infradead.org>
Signed-off-by: Sohaib Mohamed <sohaib.amhmd@gmail.com>
---
Ahmad Fatoum (3):
clk: rockchip: add RK3562 clock and reset driver support
pinctrl: rockchip: sync driver with Linux
ARM: boards: Rockchip: add RK3562-EVB2 support
Sohaib Mohamed (11):
ARM: rockchip: Add initial RK3562 SoC support
ARM: boards: Rockchip: Add device tree for kickpi k3 board
ARM: rockchip: Add RK3562 KickPi K3 board support
pmdomain: rockchip: Add RK3562 power domain support
aiodev: rockchip_saradc: Add RK3562 support
phy: rockchip-inno-usb2: Add support for RK3562 PHY
rockchip-rng: Add RK3562 support
mci: sdhci: rockchip-dwcmshc: Add RK3562 support
nvmem: rockchip-otp: Add RK3562 support
phy: rockchip: inno-dsidphy: Add RK3562 support
phy: rockchip: naneng-combphy: Add RK3562 support
arch/arm/boards/Makefile | 2 +
arch/arm/boards/rockchip-rk3562-evb2/.gitignore | 1 +
arch/arm/boards/rockchip-rk3562-evb2/Makefile | 4 +
arch/arm/boards/rockchip-rk3562-evb2/board.c | 47 +
arch/arm/boards/rockchip-rk3562-evb2/lowlevel.c | 23 +
.../boards/rockchip-rk3562-kickpi-k3/.gitignore | 1 +
arch/arm/boards/rockchip-rk3562-kickpi-k3/Makefile | 4 +
arch/arm/boards/rockchip-rk3562-kickpi-k3/board.c | 44 +
.../boards/rockchip-rk3562-kickpi-k3/lowlevel.c | 23 +
arch/arm/configs/multi_v8_defconfig | 2 +
arch/arm/configs/rockchip_v8_defconfig | 2 +
arch/arm/dts/Makefile | 2 +
arch/arm/dts/rk3562-evb2-v10.dts | 9 +
arch/arm/dts/rk3562-kickpi-k3.dts | 10 +
arch/arm/dts/rk3562-kickpi-k3.dtsi | 452 ++++++++
arch/arm/dts/rk3562.dtsi | 40 +
arch/arm/mach-rockchip/Kconfig | 16 +
arch/arm/mach-rockchip/Makefile | 1 +
arch/arm/mach-rockchip/atf.c | 38 +
arch/arm/mach-rockchip/dmc.c | 33 +
arch/arm/mach-rockchip/rk3562.c | 20 +
arch/arm/mach-rockchip/rockchip.c | 4 +
common/Kconfig.debug_ll | 9 +
drivers/aiodev/rockchip_saradc.c | 7 +
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk-rk3562.c | 1098 ++++++++++++++++++++
drivers/clk/rockchip/clk.c | 2 +-
drivers/clk/rockchip/clk.h | 268 ++++-
drivers/clk/rockchip/rst-rk3562.c | 430 ++++++++
drivers/hw_random/rockchip-rng.c | 4 +
drivers/mci/rockchip-dwcmshc-sdhci.c | 3 +
drivers/mfd/syscon.c | 18 +
drivers/nvmem/rockchip-otp.c | 89 ++
drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c | 3 +
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 52 +-
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 161 +++
drivers/pinctrl/pinctrl-rockchip.c | 768 +++++++++++++-
drivers/pinctrl/pinctrl-rockchip.h | 52 +-
drivers/pmdomain/rockchip/pm-domains.c | 47 +
firmware/Makefile | 2 +
images/Makefile.rockchip | 2 +
include/mach/rockchip/atf.h | 6 +
include/mach/rockchip/debug_ll.h | 6 +
include/mach/rockchip/dmc.h | 1 +
include/mach/rockchip/rk3562-regs.h | 21 +
include/mach/rockchip/rockchip.h | 10 +
include/mfd/syscon.h | 8 +
47 files changed, 3797 insertions(+), 49 deletions(-)
---
base-commit: 15ea9c02849d8e53c69078c88fa6df57dcce864e
change-id: 20260130-barebox-kickpi-28d6466b6466
Best regards,
--
Sohaib Mohamed <sohaib.amhmd@gmail.com>
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH v2 01/14] ARM: rockchip: Add initial RK3562 SoC support 2026-01-30 5:16 [PATCH v2 00/14] ARM: rockchip: Add initial RK3562 SoC support Sohaib Mohamed @ 2026-01-30 5:16 ` Sohaib Mohamed 2026-01-30 5:16 ` [PATCH v2 02/14] clk: rockchip: add RK3562 clock and reset driver support Sohaib Mohamed ` (12 subsequent siblings) 13 siblings, 0 replies; 23+ messages in thread From: Sohaib Mohamed @ 2026-01-30 5:16 UTC (permalink / raw) To: Sascha Hauer, BAREBOX; +Cc: Sohaib Mohamed, Ahmad Fatoum Add basic RK3562 support including ATF integration, low-level init, debug UART configuration, and bootrom integration. Co-developed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sohaib Mohamed <sohaib.amhmd@gmail.com> --- arch/arm/mach-rockchip/Kconfig | 4 ++++ arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/atf.c | 38 +++++++++++++++++++++++++++++++++++++ arch/arm/mach-rockchip/dmc.c | 33 ++++++++++++++++++++++++++++++++ arch/arm/mach-rockchip/rk3562.c | 20 +++++++++++++++++++ arch/arm/mach-rockchip/rockchip.c | 4 ++++ common/Kconfig.debug_ll | 9 +++++++++ firmware/Makefile | 2 ++ include/mach/rockchip/atf.h | 6 ++++++ include/mach/rockchip/debug_ll.h | 6 ++++++ include/mach/rockchip/dmc.h | 1 + include/mach/rockchip/rk3562-regs.h | 21 ++++++++++++++++++++ include/mach/rockchip/rockchip.h | 10 ++++++++++ 13 files changed, 155 insertions(+) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 6f6e43101c..a91e7db72d 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -27,6 +27,10 @@ config ARCH_ROCKCHIP_V8 select CPU_V8 select ARM_ATF +config ARCH_RK3562 + bool + select ARCH_ROCKCHIP_V8 + config ARCH_RK3568 bool select ARCH_ROCKCHIP_V8 diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 40454d0284..9e2ef82221 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -4,6 +4,7 @@ obj-y += rockchip.o bootrom.o pbl-$(CONFIG_ARCH_ROCKCHIP_ATF) += atf.o obj-$(CONFIG_ARCH_RK3188) += rk3188.o obj-$(CONFIG_ARCH_RK3288) += rk3288.o +obj-pbl-$(CONFIG_ARCH_RK3562) += rk3562.o obj-pbl-$(CONFIG_ARCH_RK3568) += rk3568.o obj-pbl-$(CONFIG_ARCH_RK3576) += rk3576.o obj-pbl-$(CONFIG_ARCH_RK3588) += rk3588.o diff --git a/arch/arm/mach-rockchip/atf.c b/arch/arm/mach-rockchip/atf.c index c4ed84aae6..55d9918f3e 100644 --- a/arch/arm/mach-rockchip/atf.c +++ b/arch/arm/mach-rockchip/atf.c @@ -11,6 +11,7 @@ #include <mach/rockchip/dmc.h> #include <mach/rockchip/rockchip.h> #include <mach/rockchip/bootrom.h> +#include <mach/rockchip/rk3562-regs.h> #include <mach/rockchip/rk3568-regs.h> #include <mach/rockchip/rk3576-regs.h> #include <mach/rockchip/rk3588-regs.h> @@ -132,6 +133,43 @@ static uintptr_t rk_load_optee(uintptr_t bl32, const void *bl32_image, SOC##_BAREBOX_LOAD_ADDRESS, (uintptr_t)fdt); \ } while (0) \ +void rk3562_atf_load_bl31(void *fdt) +{ + rockchip_atf_load_bl31(RK3562, rk3562_bl31_bin, rk3562_bl32_bin, fdt); +} + +void __noreturn rk3562_barebox_entry(void *fdt) +{ + unsigned long membase, endmem; + + membase = RK3562_DRAM_BOTTOM; + endmem = rk3562_ram0_size(); + + rk_scratch = (void *)arm_mem_scratch(endmem); + + if (current_el() == 3) { + rk3562_lowlevel_init(); + rockchip_store_bootrom_iram(IOMEM(RK3562_IRAM_BASE)); + + /* + * The downstream TF-A doesn't cope with our device tree when + * CONFIG_OF_OVERLAY_LIVE is enabled, supposedly because it is + * too big for some reason. Otherwise it doesn't have any visible + * effect if we pass a device tree or not, except that the TF-A + * fills in the ethernet MAC address into the device tree. + * The upstream TF-A doesn't use the device tree at all. + * + * Pass NULL for now until we have a good reason to pass a real + * device tree. + */ + rk3562_atf_load_bl31(NULL); + /* not reached when CONFIG_ARCH_ROCKCHIP_ATF */ + } + + optee_set_membase(rk_scratch_get_optee_hdr()); + barebox_arm_entry(membase, endmem - membase, fdt); +} + void rk3568_atf_load_bl31(void *fdt) { rockchip_atf_load_bl31(RK3568, rk3568_bl31_bin, rk3568_bl32_bin, fdt); diff --git a/arch/arm/mach-rockchip/dmc.c b/arch/arm/mach-rockchip/dmc.c index 3cb17b9694..4c0b9c3975 100644 --- a/arch/arm/mach-rockchip/dmc.c +++ b/arch/arm/mach-rockchip/dmc.c @@ -16,12 +16,16 @@ #include <mach/rockchip/dmc.h> #include <mach/rockchip/atf.h> #include <mach/rockchip/rk3399-regs.h> +#include <mach/rockchip/rk3562-regs.h> #include <mach/rockchip/rk3568-regs.h> #include <mach/rockchip/rk3576-regs.h> #define RK3399_PMUGRF_OS_REG2 0x308 #define RK3399_PMUGRF_OS_REG3 0x30C +#define RK3562_PMUGRF_OS_REG2 0x208 +#define RK3562_PMUGRF_OS_REG3 0x20c + #define RK3568_PMUGRF_OS_REG2 0x208 #define RK3568_PMUGRF_OS_REG3 0x20c @@ -29,6 +33,7 @@ #define RK3576_PMUGRF_OS_REG3 0x20c #define RK3399_INT_REG_START 0xf0000000 +#define RK3562_INT_REG_START RK3399_INT_REG_START #define RK3568_INT_REG_START RK3399_INT_REG_START #define RK3576_INT_REG_START 0x10000000 #define RK3588_INT_REG_START RK3399_INT_REG_START @@ -155,6 +160,23 @@ resource_size_t rk3399_ram0_size(void) return size; } +resource_size_t rk3562_ram0_size(void) +{ + void __iomem *pmugrf = IOMEM(RK3562_PMUGRF_BASE); + u32 sys_reg2, sys_reg3; + resource_size_t size; + + sys_reg2 = readl(pmugrf + RK3562_PMUGRF_OS_REG2); + sys_reg3 = readl(pmugrf + RK3562_PMUGRF_OS_REG3); + + size = rockchip_sdram_size(sys_reg2, sys_reg3); + size = min_t(resource_size_t, RK3562_INT_REG_START, size); + + pr_debug("%s() = %llu\n", __func__, (u64)size); + + return size; +} + resource_size_t rk3568_ram0_size(void) { void __iomem *pmugrf = IOMEM(RK3568_PMUGRF_BASE); @@ -314,6 +336,13 @@ static const struct rockchip_dmc_drvdata rk3399_drvdata = { .membase = RK3399_DRAM_BOTTOM, }; +static const struct rockchip_dmc_drvdata rk3562_drvdata = { + .os_reg2 = RK3562_PMUGRF_OS_REG2, + .os_reg3 = RK3562_PMUGRF_OS_REG3, + .internal_registers_start = RK3562_INT_REG_START, + .membase = RK3562_DRAM_BOTTOM, +}; + static const struct rockchip_dmc_drvdata rk3568_drvdata = { .os_reg2 = RK3568_PMUGRF_OS_REG2, .os_reg3 = RK3568_PMUGRF_OS_REG3, @@ -342,6 +371,10 @@ static struct of_device_id rockchip_dmc_dt_ids[] = { .compatible = "rockchip,rk3399-dmc", .data = &rk3399_drvdata, }, + { + .compatible = "rockchip,rk3562-dmc", + .data = &rk3562_drvdata, + }, { .compatible = "rockchip,rk3568-dmc", .data = &rk3568_drvdata, diff --git a/arch/arm/mach-rockchip/rk3562.c b/arch/arm/mach-rockchip/rk3562.c new file mode 100644 index 0000000000..9ab5b82695 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3562.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <common.h> +#include <io.h> +#include <bootsource.h> +#include <mach/rockchip/rk3562-regs.h> +#include <mach/rockchip/rockchip.h> +#include <asm/barebox-arm-head.h> +#include <mach/rockchip/bootrom.h> + +void rk3562_lowlevel_init(void) +{ + arm_cpu_lowlevel_init(); +} + +int rk3562_init(void) +{ + rockchip_parse_bootrom_iram(rockchip_scratch_space()->iram); + + return 0; +} diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c index 0828f0fa72..ce1c06ff38 100644 --- a/arch/arm/mach-rockchip/rockchip.c +++ b/arch/arm/mach-rockchip/rockchip.c @@ -17,6 +17,8 @@ int rockchip_soc(void) __rockchip_soc = 3188; else if (of_machine_is_compatible("rockchip,rk3288")) __rockchip_soc = 3288; + else if (of_machine_is_compatible("rockchip,rk3562")) + __rockchip_soc = 3562; else if (of_machine_is_compatible("rockchip,rk3566")) __rockchip_soc = 3566; else if (of_machine_is_compatible("rockchip,rk3568")) @@ -49,6 +51,8 @@ static int rockchip_init(void) return rk3188_init(); case 3288: return rk3288_init(); + case 3562: + return rk3562_init(); case 3566: return rk3568_init(); case 3568: diff --git a/common/Kconfig.debug_ll b/common/Kconfig.debug_ll index a08d29859d..75d500862b 100644 --- a/common/Kconfig.debug_ll +++ b/common/Kconfig.debug_ll @@ -198,6 +198,14 @@ config DEBUG_ROCKCHIP_RK3288_UART Say Y here if you want kernel low-level debugging support on RK3288. +config DEBUG_ROCKCHIP_RK3562_UART + bool "RK3562 Debug UART" + depends on ARCH_RK3562 + select DEBUG_ROCKCHIP_UART + help + Say Y here if you want kernel low-level debugging support + on RK3562. + config DEBUG_ROCKCHIP_RK3568_UART bool "RK3568 Debug UART" depends on ARCH_RK3568 @@ -430,6 +438,7 @@ config DEBUG_OMAP_UART_PORT config DEBUG_ROCKCHIP_UART_PORT int "RK3xxx UART debug port" if DEBUG_ROCKCHIP_RK3188_UART || \ DEBUG_ROCKCHIP_RK3288_UART || \ + DEBUG_ROCKCHIP_RK3562_UART || \ DEBUG_ROCKCHIP_RK3568_UART || \ DEBUG_ROCKCHIP_RK3576_UART || \ DEBUG_ROCKCHIP_RK3588_UART || \ diff --git a/firmware/Makefile b/firmware/Makefile index 163055554d..f0204a8bf6 100644 --- a/firmware/Makefile +++ b/firmware/Makefile @@ -28,12 +28,14 @@ fw-external-$(CONFIG_FIRMWARE_IMX8MP_OPTEE) += imx8mp-bl32.bin fw-external-$(CONFIG_FIRMWARE_IMX93_OPTEE) += imx93-bl32.bin \ mx93a1-ahab-container.img fw-external-$(CONFIG_FIRMWARE_IMX93_OPTEE_A0) += mx93a0-ahab-container.img +pbl-firmware-$(CONFIG_ARCH_RK3562) += rk3562-bl31.bin pbl-firmware-$(CONFIG_ARCH_RK3568) += rk3568-bl31.bin pbl-firmware-$(CONFIG_ARCH_RK3576) += rk3576-bl31.bin pbl-firmware-$(CONFIG_ARCH_RK3588) += rk3588-bl31.bin ifeq ($(CONFIG_ARCH_ROCKCHIP_OPTEE),y) # We install BL31 & BL32 while already running in DRAM, # so fw-external is not needed +pbl-firmware-$(CONFIG_ARCH_RK3562) += rk3562-bl32.bin pbl-firmware-$(CONFIG_ARCH_RK3568) += rk3568-bl32.bin pbl-firmware-$(CONFIG_ARCH_RK3576) += rk3576-bl32.bin pbl-firmware-$(CONFIG_ARCH_RK3588) += rk3588-bl32.bin diff --git a/include/mach/rockchip/atf.h b/include/mach/rockchip/atf.h index 8fc2a4bebe..b8627a3598 100644 --- a/include/mach/rockchip/atf.h +++ b/include/mach/rockchip/atf.h @@ -5,6 +5,7 @@ /* First usable DRAM address. Lower mem is used for ATF and OP-TEE */ #define RK3399_DRAM_BOTTOM 0xa00000 +#define RK3562_DRAM_BOTTOM 0xa00000 #define RK3568_DRAM_BOTTOM 0xa00000 #define RK3576_DRAM_BOTTOM 0x40a00000 #define RK3588_DRAM_BOTTOM 0xa00000 @@ -19,6 +20,7 @@ * The values are taken from rkbin/RKTRUST/RK3*.ini: [BL32_OPTION] ADDR */ #define RK3399_OPTEE_LOAD_ADDRESS 0x8400000 +#define RK3562_OPTEE_LOAD_ADDRESS 0x8400000 #define RK3568_OPTEE_LOAD_ADDRESS 0x8400000 #define RK3576_OPTEE_LOAD_ADDRESS 0x8400000 #define RK3588_OPTEE_LOAD_ADDRESS 0x8400000 @@ -35,22 +37,26 @@ * OP-TEE jumps to after initialization. */ #define RK3399_BAREBOX_LOAD_ADDRESS (RK3399_DRAM_BOTTOM + 1024*1024) +#define RK3562_BAREBOX_LOAD_ADDRESS (RK3562_DRAM_BOTTOM + 1024*1024) #define RK3568_BAREBOX_LOAD_ADDRESS (RK3568_DRAM_BOTTOM + 1024*1024) #define RK3576_BAREBOX_LOAD_ADDRESS (RK3576_DRAM_BOTTOM + 1024*1024) #define RK3588_BAREBOX_LOAD_ADDRESS (RK3588_DRAM_BOTTOM + 1024*1024) #ifndef __ASSEMBLY__ #ifdef CONFIG_ARCH_ROCKCHIP_ATF +void rk3562_atf_load_bl31(void *fdt); void rk3568_atf_load_bl31(void *fdt); void rk3576_atf_load_bl31(void *fdt); void rk3588_atf_load_bl31(void *fdt); #else +static inline void rk3562_atf_load_bl31(void *fdt) { } static inline void rk3568_atf_load_bl31(void *fdt) { } static inline void rk3576_atf_load_bl31(void *fdt) { } static inline void rk3588_atf_load_bl31(void *fdt) { } #endif #endif +void __noreturn rk3562_barebox_entry(void *fdt); void __noreturn rk3568_barebox_entry(void *fdt); void __noreturn rk3576_barebox_entry(void *fdt); void __noreturn rk3588_barebox_entry(void *fdt); diff --git a/include/mach/rockchip/debug_ll.h b/include/mach/rockchip/debug_ll.h index a51c2cda0b..941d1505e5 100644 --- a/include/mach/rockchip/debug_ll.h +++ b/include/mach/rockchip/debug_ll.h @@ -7,6 +7,7 @@ #include <io.h> #include <mach/rockchip/rk3188-regs.h> #include <mach/rockchip/rk3288-regs.h> +#include <mach/rockchip/rk3562-regs.h> #include <mach/rockchip/rk3568-regs.h> #include <mach/rockchip/rk3576-regs.h> #include <mach/rockchip/rk3588-regs.h> @@ -24,6 +25,11 @@ #define RK_DEBUG_UART_CLOCK 24000000 #define RK_DEBUG_SOC RK3288 +#elif defined CONFIG_DEBUG_ROCKCHIP_RK3562_UART + +#define RK_DEBUG_UART_CLOCK 24000000 +#define RK_DEBUG_SOC RK3562 + #elif defined CONFIG_DEBUG_ROCKCHIP_RK3568_UART #define RK_DEBUG_UART_CLOCK 24000000 diff --git a/include/mach/rockchip/dmc.h b/include/mach/rockchip/dmc.h index a379ba3294..ddcf989a30 100644 --- a/include/mach/rockchip/dmc.h +++ b/include/mach/rockchip/dmc.h @@ -84,6 +84,7 @@ enum { #define SYS_REG_CS1_COL_MASK 3 resource_size_t rk3399_ram0_size(void); +resource_size_t rk3562_ram0_size(void); resource_size_t rk3568_ram0_size(void); resource_size_t rk3576_ram0_size(void); resource_size_t rk3588_ram0_size(void); diff --git a/include/mach/rockchip/rk3562-regs.h b/include/mach/rockchip/rk3562-regs.h new file mode 100644 index 0000000000..e0a06e6427 --- /dev/null +++ b/include/mach/rockchip/rk3562-regs.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MACH_RK3562_REGS_H +#define __MACH_RK3562_REGS_H + +/* UART */ +#define RK3562_UART0_BASE 0xff210000 +#define RK3562_UART1_BASE 0xff670000 +#define RK3562_UART2_BASE 0xff680000 +#define RK3562_UART3_BASE 0xff690000 +#define RK3562_UART4_BASE 0xff6a0000 +#define RK3562_UART5_BASE 0xff6b0000 +#define RK3562_UART6_BASE 0xff6c0000 +#define RK3562_UART7_BASE 0xff6d0000 +#define RK3562_UART8_BASE 0xff6e0000 +#define RK3562_UART9_BASE 0xff6f0000 + +#define RK3562_IRAM_BASE 0xfe480000 +#define RK3562_PMUGRF_BASE 0xff010000 + +#endif /* __MACH_RK3562_REGS_H */ diff --git a/include/mach/rockchip/rockchip.h b/include/mach/rockchip/rockchip.h index bb9597cb01..bf115b5576 100644 --- a/include/mach/rockchip/rockchip.h +++ b/include/mach/rockchip/rockchip.h @@ -23,6 +23,15 @@ static inline int rk3288_init(void) } #endif +#ifdef CONFIG_ARCH_RK3562 +int rk3562_init(void); +#else +static inline int rk3562_init(void) +{ + return -ENOTSUPP; +} +#endif + #ifdef CONFIG_ARCH_RK3568 int rk3568_init(void); #define PMU_GRF 0xfdc20000 @@ -53,6 +62,7 @@ static inline int rk3588_init(void) } #endif +void rk3562_lowlevel_init(void); void rk3568_lowlevel_init(void); void rk3576_lowlevel_init(void); void rk3588_lowlevel_init(void); -- 2.43.0 ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 02/14] clk: rockchip: add RK3562 clock and reset driver support 2026-01-30 5:16 [PATCH v2 00/14] ARM: rockchip: Add initial RK3562 SoC support Sohaib Mohamed 2026-01-30 5:16 ` [PATCH v2 01/14] " Sohaib Mohamed @ 2026-01-30 5:16 ` Sohaib Mohamed 2026-01-30 5:16 ` [PATCH v2 03/14] pinctrl: rockchip: sync driver with Linux Sohaib Mohamed ` (11 subsequent siblings) 13 siblings, 0 replies; 23+ messages in thread From: Sohaib Mohamed @ 2026-01-30 5:16 UTC (permalink / raw) To: Sascha Hauer, BAREBOX; +Cc: Sohaib Mohamed, Ahmad Fatoum From: Ahmad Fatoum <a.fatoum@pengutronix.de> Add clock and reset controller support for RK3562 SoC with PLL configurations and clock trees for all power domains. During boot, the following errors were seen: ERROR: rockchip_rk3036_pll_set_rate: Invalid rate : 983040000 for pll clk pll_hpll ERROR: clk: couldn't set hpll clk rate to 983040000 (-22), current rate: 1000000000 The driver has not been fully tested yet and requires further testing and fixes. The current setup is kept as-is for now to avoid changing the driver without proper testing. Its enough for booting for now, especially the current rate is not far from this rate. Co-developed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sohaib Mohamed <sohaib.amhmd@gmail.com> --- drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk-rk3562.c | 1098 +++++++++++++++++++++++++++++++++++++ drivers/clk/rockchip/clk.c | 2 +- drivers/clk/rockchip/clk.h | 268 ++++++++- drivers/clk/rockchip/rst-rk3562.c | 430 +++++++++++++++ 5 files changed, 1794 insertions(+), 5 deletions(-) diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index b644926898..cfbefb88b0 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -10,6 +10,7 @@ obj-y += gate-link.o obj-$(CONFIG_RESET_CONTROLLER) += softrst.o obj-$(CONFIG_ARCH_RK3188) += clk-rk3188.o obj-$(CONFIG_ARCH_RK3288) += clk-rk3288.o +obj-$(CONFIG_ARCH_RK3562) += clk-rk3562.o rst-rk3562.o obj-$(CONFIG_ARCH_RK3568) += clk-rk3568.o obj-$(CONFIG_ARCH_RK3576) += clk-rk3576.o rst-rk3576.o obj-$(CONFIG_ARCH_RK3588) += clk-rk3588.o rst-rk3588.o diff --git a/drivers/clk/rockchip/clk-rk3562.c b/drivers/clk/rockchip/clk-rk3562.c new file mode 100644 index 0000000000..867a852f4f --- /dev/null +++ b/drivers/clk/rockchip/clk-rk3562.c @@ -0,0 +1,1098 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-Comment: Origin-URL: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/rockchip/clk-rk3562.c?id=f863d4cc79a7e2f8c734d1fac84dc275805f41c7 +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * Author: Elaine Zhang <zhangqing@rock-chips.com> + * Author: Finley Xiao <finley.xiao@rock-chips.com> + */ + +#include <common.h> +#include <linux/clk.h> +#include <of.h> +#include <of_address.h> +#include <linux/barebox-wrapper.h> +#include <init.h> +#include <linux/spinlock.h> +#include <of_device.h> +#include <dt-bindings/clock/rockchip,rk3562-cru.h> +#include "clk.h" + +#define RK3562_GRF_SOC_STATUS0 0x430 +#define ROCKCHIP_PLL_ALLOW_POWER_DOWN BIT(2) + +enum rk3562_plls { + apll, gpll, vpll, hpll, cpll, dpll, +}; + +static struct rockchip_pll_rate_table rk3562_pll_rates[] = { + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ + RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0), + RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0), + RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0), + RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0), + RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0), + RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0), + RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0), + RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0), + RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0), + RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0), + RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0), + RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0), + RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), + RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0), + RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0), + RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0), + RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0), + RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0), + RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0), + RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0), + RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0), + RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0), + RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0), + RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0), + RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0), + RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0), + RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0), + RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0), + RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0), + RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0), + RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0), + RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), + RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0), + RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0), + RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), + RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0), + RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), + RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), + RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0), + RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0), + RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0), + RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0), + RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0), + RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0), + RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), + RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0), + RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), + RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0), + RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0), + RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0), + RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0), + RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0), + { /* sentinel */ }, +}; + +PNAME(mux_pll_p) = { "xin24m" }; +PNAME(gpll_cpll_p) = { "gpll", "cpll" }; +PNAME(gpll_cpll_hpll_p) = { "gpll", "cpll", "hpll" }; +PNAME(gpll_cpll_pvtpll_dmyapll_p) = { "gpll", "cpll", "log_pvtpll", "dummy_apll" }; +PNAME(gpll_cpll_hpll_xin24m_p) = { "gpll", "cpll", "hpll", "xin24m" }; +PNAME(gpll_cpll_vpll_dmyhpll_p) = { "gpll", "cpll", "vpll", "dummy_hpll" }; +PNAME(gpll_dmyhpll_vpll_apll_p) = { "gpll", "dummy_hpll", "vpll", "apll" }; +PNAME(gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" }; +PNAME(gpll_cpll_xin24m_dmyapll_p) = { "gpll", "cpll", "xin24m", "dummy_apll" }; +PNAME(gpll_cpll_xin24m_dmyhpll_p) = { "gpll", "cpll", "xin24m", "dummy_hpll" }; +PNAME(vpll_dmyhpll_gpll_cpll_p) = { "vpll", "dummy_hpll", "gpll", "cpll" }; +PNAME(mux_xin24m_32k_p) = { "xin24m", "clk_rtc_32k" }; +PNAME(mux_50m_xin24m_p) = { "clk_matrix_50m_src", "xin24m" }; +PNAME(mux_100m_50m_xin24m_p) = { "clk_matrix_100m_src", "clk_matrix_50m_src", "xin24m" }; +PNAME(mux_125m_xin24m_p) = { "clk_matrix_125m_src", "xin24m" }; +PNAME(mux_200m_xin24m_32k_p) = { "clk_200m_pmu", "xin24m", "clk_rtc_32k" }; +PNAME(mux_200m_100m_p) = { "clk_matrix_200m_src", "clk_matrix_100m_src" }; +PNAME(mux_200m_100m_50m_xin24m_p) = { "clk_matrix_200m_src", "clk_matrix_100m_src", "clk_matrix_50m_src", "xin24m" }; +PNAME(clk_sai0_p) = { "clk_sai0_src", "clk_sai0_frac", "xin_osc0_half", "mclk_sai0_from_io" }; +PNAME(mclk_sai0_out2io_p) = { "mclk_sai0", "xin_osc0_half" }; +PNAME(clk_sai1_p) = { "clk_sai1_src", "clk_sai1_frac", "xin_osc0_half", "mclk_sai1_from_io" }; +PNAME(mclk_sai1_out2io_p) = { "mclk_sai1", "xin_osc0_half" }; +PNAME(clk_sai2_p) = { "clk_sai2_src", "clk_sai2_frac", "xin_osc0_half", "mclk_sai2_from_io" }; +PNAME(mclk_sai2_out2io_p) = { "mclk_sai2", "xin_osc0_half" }; +PNAME(clk_spdif_p) = { "clk_spdif_src", "clk_spdif_frac", "xin_osc0_half" }; +PNAME(clk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" }; +PNAME(clk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" }; +PNAME(clk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" }; +PNAME(clk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" }; +PNAME(clk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" }; +PNAME(clk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" }; +PNAME(clk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" }; +PNAME(clk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" }; +PNAME(clk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" }; +PNAME(clk_rtc32k_pmu_p) = { "clk_rtc32k_frac", "xin32k", "clk_32k_pvtm" }; +PNAME(clk_pmu1_uart0_p) = { "clk_pmu1_uart0_src", "clk_pmu1_uart0_frac", "xin24m" }; +PNAME(clk_pipephy_ref_p) = { "clk_pipephy_div", "clk_pipephy_xin24m" }; +PNAME(clk_usbphy_ref_p) = { "clk_usb2phy_xin24m", "clk_24m_sscsrc" }; +PNAME(clk_mipidsi_ref_p) = { "clk_mipidsiphy_xin24m", "clk_24m_sscsrc" }; + +static struct rockchip_pll_clock rk3562_pll_clks[] __initdata = { + [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, + 0, RK3562_PLL_CON(0), + RK3562_MODE_CON, 0, 0, + ROCKCHIP_PLL_ALLOW_POWER_DOWN, rk3562_pll_rates), + [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, + 0, RK3562_PLL_CON(24), + RK3562_MODE_CON, 2, 3, 0, rk3562_pll_rates), + [vpll] = PLL(pll_rk3328, PLL_VPLL, "vpll", mux_pll_p, + 0, RK3562_PLL_CON(32), + RK3562_MODE_CON, 6, 4, + ROCKCHIP_PLL_ALLOW_POWER_DOWN, rk3562_pll_rates), + [hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll", mux_pll_p, + 0, RK3562_PLL_CON(40), + RK3562_MODE_CON, 8, 5, + ROCKCHIP_PLL_ALLOW_POWER_DOWN, rk3562_pll_rates), + [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, + 0, RK3562_PMU1_PLL_CON(0), + RK3562_PMU1_MODE_CON, 0, 2, 0, rk3562_pll_rates), + [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, + CLK_IS_CRITICAL, RK3562_SUBDDR_PLL_CON(0), + RK3562_SUBDDR_MODE_CON, 0, 1, 0, NULL), +}; + +#define MFLAGS CLK_MUX_HIWORD_MASK +#define DFLAGS CLK_DIVIDER_HIWORD_MASK +#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) + +static struct rockchip_clk_branch rk3562_clk_sai0_fracmux __initdata = + MUX(CLK_SAI0, "clk_sai0", clk_sai0_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(3), 6, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_sai1_fracmux __initdata = + MUX(CLK_SAI1, "clk_sai1", clk_sai1_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(5), 6, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_sai2_fracmux __initdata = + MUX(CLK_SAI2, "clk_sai2", clk_sai2_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(8), 6, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_spdif_fracmux __initdata = + MUX(CLK_SPDIF, "clk_spdif", clk_spdif_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(15), 6, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_uart1_fracmux __initdata = + MUX(CLK_UART1, "clk_uart1", clk_uart1_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(21), 14, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_uart2_fracmux __initdata = + MUX(CLK_UART2, "clk_uart2", clk_uart2_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(23), 14, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_uart3_fracmux __initdata = + MUX(CLK_UART3, "clk_uart3", clk_uart3_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(25), 14, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_uart4_fracmux __initdata = + MUX(CLK_UART4, "clk_uart4", clk_uart4_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(27), 14, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_uart5_fracmux __initdata = + MUX(CLK_UART5, "clk_uart5", clk_uart5_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(29), 14, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_uart6_fracmux __initdata = + MUX(CLK_UART6, "clk_uart6", clk_uart6_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(31), 14, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_uart7_fracmux __initdata = + MUX(CLK_UART7, "clk_uart7", clk_uart7_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(33), 14, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_uart8_fracmux __initdata = + MUX(CLK_UART8, "clk_uart8", clk_uart8_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(35), 14, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_uart9_fracmux __initdata = + MUX(CLK_UART9, "clk_uart9", clk_uart9_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(37), 14, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_rtc32k_pmu_fracmux __initdata = + MUX(CLK_RTC_32K, "clk_rtc_32k", clk_rtc32k_pmu_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3562_PMU0_CLKSEL_CON(1), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_pmu1_uart0_fracmux __initdata = + MUX(CLK_PMU1_UART0, "clk_pmu1_uart0", clk_pmu1_uart0_p, CLK_SET_RATE_PARENT, + RK3562_PMU1_CLKSEL_CON(2), 6, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_branches[] __initdata = { + /* + * CRU Clock-Architecture + */ + /* PD_TOP */ + COMPOSITE(CLK_MATRIX_50M_SRC, "clk_matrix_50m_src", gpll_cpll_p, 0, + RK3562_CLKSEL_CON(0), 7, 1, MFLAGS, 0, 5, DFLAGS, + RK3562_CLKGATE_CON(0), 0, GFLAGS), + COMPOSITE(CLK_MATRIX_100M_SRC, "clk_matrix_100m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3562_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 4, DFLAGS, + RK3562_CLKGATE_CON(0), 1, GFLAGS), + COMPOSITE(CLK_MATRIX_125M_SRC, "clk_matrix_125m_src", gpll_cpll_p, 0, + RK3562_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 4, DFLAGS, + RK3562_CLKGATE_CON(0), 2, GFLAGS), + COMPOSITE(CLK_MATRIX_200M_SRC, "clk_matrix_200m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3562_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 4, DFLAGS, + RK3562_CLKGATE_CON(0), 4, GFLAGS), + COMPOSITE(CLK_MATRIX_300M_SRC, "clk_matrix_300m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3562_CLKSEL_CON(3), 7, 1, MFLAGS, 0, 4, DFLAGS, + RK3562_CLKGATE_CON(0), 6, GFLAGS), + COMPOSITE(ACLK_TOP, "aclk_top", gpll_cpll_p, CLK_IS_CRITICAL, + RK3562_CLKSEL_CON(5), 7, 1, MFLAGS, 0, 4, DFLAGS, + RK3562_CLKGATE_CON(1), 0, GFLAGS), + COMPOSITE(ACLK_TOP_VIO, "aclk_top_vio", gpll_cpll_p, 0, + RK3562_CLKSEL_CON(5), 15, 1, MFLAGS, 8, 4, DFLAGS, + RK3562_CLKGATE_CON(1), 1, GFLAGS), + COMPOSITE(CLK_24M_SSCSRC, "clk_24m_sscsrc", vpll_dmyhpll_gpll_cpll_p, 0, + RK3562_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS, + RK3562_CLKGATE_CON(1), 9, GFLAGS), + COMPOSITE(CLK_CAM0_OUT2IO, "clk_cam0_out2io", gpll_cpll_xin24m_dmyapll_p, 0, + RK3562_CLKSEL_CON(8), 6, 2, MFLAGS, 0, 6, DFLAGS, + RK3562_CLKGATE_CON(1), 12, GFLAGS), + COMPOSITE(CLK_CAM1_OUT2IO, "clk_cam1_out2io", gpll_cpll_xin24m_dmyapll_p, 0, + RK3562_CLKSEL_CON(8), 14, 2, MFLAGS, 8, 6, DFLAGS, + RK3562_CLKGATE_CON(1), 13, GFLAGS), + COMPOSITE(CLK_CAM2_OUT2IO, "clk_cam2_out2io", gpll_cpll_xin24m_dmyapll_p, 0, + RK3562_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 6, DFLAGS, + RK3562_CLKGATE_CON(1), 14, GFLAGS), + COMPOSITE(CLK_CAM3_OUT2IO, "clk_cam3_out2io", gpll_cpll_xin24m_dmyapll_p, 0, + RK3562_CLKSEL_CON(9), 14, 2, MFLAGS, 8, 6, DFLAGS, + RK3562_CLKGATE_CON(1), 15, GFLAGS), + FACTOR(0, "xin_osc0_half", "xin24m", 0, 1, 2), + + /* PD_BUS */ + COMPOSITE(ACLK_BUS, "aclk_bus", gpll_cpll_p, CLK_IS_CRITICAL, + RK3562_CLKSEL_CON(40), 7, 1, MFLAGS, 0, 5, DFLAGS, + RK3562_CLKGATE_CON(18), 0, GFLAGS), + COMPOSITE(HCLK_BUS, "hclk_bus", gpll_cpll_p, CLK_IS_CRITICAL, + RK3562_CLKSEL_CON(40), 15, 1, MFLAGS, 8, 6, DFLAGS, + RK3562_CLKGATE_CON(18), 1, GFLAGS), + COMPOSITE(PCLK_BUS, "pclk_bus", gpll_cpll_p, CLK_IS_CRITICAL, + RK3562_CLKSEL_CON(41), 7, 1, MFLAGS, 0, 5, DFLAGS, + RK3562_CLKGATE_CON(18), 2, GFLAGS), + GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, + RK3562_CLKGATE_CON(19), 0, GFLAGS), + GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0, + RK3562_CLKGATE_CON(19), 1, GFLAGS), + GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0, + RK3562_CLKGATE_CON(19), 2, GFLAGS), + GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus", 0, + RK3562_CLKGATE_CON(19), 3, GFLAGS), + GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus", 0, + RK3562_CLKGATE_CON(19), 4, GFLAGS), + COMPOSITE_NODIV(CLK_I2C, "clk_i2c", mux_200m_100m_50m_xin24m_p, 0, + RK3562_CLKSEL_CON(41), 8, 2, MFLAGS, + RK3562_CLKGATE_CON(19), 5, GFLAGS), + GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 0, + RK3562_CLKGATE_CON(19), 6, GFLAGS), + GATE(CLK_I2C2, "clk_i2c2", "clk_i2c", 0, + RK3562_CLKGATE_CON(19), 7, GFLAGS), + GATE(CLK_I2C3, "clk_i2c3", "clk_i2c", 0, + RK3562_CLKGATE_CON(19), 8, GFLAGS), + GATE(CLK_I2C4, "clk_i2c4", "clk_i2c", 0, + RK3562_CLKGATE_CON(19), 9, GFLAGS), + GATE(CLK_I2C5, "clk_i2c5", "clk_i2c", 0, + RK3562_CLKGATE_CON(19), 10, GFLAGS), + COMPOSITE_NODIV(DCLK_BUS_GPIO, "dclk_bus_gpio", mux_xin24m_32k_p, 0, + RK3562_CLKSEL_CON(41), 15, 1, MFLAGS, + RK3562_CLKGATE_CON(20), 4, GFLAGS), + GATE(DCLK_BUS_GPIO3, "dclk_bus_gpio3", "dclk_bus_gpio", 0, + RK3562_CLKGATE_CON(20), 5, GFLAGS), + GATE(DCLK_BUS_GPIO4, "dclk_bus_gpio4", "dclk_bus_gpio", 0, + RK3562_CLKGATE_CON(20), 6, GFLAGS), + GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 0, + RK3562_CLKGATE_CON(21), 0, GFLAGS), + GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0, + RK3562_CLKGATE_CON(21), 1, GFLAGS), + GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0, + RK3562_CLKGATE_CON(21), 2, GFLAGS), + GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0, + RK3562_CLKGATE_CON(21), 3, GFLAGS), + GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0, + RK3562_CLKGATE_CON(21), 4, GFLAGS), + GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0, + RK3562_CLKGATE_CON(21), 5, GFLAGS), + GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0, + RK3562_CLKGATE_CON(21), 6, GFLAGS), + GATE(PCLK_STIMER, "pclk_stimer", "pclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(21), 7, GFLAGS), + GATE(CLK_STIMER0, "clk_stimer0", "xin24m", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(21), 8, GFLAGS), + GATE(CLK_STIMER1, "clk_stimer1", "xin24m", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(21), 9, GFLAGS), + GATE(PCLK_WDTNS, "pclk_wdtns", "pclk_bus", 0, + RK3562_CLKGATE_CON(22), 0, GFLAGS), + GATE(CLK_WDTNS, "clk_wdtns", "xin24m", 0, + RK3562_CLKGATE_CON(22), 1, GFLAGS), + GATE(PCLK_GRF, "pclk_grf", "pclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(22), 2, GFLAGS), + GATE(PCLK_SGRF, "pclk_sgrf", "pclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(22), 3, GFLAGS), + GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0, + RK3562_CLKGATE_CON(22), 4, GFLAGS), + GATE(PCLK_INTC, "pclk_intc", "pclk_bus", 0, + RK3562_CLKGATE_CON(22), 5, GFLAGS), + GATE(ACLK_BUS_GIC400, "aclk_bus_gic400", "aclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(22), 6, GFLAGS), + GATE(ACLK_BUS_SPINLOCK, "aclk_bus_spinlock", "aclk_bus", 0, + RK3562_CLKGATE_CON(23), 0, GFLAGS), + GATE(ACLK_DCF, "aclk_dcf", "aclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(23), 1, GFLAGS), + GATE(PCLK_DCF, "pclk_dcf", "pclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(23), 2, GFLAGS), + GATE(FCLK_BUS_CM0_CORE, "fclk_bus_cm0_core", "hclk_bus", 0, + RK3562_CLKGATE_CON(23), 3, GFLAGS), + GATE(CLK_BUS_CM0_RTC, "clk_bus_cm0_rtc", "clk_rtc_32k", 0, + RK3562_CLKGATE_CON(23), 4, GFLAGS), + GATE(HCLK_ICACHE, "hclk_icache", "hclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(23), 8, GFLAGS), + GATE(HCLK_DCACHE, "hclk_dcache", "hclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(23), 9, GFLAGS), + GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0, + RK3562_CLKGATE_CON(24), 0, GFLAGS), + COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0, + RK3562_CLKSEL_CON(43), 0, 11, DFLAGS, + RK3562_CLKGATE_CON(24), 1, GFLAGS), + COMPOSITE_NOMUX(CLK_TSADC_TSEN, "clk_tsadc_tsen", "xin24m", 0, + RK3562_CLKSEL_CON(43), 11, 5, DFLAGS, + RK3562_CLKGATE_CON(24), 3, GFLAGS), + GATE(PCLK_DFT2APB, "pclk_dft2apb", "pclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(24), 4, GFLAGS), + COMPOSITE_NOMUX(CLK_SARADC_VCCIO156, "clk_saradc_vccio156", "xin24m", 0, + RK3562_CLKSEL_CON(44), 0, 12, DFLAGS, + RK3562_CLKGATE_CON(24), 9, GFLAGS), + GATE(PCLK_GMAC, "pclk_gmac", "pclk_bus", 0, + RK3562_CLKGATE_CON(25), 0, GFLAGS), + GATE(ACLK_GMAC, "aclk_gmac", "aclk_bus", 0, + RK3562_CLKGATE_CON(25), 1, GFLAGS), + COMPOSITE_NODIV(CLK_GMAC_125M_CRU_I, "clk_gmac_125m_cru_i", mux_125m_xin24m_p, 0, + RK3562_CLKSEL_CON(45), 8, 1, MFLAGS, + RK3562_CLKGATE_CON(25), 2, GFLAGS), + COMPOSITE_NODIV(CLK_GMAC_50M_CRU_I, "clk_gmac_50m_cru_i", mux_50m_xin24m_p, 0, + RK3562_CLKSEL_CON(45), 7, 1, MFLAGS, + RK3562_CLKGATE_CON(25), 3, GFLAGS), + COMPOSITE(CLK_GMAC_ETH_OUT2IO, "clk_gmac_eth_out2io", gpll_cpll_p, 0, + RK3562_CLKSEL_CON(46), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3562_CLKGATE_CON(25), 4, GFLAGS), + GATE(PCLK_APB2ASB_VCCIO156, "pclk_apb2asb_vccio156", "pclk_bus", CLK_IS_CRITICAL, + RK3562_CLKGATE_CON(25), 5, GFLAGS), + GATE(PCLK_TO_VCCIO156, "pclk_to_vccio156", "pclk_bus", CLK_IS_CRITICAL, + RK3562_CLKGATE_CON(25), 6, GFLAGS), + GATE(PCLK_DSIPHY, "pclk_dsiphy", "pclk_bus", 0, + RK3562_CLKGATE_CON(25), 8, GFLAGS), + GATE(PCLK_DSITX, "pclk_dsitx", "pclk_bus", 0, + RK3562_CLKGATE_CON(25), 9, GFLAGS), + GATE(PCLK_CPU_EMA_DET, "pclk_cpu_ema_det", "pclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(25), 10, GFLAGS), + GATE(PCLK_HASH, "pclk_hash", "pclk_bus", 0, + RK3562_CLKGATE_CON(25), 11, GFLAGS), + GATE(PCLK_TOPCRU, "pclk_topcru", "pclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(25), 15, GFLAGS), + GATE(PCLK_ASB2APB_VCCIO156, "pclk_asb2apb_vccio156", "pclk_to_vccio156", CLK_IS_CRITICAL, + RK3562_CLKGATE_CON(26), 0, GFLAGS), + GATE(PCLK_IOC_VCCIO156, "pclk_ioc_vccio156", "pclk_to_vccio156", CLK_IS_CRITICAL, + RK3562_CLKGATE_CON(26), 1, GFLAGS), + GATE(PCLK_GPIO3_VCCIO156, "pclk_gpio3_vccio156", "pclk_to_vccio156", 0, + RK3562_CLKGATE_CON(26), 2, GFLAGS), + GATE(PCLK_GPIO4_VCCIO156, "pclk_gpio4_vccio156", "pclk_to_vccio156", 0, + RK3562_CLKGATE_CON(26), 3, GFLAGS), + GATE(PCLK_SARADC_VCCIO156, "pclk_saradc_vccio156", "pclk_to_vccio156", 0, + RK3562_CLKGATE_CON(26), 4, GFLAGS), + GATE(PCLK_MAC100, "pclk_mac100", "pclk_bus", 0, + RK3562_CLKGATE_CON(27), 0, GFLAGS), + GATE(ACLK_MAC100, "aclk_mac100", "aclk_bus", 0, + RK3562_CLKGATE_CON(27), 1, GFLAGS), + COMPOSITE_NODIV(CLK_MAC100_50M_MATRIX, "clk_mac100_50m_matrix", mux_50m_xin24m_p, 0, + RK3562_CLKSEL_CON(47), 7, 1, MFLAGS, + RK3562_CLKGATE_CON(27), 2, GFLAGS), + + /* PD_CORE */ + COMPOSITE_NOMUX(0, "aclk_core_pre", "scmi_clk_cpu", CLK_IGNORE_UNUSED, + RK3562_CLKSEL_CON(11), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3562_CLKGATE_CON(4), 3, GFLAGS), + COMPOSITE_NOMUX(0, "pclk_dbg_pre", "scmi_clk_cpu", CLK_IGNORE_UNUSED, + RK3562_CLKSEL_CON(12), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3562_CLKGATE_CON(4), 5, GFLAGS), + COMPOSITE_NOMUX(HCLK_CORE, "hclk_core", "gpll", CLK_IS_CRITICAL, + RK3562_CLKSEL_CON(13), 0, 6, DFLAGS, + RK3562_CLKGATE_CON(5), 2, GFLAGS), + GATE(0, "pclk_dbg_daplite", "pclk_dbg_pre", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(4), 10, GFLAGS), + + /* PD_DDR */ + FACTOR_GATE(0, "clk_gpll_mux_to_ddr", "gpll", 0, 1, 4, + RK3328_CLKGATE_CON(1), 6, GFLAGS), + COMPOSITE_NOMUX(PCLK_DDR, "pclk_ddr", "clk_gpll_mux_to_ddr", CLK_IS_CRITICAL, + RK3562_DDR_CLKSEL_CON(1), 8, 5, DFLAGS, + RK3562_DDR_CLKGATE_CON(0), 3, GFLAGS), + COMPOSITE_NOMUX(CLK_MSCH_BRG_BIU, "clk_msch_brg_biu", "clk_gpll_mux_to_ddr", CLK_IS_CRITICAL, + RK3562_DDR_CLKSEL_CON(1), 0, 4, DFLAGS, + RK3562_DDR_CLKGATE_CON(0), 4, GFLAGS), + GATE(PCLK_DDR_HWLP, "pclk_ddr_hwlp", "pclk_ddr", CLK_IGNORE_UNUSED, + RK3562_DDR_CLKGATE_CON(0), 6, GFLAGS), + GATE(PCLK_DDR_UPCTL, "pclk_ddr_upctl", "pclk_ddr", CLK_IGNORE_UNUSED, + RK3562_DDR_CLKGATE_CON(0), 7, GFLAGS), + GATE(PCLK_DDR_PHY, "pclk_ddr_phy", "pclk_ddr", CLK_IGNORE_UNUSED, + RK3562_DDR_CLKGATE_CON(0), 8, GFLAGS), + GATE(PCLK_DDR_DFICTL, "pclk_ddr_dfictl", "pclk_ddr", CLK_IGNORE_UNUSED, + RK3562_DDR_CLKGATE_CON(0), 9, GFLAGS), + GATE(PCLK_DDR_DMA2DDR, "pclk_ddr_dma2ddr", "pclk_ddr", CLK_IGNORE_UNUSED, + RK3562_DDR_CLKGATE_CON(0), 10, GFLAGS), + GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", CLK_IGNORE_UNUSED, + RK3562_DDR_CLKGATE_CON(1), 0, GFLAGS), + GATE(TMCLK_DDR_MON, "tmclk_ddr_mon", "xin24m", CLK_IGNORE_UNUSED, + RK3562_DDR_CLKGATE_CON(1), 1, GFLAGS), + GATE(PCLK_DDR_GRF, "pclk_ddr_grf", "pclk_ddr", CLK_IGNORE_UNUSED, + RK3562_DDR_CLKGATE_CON(1), 2, GFLAGS), + GATE(PCLK_DDR_CRU, "pclk_ddr_cru", "pclk_ddr", CLK_IGNORE_UNUSED, + RK3562_DDR_CLKGATE_CON(1), 3, GFLAGS), + GATE(PCLK_SUBDDR_CRU, "pclk_subddr_cru", "pclk_ddr", CLK_IGNORE_UNUSED, + RK3562_DDR_CLKGATE_CON(1), 4, GFLAGS), + + /* PD_GPU */ + COMPOSITE(CLK_GPU_PRE, "clk_gpu_pre", gpll_cpll_p, 0, + RK3562_CLKSEL_CON(18), 7, 1, MFLAGS, 0, 4, DFLAGS, + RK3562_CLKGATE_CON(8), 0, GFLAGS), + COMPOSITE_NOMUX(ACLK_GPU_PRE, "aclk_gpu_pre", "clk_gpu_pre", 0, + RK3562_CLKSEL_CON(19), 0, 4, DFLAGS, + RK3562_CLKGATE_CON(8), 2, GFLAGS), + GATE(CLK_GPU, "clk_gpu", "clk_gpu_pre", 0, + RK3562_CLKGATE_CON(8), 4, GFLAGS), + COMPOSITE_NODIV(CLK_GPU_BRG, "clk_gpu_brg", mux_200m_100m_p, 0, + RK3562_CLKSEL_CON(19), 15, 1, MFLAGS, + RK3562_CLKGATE_CON(8), 8, GFLAGS), + + /* PD_NPU */ + COMPOSITE(CLK_NPU_PRE, "clk_npu_pre", gpll_cpll_p, 0, + RK3562_CLKSEL_CON(15), 7, 1, MFLAGS, 0, 4, DFLAGS, + RK3562_CLKGATE_CON(6), 0, GFLAGS), + COMPOSITE_NOMUX(HCLK_NPU_PRE, "hclk_npu_pre", "clk_npu_pre", 0, + RK3562_CLKSEL_CON(16), 0, 4, DFLAGS, + RK3562_CLKGATE_CON(6), 1, GFLAGS), + GATE(ACLK_RKNN, "aclk_rknn", "clk_npu_pre", 0, + RK3562_CLKGATE_CON(6), 4, GFLAGS), + GATE(HCLK_RKNN, "hclk_rknn", "hclk_npu_pre", 0, + RK3562_CLKGATE_CON(6), 5, GFLAGS), + + /* PD_PERI */ + COMPOSITE(ACLK_PERI, "aclk_peri", gpll_cpll_p, CLK_IS_CRITICAL, + RK3562_PERI_CLKSEL_CON(0), 7, 1, MFLAGS, 0, 5, DFLAGS, + RK3562_PERI_CLKGATE_CON(1), 0, GFLAGS), + COMPOSITE(HCLK_PERI, "hclk_peri", gpll_cpll_p, CLK_IS_CRITICAL, + RK3562_PERI_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 6, DFLAGS, + RK3562_PERI_CLKGATE_CON(1), 1, GFLAGS), + COMPOSITE(PCLK_PERI, "pclk_peri", gpll_cpll_p, CLK_IS_CRITICAL, + RK3562_PERI_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 5, DFLAGS, + RK3562_PERI_CLKGATE_CON(1), 2, GFLAGS), + GATE(PCLK_PERICRU, "pclk_pericru", "pclk_peri", CLK_IGNORE_UNUSED, + RK3562_PERI_CLKGATE_CON(1), 6, GFLAGS), + GATE(HCLK_SAI0, "hclk_sai0", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(2), 0, GFLAGS), + COMPOSITE(CLK_SAI0_SRC, "clk_sai0_src", gpll_cpll_hpll_p, 0, + RK3562_PERI_CLKSEL_CON(1), 14, 2, MFLAGS, 8, 6, DFLAGS, + RK3562_PERI_CLKGATE_CON(2), 1, GFLAGS), + COMPOSITE_FRACMUX(CLK_SAI0_FRAC, "clk_sai0_frac", "clk_sai0_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(2), 0, + RK3562_PERI_CLKGATE_CON(2), 2, GFLAGS, + &rk3562_clk_sai0_fracmux), + GATE(MCLK_SAI0, "mclk_sai0", "clk_sai0", 0, + RK3562_PERI_CLKGATE_CON(2), 3, GFLAGS), + COMPOSITE_NODIV(MCLK_SAI0_OUT2IO, "mclk_sai0_out2io", mclk_sai0_out2io_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(3), 5, 1, MFLAGS, + RK3562_PERI_CLKGATE_CON(2), 4, GFLAGS), + GATE(HCLK_SAI1, "hclk_sai1", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(2), 5, GFLAGS), + COMPOSITE(CLK_SAI1_SRC, "clk_sai1_src", gpll_cpll_hpll_p, 0, + RK3562_PERI_CLKSEL_CON(3), 14, 2, MFLAGS, 8, 6, DFLAGS, + RK3562_PERI_CLKGATE_CON(2), 6, GFLAGS), + COMPOSITE_FRACMUX(CLK_SAI1_FRAC, "clk_sai1_frac", "clk_sai1_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(4), 0, + RK3562_PERI_CLKGATE_CON(2), 7, GFLAGS, + &rk3562_clk_sai1_fracmux), + GATE(MCLK_SAI1, "mclk_sai1", "clk_sai1", 0, + RK3562_PERI_CLKGATE_CON(2), 8, GFLAGS), + COMPOSITE_NODIV(MCLK_SAI1_OUT2IO, "mclk_sai1_out2io", mclk_sai1_out2io_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(5), 5, 1, MFLAGS, + RK3562_PERI_CLKGATE_CON(2), 9, GFLAGS), + GATE(HCLK_SAI2, "hclk_sai2", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(2), 10, GFLAGS), + COMPOSITE(CLK_SAI2_SRC, "clk_sai2_src", gpll_cpll_hpll_p, 0, + RK3562_PERI_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS, + RK3562_PERI_CLKGATE_CON(2), 11, GFLAGS), + COMPOSITE_FRACMUX(CLK_SAI2_FRAC, "clk_sai2_frac", "clk_sai2_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(7), 0, + RK3562_PERI_CLKGATE_CON(2), 12, GFLAGS, + &rk3562_clk_sai2_fracmux), + GATE(MCLK_SAI2, "mclk_sai2", "clk_sai2", 0, + RK3562_PERI_CLKGATE_CON(2), 13, GFLAGS), + COMPOSITE_NODIV(MCLK_SAI2_OUT2IO, "mclk_sai2_out2io", mclk_sai2_out2io_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(8), 5, 1, MFLAGS, + RK3562_PERI_CLKGATE_CON(2), 14, GFLAGS), + GATE(HCLK_DSM, "hclk_dsm", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(3), 1, GFLAGS), + GATE(CLK_DSM, "clk_dsm", "mclk_sai1", 0, + RK3562_PERI_CLKGATE_CON(3), 2, GFLAGS), + GATE(HCLK_PDM, "hclk_pdm", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(3), 4, GFLAGS), + COMPOSITE(MCLK_PDM, "mclk_pdm", gpll_cpll_hpll_xin24m_p, 0, + RK3562_PERI_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3562_PERI_CLKGATE_CON(3), 5, GFLAGS), + GATE(HCLK_SPDIF, "hclk_spdif", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(3), 8, GFLAGS), + COMPOSITE(CLK_SPDIF_SRC, "clk_spdif_src", gpll_cpll_hpll_p, 0, + RK3562_PERI_CLKSEL_CON(13), 14, 2, MFLAGS, 8, 6, DFLAGS, + RK3562_PERI_CLKGATE_CON(3), 9, GFLAGS), + COMPOSITE_FRACMUX(CLK_SPDIF_FRAC, "clk_spdif_frac", "clk_spdif_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(14), 0, + RK3562_PERI_CLKGATE_CON(3), 10, GFLAGS, + &rk3562_clk_spdif_fracmux), + GATE(MCLK_SPDIF, "mclk_spdif", "clk_spdif", 0, + RK3562_PERI_CLKGATE_CON(3), 11, GFLAGS), + GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(4), 0, GFLAGS), + COMPOSITE(CCLK_SDMMC0, "cclk_sdmmc0", gpll_cpll_xin24m_dmyhpll_p, 0, + RK3562_PERI_CLKSEL_CON(16), 14, 2, MFLAGS, 0, 8, DFLAGS, + RK3562_PERI_CLKGATE_CON(4), 1, GFLAGS), + MMC(SCLK_SDMMC0_DRV, "sdmmc0_drv", "cclk_sdmmc0", RK3562_SDMMC0_CON0, 1), + MMC(SCLK_SDMMC0_SAMPLE, "sdmmc0_sample", "cclk_sdmmc0", RK3562_SDMMC0_CON1, 1), + GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(4), 2, GFLAGS), + COMPOSITE(CCLK_SDMMC1, "cclk_sdmmc1", gpll_cpll_xin24m_dmyhpll_p, 0, + RK3562_PERI_CLKSEL_CON(17), 14, 2, MFLAGS, 0, 8, DFLAGS, + RK3562_PERI_CLKGATE_CON(4), 3, GFLAGS), + MMC(SCLK_SDMMC1_DRV, "sdmmc1_drv", "cclk_sdmmc1", RK3562_SDMMC1_CON0, 1), + MMC(SCLK_SDMMC1_SAMPLE, "sdmmc1_sample", "cclk_sdmmc1", RK3562_SDMMC1_CON1, 1), + GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(4), 8, GFLAGS), + GATE(ACLK_EMMC, "aclk_emmc", "aclk_peri", 0, + RK3562_PERI_CLKGATE_CON(4), 9, GFLAGS), + COMPOSITE(CCLK_EMMC, "cclk_emmc", gpll_cpll_xin24m_dmyhpll_p, 0, + RK3562_PERI_CLKSEL_CON(18), 14, 2, MFLAGS, 0, 8, DFLAGS, + RK3562_PERI_CLKGATE_CON(4), 10, GFLAGS), + COMPOSITE(BCLK_EMMC, "bclk_emmc", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(19), 15, 1, MFLAGS, 8, 7, DFLAGS, + RK3562_PERI_CLKGATE_CON(4), 11, GFLAGS), + GATE(TMCLK_EMMC, "tmclk_emmc", "xin24m", 0, + RK3562_PERI_CLKGATE_CON(4), 12, GFLAGS), + COMPOSITE(SCLK_SFC, "sclk_sfc", gpll_cpll_xin24m_p, 0, + RK3562_PERI_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3562_PERI_CLKGATE_CON(4), 13, GFLAGS), + GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(4), 14, GFLAGS), + GATE(HCLK_USB2HOST, "hclk_usb2host", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(5), 0, GFLAGS), + GATE(HCLK_USB2HOST_ARB, "hclk_usb2host_arb", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(5), 1, GFLAGS), + GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(6), 0, GFLAGS), + COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_xin24m_p, 0, + RK3562_PERI_CLKSEL_CON(20), 12, 2, MFLAGS, + RK3562_PERI_CLKGATE_CON(6), 1, GFLAGS), + GATE(SCLK_IN_SPI1, "sclk_in_spi1", "sclk_in_spi1_io", 0, + RK3562_PERI_CLKGATE_CON(6), 2, GFLAGS), + GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(6), 3, GFLAGS), + COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", mux_200m_100m_50m_xin24m_p, 0, + RK3562_PERI_CLKSEL_CON(20), 14, 2, MFLAGS, + RK3562_PERI_CLKGATE_CON(6), 4, GFLAGS), + GATE(SCLK_IN_SPI2, "sclk_in_spi2", "sclk_in_spi2_io", 0, + RK3562_PERI_CLKGATE_CON(6), 5, GFLAGS), + GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(7), 0, GFLAGS), + GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(7), 1, GFLAGS), + GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(7), 2, GFLAGS), + GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(7), 3, GFLAGS), + GATE(PCLK_UART5, "pclk_uart5", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(7), 4, GFLAGS), + GATE(PCLK_UART6, "pclk_uart6", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(7), 5, GFLAGS), + GATE(PCLK_UART7, "pclk_uart7", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(7), 6, GFLAGS), + GATE(PCLK_UART8, "pclk_uart8", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(7), 7, GFLAGS), + GATE(PCLK_UART9, "pclk_uart9", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(7), 8, GFLAGS), + COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(21), 8, 1, MFLAGS, 0, 7, DFLAGS, + RK3562_PERI_CLKGATE_CON(7), 9, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(22), 0, + RK3562_PERI_CLKGATE_CON(7), 10, GFLAGS, + &rk3562_clk_uart1_fracmux), + GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0, + RK3562_PERI_CLKGATE_CON(7), 11, GFLAGS), + COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(23), 8, 1, MFLAGS, 0, 7, DFLAGS, + RK3562_PERI_CLKGATE_CON(7), 12, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(24), 0, + RK3562_PERI_CLKGATE_CON(7), 13, GFLAGS, + &rk3562_clk_uart2_fracmux), + GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0, + RK3562_PERI_CLKGATE_CON(7), 14, GFLAGS), + COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(25), 8, 1, MFLAGS, 0, 7, DFLAGS, + RK3562_PERI_CLKGATE_CON(7), 15, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(26), 0, + RK3562_PERI_CLKGATE_CON(8), 0, GFLAGS, + &rk3562_clk_uart3_fracmux), + GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0, + RK3562_PERI_CLKGATE_CON(8), 1, GFLAGS), + COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(27), 8, 1, MFLAGS, 0, 7, DFLAGS, + RK3562_PERI_CLKGATE_CON(8), 2, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(28), 0, + RK3562_PERI_CLKGATE_CON(8), 3, GFLAGS, + &rk3562_clk_uart4_fracmux), + GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0, + RK3562_PERI_CLKGATE_CON(8), 4, GFLAGS), + COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(29), 8, 1, MFLAGS, 0, 7, DFLAGS, + RK3562_PERI_CLKGATE_CON(8), 5, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(30), 0, + RK3562_PERI_CLKGATE_CON(8), 6, GFLAGS, + &rk3562_clk_uart5_fracmux), + GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0, + RK3562_PERI_CLKGATE_CON(8), 7, GFLAGS), + COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(31), 8, 1, MFLAGS, 0, 7, DFLAGS, + RK3562_PERI_CLKGATE_CON(8), 8, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(32), 0, + RK3562_PERI_CLKGATE_CON(8), 9, GFLAGS, + &rk3562_clk_uart6_fracmux), + GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0, + RK3562_PERI_CLKGATE_CON(8), 10, GFLAGS), + COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 7, DFLAGS, + RK3562_PERI_CLKGATE_CON(8), 11, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(34), 0, + RK3562_PERI_CLKGATE_CON(8), 12, GFLAGS, + &rk3562_clk_uart7_fracmux), + GATE(SCLK_UART7, "sclk_uart7", "clk_uart7", 0, + RK3562_PERI_CLKGATE_CON(8), 13, GFLAGS), + COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(35), 8, 1, MFLAGS, 0, 7, DFLAGS, + RK3562_PERI_CLKGATE_CON(8), 14, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(36), 0, + RK3562_PERI_CLKGATE_CON(8), 15, GFLAGS, + &rk3562_clk_uart8_fracmux), + GATE(SCLK_UART8, "sclk_uart8", "clk_uart8", 0, + RK3562_PERI_CLKGATE_CON(9), 0, GFLAGS), + COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(37), 8, 1, MFLAGS, 0, 7, DFLAGS, + RK3562_PERI_CLKGATE_CON(9), 1, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(38), 0, + RK3562_PERI_CLKGATE_CON(9), 2, GFLAGS, + &rk3562_clk_uart9_fracmux), + GATE(SCLK_UART9, "sclk_uart9", "clk_uart9", 0, + RK3562_PERI_CLKGATE_CON(9), 3, GFLAGS), + GATE(PCLK_PWM1_PERI, "pclk_pwm1_peri", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(10), 0, GFLAGS), + COMPOSITE_NODIV(CLK_PWM1_PERI, "clk_pwm1_peri", mux_100m_50m_xin24m_p, 0, + RK3562_PERI_CLKSEL_CON(40), 0, 2, MFLAGS, + RK3562_PERI_CLKGATE_CON(10), 1, GFLAGS), + GATE(CLK_CAPTURE_PWM1_PERI, "clk_capture_pwm1_peri", "xin24m", 0, + RK3562_PERI_CLKGATE_CON(10), 2, GFLAGS), + GATE(PCLK_PWM2_PERI, "pclk_pwm2_peri", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(10), 3, GFLAGS), + COMPOSITE_NODIV(CLK_PWM2_PERI, "clk_pwm2_peri", mux_100m_50m_xin24m_p, 0, + RK3562_PERI_CLKSEL_CON(40), 6, 2, MFLAGS, + RK3562_PERI_CLKGATE_CON(10), 4, GFLAGS), + GATE(CLK_CAPTURE_PWM2_PERI, "clk_capture_pwm2_peri", "xin24m", 0, + RK3562_PERI_CLKGATE_CON(10), 5, GFLAGS), + GATE(PCLK_PWM3_PERI, "pclk_pwm3_peri", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(10), 6, GFLAGS), + COMPOSITE_NODIV(CLK_PWM3_PERI, "clk_pwm3_peri", mux_100m_50m_xin24m_p, 0, + RK3562_PERI_CLKSEL_CON(40), 8, 2, MFLAGS, + RK3562_PERI_CLKGATE_CON(10), 7, GFLAGS), + GATE(CLK_CAPTURE_PWM3_PERI, "clk_capture_pwm3_peri", "xin24m", 0, + RK3562_PERI_CLKGATE_CON(10), 8, GFLAGS), + GATE(PCLK_CAN0, "pclk_can0", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(11), 0, GFLAGS), + COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(41), 7, 1, MFLAGS, 0, 5, DFLAGS, + RK3562_PERI_CLKGATE_CON(11), 1, GFLAGS), + GATE(PCLK_CAN1, "pclk_can1", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(11), 2, GFLAGS), + COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(41), 15, 1, MFLAGS, 8, 5, DFLAGS, + RK3562_PERI_CLKGATE_CON(11), 3, GFLAGS), + GATE(PCLK_PERI_WDT, "pclk_peri_wdt", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(13), 0, GFLAGS), + COMPOSITE_NODIV(TCLK_PERI_WDT, "tclk_peri_wdt", mux_xin24m_32k_p, 0, + RK3562_PERI_CLKSEL_CON(43), 15, 1, MFLAGS, + RK3562_PERI_CLKGATE_CON(13), 1, GFLAGS), + GATE(ACLK_SYSMEM, "aclk_sysmem", "aclk_peri", CLK_IGNORE_UNUSED, + RK3562_PERI_CLKGATE_CON(13), 2, GFLAGS), + GATE(HCLK_BOOTROM, "hclk_bootrom", "hclk_peri", CLK_IGNORE_UNUSED, + RK3562_PERI_CLKGATE_CON(13), 3, GFLAGS), + GATE(PCLK_PERI_GRF, "pclk_peri_grf", "pclk_peri", CLK_IGNORE_UNUSED, + RK3562_PERI_CLKGATE_CON(13), 4, GFLAGS), + GATE(ACLK_DMAC, "aclk_dmac", "aclk_peri", 0, + RK3562_PERI_CLKGATE_CON(13), 5, GFLAGS), + GATE(ACLK_RKDMAC, "aclk_rkdmac", "aclk_peri", 0, + RK3562_PERI_CLKGATE_CON(13), 6, GFLAGS), + GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(14), 0, GFLAGS), + GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m", 0, + RK3562_PERI_CLKGATE_CON(14), 1, GFLAGS), + COMPOSITE_NOMUX(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "xin24m", 0, + RK3562_PERI_CLKSEL_CON(44), 0, 8, DFLAGS, + RK3562_PERI_CLKGATE_CON(14), 2, GFLAGS), + GATE(PCLK_OTPC_S, "pclk_otpc_s", "pclk_peri", CLK_IGNORE_UNUSED, + RK3562_PERI_CLKGATE_CON(14), 3, GFLAGS), + GATE(CLK_SBPI_OTPC_S, "clk_sbpi_otpc_s", "xin24m", CLK_IGNORE_UNUSED, + RK3562_PERI_CLKGATE_CON(14), 4, GFLAGS), + COMPOSITE_NOMUX(CLK_USER_OTPC_S, "clk_user_otpc_s", "xin24m", CLK_IGNORE_UNUSED, + RK3562_PERI_CLKSEL_CON(44), 8, 8, DFLAGS, + RK3562_PERI_CLKGATE_CON(14), 5, GFLAGS), + GATE(CLK_OTPC_ARB, "clk_otpc_arb", "xin24m", 0, + RK3562_PERI_CLKGATE_CON(14), 6, GFLAGS), + GATE(PCLK_OTPPHY, "pclk_otpphy", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(14), 7, GFLAGS), + GATE(PCLK_USB2PHY, "pclk_usb2phy", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(15), 0, GFLAGS), + GATE(PCLK_PIPEPHY, "pclk_pipephy", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(15), 7, GFLAGS), + GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(16), 4, GFLAGS), + COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0, + RK3562_PERI_CLKSEL_CON(46), 0, 12, DFLAGS, + RK3562_PERI_CLKGATE_CON(16), 5, GFLAGS), + GATE(PCLK_IOC_VCCIO234, "pclk_ioc_vccio234", "pclk_peri", CLK_IS_CRITICAL, + RK3562_PERI_CLKGATE_CON(16), 12, GFLAGS), + GATE(PCLK_PERI_GPIO1, "pclk_peri_gpio1", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(17), 0, GFLAGS), + GATE(PCLK_PERI_GPIO2, "pclk_peri_gpio2", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(17), 1, GFLAGS), + COMPOSITE_NODIV(DCLK_PERI_GPIO, "dclk_peri_gpio", mux_xin24m_32k_p, 0, + RK3562_PERI_CLKSEL_CON(47), 8, 1, MFLAGS, + RK3562_PERI_CLKGATE_CON(17), 4, GFLAGS), + GATE(DCLK_PERI_GPIO1, "dclk_peri_gpio1", "dclk_peri_gpio", 0, + RK3562_PERI_CLKGATE_CON(17), 2, GFLAGS), + GATE(DCLK_PERI_GPIO2, "dclk_peri_gpio2", "dclk_peri_gpio", 0, + RK3562_PERI_CLKGATE_CON(17), 3, GFLAGS), + + /* PD_PHP */ + COMPOSITE(ACLK_PHP, "aclk_php", gpll_cpll_p, 0, + RK3562_CLKSEL_CON(36), 7, 1, MFLAGS, 0, 4, DFLAGS, + RK3562_CLKGATE_CON(16), 0, GFLAGS), + COMPOSITE_NOMUX(PCLK_PHP, "pclk_php", "aclk_php", 0, + RK3562_CLKSEL_CON(36), 8, 4, DFLAGS, + RK3562_CLKGATE_CON(16), 1, GFLAGS), + GATE(ACLK_PCIE20_MST, "aclk_pcie20_mst", "aclk_php", 0, + RK3562_CLKGATE_CON(16), 4, GFLAGS), + GATE(ACLK_PCIE20_SLV, "aclk_pcie20_slv", "aclk_php", 0, + RK3562_CLKGATE_CON(16), 5, GFLAGS), + GATE(ACLK_PCIE20_DBI, "aclk_pcie20_dbi", "aclk_php", 0, + RK3562_CLKGATE_CON(16), 6, GFLAGS), + GATE(PCLK_PCIE20, "pclk_pcie20", "pclk_php", 0, + RK3562_CLKGATE_CON(16), 7, GFLAGS), + GATE(CLK_PCIE20_AUX, "clk_pcie20_aux", "xin24m", 0, + RK3562_CLKGATE_CON(16), 8, GFLAGS), + GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_php", 0, + RK3562_CLKGATE_CON(16), 10, GFLAGS), + COMPOSITE_NODIV(CLK_USB3OTG_SUSPEND, "clk_usb3otg_suspend", mux_xin24m_32k_p, 0, + RK3562_CLKSEL_CON(36), 15, 1, MFLAGS, + RK3562_CLKGATE_CON(16), 11, GFLAGS), + GATE(CLK_USB3OTG_REF, "clk_usb3otg_ref", "xin24m", 0, + RK3562_CLKGATE_CON(16), 12, GFLAGS), + GATE(CLK_PIPEPHY_REF_FUNC, "clk_pipephy_ref_func", "pclk_pcie20", 0, + RK3562_CLKGATE_CON(17), 3, GFLAGS), + + /* PD_PMU1 */ + COMPOSITE_NOMUX(CLK_200M_PMU, "clk_200m_pmu", "cpll", CLK_IS_CRITICAL, + RK3562_PMU1_CLKSEL_CON(0), 0, 5, DFLAGS, + RK3562_PMU1_CLKGATE_CON(0), 1, GFLAGS), + /* PD_PMU0 */ + COMPOSITE_FRACMUX(CLK_RTC32K_FRAC, "clk_rtc32k_frac", "xin24m", CLK_IS_CRITICAL, + RK3562_PMU0_CLKSEL_CON(0), 0, + RK3562_PMU0_CLKGATE_CON(0), 15, GFLAGS, + &rk3562_rtc32k_pmu_fracmux), + COMPOSITE_NOMUX(BUSCLK_PDPMU0, "busclk_pdpmu0", "clk_200m_pmu", CLK_IS_CRITICAL, + RK3562_PMU0_CLKSEL_CON(1), 3, 2, DFLAGS, + RK3562_PMU0_CLKGATE_CON(0), 14, GFLAGS), + GATE(PCLK_PMU0_CRU, "pclk_pmu0_cru", "busclk_pdpmu0", CLK_IGNORE_UNUSED, + RK3562_PMU0_CLKGATE_CON(0), 0, GFLAGS), + GATE(PCLK_PMU0_PMU, "pclk_pmu0_pmu", "busclk_pdpmu0", CLK_IGNORE_UNUSED, + RK3562_PMU0_CLKGATE_CON(0), 1, GFLAGS), + GATE(CLK_PMU0_PMU, "clk_pmu0_pmu", "xin24m", CLK_IGNORE_UNUSED, + RK3562_PMU0_CLKGATE_CON(0), 2, GFLAGS), + GATE(PCLK_PMU0_HP_TIMER, "pclk_pmu0_hp_timer", "busclk_pdpmu0", CLK_IGNORE_UNUSED, + RK3562_PMU0_CLKGATE_CON(0), 3, GFLAGS), + GATE(CLK_PMU0_HP_TIMER, "clk_pmu0_hp_timer", "xin24m", CLK_IGNORE_UNUSED, + RK3562_PMU0_CLKGATE_CON(0), 4, GFLAGS), + GATE(CLK_PMU0_32K_HP_TIMER, "clk_pmu0_32k_hp_timer", "clk_rtc_32k", CLK_IGNORE_UNUSED, + RK3562_PMU0_CLKGATE_CON(0), 5, GFLAGS), + GATE(PCLK_PMU0_PVTM, "pclk_pmu0_pvtm", "busclk_pdpmu0", 0, + RK3562_PMU0_CLKGATE_CON(0), 6, GFLAGS), + GATE(CLK_PMU0_PVTM, "clk_pmu0_pvtm", "xin24m", 0, + RK3562_PMU0_CLKGATE_CON(0), 7, GFLAGS), + GATE(PCLK_IOC_PMUIO, "pclk_ioc_pmuio", "busclk_pdpmu0", CLK_IS_CRITICAL, + RK3562_PMU0_CLKGATE_CON(0), 8, GFLAGS), + GATE(PCLK_PMU0_GPIO0, "pclk_pmu0_gpio0", "busclk_pdpmu0", 0, + RK3562_PMU0_CLKGATE_CON(0), 9, GFLAGS), + GATE(DBCLK_PMU0_GPIO0, "dbclk_pmu0_gpio0", "xin24m", 0, + RK3562_PMU0_CLKGATE_CON(0), 10, GFLAGS), + GATE(PCLK_PMU0_GRF, "pclk_pmu0_grf", "busclk_pdpmu0", CLK_IGNORE_UNUSED, + RK3562_PMU0_CLKGATE_CON(0), 11, GFLAGS), + GATE(PCLK_PMU0_SGRF, "pclk_pmu0_sgrf", "busclk_pdpmu0", CLK_IGNORE_UNUSED, + RK3562_PMU0_CLKGATE_CON(0), 12, GFLAGS), + GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "xin24m", CLK_IGNORE_UNUSED, + RK3562_PMU0_CLKGATE_CON(1), 0, GFLAGS), + GATE(PCLK_PMU0_SCRKEYGEN, "pclk_pmu0_scrkeygen", "busclk_pdpmu0", CLK_IGNORE_UNUSED, + RK3562_PMU0_CLKGATE_CON(1), 1, GFLAGS), + COMPOSITE_NOMUX(CLK_PIPEPHY_DIV, "clk_pipephy_div", "cpll", 0, + RK3562_PMU0_CLKSEL_CON(2), 0, 6, DFLAGS, + RK3562_PMU0_CLKGATE_CON(2), 0, GFLAGS), + GATE(CLK_PIPEPHY_XIN24M, "clk_pipephy_xin24m", "xin24m", 0, + RK3562_PMU0_CLKGATE_CON(2), 1, GFLAGS), + COMPOSITE_NODIV(CLK_PIPEPHY_REF, "clk_pipephy_ref", clk_pipephy_ref_p, 0, + RK3562_PMU0_CLKSEL_CON(2), 7, 1, MFLAGS, + RK3562_PMU0_CLKGATE_CON(2), 2, GFLAGS), + GATE(CLK_USB2PHY_XIN24M, "clk_usb2phy_xin24m", "xin24m", 0, + RK3562_PMU0_CLKGATE_CON(2), 4, GFLAGS), + COMPOSITE_NODIV(CLK_USB2PHY_REF, "clk_usb2phy_ref", clk_usbphy_ref_p, 0, + RK3562_PMU0_CLKSEL_CON(2), 8, 1, MFLAGS, + RK3562_PMU0_CLKGATE_CON(2), 5, GFLAGS), + GATE(CLK_MIPIDSIPHY_XIN24M, "clk_mipidsiphy_xin24m", "xin24m", 0, + RK3562_PMU0_CLKGATE_CON(2), 6, GFLAGS), + COMPOSITE_NODIV(CLK_MIPIDSIPHY_REF, "clk_mipidsiphy_ref", clk_mipidsi_ref_p, 0, + RK3562_PMU0_CLKSEL_CON(2), 15, 1, MFLAGS, + RK3562_PMU0_CLKGATE_CON(2), 7, GFLAGS), + GATE(PCLK_PMU0_I2C0, "pclk_pmu0_i2c0", "busclk_pdpmu0", 0, + RK3562_PMU0_CLKGATE_CON(2), 8, GFLAGS), + COMPOSITE(CLK_PMU0_I2C0, "clk_pmu0_i2c0", mux_200m_xin24m_32k_p, 0, + RK3562_PMU0_CLKSEL_CON(3), 14, 2, MFLAGS, 8, 5, DFLAGS, + RK3562_PMU0_CLKGATE_CON(2), 9, GFLAGS), + /* PD_PMU1 */ + GATE(PCLK_PMU1_CRU, "pclk_pmu1_cru", "busclk_pdpmu0", CLK_IGNORE_UNUSED, + RK3562_PMU1_CLKGATE_CON(0), 0, GFLAGS), + GATE(HCLK_PMU1_MEM, "hclk_pmu1_mem", "busclk_pdpmu0", CLK_IGNORE_UNUSED, + RK3562_PMU1_CLKGATE_CON(0), 2, GFLAGS), + GATE(PCLK_PMU1_UART0, "pclk_pmu1_uart0", "busclk_pdpmu0", 0, + RK3562_PMU1_CLKGATE_CON(0), 7, GFLAGS), + COMPOSITE_NOMUX(CLK_PMU1_UART0_SRC, "clk_pmu1_uart0_src", "cpll", 0, + RK3562_PMU1_CLKSEL_CON(2), 0, 4, DFLAGS, + RK3562_PMU1_CLKGATE_CON(0), 8, GFLAGS), + COMPOSITE_FRACMUX(CLK_PMU1_UART0_FRAC, "clk_pmu1_uart0_frac", "clk_pmu1_uart0_src", CLK_SET_RATE_PARENT, + RK3562_PMU1_CLKSEL_CON(3), 0, + RK3562_PMU1_CLKGATE_CON(0), 9, GFLAGS, + &rk3562_clk_pmu1_uart0_fracmux), + GATE(SCLK_PMU1_UART0, "sclk_pmu1_uart0", "clk_pmu1_uart0", 0, + RK3562_PMU1_CLKGATE_CON(0), 10, GFLAGS), + GATE(PCLK_PMU1_SPI0, "pclk_pmu1_spi0", "busclk_pdpmu0", 0, + RK3562_PMU1_CLKGATE_CON(1), 0, GFLAGS), + COMPOSITE(CLK_PMU1_SPI0, "clk_pmu1_spi0", mux_200m_xin24m_32k_p, 0, + RK3562_PMU1_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 2, DFLAGS, + RK3562_PMU1_CLKGATE_CON(1), 1, GFLAGS), + GATE(SCLK_IN_PMU1_SPI0, "sclk_in_pmu1_spi0", "sclk_in_pmu1_spi0_io", 0, + RK3562_PMU1_CLKGATE_CON(1), 2, GFLAGS), + GATE(PCLK_PMU1_PWM0, "pclk_pmu1_pwm0", "busclk_pdpmu0", 0, + RK3562_PMU1_CLKGATE_CON(1), 3, GFLAGS), + COMPOSITE(CLK_PMU1_PWM0, "clk_pmu1_pwm0", mux_200m_xin24m_32k_p, 0, + RK3562_PMU1_CLKSEL_CON(4), 14, 2, MFLAGS, 8, 2, DFLAGS, + RK3562_PMU1_CLKGATE_CON(1), 4, GFLAGS), + GATE(CLK_CAPTURE_PMU1_PWM0, "clk_capture_pmu1_pwm0", "xin24m", 0, + RK3562_PMU1_CLKGATE_CON(1), 5, GFLAGS), + GATE(CLK_PMU1_WIFI, "clk_pmu1_wifi", "xin24m", 0, + RK3562_PMU1_CLKGATE_CON(1), 6, GFLAGS), + GATE(FCLK_PMU1_CM0_CORE, "fclk_pmu1_cm0_core", "busclk_pdpmu0", 0, + RK3562_PMU1_CLKGATE_CON(2), 0, GFLAGS), + GATE(CLK_PMU1_CM0_RTC, "clk_pmu1_cm0_rtc", "clk_rtc_32k", 0, + RK3562_PMU1_CLKGATE_CON(2), 1, GFLAGS), + GATE(PCLK_PMU1_WDTNS, "pclk_pmu1_wdtns", "busclk_pdpmu0", 0, + RK3562_PMU1_CLKGATE_CON(2), 3, GFLAGS), + GATE(CLK_PMU1_WDTNS, "clk_pmu1_wdtns", "xin24m", 0, + RK3562_PMU1_CLKGATE_CON(2), 4, GFLAGS), + GATE(PCLK_PMU1_MAILBOX, "pclk_pmu1_mailbox", "busclk_pdpmu0", 0, + RK3562_PMU1_CLKGATE_CON(3), 8, GFLAGS), + + /* PD_RGA */ + COMPOSITE(ACLK_RGA_PRE, "aclk_rga_pre", gpll_cpll_pvtpll_dmyapll_p, 0, + RK3562_CLKSEL_CON(32), 6, 2, MFLAGS, 0, 4, DFLAGS, + RK3562_CLKGATE_CON(14), 0, GFLAGS), + COMPOSITE_NOMUX(HCLK_RGA_PRE, "hclk_rga_pre", "aclk_rga_jdec", 0, + RK3562_CLKSEL_CON(32), 8, 3, DFLAGS, + RK3562_CLKGATE_CON(14), 1, GFLAGS), + GATE(ACLK_RGA, "aclk_rga", "aclk_rga_jdec", 0, + RK3562_CLKGATE_CON(14), 6, GFLAGS), + GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0, + RK3562_CLKGATE_CON(14), 7, GFLAGS), + COMPOSITE(CLK_RGA_CORE, "clk_rga_core", gpll_cpll_pvtpll_dmyapll_p, 0, + RK3562_CLKSEL_CON(33), 6, 2, MFLAGS, 0, 4, DFLAGS, + RK3562_CLKGATE_CON(14), 8, GFLAGS), + GATE(ACLK_JDEC, "aclk_jdec", "aclk_rga_jdec", 0, + RK3562_CLKGATE_CON(14), 9, GFLAGS), + GATE(HCLK_JDEC, "hclk_jdec", "hclk_rga_pre", 0, + RK3562_CLKGATE_CON(14), 10, GFLAGS), + + /* PD_VDPU */ + COMPOSITE(ACLK_VDPU_PRE, "aclk_vdpu_pre", gpll_cpll_pvtpll_dmyapll_p, 0, + RK3562_CLKSEL_CON(22), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3562_CLKGATE_CON(10), 0, GFLAGS), + COMPOSITE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", gpll_cpll_pvtpll_dmyapll_p, 0, + RK3562_CLKSEL_CON(23), 14, 2, MFLAGS, 8, 5, DFLAGS, + RK3562_CLKGATE_CON(10), 3, GFLAGS), + COMPOSITE_NOMUX(HCLK_VDPU_PRE, "hclk_vdpu_pre", "aclk_vdpu", 0, + RK3562_CLKSEL_CON(24), 0, 4, DFLAGS, + RK3562_CLKGATE_CON(10), 4, GFLAGS), + GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_vdpu", 0, + RK3562_CLKGATE_CON(10), 7, GFLAGS), + GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_vdpu_pre", 0, + RK3562_CLKGATE_CON(10), 8, GFLAGS), + + /* PD_VEPU */ + COMPOSITE(CLK_RKVENC_CORE, "clk_rkvenc_core", gpll_cpll_pvtpll_dmyapll_p, 0, + RK3562_CLKSEL_CON(20), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3562_CLKGATE_CON(9), 0, GFLAGS), + COMPOSITE(ACLK_VEPU_PRE, "aclk_vepu_pre", gpll_cpll_pvtpll_dmyapll_p, 0, + RK3562_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS, + RK3562_CLKGATE_CON(9), 1, GFLAGS), + COMPOSITE_NOMUX(HCLK_VEPU_PRE, "hclk_vepu_pre", "aclk_vepu", 0, + RK3562_CLKSEL_CON(21), 0, 4, DFLAGS, + RK3562_CLKGATE_CON(9), 2, GFLAGS), + GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_vepu", 0, + RK3562_CLKGATE_CON(9), 5, GFLAGS), + GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_vepu", 0, + RK3562_CLKGATE_CON(9), 6, GFLAGS), + + /* PD_VI */ + COMPOSITE(ACLK_VI, "aclk_vi", gpll_cpll_pvtpll_dmyapll_p, 0, + RK3562_CLKSEL_CON(25), 6, 2, MFLAGS, 0, 4, DFLAGS, + RK3562_CLKGATE_CON(11), 0, GFLAGS), + COMPOSITE_NOMUX(HCLK_VI, "hclk_vi", "aclk_vi_isp", 0, + RK3562_CLKSEL_CON(26), 0, 4, DFLAGS, + RK3562_CLKGATE_CON(11), 1, GFLAGS), + COMPOSITE_NOMUX(PCLK_VI, "pclk_vi", "aclk_vi_isp", 0, + RK3562_CLKSEL_CON(26), 8, 4, DFLAGS, + RK3562_CLKGATE_CON(11), 2, GFLAGS), + GATE(ACLK_ISP, "aclk_isp", "aclk_vi_isp", 0, + RK3562_CLKGATE_CON(11), 6, GFLAGS), + GATE(HCLK_ISP, "hclk_isp", "hclk_vi", 0, + RK3562_CLKGATE_CON(11), 7, GFLAGS), + COMPOSITE(CLK_ISP, "clk_isp", gpll_cpll_pvtpll_dmyapll_p, 0, + RK3562_CLKSEL_CON(27), 6, 2, MFLAGS, 0, 4, DFLAGS, + RK3562_CLKGATE_CON(11), 8, GFLAGS), + GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_isp", 0, + RK3562_CLKGATE_CON(11), 9, GFLAGS), + GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi", 0, + RK3562_CLKGATE_CON(11), 10, GFLAGS), + COMPOSITE(DCLK_VICAP, "dclk_vicap", gpll_cpll_pvtpll_dmyapll_p, 0, + RK3562_CLKSEL_CON(27), 14, 2, MFLAGS, 8, 4, DFLAGS, + RK3562_CLKGATE_CON(11), 11, GFLAGS), + GATE(CSIRX0_CLK_DATA, "csirx0_clk_data", "csirx0_clk_data_io", 0, + RK3562_CLKGATE_CON(11), 12, GFLAGS), + GATE(CSIRX1_CLK_DATA, "csirx1_clk_data", "csirx1_clk_data_io", 0, + RK3562_CLKGATE_CON(11), 13, GFLAGS), + GATE(CSIRX2_CLK_DATA, "csirx2_clk_data", "csirx2_clk_data_io", 0, + RK3562_CLKGATE_CON(11), 14, GFLAGS), + GATE(CSIRX3_CLK_DATA, "csirx3_clk_data", "csirx3_clk_data_io", 0, + RK3562_CLKGATE_CON(11), 15, GFLAGS), + GATE(PCLK_CSIHOST0, "pclk_csihost0", "pclk_vi", 0, + RK3562_CLKGATE_CON(12), 0, GFLAGS), + GATE(PCLK_CSIHOST1, "pclk_csihost1", "pclk_vi", 0, + RK3562_CLKGATE_CON(12), 1, GFLAGS), + GATE(PCLK_CSIHOST2, "pclk_csihost2", "pclk_vi", 0, + RK3562_CLKGATE_CON(12), 2, GFLAGS), + GATE(PCLK_CSIHOST3, "pclk_csihost3", "pclk_vi", 0, + RK3562_CLKGATE_CON(12), 3, GFLAGS), + GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_vi", 0, + RK3562_CLKGATE_CON(12), 4, GFLAGS), + GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_vi", 0, + RK3562_CLKGATE_CON(12), 5, GFLAGS), + + /* PD_VO */ + COMPOSITE(ACLK_VO_PRE, "aclk_vo_pre", gpll_cpll_vpll_dmyhpll_p, 0, + RK3562_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3562_CLKGATE_CON(13), 0, GFLAGS), + COMPOSITE_NOMUX(HCLK_VO_PRE, "hclk_vo_pre", "aclk_vo", 0, + RK3562_CLKSEL_CON(29), 0, 5, DFLAGS, + RK3562_CLKGATE_CON(13), 1, GFLAGS), + GATE(ACLK_VOP, "aclk_vop", "aclk_vo", 0, + RK3562_CLKGATE_CON(13), 6, GFLAGS), + GATE(HCLK_VOP, "hclk_vop", "hclk_vo_pre", 0, + RK3562_CLKGATE_CON(13), 7, GFLAGS), + COMPOSITE(DCLK_VOP, "dclk_vop", gpll_dmyhpll_vpll_apll_p, CLK_SET_RATE_NO_REPARENT, + RK3562_CLKSEL_CON(30), 14, 2, MFLAGS, 0, 8, DFLAGS, + RK3562_CLKGATE_CON(13), 8, GFLAGS), + COMPOSITE(DCLK_VOP1, "dclk_vop1", gpll_dmyhpll_vpll_apll_p, CLK_SET_RATE_NO_REPARENT, + RK3562_CLKSEL_CON(31), 14, 2, MFLAGS, 0, 8, DFLAGS, + RK3562_CLKGATE_CON(13), 9, GFLAGS), +}; + +static void __init rk3562_clk_init(struct device_node *np) +{ + struct rockchip_clk_provider *ctx; + unsigned long clk_nr_clks; + void __iomem *reg_base; + + clk_nr_clks = rockchip_clk_find_max_clk_id(rk3562_clk_branches, + ARRAY_SIZE(rk3562_clk_branches)) + 1; + + reg_base = of_iomap(np, 0); + if (!reg_base) { + pr_err("%s: could not map cru region\n", __func__); + return; + } + + ctx = rockchip_clk_init(np, reg_base, clk_nr_clks); + if (IS_ERR(ctx)) { + pr_err("%s: rockchip clk init failed\n", __func__); + iounmap(reg_base); + return; + } + + rockchip_clk_register_plls(ctx, rk3562_pll_clks, + ARRAY_SIZE(rk3562_pll_clks), + RK3562_GRF_SOC_STATUS0); + + rockchip_clk_register_branches(ctx, rk3562_clk_branches, + ARRAY_SIZE(rk3562_clk_branches)); + + rk3562_rst_init(np, reg_base); + + rockchip_register_restart_notifier(ctx, RK3562_GLB_SRST_FST); + + rockchip_clk_of_add_provider(np, ctx); +} + +struct clk_rk3562_inits { + void (*inits)(struct device_node *np); +}; + +static const struct clk_rk3562_inits clk_rk3562_cru_init = { + .inits = rk3562_clk_init, +}; + +static const struct of_device_id clk_rk3562_match_table[] = { + { + .compatible = "rockchip,rk3562-cru", + .data = &clk_rk3562_cru_init, + }, + { } +}; + +static int clk_rk3562_probe(struct device *dev) +{ + const struct clk_rk3562_inits *init_data; + + init_data = device_get_match_data(dev); + if (!init_data) + return -EINVAL; + + if (init_data->inits) + init_data->inits(dev->of_node); + + return 0; +} + +static struct driver clk_rk3562_driver = { + .probe = clk_rk3562_probe, + .name = "clk-rk3562", + .of_match_table = clk_rk3562_match_table, +}; + +core_platform_driver(clk_rk3562_driver); diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 2b992b6061..987c3bc518 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -436,7 +436,7 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, list->mux_shift, list->mux_width, list->mux_flags, &ctx->lock); break; - case branch_muxgrf: + case branch_grf_mux: clk = rockchip_clk_register_muxgrf(list->name, list->parent_names, list->num_parents, flags, ctx->grfmap[list->grf_type], diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 988a9a82a3..a56a42aaf5 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -21,6 +21,8 @@ #include <linux/clk.h> #include <restart.h> +struct clk; + #define HIWORD_UPDATE(val, mask, shift) \ ((val) << (shift) | (mask) << ((shift) + 16)) @@ -78,6 +80,92 @@ #define RV1108_EMMC_CON0 0x1e8 #define RV1108_EMMC_CON1 0x1ec +#define RV1126_PMU_MODE 0x0 +#define RV1126_PMU_PLL_CON(x) ((x) * 0x4 + 0x10) +#define RV1126_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100) +#define RV1126_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180) +#define RV1126_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200) +#define RV1126_PLL_CON(x) ((x) * 0x4) +#define RV1126_MODE_CON 0x90 +#define RV1126_CLKSEL_CON(x) ((x) * 0x4 + 0x100) +#define RV1126_CLKGATE_CON(x) ((x) * 0x4 + 0x280) +#define RV1126_SOFTRST_CON(x) ((x) * 0x4 + 0x300) +#define RV1126_GLB_SRST_FST 0x408 +#define RV1126_GLB_SRST_SND 0x40c +#define RV1126_SDMMC_CON0 0x440 +#define RV1126_SDMMC_CON1 0x444 +#define RV1126_SDIO_CON0 0x448 +#define RV1126_SDIO_CON1 0x44c +#define RV1126_EMMC_CON0 0x450 +#define RV1126_EMMC_CON1 0x454 + +#define RV1126B_TOPCRU_BASE 0x0 +#define RV1126B_BUSCRU_BASE 0x10000 +#define RV1126B_PERICRU_BASE 0x20000 +#define RV1126B_CORECRU_BASE 0x30000 +#define RV1126B_PMUCRU_BASE 0x40000 +#define RV1126B_PMU1CRU_BASE 0x50000 +#define RV1126B_DDRCRU_BASE 0x60000 +#define RV1126B_SUBDDRCRU_BASE 0x68000 +#define RV1126B_VICRU_BASE 0x70000 +#define RV1126B_VEPUCRU_BASE 0x80000 +#define RV1126B_NPUCRU_BASE 0x90000 +#define RV1126B_VDOCRU_BASE 0xA0000 +#define RV1126B_VCPCRU_BASE 0xB0000 + +#define RV1126B_PLL_CON(x) ((x) * 0x4 + RV1126B_TOPCRU_BASE) +#define RV1126B_MODE_CON (0x280 + RV1126B_TOPCRU_BASE) +#define RV1126B_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_TOPCRU_BASE) +#define RV1126B_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_TOPCRU_BASE) +#define RV1126B_SOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_TOPCRU_BASE) +#define RV1126B_GLB_SRST_FST (0xc08 + RV1126B_TOPCRU_BASE) +#define RV1126B_GLB_SRST_SND (0xc0c + RV1126B_TOPCRU_BASE) +#define RV1126B_CLK_CM_FRAC0_DIV_H (0xcc0 + RV1126B_TOPCRU_BASE) +#define RV1126B_CLK_CM_FRAC1_DIV_H (0xcc4 + RV1126B_TOPCRU_BASE) +#define RV1126B_CLK_CM_FRAC2_DIV_H (0xcc8 + RV1126B_TOPCRU_BASE) +#define RV1126B_CLK_UART_FRAC0_DIV_H (0xccc + RV1126B_TOPCRU_BASE) +#define RV1126B_CLK_UART_FRAC1_DIV_H (0xcd0 + RV1126B_TOPCRU_BASE) +#define RV1126B_CLK_AUDIO_FRAC0_DIV_H (0xcd4 + RV1126B_TOPCRU_BASE) +#define RV1126B_CLK_AUDIO_FRAC1_DIV_H (0xcd8 + RV1126B_TOPCRU_BASE) +#define RV1126B_BUSCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_BUSCRU_BASE) +#define RV1126B_BUSCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_BUSCRU_BASE) +#define RV1126B_BUSSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_BUSCRU_BASE) +#define RV1126B_PERIPLL_CON(x) ((x) * 0x4 + RV1126B_PERICRU_BASE) +#define RV1126B_PERICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_PERICRU_BASE) +#define RV1126B_PERICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_PERICRU_BASE) +#define RV1126B_PERISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_PERICRU_BASE) +#define RV1126B_CORECLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_CORECRU_BASE) +#define RV1126B_CORECLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_CORECRU_BASE) +#define RV1126B_CORESOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_CORECRU_BASE) +#define RV1126B_PMUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_PMUCRU_BASE) +#define RV1126B_PMUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_PMUCRU_BASE) +#define RV1126B_PMUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_PMUCRU_BASE) +#define RV1126B_PMU1CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_PMU1CRU_BASE) +#define RV1126B_PMU1CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_PMU1CRU_BASE) +#define RV1126B_PMU1SOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_PMU1CRU_BASE) +#define RV1126B_DDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_DDRCRU_BASE) +#define RV1126B_DDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_DDRCRU_BASE) +#define RV1126B_DDRSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_DDRCRU_BASE) +#define RV1126B_SUBDDRPLL_CON(x) ((x) * 0x4 + RV1126B_SUBDDRCRU_BASE) +#define RV1126B_SUBDDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_SUBDDRCRU_BASE) +#define RV1126B_SUBDDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_SUBDDRCRU_BASE) +#define RV1126B_SUBDDRSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_SUBDDRCRU_BASE) +#define RV1126B_VICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_VICRU_BASE) +#define RV1126B_VICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_VICRU_BASE) +#define RV1126B_VISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_VICRU_BASE) +#define RV1126B_VEPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_VEPUCRU_BASE) +#define RV1126B_VEPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_VEPUCRU_BASE) +#define RV1126B_VEPUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_VEPUCRU_BASE) +#define RV1126B_NPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_NPUCRU_BASE) +#define RV1126B_NPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_NPUCRU_BASE) +#define RV1126B_NPUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_NPUCRU_BASE) +#define RV1126B_VDOCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_VDOCRU_BASE) +#define RV1126B_VDOCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_VDOCRU_BASE) +#define RV1126B_VDOSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_VDOCRU_BASE) +#define RV1126B_VCPCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_VCPCRU_BASE) +#define RV1126B_VCPCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_VCPCRU_BASE) +#define RV1126B_VCPSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_VCPCRU_BASE) + #define RK2928_PLL_CON(x) ((x) * 0x4) #define RK2928_MODE_CON 0x40 #define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44) @@ -187,6 +275,80 @@ #define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100) #define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110) +#define RK3506_PMU_CRU_BASE 0x10000 +#define RK3506_PLL_CON(x) ((x) * 0x4 + RK3506_PMU_CRU_BASE) +#define RK3506_CLKSEL_CON(x) ((x) * 0x4 + 0x300) +#define RK3506_CLKGATE_CON(x) ((x) * 0x4 + 0x800) +#define RK3506_SOFTRST_CON(x) ((x) * 0x4 + 0xa00) +#define RK3506_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3506_PMU_CRU_BASE) +#define RK3506_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3506_PMU_CRU_BASE) +#define RK3506_MODE_CON 0x280 +#define RK3506_GLB_CNT_TH 0xc00 +#define RK3506_GLB_SRST_FST 0xc08 +#define RK3506_GLB_SRST_SND 0xc0c + +#define RK3528_PMU_CRU_BASE 0x10000 +#define RK3528_PCIE_CRU_BASE 0x20000 +#define RK3528_DDRPHY_CRU_BASE 0x28000 +#define RK3528_PLL_CON(x) RK2928_PLL_CON(x) +#define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE) +#define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE) +#define RK3528_MODE_CON 0x280 +#define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300) +#define RK3528_CLKGATE_CON(x) ((x) * 0x4 + 0x800) +#define RK3528_SOFTRST_CON(x) ((x) * 0x4 + 0xa00) +#define RK3528_SDMMC_CON(x) ((x) * 0x4 + 0x24) +#define RK3528_SDIO0_CON(x) ((x) * 0x4 + 0x4) +#define RK3528_SDIO1_CON(x) ((x) * 0x4 + 0xc) +#define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE) +#define RK3528_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PMU_CRU_BASE) +#define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE) +#define RK3528_PCIE_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PCIE_CRU_BASE) +#define RK3528_DDRPHY_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_DDRPHY_CRU_BASE) +#define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE) +#define RK3528_GLB_CNT_TH 0xc00 +#define RK3528_GLB_SRST_FST 0xc08 +#define RK3528_GLB_SRST_SND 0xc0c + +#define RK3562_PMU0_CRU_BASE 0x10000 +#define RK3562_PMU1_CRU_BASE 0x18000 +#define RK3562_DDR_CRU_BASE 0x20000 +#define RK3562_SUBDDR_CRU_BASE 0x28000 +#define RK3562_PERI_CRU_BASE 0x30000 + +#define RK3562_PLL_CON(x) RK2928_PLL_CON(x) +#define RK3562_PMU1_PLL_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x40) +#define RK3562_SUBDDR_PLL_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x20) +#define RK3562_MODE_CON 0x600 +#define RK3562_PMU1_MODE_CON (RK3562_PMU1_CRU_BASE + 0x380) +#define RK3562_SUBDDR_MODE_CON (RK3562_SUBDDR_CRU_BASE + 0x380) +#define RK3562_CLKSEL_CON(x) ((x) * 0x4 + 0x100) +#define RK3562_CLKGATE_CON(x) ((x) * 0x4 + 0x300) +#define RK3562_SOFTRST_CON(x) ((x) * 0x4 + 0x400) +#define RK3562_DDR_CLKSEL_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x100) +#define RK3562_DDR_CLKGATE_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x180) +#define RK3562_DDR_SOFTRST_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x200) +#define RK3562_SUBDDR_CLKSEL_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x100) +#define RK3562_SUBDDR_CLKGATE_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x180) +#define RK3562_SUBDDR_SOFTRST_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x200) +#define RK3562_PERI_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x100) +#define RK3562_PERI_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x300) +#define RK3562_PERI_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x400) +#define RK3562_PMU0_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x100) +#define RK3562_PMU0_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x180) +#define RK3562_PMU0_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x200) +#define RK3562_PMU1_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x100) +#define RK3562_PMU1_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x180) +#define RK3562_PMU1_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x200) +#define RK3562_GLB_SRST_FST 0x614 +#define RK3562_GLB_SRST_SND 0x618 +#define RK3562_GLB_RST_CON 0x61c +#define RK3562_GLB_RST_ST 0x620 +#define RK3562_SDMMC0_CON0 0x624 +#define RK3562_SDMMC0_CON1 0x628 +#define RK3562_SDMMC1_CON0 0x62c +#define RK3562_SDMMC1_CON1 0x630 + #define RK3568_PLL_CON(x) RK2928_PLL_CON(x) #define RK3568_MODE_CON0 0xc0 #define RK3568_MISC_CON0 0xc4 @@ -371,12 +533,28 @@ enum rockchip_grf_type { grf_type_num }; +/* ceil(sqrt(enums in rockchip_grf_type - 1)) */ +#define GRF_HASH_ORDER 2 + +/** + * struct rockchip_aux_grf - entry for the aux_grf_table hashtable + * @grf: pointer to the grf this entry references + * @type: what type of GRF this is + * @node: hlist node + */ +struct rockchip_aux_grf { + struct regmap *grf; + enum rockchip_grf_type type; + struct hlist_node node; +}; + /** * struct rockchip_clk_provider - information about clock provider * @reg_base: virtual address for the register base. * @clk_data: holds clock related data like clk* and number of clocks. * @cru_node: device-node of the clock-provider * @grf: regmap of the general-register-files syscon + * @aux_grf_table: hashtable of auxiliary GRF regmaps, indexed by grf_type * @lock: maintains exclusion between callbacks for a given clock-provider. */ struct rockchip_clk_provider { @@ -436,7 +614,8 @@ struct rockchip_pll_rate_table { * * Flags: * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the - * rate_table parameters and ajust them if necessary. + * rate_table parameters and adjust them if necessary. + * ROCKCHIP_PLL_FIXED_MODE - the pll operates in normal mode only */ struct rockchip_pll_clock { unsigned int id; @@ -454,6 +633,7 @@ struct rockchip_pll_clock { }; #define ROCKCHIP_PLL_SYNC_RATE BIT(0) +#define ROCKCHIP_PLL_FIXED_MODE BIT(1) #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \ _lshift, _pflags, _rtable) \ @@ -559,7 +739,7 @@ struct clk *rockchip_clk_register_muxgrf(const char *name, enum rockchip_clk_branch_type { branch_composite, branch_mux, - branch_muxgrf, + branch_grf_mux, branch_divider, branch_fraction_divider, branch_gate, @@ -816,10 +996,26 @@ struct rockchip_clk_branch { .gate_offset = -1, \ } +#define MUXTBL(_id, cname, pnames, f, o, s, w, mf, mt) \ + { \ + .id = _id, \ + .branch_type = branch_mux, \ + .name = cname, \ + .parent_names = pnames, \ + .num_parents = ARRAY_SIZE(pnames), \ + .flags = f, \ + .muxdiv_offset = o, \ + .mux_shift = s, \ + .mux_width = w, \ + .mux_flags = mf, \ + .gate_offset = -1, \ + .mux_table = mt, \ + } + #define MUXGRF(_id, cname, pnames, f, o, s, w, mf, gt) \ { \ .id = _id, \ - .branch_type = branch_muxgrf, \ + .branch_type = branch_grf_mux, \ .name = cname, \ .parent_names = pnames, \ .num_parents = ARRAY_SIZE(pnames), \ @@ -900,6 +1096,18 @@ struct rockchip_clk_branch { .div_shift = shift, \ } +#define MMC_GRF(_id, cname, pname, offset, shift, grftype) \ + { \ + .id = _id, \ + .branch_type = branch_grf_mmc, \ + .name = cname, \ + .parent_names = (const char *[]){ pname }, \ + .num_parents = 1, \ + .muxdiv_offset = offset, \ + .div_shift = shift, \ + .grf_type = grftype, \ + } + #define INVERTER(_id, cname, pname, io, is, if) \ { \ .id = _id, \ @@ -960,6 +1168,58 @@ struct rockchip_clk_branch { .gate_flags = gf, \ } +#define COMPOSITE_NOGATE_HALFDIV(_id, cname, pnames, f, mo, ms, mw, mf, \ + ds, dw, df) \ + { \ + .id = _id, \ + .branch_type = branch_half_divider, \ + .name = cname, \ + .parent_names = pnames, \ + .num_parents = ARRAY_SIZE(pnames), \ + .flags = f, \ + .muxdiv_offset = mo, \ + .mux_shift = ms, \ + .mux_width = mw, \ + .mux_flags = mf, \ + .div_shift = ds, \ + .div_width = dw, \ + .div_flags = df, \ + .gate_offset = -1, \ + } + +#define COMPOSITE_NOMUX_HALFDIV(_id, cname, pname, f, mo, ds, dw, df, \ + go, gs, gf) \ + { \ + .id = _id, \ + .branch_type = branch_half_divider, \ + .name = cname, \ + .parent_names = (const char *[]){ pname }, \ + .num_parents = 1, \ + .flags = f, \ + .muxdiv_offset = mo, \ + .div_shift = ds, \ + .div_width = dw, \ + .div_flags = df, \ + .gate_offset = go, \ + .gate_shift = gs, \ + .gate_flags = gf, \ + } + +#define DIV_HALF(_id, cname, pname, f, o, s, w, df) \ + { \ + .id = _id, \ + .branch_type = branch_half_divider, \ + .name = cname, \ + .parent_names = (const char *[]){ pname }, \ + .num_parents = 1, \ + .flags = f, \ + .muxdiv_offset = o, \ + .div_shift = s, \ + .div_width = w, \ + .div_flags = df, \ + .gate_offset = -1, \ + } + /* SGRF clocks are only accessible from secure mode, so not controllable */ #define SGRF_GATE(_id, cname, pname) \ FACTOR(_id, cname, pname, 0, 1, 1) @@ -994,7 +1254,6 @@ void rockchip_clk_register_late_branches(struct device *dev, struct rockchip_clk_provider *ctx, struct rockchip_clk_branch *list, unsigned int nr_clk); - void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx, struct rockchip_pll_clock *pll_list, unsigned int nr_pll, int grf_lock_offset); @@ -1031,6 +1290,7 @@ static inline void rockchip_register_softrst(struct device_node *np, return rockchip_register_softrst_lut(np, NULL, num_regs, base, flags); } +void rk3562_rst_init(struct device_node *np, void __iomem *reg_base); void rk3576_rst_init(struct device_node *np, void __iomem *reg_base); void rk3588_rst_init(struct device_node *np, void __iomem *reg_base); diff --git a/drivers/clk/rockchip/rst-rk3562.c b/drivers/clk/rockchip/rst-rk3562.c new file mode 100644 index 0000000000..e0b30194f7 --- /dev/null +++ b/drivers/clk/rockchip/rst-rk3562.c @@ -0,0 +1,430 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * Copyright (c) 2024 Collabora Ltd. + * Author: Detlev Casanova <detlev.casanova@collabora.com> + * Based on Sebastien Reichel's implementation for RK3588 + */ + +#include <linux/module.h> +#include <linux/array_size.h> +#include <of.h> +#include <dt-bindings/reset/rockchip,rk3562-cru.h> +#include "clk.h" + +/* 0xff100000 + 0x0A00 */ +#define RK3562_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit) +/* 0xff110000 + 0x0A00 */ +#define RK3562_PMU0CRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000*4 + reg * 16 + bit) +/* 0xff118000 + 0x0A00 */ +#define RK3562_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x18000*4 + reg * 16 + bit) +/* 0xff120000 + 0x0A00 */ +#define RK3562_DDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000*4 + reg * 16 + bit) +/* 0xff128000 + 0x0A00 */ +#define RK3562_SUBDDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x28000*4 + reg * 16 + bit) +/* 0xff130000 + 0x0A00 */ +#define RK3562_PERICRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000*4 + reg * 16 + bit) + +/* mapping table for reset ID to register offset */ +static const int rk3562_register_offset[] = { + /* SOFTRST_CON01 */ + RK3562_CRU_RESET_OFFSET(SRST_A_TOP_BIU, 1, 0), + RK3562_CRU_RESET_OFFSET(SRST_A_TOP_VIO_BIU, 1, 1), + RK3562_CRU_RESET_OFFSET(SRST_REF_PVTPLL_LOGIC, 1, 2), + + /* SOFTRST_CON03 */ + RK3562_CRU_RESET_OFFSET(SRST_NCOREPORESET0, 3, 0), + RK3562_CRU_RESET_OFFSET(SRST_NCOREPORESET1, 3, 1), + RK3562_CRU_RESET_OFFSET(SRST_NCOREPORESET2, 3, 2), + RK3562_CRU_RESET_OFFSET(SRST_NCOREPORESET3, 3, 3), + RK3562_CRU_RESET_OFFSET(SRST_NCORESET0, 3, 4), + RK3562_CRU_RESET_OFFSET(SRST_NCORESET1, 3, 5), + RK3562_CRU_RESET_OFFSET(SRST_NCORESET2, 3, 6), + RK3562_CRU_RESET_OFFSET(SRST_NCORESET3, 3, 7), + RK3562_CRU_RESET_OFFSET(SRST_NL2RESET, 3, 8), + + /* SOFTRST_CON04 */ + RK3562_CRU_RESET_OFFSET(SRST_DAP, 4, 9), + RK3562_CRU_RESET_OFFSET(SRST_P_DBG_DAPLITE, 4, 10), + RK3562_CRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 4, 13), + + /* SOFTRST_CON05 */ + RK3562_CRU_RESET_OFFSET(SRST_A_CORE_BIU, 5, 0), + RK3562_CRU_RESET_OFFSET(SRST_P_CORE_BIU, 5, 1), + RK3562_CRU_RESET_OFFSET(SRST_H_CORE_BIU, 5, 2), + + /* SOFTRST_CON06 */ + RK3562_CRU_RESET_OFFSET(SRST_A_NPU_BIU, 6, 2), + RK3562_CRU_RESET_OFFSET(SRST_H_NPU_BIU, 6, 3), + RK3562_CRU_RESET_OFFSET(SRST_A_RKNN, 6, 4), + RK3562_CRU_RESET_OFFSET(SRST_H_RKNN, 6, 5), + RK3562_CRU_RESET_OFFSET(SRST_REF_PVTPLL_NPU, 6, 6), + + /* SOFTRST_CON08 */ + RK3562_CRU_RESET_OFFSET(SRST_A_GPU_BIU, 8, 3), + RK3562_CRU_RESET_OFFSET(SRST_GPU, 8, 4), + RK3562_CRU_RESET_OFFSET(SRST_REF_PVTPLL_GPU, 8, 5), + RK3562_CRU_RESET_OFFSET(SRST_GPU_BRG_BIU, 8, 8), + + /* SOFTRST_CON09 */ + RK3562_CRU_RESET_OFFSET(SRST_RKVENC_CORE, 9, 0), + RK3562_CRU_RESET_OFFSET(SRST_A_VEPU_BIU, 9, 3), + RK3562_CRU_RESET_OFFSET(SRST_H_VEPU_BIU, 9, 4), + RK3562_CRU_RESET_OFFSET(SRST_A_RKVENC, 9, 5), + RK3562_CRU_RESET_OFFSET(SRST_H_RKVENC, 9, 6), + + /* SOFTRST_CON10 */ + RK3562_CRU_RESET_OFFSET(SRST_RKVDEC_HEVC_CA, 10, 2), + RK3562_CRU_RESET_OFFSET(SRST_A_VDPU_BIU, 10, 5), + RK3562_CRU_RESET_OFFSET(SRST_H_VDPU_BIU, 10, 6), + RK3562_CRU_RESET_OFFSET(SRST_A_RKVDEC, 10, 7), + RK3562_CRU_RESET_OFFSET(SRST_H_RKVDEC, 10, 8), + + /* SOFTRST_CON11 */ + RK3562_CRU_RESET_OFFSET(SRST_A_VI_BIU, 11, 3), + RK3562_CRU_RESET_OFFSET(SRST_H_VI_BIU, 11, 4), + RK3562_CRU_RESET_OFFSET(SRST_P_VI_BIU, 11, 5), + RK3562_CRU_RESET_OFFSET(SRST_ISP, 11, 8), + RK3562_CRU_RESET_OFFSET(SRST_A_VICAP, 11, 9), + RK3562_CRU_RESET_OFFSET(SRST_H_VICAP, 11, 10), + RK3562_CRU_RESET_OFFSET(SRST_D_VICAP, 11, 11), + RK3562_CRU_RESET_OFFSET(SRST_I0_VICAP, 11, 12), + RK3562_CRU_RESET_OFFSET(SRST_I1_VICAP, 11, 13), + RK3562_CRU_RESET_OFFSET(SRST_I2_VICAP, 11, 14), + RK3562_CRU_RESET_OFFSET(SRST_I3_VICAP, 11, 15), + + /* SOFTRST_CON12 */ + RK3562_CRU_RESET_OFFSET(SRST_P_CSIHOST0, 12, 0), + RK3562_CRU_RESET_OFFSET(SRST_P_CSIHOST1, 12, 1), + RK3562_CRU_RESET_OFFSET(SRST_P_CSIHOST2, 12, 2), + RK3562_CRU_RESET_OFFSET(SRST_P_CSIHOST3, 12, 3), + RK3562_CRU_RESET_OFFSET(SRST_P_CSIPHY0, 12, 4), + RK3562_CRU_RESET_OFFSET(SRST_P_CSIPHY1, 12, 5), + + /* SOFTRST_CON13 */ + RK3562_CRU_RESET_OFFSET(SRST_A_VO_BIU, 13, 3), + RK3562_CRU_RESET_OFFSET(SRST_H_VO_BIU, 13, 4), + RK3562_CRU_RESET_OFFSET(SRST_A_VOP, 13, 6), + RK3562_CRU_RESET_OFFSET(SRST_H_VOP, 13, 7), + RK3562_CRU_RESET_OFFSET(SRST_D_VOP, 13, 8), + RK3562_CRU_RESET_OFFSET(SRST_D_VOP1, 13, 9), + + /* SOFTRST_CON14 */ + RK3562_CRU_RESET_OFFSET(SRST_A_RGA_BIU, 14, 3), + RK3562_CRU_RESET_OFFSET(SRST_H_RGA_BIU, 14, 4), + RK3562_CRU_RESET_OFFSET(SRST_A_RGA, 14, 6), + RK3562_CRU_RESET_OFFSET(SRST_H_RGA, 14, 7), + RK3562_CRU_RESET_OFFSET(SRST_RGA_CORE, 14, 8), + RK3562_CRU_RESET_OFFSET(SRST_A_JDEC, 14, 9), + RK3562_CRU_RESET_OFFSET(SRST_H_JDEC, 14, 10), + + /* SOFTRST_CON15 */ + RK3562_CRU_RESET_OFFSET(SRST_B_EBK_BIU, 15, 2), + RK3562_CRU_RESET_OFFSET(SRST_P_EBK_BIU, 15, 3), + RK3562_CRU_RESET_OFFSET(SRST_AHB2AXI_EBC, 15, 4), + RK3562_CRU_RESET_OFFSET(SRST_H_EBC, 15, 5), + RK3562_CRU_RESET_OFFSET(SRST_D_EBC, 15, 6), + RK3562_CRU_RESET_OFFSET(SRST_H_EINK, 15, 7), + RK3562_CRU_RESET_OFFSET(SRST_P_EINK, 15, 8), + + /* SOFTRST_CON16 */ + RK3562_CRU_RESET_OFFSET(SRST_P_PHP_BIU, 16, 2), + RK3562_CRU_RESET_OFFSET(SRST_A_PHP_BIU, 16, 3), + RK3562_CRU_RESET_OFFSET(SRST_P_PCIE20, 16, 7), + RK3562_CRU_RESET_OFFSET(SRST_PCIE20_POWERUP, 16, 8), + RK3562_CRU_RESET_OFFSET(SRST_USB3OTG, 16, 10), + + /* SOFTRST_CON17 */ + RK3562_CRU_RESET_OFFSET(SRST_PIPEPHY, 17, 3), + + /* SOFTRST_CON18 */ + RK3562_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 18, 3), + RK3562_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 18, 4), + RK3562_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 18, 5), + + /* SOFTRST_CON19 */ + RK3562_CRU_RESET_OFFSET(SRST_P_I2C1, 19, 0), + RK3562_CRU_RESET_OFFSET(SRST_P_I2C2, 19, 1), + RK3562_CRU_RESET_OFFSET(SRST_P_I2C3, 19, 2), + RK3562_CRU_RESET_OFFSET(SRST_P_I2C4, 19, 3), + RK3562_CRU_RESET_OFFSET(SRST_P_I2C5, 19, 4), + RK3562_CRU_RESET_OFFSET(SRST_I2C1, 19, 6), + RK3562_CRU_RESET_OFFSET(SRST_I2C2, 19, 7), + RK3562_CRU_RESET_OFFSET(SRST_I2C3, 19, 8), + RK3562_CRU_RESET_OFFSET(SRST_I2C4, 19, 9), + RK3562_CRU_RESET_OFFSET(SRST_I2C5, 19, 10), + + /* SOFTRST_CON20 */ + RK3562_CRU_RESET_OFFSET(SRST_BUS_GPIO3, 20, 5), + RK3562_CRU_RESET_OFFSET(SRST_BUS_GPIO4, 20, 6), + + /* SOFTRST_CON21 */ + RK3562_CRU_RESET_OFFSET(SRST_P_TIMER, 21, 0), + RK3562_CRU_RESET_OFFSET(SRST_TIMER0, 21, 1), + RK3562_CRU_RESET_OFFSET(SRST_TIMER1, 21, 2), + RK3562_CRU_RESET_OFFSET(SRST_TIMER2, 21, 3), + RK3562_CRU_RESET_OFFSET(SRST_TIMER3, 21, 4), + RK3562_CRU_RESET_OFFSET(SRST_TIMER4, 21, 5), + RK3562_CRU_RESET_OFFSET(SRST_TIMER5, 21, 6), + RK3562_CRU_RESET_OFFSET(SRST_P_STIMER, 21, 7), + RK3562_CRU_RESET_OFFSET(SRST_STIMER0, 21, 8), + RK3562_CRU_RESET_OFFSET(SRST_STIMER1, 21, 9), + + /* SOFTRST_CON22 */ + RK3562_CRU_RESET_OFFSET(SRST_P_WDTNS, 22, 0), + RK3562_CRU_RESET_OFFSET(SRST_WDTNS, 22, 1), + RK3562_CRU_RESET_OFFSET(SRST_P_GRF, 22, 2), + RK3562_CRU_RESET_OFFSET(SRST_P_SGRF, 22, 3), + RK3562_CRU_RESET_OFFSET(SRST_P_MAILBOX, 22, 4), + RK3562_CRU_RESET_OFFSET(SRST_P_INTC, 22, 5), + RK3562_CRU_RESET_OFFSET(SRST_A_BUS_GIC400, 22, 6), + RK3562_CRU_RESET_OFFSET(SRST_A_BUS_GIC400_DEBUG, 22, 7), + + /* SOFTRST_CON23 */ + RK3562_CRU_RESET_OFFSET(SRST_A_BUS_SPINLOCK, 23, 0), + RK3562_CRU_RESET_OFFSET(SRST_A_DCF, 23, 1), + RK3562_CRU_RESET_OFFSET(SRST_P_DCF, 23, 2), + RK3562_CRU_RESET_OFFSET(SRST_F_BUS_CM0_CORE, 23, 3), + RK3562_CRU_RESET_OFFSET(SRST_T_BUS_CM0_JTAG, 23, 5), + RK3562_CRU_RESET_OFFSET(SRST_H_ICACHE, 23, 8), + RK3562_CRU_RESET_OFFSET(SRST_H_DCACHE, 23, 9), + + /* SOFTRST_CON24 */ + RK3562_CRU_RESET_OFFSET(SRST_P_TSADC, 24, 0), + RK3562_CRU_RESET_OFFSET(SRST_TSADC, 24, 1), + RK3562_CRU_RESET_OFFSET(SRST_TSADCPHY, 24, 2), + RK3562_CRU_RESET_OFFSET(SRST_P_DFT2APB, 24, 4), + + /* SOFTRST_CON25 */ + RK3562_CRU_RESET_OFFSET(SRST_A_GMAC, 25, 0), + RK3562_CRU_RESET_OFFSET(SRST_P_APB2ASB_VCCIO156, 25, 1), + RK3562_CRU_RESET_OFFSET(SRST_P_DSIPHY, 25, 5), + RK3562_CRU_RESET_OFFSET(SRST_P_DSITX, 25, 8), + RK3562_CRU_RESET_OFFSET(SRST_P_CPU_EMA_DET, 25, 9), + RK3562_CRU_RESET_OFFSET(SRST_P_HASH, 25, 10), + RK3562_CRU_RESET_OFFSET(SRST_P_TOPCRU, 25, 11), + + /* SOFTRST_CON26 */ + RK3562_CRU_RESET_OFFSET(SRST_P_ASB2APB_VCCIO156, 26, 0), + RK3562_CRU_RESET_OFFSET(SRST_P_IOC_VCCIO156, 26, 1), + RK3562_CRU_RESET_OFFSET(SRST_P_GPIO3_VCCIO156, 26, 2), + RK3562_CRU_RESET_OFFSET(SRST_P_GPIO4_VCCIO156, 26, 3), + RK3562_CRU_RESET_OFFSET(SRST_P_SARADC_VCCIO156, 26, 4), + RK3562_CRU_RESET_OFFSET(SRST_SARADC_VCCIO156, 26, 5), + RK3562_CRU_RESET_OFFSET(SRST_SARADC_VCCIO156_PHY, 26, 6), + + /* SOFTRST_CON27 */ + RK3562_CRU_RESET_OFFSET(SRST_A_MAC100, 27, 1), + + /* PMU0_SOFTRST_CON00 */ + RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_CRU, 0, 0), + RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_PMU, 0, 1), + RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_PMU, 0, 2), + RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_HP_TIMER, 0, 3), + RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_HP_TIMER, 0, 4), + RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_32K_HP_TIMER, 0, 5), + RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_PVTM, 0, 6), + RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_PVTM, 0, 7), + RK3562_PMU0CRU_RESET_OFFSET(SRST_P_IOC_PMUIO, 0, 8), + RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_GPIO0, 0, 9), + RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_GPIO0, 0, 10), + RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_GRF, 0, 11), + RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_SGRF, 0, 12), + + /* PMU0_SOFTRST_CON01 */ + RK3562_PMU0CRU_RESET_OFFSET(SRST_DDR_FAIL_SAFE, 1, 0), + RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_SCRKEYGEN, 1, 1), + + /* PMU0_SOFTRST_CON02 */ + RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_I2C0, 2, 8), + RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_I2C0, 2, 9), + + /* PMU1_SOFTRST_CON00 */ + RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_CRU, 0, 0), + RK3562_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_MEM, 0, 2), + RK3562_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 0, 3), + RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_BIU, 0, 4), + RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_UART0, 0, 7), + RK3562_PMU1CRU_RESET_OFFSET(SRST_S_PMU1_UART0, 0, 10), + + /* PMU1_SOFTRST_CON01 */ + RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_SPI0, 1, 0), + RK3562_PMU1CRU_RESET_OFFSET(SRST_PMU1_SPI0, 1, 1), + RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_PWM0, 1, 3), + RK3562_PMU1CRU_RESET_OFFSET(SRST_PMU1_PWM0, 1, 4), + + /* PMU1_SOFTRST_CON02 */ + RK3562_PMU1CRU_RESET_OFFSET(SRST_F_PMU1_CM0_CORE, 2, 0), + RK3562_PMU1CRU_RESET_OFFSET(SRST_T_PMU1_CM0_JTAG, 2, 2), + RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_WDTNS, 2, 3), + RK3562_PMU1CRU_RESET_OFFSET(SRST_PMU1_WDTNS, 2, 4), + RK3562_PMU1CRU_RESET_OFFSET(SRST_PMU1_MAILBOX, 2, 8), + + /* DDR_SOFTRST_CON00 */ + RK3562_DDRCRU_RESET_OFFSET(SRST_MSCH_BRG_BIU, 0, 4), + RK3562_DDRCRU_RESET_OFFSET(SRST_P_MSCH_BIU, 0, 5), + RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_HWLP, 0, 6), + RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_PHY, 0, 8), + RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_DFICTL, 0, 9), + RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_DMA2DDR, 0, 10), + + /* DDR_SOFTRST_CON01 */ + RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_MON, 1, 0), + RK3562_DDRCRU_RESET_OFFSET(SRST_TM_DDR_MON, 1, 1), + RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_GRF, 1, 2), + RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_CRU, 1, 3), + RK3562_DDRCRU_RESET_OFFSET(SRST_P_SUBDDR_CRU, 1, 4), + + /* SUBDDR_SOFTRST_CON00 */ + RK3562_SUBDDRCRU_RESET_OFFSET(SRST_MSCH_BIU, 0, 1), + RK3562_SUBDDRCRU_RESET_OFFSET(SRST_DDR_PHY, 0, 4), + RK3562_SUBDDRCRU_RESET_OFFSET(SRST_DDR_DFICTL, 0, 5), + RK3562_SUBDDRCRU_RESET_OFFSET(SRST_DDR_SCRAMBLE, 0, 6), + RK3562_SUBDDRCRU_RESET_OFFSET(SRST_DDR_MON, 0, 7), + RK3562_SUBDDRCRU_RESET_OFFSET(SRST_A_DDR_SPLIT, 0, 8), + RK3562_SUBDDRCRU_RESET_OFFSET(SRST_DDR_DMA2DDR, 0, 9), + + /* PERI_SOFTRST_CON01 */ + RK3562_PERICRU_RESET_OFFSET(SRST_A_PERI_BIU, 1, 3), + RK3562_PERICRU_RESET_OFFSET(SRST_H_PERI_BIU, 1, 4), + RK3562_PERICRU_RESET_OFFSET(SRST_P_PERI_BIU, 1, 5), + RK3562_PERICRU_RESET_OFFSET(SRST_P_PERICRU, 1, 6), + + /* PERI_SOFTRST_CON02 */ + RK3562_PERICRU_RESET_OFFSET(SRST_H_SAI0_8CH, 2, 0), + RK3562_PERICRU_RESET_OFFSET(SRST_M_SAI0_8CH, 2, 3), + RK3562_PERICRU_RESET_OFFSET(SRST_H_SAI1_8CH, 2, 5), + RK3562_PERICRU_RESET_OFFSET(SRST_M_SAI1_8CH, 2, 8), + RK3562_PERICRU_RESET_OFFSET(SRST_H_SAI2_2CH, 2, 10), + RK3562_PERICRU_RESET_OFFSET(SRST_M_SAI2_2CH, 2, 13), + + /* PERI_SOFTRST_CON03 */ + RK3562_PERICRU_RESET_OFFSET(SRST_H_DSM, 3, 1), + RK3562_PERICRU_RESET_OFFSET(SRST_DSM, 3, 2), + RK3562_PERICRU_RESET_OFFSET(SRST_H_PDM, 3, 4), + RK3562_PERICRU_RESET_OFFSET(SRST_M_PDM, 3, 5), + RK3562_PERICRU_RESET_OFFSET(SRST_H_SPDIF, 3, 8), + RK3562_PERICRU_RESET_OFFSET(SRST_M_SPDIF, 3, 11), + + /* PERI_SOFTRST_CON04 */ + RK3562_PERICRU_RESET_OFFSET(SRST_H_SDMMC0, 4, 0), + RK3562_PERICRU_RESET_OFFSET(SRST_H_SDMMC1, 4, 2), + RK3562_PERICRU_RESET_OFFSET(SRST_H_EMMC, 4, 8), + RK3562_PERICRU_RESET_OFFSET(SRST_A_EMMC, 4, 9), + RK3562_PERICRU_RESET_OFFSET(SRST_C_EMMC, 4, 10), + RK3562_PERICRU_RESET_OFFSET(SRST_B_EMMC, 4, 11), + RK3562_PERICRU_RESET_OFFSET(SRST_T_EMMC, 4, 12), + RK3562_PERICRU_RESET_OFFSET(SRST_S_SFC, 4, 13), + RK3562_PERICRU_RESET_OFFSET(SRST_H_SFC, 4, 14), + + /* PERI_SOFTRST_CON05 */ + RK3562_PERICRU_RESET_OFFSET(SRST_H_USB2HOST, 5, 0), + RK3562_PERICRU_RESET_OFFSET(SRST_H_USB2HOST_ARB, 5, 1), + RK3562_PERICRU_RESET_OFFSET(SRST_USB2HOST_UTMI, 5, 2), + + /* PERI_SOFTRST_CON06 */ + RK3562_PERICRU_RESET_OFFSET(SRST_P_SPI1, 6, 0), + RK3562_PERICRU_RESET_OFFSET(SRST_SPI1, 6, 1), + RK3562_PERICRU_RESET_OFFSET(SRST_P_SPI2, 6, 3), + RK3562_PERICRU_RESET_OFFSET(SRST_SPI2, 6, 4), + + /* PERI_SOFTRST_CON07 */ + RK3562_PERICRU_RESET_OFFSET(SRST_P_UART1, 7, 0), + RK3562_PERICRU_RESET_OFFSET(SRST_P_UART2, 7, 1), + RK3562_PERICRU_RESET_OFFSET(SRST_P_UART3, 7, 2), + RK3562_PERICRU_RESET_OFFSET(SRST_P_UART4, 7, 3), + RK3562_PERICRU_RESET_OFFSET(SRST_P_UART5, 7, 4), + RK3562_PERICRU_RESET_OFFSET(SRST_P_UART6, 7, 5), + RK3562_PERICRU_RESET_OFFSET(SRST_P_UART7, 7, 6), + RK3562_PERICRU_RESET_OFFSET(SRST_P_UART8, 7, 7), + RK3562_PERICRU_RESET_OFFSET(SRST_P_UART9, 7, 8), + RK3562_PERICRU_RESET_OFFSET(SRST_S_UART1, 7, 11), + RK3562_PERICRU_RESET_OFFSET(SRST_S_UART2, 7, 14), + + /* PERI_SOFTRST_CON08 */ + RK3562_PERICRU_RESET_OFFSET(SRST_S_UART3, 8, 1), + RK3562_PERICRU_RESET_OFFSET(SRST_S_UART4, 8, 4), + RK3562_PERICRU_RESET_OFFSET(SRST_S_UART5, 8, 7), + RK3562_PERICRU_RESET_OFFSET(SRST_S_UART6, 8, 10), + RK3562_PERICRU_RESET_OFFSET(SRST_S_UART7, 8, 13), + + /* PERI_SOFTRST_CON09 */ + RK3562_PERICRU_RESET_OFFSET(SRST_S_UART8, 9, 0), + RK3562_PERICRU_RESET_OFFSET(SRST_S_UART9, 9, 3), + + /* PERI_SOFTRST_CON10 */ + RK3562_PERICRU_RESET_OFFSET(SRST_P_PWM1_PERI, 10, 0), + RK3562_PERICRU_RESET_OFFSET(SRST_PWM1_PERI, 10, 1), + RK3562_PERICRU_RESET_OFFSET(SRST_P_PWM2_PERI, 10, 3), + RK3562_PERICRU_RESET_OFFSET(SRST_PWM2_PERI, 10, 4), + RK3562_PERICRU_RESET_OFFSET(SRST_P_PWM3_PERI, 10, 6), + RK3562_PERICRU_RESET_OFFSET(SRST_PWM3_PERI, 10, 7), + + /* PERI_SOFTRST_CON11 */ + RK3562_PERICRU_RESET_OFFSET(SRST_P_CAN0, 11, 0), + RK3562_PERICRU_RESET_OFFSET(SRST_CAN0, 11, 1), + RK3562_PERICRU_RESET_OFFSET(SRST_P_CAN1, 11, 2), + RK3562_PERICRU_RESET_OFFSET(SRST_CAN1, 11, 3), + + /* PERI_SOFTRST_CON12 */ + RK3562_PERICRU_RESET_OFFSET(SRST_A_CRYPTO, 12, 0), + RK3562_PERICRU_RESET_OFFSET(SRST_H_CRYPTO, 12, 1), + RK3562_PERICRU_RESET_OFFSET(SRST_P_CRYPTO, 12, 2), + RK3562_PERICRU_RESET_OFFSET(SRST_CORE_CRYPTO, 12, 3), + RK3562_PERICRU_RESET_OFFSET(SRST_PKA_CRYPTO, 12, 4), + RK3562_PERICRU_RESET_OFFSET(SRST_H_KLAD, 12, 5), + RK3562_PERICRU_RESET_OFFSET(SRST_P_KEY_READER, 12, 6), + RK3562_PERICRU_RESET_OFFSET(SRST_H_RK_RNG_NS, 12, 7), + RK3562_PERICRU_RESET_OFFSET(SRST_H_RK_RNG_S, 12, 8), + RK3562_PERICRU_RESET_OFFSET(SRST_H_TRNG_NS, 12, 9), + RK3562_PERICRU_RESET_OFFSET(SRST_H_TRNG_S, 12, 10), + RK3562_PERICRU_RESET_OFFSET(SRST_H_CRYPTO_S, 12, 11), + + /* PERI_SOFTRST_CON13 */ + RK3562_PERICRU_RESET_OFFSET(SRST_P_PERI_WDT, 13, 0), + RK3562_PERICRU_RESET_OFFSET(SRST_T_PERI_WDT, 13, 1), + RK3562_PERICRU_RESET_OFFSET(SRST_A_SYSMEM, 13, 2), + RK3562_PERICRU_RESET_OFFSET(SRST_H_BOOTROM, 13, 3), + RK3562_PERICRU_RESET_OFFSET(SRST_P_PERI_GRF, 13, 4), + RK3562_PERICRU_RESET_OFFSET(SRST_A_DMAC, 13, 5), + RK3562_PERICRU_RESET_OFFSET(SRST_A_RKDMAC, 13, 6), + + /* PERI_SOFTRST_CON14 */ + RK3562_PERICRU_RESET_OFFSET(SRST_P_OTPC_NS, 14, 0), + RK3562_PERICRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 14, 1), + RK3562_PERICRU_RESET_OFFSET(SRST_USER_OTPC_NS, 14, 2), + RK3562_PERICRU_RESET_OFFSET(SRST_P_OTPC_S, 14, 3), + RK3562_PERICRU_RESET_OFFSET(SRST_SBPI_OTPC_S, 14, 4), + RK3562_PERICRU_RESET_OFFSET(SRST_USER_OTPC_S, 14, 5), + RK3562_PERICRU_RESET_OFFSET(SRST_OTPC_ARB, 14, 6), + RK3562_PERICRU_RESET_OFFSET(SRST_P_OTPPHY, 14, 7), + RK3562_PERICRU_RESET_OFFSET(SRST_OTP_NPOR, 14, 8), + + /* PERI_SOFTRST_CON15 */ + RK3562_PERICRU_RESET_OFFSET(SRST_P_USB2PHY, 15, 0), + RK3562_PERICRU_RESET_OFFSET(SRST_USB2PHY_POR, 15, 4), + RK3562_PERICRU_RESET_OFFSET(SRST_USB2PHY_OTG, 15, 5), + RK3562_PERICRU_RESET_OFFSET(SRST_USB2PHY_HOST, 15, 6), + RK3562_PERICRU_RESET_OFFSET(SRST_P_PIPEPHY, 15, 7), + + /* PERI_SOFTRST_CON16 */ + RK3562_PERICRU_RESET_OFFSET(SRST_P_SARADC, 16, 4), + RK3562_PERICRU_RESET_OFFSET(SRST_SARADC, 16, 5), + RK3562_PERICRU_RESET_OFFSET(SRST_SARADC_PHY, 16, 6), + RK3562_PERICRU_RESET_OFFSET(SRST_P_IOC_VCCIO234, 16, 12), + + /* PERI_SOFTRST_CON17 */ + RK3562_PERICRU_RESET_OFFSET(SRST_P_PERI_GPIO1, 17, 0), + RK3562_PERICRU_RESET_OFFSET(SRST_P_PERI_GPIO2, 17, 1), + RK3562_PERICRU_RESET_OFFSET(SRST_PERI_GPIO1, 17, 2), + RK3562_PERICRU_RESET_OFFSET(SRST_PERI_GPIO2, 17, 3), +}; + +void rk3562_rst_init(struct device_node *np, void __iomem *reg_base) +{ + rockchip_register_softrst_lut(np, + rk3562_register_offset, + ARRAY_SIZE(rk3562_register_offset), + reg_base + RK3562_SOFTRST_CON(0), + ROCKCHIP_SOFTRST_HIWORD_MASK); +} -- 2.43.0 ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 03/14] pinctrl: rockchip: sync driver with Linux 2026-01-30 5:16 [PATCH v2 00/14] ARM: rockchip: Add initial RK3562 SoC support Sohaib Mohamed 2026-01-30 5:16 ` [PATCH v2 01/14] " Sohaib Mohamed 2026-01-30 5:16 ` [PATCH v2 02/14] clk: rockchip: add RK3562 clock and reset driver support Sohaib Mohamed @ 2026-01-30 5:16 ` Sohaib Mohamed 2026-01-30 5:16 ` [PATCH v2 04/14] ARM: boards: Rockchip: add RK3562-EVB2 support Sohaib Mohamed ` (10 subsequent siblings) 13 siblings, 0 replies; 23+ messages in thread From: Sohaib Mohamed @ 2026-01-30 5:16 UTC (permalink / raw) To: Sascha Hauer, BAREBOX; +Cc: Sohaib Mohamed, Ahmad Fatoum From: Ahmad Fatoum <a.fatoum@pengutronix.de> To add RK3562 support, sync the driver with Linux and while at it, add also support for other new 64-bit Rockchip SoCs. And remove rockchip_gpio_regs unused struct. Co-developed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sohaib Mohamed <sohaib.amhmd@gmail.com> --- drivers/mfd/syscon.c | 18 + drivers/pinctrl/pinctrl-rockchip.c | 768 ++++++++++++++++++++++++++++++++++++- drivers/pinctrl/pinctrl-rockchip.h | 52 +-- include/mfd/syscon.h | 8 + 4 files changed, 803 insertions(+), 43 deletions(-) diff --git a/drivers/mfd/syscon.c b/drivers/mfd/syscon.c index 3c2e1241fd..bd6626029d 100644 --- a/drivers/mfd/syscon.c +++ b/drivers/mfd/syscon.c @@ -217,6 +217,24 @@ struct regmap *syscon_regmap_lookup_by_phandle(struct device_node *np, return regmap; } +/* + * It behaves the same as syscon_regmap_lookup_by_phandle() except where + * there is no regmap phandle. In this case, instead of returning -ENODEV, + * the function returns NULL. + */ +struct regmap *syscon_regmap_lookup_by_phandle_optional(struct device_node *np, + const char *property) +{ + struct regmap *regmap; + + regmap = syscon_regmap_lookup_by_phandle(np, property); + if (IS_ERR(regmap) && PTR_ERR(regmap) == -ENODEV) + return NULL; + + return regmap; +} +EXPORT_SYMBOL_GPL(syscon_regmap_lookup_by_phandle_optional); + static int syscon_probe(struct device *dev) { struct syscon *syscon; diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 58e9153bd6..f2a6c0266b 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -94,6 +94,29 @@ .pull_type[3] = pull3, \ } +#define PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(id, pins, label, iom0, \ + iom1, iom2, iom3, \ + offset0, offset1, \ + offset2, offset3, drv0, \ + drv1, drv2, drv3) \ + { \ + .bank_num = id, \ + .nr_pins = pins, \ + .name = label, \ + .iomux = { \ + { .type = iom0, .offset = offset0 }, \ + { .type = iom1, .offset = offset1 }, \ + { .type = iom2, .offset = offset2 }, \ + { .type = iom3, .offset = offset3 }, \ + }, \ + .drv = { \ + { .drv_type = drv0, .offset = -1 }, \ + { .drv_type = drv1, .offset = -1 }, \ + { .drv_type = drv2, .offset = -1 }, \ + { .drv_type = drv3, .offset = -1 }, \ + }, \ + } + #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ { \ .bank_num = id, \ @@ -222,6 +245,35 @@ .pull_type[3] = pull3, \ } +#define PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS_PULL_FLAGS(id, pins, \ + label, iom0, iom1, \ + iom2, iom3, offset0, \ + offset1, offset2, \ + offset3, drv0, drv1, \ + drv2, drv3, pull0, \ + pull1, pull2, pull3) \ + { \ + .bank_num = id, \ + .nr_pins = pins, \ + .name = label, \ + .iomux = { \ + { .type = iom0, .offset = offset0 }, \ + { .type = iom1, .offset = offset1 }, \ + { .type = iom2, .offset = offset2 }, \ + { .type = iom3, .offset = offset3 }, \ + }, \ + .drv = { \ + { .drv_type = drv0, .offset = -1 }, \ + { .drv_type = drv1, .offset = -1 }, \ + { .drv_type = drv2, .offset = -1 }, \ + { .drv_type = drv3, .offset = -1 }, \ + }, \ + .pull_type[0] = pull0, \ + .pull_type[1] = pull1, \ + .pull_type[2] = pull2, \ + .pull_type[3] = pull3, \ + } + #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \ { \ .bank_num = ID, \ @@ -1010,6 +1062,13 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) else regmap = info->regmap_base; + if (ctrl->type == RK3506) { + if (bank->bank_num == 1) + regmap = info->regmap_ioc1; + else if (bank->bank_num == 4) + return 0; + } + /* get basic quadrupel of mux registers and the correct reg inside */ mux_type = bank->iomux[iomux_num].type; reg = bank->iomux[iomux_num].offset; @@ -1774,6 +1833,516 @@ static int rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, return 0; } +#define RK3506_DRV_BITS_PER_PIN 8 +#define RK3506_DRV_PINS_PER_REG 2 +#define RK3506_DRV_GPIO0_A_OFFSET 0x100 +#define RK3506_DRV_GPIO0_D_OFFSET 0x830 +#define RK3506_DRV_GPIO1_OFFSET 0x140 +#define RK3506_DRV_GPIO2_OFFSET 0x180 +#define RK3506_DRV_GPIO3_OFFSET 0x1c0 +#define RK3506_DRV_GPIO4_OFFSET 0x840 + +static int rk3506_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + int ret = 0; + + switch (bank->bank_num) { + case 0: + *regmap = info->regmap_pmu; + if (pin_num > 24) { + ret = -EINVAL; + } else if (pin_num < 24) { + *reg = RK3506_DRV_GPIO0_A_OFFSET; + } else { + *reg = RK3506_DRV_GPIO0_D_OFFSET; + *bit = 3; + + return 0; + } + break; + + case 1: + *regmap = info->regmap_ioc1; + if (pin_num < 28) + *reg = RK3506_DRV_GPIO1_OFFSET; + else + ret = -EINVAL; + break; + + case 2: + *regmap = info->regmap_base; + if (pin_num < 17) + *reg = RK3506_DRV_GPIO2_OFFSET; + else + ret = -EINVAL; + break; + + case 3: + *regmap = info->regmap_base; + if (pin_num < 15) + *reg = RK3506_DRV_GPIO3_OFFSET; + else + ret = -EINVAL; + break; + + case 4: + *regmap = info->regmap_base; + if (pin_num < 8 || pin_num > 11) { + ret = -EINVAL; + } else { + *reg = RK3506_DRV_GPIO4_OFFSET; + *bit = 10; + + return 0; + } + break; + + default: + ret = -EINVAL; + break; + } + + if (ret) { + dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num); + + return ret; + } + + *reg += ((pin_num / RK3506_DRV_PINS_PER_REG) * 4); + *bit = pin_num % RK3506_DRV_PINS_PER_REG; + *bit *= RK3506_DRV_BITS_PER_PIN; + + return 0; +} + +#define RK3506_PULL_BITS_PER_PIN 2 +#define RK3506_PULL_PINS_PER_REG 8 +#define RK3506_PULL_GPIO0_A_OFFSET 0x200 +#define RK3506_PULL_GPIO0_D_OFFSET 0x830 +#define RK3506_PULL_GPIO1_OFFSET 0x210 +#define RK3506_PULL_GPIO2_OFFSET 0x220 +#define RK3506_PULL_GPIO3_OFFSET 0x230 +#define RK3506_PULL_GPIO4_OFFSET 0x840 + +static int rk3506_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + int ret = 0; + + switch (bank->bank_num) { + case 0: + *regmap = info->regmap_pmu; + if (pin_num > 24) { + ret = -EINVAL; + } else if (pin_num < 24) { + *reg = RK3506_PULL_GPIO0_A_OFFSET; + } else { + *reg = RK3506_PULL_GPIO0_D_OFFSET; + *bit = 5; + + return 0; + } + break; + + case 1: + *regmap = info->regmap_ioc1; + if (pin_num < 28) + *reg = RK3506_PULL_GPIO1_OFFSET; + else + ret = -EINVAL; + break; + + case 2: + *regmap = info->regmap_base; + if (pin_num < 17) + *reg = RK3506_PULL_GPIO2_OFFSET; + else + ret = -EINVAL; + break; + + case 3: + *regmap = info->regmap_base; + if (pin_num < 15) + *reg = RK3506_PULL_GPIO3_OFFSET; + else + ret = -EINVAL; + break; + + case 4: + *regmap = info->regmap_base; + if (pin_num < 8 || pin_num > 11) { + ret = -EINVAL; + } else { + *reg = RK3506_PULL_GPIO4_OFFSET; + *bit = 13; + + return 0; + } + break; + + default: + ret = -EINVAL; + break; + } + + if (ret) { + dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num); + + return ret; + } + + *reg += ((pin_num / RK3506_PULL_PINS_PER_REG) * 4); + *bit = pin_num % RK3506_PULL_PINS_PER_REG; + *bit *= RK3506_PULL_BITS_PER_PIN; + + return 0; +} + +#define RK3506_SMT_BITS_PER_PIN 1 +#define RK3506_SMT_PINS_PER_REG 8 +#define RK3506_SMT_GPIO0_A_OFFSET 0x400 +#define RK3506_SMT_GPIO0_D_OFFSET 0x830 +#define RK3506_SMT_GPIO1_OFFSET 0x410 +#define RK3506_SMT_GPIO2_OFFSET 0x420 +#define RK3506_SMT_GPIO3_OFFSET 0x430 +#define RK3506_SMT_GPIO4_OFFSET 0x840 + +static int rk3506_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, + struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + int ret = 0; + + switch (bank->bank_num) { + case 0: + *regmap = info->regmap_pmu; + if (pin_num > 24) { + ret = -EINVAL; + } else if (pin_num < 24) { + *reg = RK3506_SMT_GPIO0_A_OFFSET; + } else { + *reg = RK3506_SMT_GPIO0_D_OFFSET; + *bit = 9; + + return 0; + } + break; + + case 1: + *regmap = info->regmap_ioc1; + if (pin_num < 28) + *reg = RK3506_SMT_GPIO1_OFFSET; + else + ret = -EINVAL; + break; + + case 2: + *regmap = info->regmap_base; + if (pin_num < 17) + *reg = RK3506_SMT_GPIO2_OFFSET; + else + ret = -EINVAL; + break; + + case 3: + *regmap = info->regmap_base; + if (pin_num < 15) + *reg = RK3506_SMT_GPIO3_OFFSET; + else + ret = -EINVAL; + break; + + case 4: + *regmap = info->regmap_base; + if (pin_num < 8 || pin_num > 11) { + ret = -EINVAL; + } else { + *reg = RK3506_SMT_GPIO4_OFFSET; + *bit = 8; + + return 0; + } + break; + + default: + ret = -EINVAL; + break; + } + + if (ret) { + dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num); + + return ret; + } + + *reg += ((pin_num / RK3506_SMT_PINS_PER_REG) * 4); + *bit = pin_num % RK3506_SMT_PINS_PER_REG; + *bit *= RK3506_SMT_BITS_PER_PIN; + + return 0; +} + +#define RK3528_DRV_BITS_PER_PIN 8 +#define RK3528_DRV_PINS_PER_REG 2 +#define RK3528_DRV_GPIO0_OFFSET 0x100 +#define RK3528_DRV_GPIO1_OFFSET 0x20120 +#define RK3528_DRV_GPIO2_OFFSET 0x30160 +#define RK3528_DRV_GPIO3_OFFSET 0x20190 +#define RK3528_DRV_GPIO4_OFFSET 0x101C0 + +static int rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + *regmap = info->regmap_base; + + if (bank->bank_num == 0) + *reg = RK3528_DRV_GPIO0_OFFSET; + else if (bank->bank_num == 1) + *reg = RK3528_DRV_GPIO1_OFFSET; + else if (bank->bank_num == 2) + *reg = RK3528_DRV_GPIO2_OFFSET; + else if (bank->bank_num == 3) + *reg = RK3528_DRV_GPIO3_OFFSET; + else if (bank->bank_num == 4) + *reg = RK3528_DRV_GPIO4_OFFSET; + else + dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); + + *reg += ((pin_num / RK3528_DRV_PINS_PER_REG) * 4); + *bit = pin_num % RK3528_DRV_PINS_PER_REG; + *bit *= RK3528_DRV_BITS_PER_PIN; + + return 0; +} + +#define RK3528_PULL_BITS_PER_PIN 2 +#define RK3528_PULL_PINS_PER_REG 8 +#define RK3528_PULL_GPIO0_OFFSET 0x200 +#define RK3528_PULL_GPIO1_OFFSET 0x20210 +#define RK3528_PULL_GPIO2_OFFSET 0x30220 +#define RK3528_PULL_GPIO3_OFFSET 0x20230 +#define RK3528_PULL_GPIO4_OFFSET 0x10240 + +static int rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + *regmap = info->regmap_base; + + if (bank->bank_num == 0) + *reg = RK3528_PULL_GPIO0_OFFSET; + else if (bank->bank_num == 1) + *reg = RK3528_PULL_GPIO1_OFFSET; + else if (bank->bank_num == 2) + *reg = RK3528_PULL_GPIO2_OFFSET; + else if (bank->bank_num == 3) + *reg = RK3528_PULL_GPIO3_OFFSET; + else if (bank->bank_num == 4) + *reg = RK3528_PULL_GPIO4_OFFSET; + else + dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); + + *reg += ((pin_num / RK3528_PULL_PINS_PER_REG) * 4); + *bit = pin_num % RK3528_PULL_PINS_PER_REG; + *bit *= RK3528_PULL_BITS_PER_PIN; + + return 0; +} + +#define RK3528_SMT_BITS_PER_PIN 1 +#define RK3528_SMT_PINS_PER_REG 8 +#define RK3528_SMT_GPIO0_OFFSET 0x400 +#define RK3528_SMT_GPIO1_OFFSET 0x20410 +#define RK3528_SMT_GPIO2_OFFSET 0x30420 +#define RK3528_SMT_GPIO3_OFFSET 0x20430 +#define RK3528_SMT_GPIO4_OFFSET 0x10440 + +static int rk3528_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, + struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + *regmap = info->regmap_base; + + if (bank->bank_num == 0) + *reg = RK3528_SMT_GPIO0_OFFSET; + else if (bank->bank_num == 1) + *reg = RK3528_SMT_GPIO1_OFFSET; + else if (bank->bank_num == 2) + *reg = RK3528_SMT_GPIO2_OFFSET; + else if (bank->bank_num == 3) + *reg = RK3528_SMT_GPIO3_OFFSET; + else if (bank->bank_num == 4) + *reg = RK3528_SMT_GPIO4_OFFSET; + else + dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); + + *reg += ((pin_num / RK3528_SMT_PINS_PER_REG) * 4); + *bit = pin_num % RK3528_SMT_PINS_PER_REG; + *bit *= RK3528_SMT_BITS_PER_PIN; + + return 0; +} + +#define RK3562_DRV_BITS_PER_PIN 8 +#define RK3562_DRV_PINS_PER_REG 2 +#define RK3562_DRV_GPIO0_OFFSET 0x20070 +#define RK3562_DRV_GPIO1_OFFSET 0x200 +#define RK3562_DRV_GPIO2_OFFSET 0x240 +#define RK3562_DRV_GPIO3_OFFSET 0x10280 +#define RK3562_DRV_GPIO4_OFFSET 0x102C0 + +static int rk3562_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + *regmap = info->regmap_base; + switch (bank->bank_num) { + case 0: + *reg = RK3562_DRV_GPIO0_OFFSET; + break; + + case 1: + *reg = RK3562_DRV_GPIO1_OFFSET; + break; + + case 2: + *reg = RK3562_DRV_GPIO2_OFFSET; + break; + + case 3: + *reg = RK3562_DRV_GPIO3_OFFSET; + break; + + case 4: + *reg = RK3562_DRV_GPIO4_OFFSET; + break; + + default: + dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); + break; + } + + *reg += ((pin_num / RK3562_DRV_PINS_PER_REG) * 4); + *bit = pin_num % RK3562_DRV_PINS_PER_REG; + *bit *= RK3562_DRV_BITS_PER_PIN; + + return 0; +} + +#define RK3562_PULL_BITS_PER_PIN 2 +#define RK3562_PULL_PINS_PER_REG 8 +#define RK3562_PULL_GPIO0_OFFSET 0x20020 +#define RK3562_PULL_GPIO1_OFFSET 0x80 +#define RK3562_PULL_GPIO2_OFFSET 0x90 +#define RK3562_PULL_GPIO3_OFFSET 0x100A0 +#define RK3562_PULL_GPIO4_OFFSET 0x100B0 + +static int rk3562_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + *regmap = info->regmap_base; + switch (bank->bank_num) { + case 0: + *reg = RK3562_PULL_GPIO0_OFFSET; + break; + + case 1: + *reg = RK3562_PULL_GPIO1_OFFSET; + break; + + case 2: + *reg = RK3562_PULL_GPIO2_OFFSET; + break; + + case 3: + *reg = RK3562_PULL_GPIO3_OFFSET; + break; + + case 4: + *reg = RK3562_PULL_GPIO4_OFFSET; + break; + + default: + dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); + break; + } + + *reg += ((pin_num / RK3562_PULL_PINS_PER_REG) * 4); + *bit = pin_num % RK3562_PULL_PINS_PER_REG; + *bit *= RK3562_PULL_BITS_PER_PIN; + + return 0; +} + +#define RK3562_SMT_BITS_PER_PIN 2 +#define RK3562_SMT_PINS_PER_REG 8 +#define RK3562_SMT_GPIO0_OFFSET 0x20030 +#define RK3562_SMT_GPIO1_OFFSET 0xC0 +#define RK3562_SMT_GPIO2_OFFSET 0xD0 +#define RK3562_SMT_GPIO3_OFFSET 0x100E0 +#define RK3562_SMT_GPIO4_OFFSET 0x100F0 + +static int rk3562_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, + struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + *regmap = info->regmap_base; + switch (bank->bank_num) { + case 0: + *reg = RK3562_SMT_GPIO0_OFFSET; + break; + + case 1: + *reg = RK3562_SMT_GPIO1_OFFSET; + break; + + case 2: + *reg = RK3562_SMT_GPIO2_OFFSET; + break; + + case 3: + *reg = RK3562_SMT_GPIO3_OFFSET; + break; + + case 4: + *reg = RK3562_SMT_GPIO4_OFFSET; + break; + + default: + dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); + break; + } + + *reg += ((pin_num / RK3562_SMT_PINS_PER_REG) * 4); + *bit = pin_num % RK3562_SMT_PINS_PER_REG; + *bit *= RK3562_SMT_BITS_PER_PIN; + + return 0; +} + #define RK3568_PULL_PMU_OFFSET 0x20 #define RK3568_PULL_GRF_OFFSET 0x80 #define RK3568_PULL_BITS_PER_PIN 2 @@ -2187,7 +2756,10 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, rmask_bits = RK3588_DRV_BITS_PER_PIN; ret = strength; goto config; - } else if (ctrl->type == RK3568) { + } else if (ctrl->type == RK3506 || + ctrl->type == RK3528 || + ctrl->type == RK3562 || + ctrl->type == RK3568) { rmask_bits = RK3568_DRV_BITS_PER_PIN; ret = (1 << (strength + 1)) - 1; goto config; @@ -2264,12 +2836,37 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, case DRV_TYPE_IO_1V8_ONLY: rmask_bits = RK3288_DRV_BITS_PER_PIN; break; + case DRV_TYPE_IO_LEVEL_2_BIT: + ret = regmap_read(regmap, reg, &data); + if (ret) + return ret; + data >>= bit; + + return data & 0x3; + case DRV_TYPE_IO_LEVEL_8_BIT: + ret = regmap_read(regmap, reg, &data); + if (ret) + return ret; + data >>= bit; + data &= (1 << 8) - 1; + + ret = hweight8(data); + if (ret > 0) + return ret - 1; + else + return -EINVAL; default: dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type); return -EINVAL; } config: + if (ctrl->type == RK3506) { + if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4) { + rmask_bits = 2; + ret = strength; + } + } /* enable the write to the equivalent lower bits */ data = ((1 << rmask_bits) - 1) << (bit + 16); rmask = data | (data >> 16); @@ -2332,6 +2929,9 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, case RK3308: case RK3368: case RK3399: + case RK3506: + case RK3528: + case RK3562: case RK3568: case RK3576: case RK3588: @@ -2711,6 +3311,9 @@ static int rockchip_pinctrl_probe(struct device *dev) dev->priv = info; + /* try to find the optional reference to the ioc1 syscon */ + info->regmap_ioc1 = syscon_regmap_lookup_by_phandle_optional(np, "rockchip,ioc1"); + ret = of_platform_populate(np, NULL, dev); if (ret) return dev_err_probe(dev, ret, "failed to register gpio device\n"); @@ -3120,6 +3723,157 @@ static __maybe_unused struct rockchip_pin_ctrl rk3399_pin_ctrl = { .drv_calc_reg = rk3399_calc_drv_reg_and_bit, }; +static struct rockchip_pin_bank rk3506_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS_PULL_FLAGS(0, 32, "gpio0", + IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, + IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, + IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, + IOMUX_WIDTH_2BIT | IOMUX_SOURCE_PMU, + 0x0, 0x8, 0x10, 0x830, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_2_BIT, + 0, 0, 0, 1), + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(1, 32, "gpio1", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x20, 0x28, 0x30, 0x38, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT), + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(2, 32, "gpio2", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x40, 0x48, 0x50, 0x58, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT), + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(3, 32, "gpio3", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x60, 0x68, 0x70, 0x78, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT), + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS_PULL_FLAGS(4, 32, "gpio4", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x80, 0x88, 0x90, 0x98, + DRV_TYPE_IO_LEVEL_2_BIT, + DRV_TYPE_IO_LEVEL_2_BIT, + DRV_TYPE_IO_LEVEL_2_BIT, + DRV_TYPE_IO_LEVEL_2_BIT, + 1, 1, 1, 1), +}; + +static struct rockchip_pin_ctrl rk3506_pin_ctrl __maybe_unused = { + .pin_banks = rk3506_pin_banks, + .nr_banks = ARRAY_SIZE(rk3506_pin_banks), + .label = "RK3506-GPIO", + .type = RK3506, + .pull_calc_reg = rk3506_calc_pull_reg_and_bit, + .drv_calc_reg = rk3506_calc_drv_reg_and_bit, + .schmitt_calc_reg = rk3506_calc_schmitt_reg_and_bit, +}; + +static struct rockchip_pin_bank rk3528_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0, 0, 0, 0), + PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x20020, 0x20028, 0x20030, 0x20038), + PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x30040, 0, 0, 0), + PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x20060, 0x20068, 0x20070, 0), + PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x10080, 0x10088, 0x10090, 0x10098), +}; + +static struct rockchip_pin_ctrl rk3528_pin_ctrl __maybe_unused = { + .pin_banks = rk3528_pin_banks, + .nr_banks = ARRAY_SIZE(rk3528_pin_banks), + .label = "RK3528-GPIO", + .type = RK3528, + .pull_calc_reg = rk3528_calc_pull_reg_and_bit, + .drv_calc_reg = rk3528_calc_drv_reg_and_bit, + .schmitt_calc_reg = rk3528_calc_schmitt_reg_and_bit, +}; + +static struct rockchip_pin_bank rk3562_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x20000, 0x20008, 0x20010, 0x20018), + PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0, 0x08, 0x10, 0x18), + PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x20, 0, 0, 0), + PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x10040, 0x10048, 0x10050, 0x10058), + PIN_BANK_IOMUX_FLAGS_OFFSET(4, 16, "gpio4", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0, + 0, + 0x10060, 0x10068, 0, 0), +}; + +static struct rockchip_pin_ctrl rk3562_pin_ctrl __maybe_unused = { + .pin_banks = rk3562_pin_banks, + .nr_banks = ARRAY_SIZE(rk3562_pin_banks), + .label = "RK3562-GPIO", + .type = RK3562, + .pull_calc_reg = rk3562_calc_pull_reg_and_bit, + .drv_calc_reg = rk3562_calc_drv_reg_and_bit, + .schmitt_calc_reg = rk3562_calc_schmitt_reg_and_bit, +}; + static __maybe_unused struct rockchip_pin_bank rk3568_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, @@ -3266,6 +4020,18 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = { { .compatible = "rockchip,rk3399-pinctrl", .data = &rk3399_pin_ctrl }, #endif +#ifdef CONFIG_ARCH_RK3506 + { .compatible = "rockchip,rk3506-pinctrl", + .data = &rk3506_pin_ctrl }, +#endif +#ifdef CONFIG_ARCH_RK3528 + { .compatible = "rockchip,rk3528-pinctrl", + .data = &rk3528_pin_ctrl }, +#endif +#ifdef CONFIG_ARCH_RK3562 + { .compatible = "rockchip,rk3562-pinctrl", + .data = &rk3562_pin_ctrl }, +#endif #ifdef CONFIG_ARCH_RK3568 { .compatible = "rockchip,rk3568-pinctrl", .data = &rk3568_pin_ctrl }, diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h index f9c00f802b..62c542bc68 100644 --- a/drivers/pinctrl/pinctrl-rockchip.h +++ b/drivers/pinctrl/pinctrl-rockchip.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2020-2021 Rockchip Electronics Co. Ltd. + * Copyright (c) 2020-2024 Rockchip Electronics Co., Ltd. * * Copyright (c) 2013 MundoReader S.L. * Author: Heiko Stuebner <heiko@sntech.de> @@ -18,6 +18,8 @@ #ifndef _PINCTRL_ROCKCHIP_H #define _PINCTRL_ROCKCHIP_H +#include <linux/types.h> + #define RK_GPIO0_A0 0 #define RK_GPIO0_A1 1 #define RK_GPIO0_A2 2 @@ -193,49 +195,17 @@ enum rockchip_pinctrl_type { RK3188, RK3288, RK3308, + RK3328, RK3368, RK3399, + RK3506, + RK3528, + RK3562, RK3568, RK3576, RK3588, }; -/** - * struct rockchip_gpio_regs - * @port_dr: data register - * @port_ddr: data direction register - * @int_en: interrupt enable - * @int_mask: interrupt mask - * @int_type: interrupt trigger type, such as high, low, edge trriger type. - * @int_polarity: interrupt polarity enable register - * @int_bothedge: interrupt bothedge enable register - * @int_status: interrupt status register - * @int_rawstatus: int_status = int_rawstatus & int_mask - * @debounce: enable debounce for interrupt signal - * @dbclk_div_en: enable divider for debounce clock - * @dbclk_div_con: setting for divider of debounce clock - * @port_eoi: end of interrupt of the port - * @ext_port: port data from external - * @version_id: controller version register - */ -struct rockchip_gpio_regs { - u32 port_dr; - u32 port_ddr; - u32 int_en; - u32 int_mask; - u32 int_type; - u32 int_polarity; - u32 int_bothedge; - u32 int_status; - u32 int_rawstatus; - u32 debounce; - u32 dbclk_div_en; - u32 dbclk_div_con; - u32 port_eoi; - u32 ext_port; - u32 version_id; -}; - /** * struct rockchip_iomux * @type: iomux variant using IOMUX_* constants @@ -257,6 +227,8 @@ enum rockchip_pin_drv_type { DRV_TYPE_IO_1V8_ONLY, DRV_TYPE_IO_1V8_3V0_AUTO, DRV_TYPE_IO_3V3_ONLY, + DRV_TYPE_IO_LEVEL_2_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, DRV_TYPE_MAX }; @@ -301,15 +273,10 @@ struct rockchip_drv { * @valid: is all necessary information present * @of_node: dt node of this bank * @drvdata: common pinctrl basedata - * @domain: irqdomain of the gpio bank - * @gpio_chip: gpiolib chip - * @grange: gpio range - * @slock: spinlock for the gpio bank * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode * @recalced_mask: bit mask to indicate a need to recalulate the mask * @route_mask: bits describing the routing pins of per bank * @deferred_output: gpio output settings to be done after gpio bank probed - * @deferred_lock: mutex for the deferred_output shared btw gpio and pinctrl */ struct rockchip_pin_bank { struct device *dev; @@ -445,6 +412,7 @@ struct rockchip_pinctrl { int reg_size; struct regmap *regmap_pull; struct regmap *regmap_pmu; + struct regmap *regmap_ioc1; struct device *dev; struct rockchip_pin_ctrl *ctrl; struct pinctrl_device pctl_dev; diff --git a/include/mfd/syscon.h b/include/mfd/syscon.h index 288dd464b7..215b97ab3e 100644 --- a/include/mfd/syscon.h +++ b/include/mfd/syscon.h @@ -25,6 +25,8 @@ struct regmap *syscon_regmap_lookup_by_compatible(const char *s); extern struct regmap *syscon_regmap_lookup_by_phandle( struct device_node *np, const char *property); +struct regmap *syscon_regmap_lookup_by_phandle_optional(struct device_node *np, + const char *property); #else static inline void __iomem *syscon_base_lookup_by_phandle (struct device_node *np, const char *property) @@ -50,6 +52,12 @@ static inline struct regmap *syscon_regmap_lookup_by_phandle( { return ERR_PTR(-ENOSYS); } +static inline struct regmap *syscon_regmap_lookup_by_phandle_optional( + struct device_node *np, + const char *property) +{ + return NULL; +} #endif #endif -- 2.43.0 ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 04/14] ARM: boards: Rockchip: add RK3562-EVB2 support 2026-01-30 5:16 [PATCH v2 00/14] ARM: rockchip: Add initial RK3562 SoC support Sohaib Mohamed ` (2 preceding siblings ...) 2026-01-30 5:16 ` [PATCH v2 03/14] pinctrl: rockchip: sync driver with Linux Sohaib Mohamed @ 2026-01-30 5:16 ` Sohaib Mohamed 2026-01-30 5:16 ` [PATCH v2 05/14] ARM: boards: Rockchip: Add device tree for kickpi k3 board Sohaib Mohamed ` (9 subsequent siblings) 13 siblings, 0 replies; 23+ messages in thread From: Sohaib Mohamed @ 2026-01-30 5:16 UTC (permalink / raw) To: Sascha Hauer, BAREBOX; +Cc: Sohaib Mohamed, Ahmad Fatoum From: Ahmad Fatoum <a.fatoum@pengutronix.de> Add board support for RK3562-EVB2 with boot source detection and BBU handlers for eMMC and SD card. Co-developed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sohaib Mohamed <sohaib.amhmd@gmail.com> --- arch/arm/boards/Makefile | 1 + arch/arm/boards/rockchip-rk3562-evb2/.gitignore | 1 + arch/arm/boards/rockchip-rk3562-evb2/Makefile | 4 +++ arch/arm/boards/rockchip-rk3562-evb2/board.c | 47 +++++++++++++++++++++++++ arch/arm/boards/rockchip-rk3562-evb2/lowlevel.c | 23 ++++++++++++ arch/arm/configs/multi_v8_defconfig | 1 + arch/arm/configs/rockchip_v8_defconfig | 1 + arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3562-evb2-v10.dts | 9 +++++ arch/arm/dts/rk3562.dtsi | 40 +++++++++++++++++++++ arch/arm/mach-rockchip/Kconfig | 6 ++++ images/Makefile.rockchip | 1 + 12 files changed, 135 insertions(+) diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index 4c586de2a9..946af95560 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -185,6 +185,7 @@ obj-$(CONFIG_MACH_TQMLS1046A) += tqmls1046a/ obj-$(CONFIG_MACH_LS1021AIOT) += ls1021aiot/ obj-$(CONFIG_MACH_MNT_REFORM) += mnt-reform/ obj-$(CONFIG_MACH_SKOV_ARM9CPU) += skov-arm9cpu/ +obj-$(CONFIG_MACH_RK3562_EVB2) += rockchip-rk3562-evb2/ obj-$(CONFIG_MACH_RK3568_EVB) += rockchip-rk3568-evb/ obj-$(CONFIG_MACH_RK3568_BPI_R2PRO) += rockchip-rk3568-bpi-r2pro/ obj-$(CONFIG_MACH_PINE64_PINETAB2) += pine64-pinetab2/ diff --git a/arch/arm/boards/rockchip-rk3562-evb2/.gitignore b/arch/arm/boards/rockchip-rk3562-evb2/.gitignore new file mode 100644 index 0000000000..f458f794b5 --- /dev/null +++ b/arch/arm/boards/rockchip-rk3562-evb2/.gitignore @@ -0,0 +1 @@ +sdram-init.bin diff --git a/arch/arm/boards/rockchip-rk3562-evb2/Makefile b/arch/arm/boards/rockchip-rk3562-evb2/Makefile new file mode 100644 index 0000000000..da63d2625f --- /dev/null +++ b/arch/arm/boards/rockchip-rk3562-evb2/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/rockchip-rk3562-evb2/board.c b/arch/arm/boards/rockchip-rk3562-evb2/board.c new file mode 100644 index 0000000000..d00815822e --- /dev/null +++ b/arch/arm/boards/rockchip-rk3562-evb2/board.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#define pr_fmt(fmt) "rk3562-evb: " fmt + +#include <common.h> +#include <init.h> +#include <mach/rockchip/bbu.h> +#include <aiodev.h> +#include <bootsource.h> +#include <environment.h> +#include <globalvar.h> +#include <magicvar.h> +#include <deep-probe.h> + +static int rk3562_evb2_probe(struct device *dev) +{ + int emmc_bbu_flag = 0; + int sd_bbu_flag = 0; + + if (bootsource_get() == BOOTSOURCE_MMC) { + if (bootsource_get_instance() == 2) + emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + else + sd_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } else { + emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } + + rockchip_bbu_mmc_register("sd", sd_bbu_flag, "/dev/mmc1"); + rockchip_bbu_mmc_register("emmc", emmc_bbu_flag, "/dev/mmc0"); + + return 0; +} + +static const struct of_device_id rk3562_evb2_of_match[] = { + { .compatible = "rockchip,rk3562-evb2-v10" }, + { /* Sentinel */}, +}; + +static struct driver rk3562_evb2_board_driver = { + .name = "board-rk3562-evb", + .probe = rk3562_evb2_probe, + .of_compatible = rk3562_evb2_of_match, +}; +coredevice_platform_driver(rk3562_evb2_board_driver); + +BAREBOX_DEEP_PROBE_ENABLE(rk3562_evb2_of_match); diff --git a/arch/arm/boards/rockchip-rk3562-evb2/lowlevel.c b/arch/arm/boards/rockchip-rk3562-evb2/lowlevel.c new file mode 100644 index 0000000000..474f1a1332 --- /dev/null +++ b/arch/arm/boards/rockchip-rk3562-evb2/lowlevel.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <common.h> +#include <asm/barebox-arm.h> +#include <mach/rockchip/hardware.h> +#include <mach/rockchip/atf.h> +#include <debug_ll.h> + +extern char __dtb_rk3562_evb2_v10_start[]; + +ENTRY_FUNCTION(start_rk3562_evb2, r0, r1, r2) +{ + putc_ll('>'); + + if (current_el() == 3) + relocate_to_adr_full(RK3562_BAREBOX_LOAD_ADDRESS); + else + relocate_to_current_adr(); + + setup_c(); + + rk3562_barebox_entry(__dtb_rk3562_evb2_v10_start); +} diff --git a/arch/arm/configs/multi_v8_defconfig b/arch/arm/configs/multi_v8_defconfig index e63bb46189..e576cecd89 100644 --- a/arch/arm/configs/multi_v8_defconfig +++ b/arch/arm/configs/multi_v8_defconfig @@ -29,6 +29,7 @@ CONFIG_MACH_TQMA93XX=y CONFIG_MACH_NXP_IMX93_FRDM=y CONFIG_IMX_IIM=y CONFIG_MACH_BEAGLEPLAY=y +CONFIG_MACH_RK3562_EVB2=y CONFIG_MACH_RK3568_EVB=y CONFIG_MACH_RK3568_BPI_R2PRO=y CONFIG_MACH_PINE64_PINETAB2=y diff --git a/arch/arm/configs/rockchip_v8_defconfig b/arch/arm/configs/rockchip_v8_defconfig index f8f8ceb805..3e5f76077d 100644 --- a/arch/arm/configs/rockchip_v8_defconfig +++ b/arch/arm/configs/rockchip_v8_defconfig @@ -1,4 +1,5 @@ CONFIG_ARCH_ROCKCHIP=y +CONFIG_MACH_RK3562_EVB2=y CONFIG_MACH_RK3568_EVB=y CONFIG_MACH_RK3568_BPI_R2PRO=y CONFIG_MACH_PINE64_PINETAB2=y diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a84e09e388..d5e37d3e4e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -139,6 +139,7 @@ lwl-$(CONFIG_MACH_RADXA_ROCK5) += \ lwl-$(CONFIG_MACH_RADXA_CM3) += rk3566-cm3-io.dtb.o lwl-$(CONFIG_MACH_PHYTEC_SOM_RK3288) += rk3288-phycore-som.dtb.o lwl-$(CONFIG_MACH_REALQ7) += imx6q-dmo-edmqmx6.dtb.o +lwl-$(CONFIG_MACH_RK3562_EVB2) += rk3562-evb2-v10.dtb.o lwl-$(CONFIG_MACH_RK3568_EVB) += rk3568-evb1-v10.dtb.o lwl-$(CONFIG_MACH_RK3568_BPI_R2PRO) += rk3568-bpi-r2-pro.dtb.o lwl-$(CONFIG_MACH_RPI) += bcm2835-rpi.dtb.o diff --git a/arch/arm/dts/rk3562-evb2-v10.dts b/arch/arm/dts/rk3562-evb2-v10.dts new file mode 100644 index 0000000000..40a5084ee3 --- /dev/null +++ b/arch/arm/dts/rk3562-evb2-v10.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include <arm64/rockchip/rk3562-evb2-v10.dts> +#include "rk3562.dtsi" diff --git a/arch/arm/dts/rk3562.dtsi b/arch/arm/dts/rk3562.dtsi new file mode 100644 index 0000000000..f1a291d456 --- /dev/null +++ b/arch/arm/dts/rk3562.dtsi @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/ { + aliases { + pmugrf.reboot_mode = &reboot_mode; + pwm0 = &pwm0; + pwm1 = &pwm1; + pwm2 = &pwm2; + pwm3 = &pwm3; + pwm4 = &pwm4; + pwm5 = &pwm5; + pwm6 = &pwm6; + pwm7 = &pwm7; + pwm8 = &pwm8; + pwm9 = &pwm9; + pwm10 = &pwm10; + pwm11 = &pwm11; + pwm12 = &pwm12; + pwm13 = &pwm13; + pwm14 = &pwm14; + pwm15 = &pwm15; + i2c0 = &i2c0; + i2c5 = &i2c5; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &sfc; + }; + + chosen { + barebox,bootsource-mmc0 = &sdhci; + barebox,bootsource-mmc1 = &sdmmc0; + barebox,bootsource-mmc2 = &sdmmc1; + }; + + dmc: memory-controller { + compatible = "rockchip,rk3562-dmc"; + rockchip,pmu = <&pmu_grf>; + }; +}; diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index a91e7db72d..d359307eb7 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -64,6 +64,12 @@ endif if 64BIT +config MACH_RK3562_EVB2 + select ARCH_RK3562 + bool "RK3562 EVB2" + help + Say Y here if you are using a RK3562 EVB2 + config MACH_RK3568_EVB select ARCH_RK3568 bool "RK3568 EVB" diff --git a/images/Makefile.rockchip b/images/Makefile.rockchip index 191ef15aab..1122db4629 100644 --- a/images/Makefile.rockchip +++ b/images/Makefile.rockchip @@ -37,6 +37,7 @@ pblb-$(CONFIG_MACH_PHYTEC_SOM_RK3288) += start_rk3288_phycore_som FILE_barebox-rk3288-phycore-som.img = start_rk3288_phycore_som.pblb image-$(CONFIG_MACH_PHYTEC_SOM_RK3288) += barebox-rk3288-phycore-som.img +$(call build_rockchip_image, CONFIG_MACH_RK3562_EVB2, start_rk3562_evb2, rockchip-rk3562-evb2/sdram-init.bin, rk3562-evb2) $(call build_rockchip_image, CONFIG_MACH_RK3568_EVB, start_rk3568_evb, rockchip-rk3568-evb/sdram-init.bin, rk3568-evb) $(call build_rockchip_image, CONFIG_MACH_RK3568_BPI_R2PRO, start_rk3568_bpi_r2pro, rockchip-rk3568-bpi-r2pro/sdram-init.bin, rk3568-bpi-r2pro) $(call build_rockchip_image, CONFIG_MACH_PINE64_PINETAB2, start_pinetab2_v0, pine64-pinetab2/sdram-init.bin, pinetab2-v0) -- 2.43.0 ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 05/14] ARM: boards: Rockchip: Add device tree for kickpi k3 board 2026-01-30 5:16 [PATCH v2 00/14] ARM: rockchip: Add initial RK3562 SoC support Sohaib Mohamed ` (3 preceding siblings ...) 2026-01-30 5:16 ` [PATCH v2 04/14] ARM: boards: Rockchip: add RK3562-EVB2 support Sohaib Mohamed @ 2026-01-30 5:16 ` Sohaib Mohamed 2026-01-30 5:16 ` [PATCH v2 06/14] ARM: rockchip: Add RK3562 KickPi K3 board support Sohaib Mohamed ` (8 subsequent siblings) 13 siblings, 0 replies; 23+ messages in thread From: Sohaib Mohamed @ 2026-01-30 5:16 UTC (permalink / raw) To: Sascha Hauer, BAREBOX; +Cc: Sohaib Mohamed Add device tree for RK3562 KickPi K3 board with RK809 PMIC, eMMC/SD, PCIe, UARTs, I2C, and GPIO LEDs. Signed-off-by: Sohaib Mohamed <sohaib.amhmd@gmail.com> --- arch/arm/dts/rk3562-kickpi-k3.dtsi | 452 +++++++++++++++++++++++++++++++++++++ 1 file changed, 452 insertions(+) diff --git a/arch/arm/dts/rk3562-kickpi-k3.dtsi b/arch/arm/dts/rk3562-kickpi-k3.dtsi new file mode 100644 index 0000000000..ad5349d7c4 --- /dev/null +++ b/arch/arm/dts/rk3562-kickpi-k3.dtsi @@ -0,0 +1,452 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2026, Sohaib Mohamed <sohaib.amhmd@gmail.com> + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <arm64/rockchip/rk3562.dtsi> + +/ { + model = "Rockchip RK3562 kickpi k3"; + compatible = "kickpi,rk3562-kickpi-k3", "rockchip,rk3562"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; + + vcc3v3_pcie20: regulator-vcc3v3-pcie20 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie20"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&dc_12v>; + }; + + + vcc5v0_usb: regulator-vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb_otg: regulator-vcc5v0-usb-otg { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg_pwren>; + }; + + dc_12v: regulator-dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc3v3_clk: regulator-vcc3v3-clk { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_clk"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_sys: regulator-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc25_ddr: regulator-vcc25-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc25_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vin-supply = <&vcc3v3_sys>; + }; + + leds: leds { + compatible = "gpio-leds"; + gpio3c0 { + gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + gpio3c1 { + gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + gpio0a6 { + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + gpio4b6 { + gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + work_led: work-led { + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + fan: fan { + gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; +}; + +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m0_xfer>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4m0_xfer>; + status = "okay"; +}; + +&combphy { + status = "okay"; +}; + +&pcie2x1 { + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie20>; + status = "okay"; +}; + +&pinctrl { + usb { + usb_otg_pwren: usb-otg-pwren { + rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + headphone { + hp_det: hp-det { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3m0_xfer>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&sdmmc0 { + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + pmic-reset-func = <0>; + not-save-power-en = <1>; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_cpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG1 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; -- 2.43.0 ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 06/14] ARM: rockchip: Add RK3562 KickPi K3 board support 2026-01-30 5:16 [PATCH v2 00/14] ARM: rockchip: Add initial RK3562 SoC support Sohaib Mohamed ` (4 preceding siblings ...) 2026-01-30 5:16 ` [PATCH v2 05/14] ARM: boards: Rockchip: Add device tree for kickpi k3 board Sohaib Mohamed @ 2026-01-30 5:16 ` Sohaib Mohamed 2026-01-30 5:16 ` [PATCH v2 07/14] pmdomain: rockchip: Add RK3562 power domain support Sohaib Mohamed ` (7 subsequent siblings) 13 siblings, 0 replies; 23+ messages in thread From: Sohaib Mohamed @ 2026-01-30 5:16 UTC (permalink / raw) To: Sascha Hauer, BAREBOX; +Cc: Sohaib Mohamed KICKPI-K3 is a development board based on Rockchip RK3562, the main control chip. It has a quad-core 64-bit Cortex-A53 processor, a main frequency of up to 2.0GHz, low power consumption, and high performance. Signed-off-by: Sohaib Mohamed <sohaib.amhmd@gmail.com> --- arch/arm/boards/Makefile | 1 + .../boards/rockchip-rk3562-kickpi-k3/.gitignore | 1 + arch/arm/boards/rockchip-rk3562-kickpi-k3/Makefile | 4 ++ arch/arm/boards/rockchip-rk3562-kickpi-k3/board.c | 44 ++++++++++++++++++++++ .../boards/rockchip-rk3562-kickpi-k3/lowlevel.c | 23 +++++++++++ arch/arm/configs/multi_v8_defconfig | 1 + arch/arm/configs/rockchip_v8_defconfig | 1 + arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3562-kickpi-k3.dts | 10 +++++ arch/arm/mach-rockchip/Kconfig | 6 +++ images/Makefile.rockchip | 1 + 11 files changed, 93 insertions(+) diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index 946af95560..2a8e85e0b3 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -186,6 +186,7 @@ obj-$(CONFIG_MACH_LS1021AIOT) += ls1021aiot/ obj-$(CONFIG_MACH_MNT_REFORM) += mnt-reform/ obj-$(CONFIG_MACH_SKOV_ARM9CPU) += skov-arm9cpu/ obj-$(CONFIG_MACH_RK3562_EVB2) += rockchip-rk3562-evb2/ +obj-$(CONFIG_MACH_RK3562_KICKPI_K3) += rockchip-rk3562-kickpi-k3/ obj-$(CONFIG_MACH_RK3568_EVB) += rockchip-rk3568-evb/ obj-$(CONFIG_MACH_RK3568_BPI_R2PRO) += rockchip-rk3568-bpi-r2pro/ obj-$(CONFIG_MACH_PINE64_PINETAB2) += pine64-pinetab2/ diff --git a/arch/arm/boards/rockchip-rk3562-kickpi-k3/.gitignore b/arch/arm/boards/rockchip-rk3562-kickpi-k3/.gitignore new file mode 100644 index 0000000000..f458f794b5 --- /dev/null +++ b/arch/arm/boards/rockchip-rk3562-kickpi-k3/.gitignore @@ -0,0 +1 @@ +sdram-init.bin diff --git a/arch/arm/boards/rockchip-rk3562-kickpi-k3/Makefile b/arch/arm/boards/rockchip-rk3562-kickpi-k3/Makefile new file mode 100644 index 0000000000..da63d2625f --- /dev/null +++ b/arch/arm/boards/rockchip-rk3562-kickpi-k3/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/rockchip-rk3562-kickpi-k3/board.c b/arch/arm/boards/rockchip-rk3562-kickpi-k3/board.c new file mode 100644 index 0000000000..6be79a8630 --- /dev/null +++ b/arch/arm/boards/rockchip-rk3562-kickpi-k3/board.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#define pr_fmt(fmt) "rk3562-kickpi-k3: " fmt + +#include <bootsource.h> +#include <common.h> +#include <init.h> +#include <mach/rockchip/bbu.h> + +static int rk3562_kickpi_k3_probe(struct device *dev) +{ + int emmc_bbu_flag = 0; + int sd_bbu_flag = 0; + + if (bootsource_get() == BOOTSOURCE_MMC) { + if (bootsource_get_instance() == 2) + emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + else + sd_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } else { + emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } + + rockchip_bbu_mmc_register("sd", sd_bbu_flag, "/dev/mmc1"); + rockchip_bbu_mmc_register("emmc", emmc_bbu_flag, "/dev/mmc0"); + + return 0; +} + +static const struct of_device_id rk3562_kickpi_k3_of_match[] = { + { + .compatible = "kickpi,rk3562-kickpi-k3", + }, + { /* Sentinel */}, +}; + +static struct driver rk3562_kickpi_k3_board_driver = { + .name = "board-rk3562-kickpi-k3", + .probe = rk3562_kickpi_k3_probe, + .of_compatible = rk3562_kickpi_k3_of_match, +}; +coredevice_platform_driver(rk3562_kickpi_k3_board_driver); + +BAREBOX_DEEP_PROBE_ENABLE(rk3562_kickpi_k3_of_match); diff --git a/arch/arm/boards/rockchip-rk3562-kickpi-k3/lowlevel.c b/arch/arm/boards/rockchip-rk3562-kickpi-k3/lowlevel.c new file mode 100644 index 0000000000..4afe83189d --- /dev/null +++ b/arch/arm/boards/rockchip-rk3562-kickpi-k3/lowlevel.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <common.h> +#include <asm/barebox-arm.h> +#include <mach/rockchip/hardware.h> +#include <mach/rockchip/atf.h> +#include <debug_ll.h> + +extern char __dtb_rk3562_kickpi_k3_start[]; + +ENTRY_FUNCTION(start_rk3562_kickpi_k3, r0, r1, r2) +{ + putc_ll('>'); + + if (current_el() == 3) + relocate_to_adr_full(RK3562_BAREBOX_LOAD_ADDRESS); + else + relocate_to_current_adr(); + + setup_c(); + + rk3562_barebox_entry(__dtb_rk3562_kickpi_k3_start); +} diff --git a/arch/arm/configs/multi_v8_defconfig b/arch/arm/configs/multi_v8_defconfig index e576cecd89..64ac712d4a 100644 --- a/arch/arm/configs/multi_v8_defconfig +++ b/arch/arm/configs/multi_v8_defconfig @@ -30,6 +30,7 @@ CONFIG_MACH_NXP_IMX93_FRDM=y CONFIG_IMX_IIM=y CONFIG_MACH_BEAGLEPLAY=y CONFIG_MACH_RK3562_EVB2=y +CONFIG_MACH_RK3562_KICKPI_K3=y CONFIG_MACH_RK3568_EVB=y CONFIG_MACH_RK3568_BPI_R2PRO=y CONFIG_MACH_PINE64_PINETAB2=y diff --git a/arch/arm/configs/rockchip_v8_defconfig b/arch/arm/configs/rockchip_v8_defconfig index 3e5f76077d..117117b047 100644 --- a/arch/arm/configs/rockchip_v8_defconfig +++ b/arch/arm/configs/rockchip_v8_defconfig @@ -1,5 +1,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_MACH_RK3562_EVB2=y +CONFIG_MACH_RK3562_KICKPI_K3=y CONFIG_MACH_RK3568_EVB=y CONFIG_MACH_RK3568_BPI_R2PRO=y CONFIG_MACH_PINE64_PINETAB2=y diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d5e37d3e4e..ac42a6a6ae 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -141,6 +141,7 @@ lwl-$(CONFIG_MACH_PHYTEC_SOM_RK3288) += rk3288-phycore-som.dtb.o lwl-$(CONFIG_MACH_REALQ7) += imx6q-dmo-edmqmx6.dtb.o lwl-$(CONFIG_MACH_RK3562_EVB2) += rk3562-evb2-v10.dtb.o lwl-$(CONFIG_MACH_RK3568_EVB) += rk3568-evb1-v10.dtb.o +lwl-$(CONFIG_MACH_RK3562_KICKPI_K3) += rk3562-kickpi-k3.dtb.o lwl-$(CONFIG_MACH_RK3568_BPI_R2PRO) += rk3568-bpi-r2-pro.dtb.o lwl-$(CONFIG_MACH_RPI) += bcm2835-rpi.dtb.o lwl-$(CONFIG_MACH_RPI2) += bcm2836-rpi-2.dtb.o diff --git a/arch/arm/dts/rk3562-kickpi-k3.dts b/arch/arm/dts/rk3562-kickpi-k3.dts new file mode 100644 index 0000000000..78e0578d9d --- /dev/null +++ b/arch/arm/dts/rk3562-kickpi-k3.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3562-kickpi-k3.dtsi" +#include "rk3562.dtsi" diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index d359307eb7..c1c96c545e 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -70,6 +70,12 @@ config MACH_RK3562_EVB2 help Say Y here if you are using a RK3562 EVB2 +config MACH_RK3562_KICKPI_K3 + select ARCH_RK3562 + bool "RK3562 KICKPI K3" + help + Say Y here if you are using a RK3562 KICKPI K3 + config MACH_RK3568_EVB select ARCH_RK3568 bool "RK3568 EVB" diff --git a/images/Makefile.rockchip b/images/Makefile.rockchip index 1122db4629..7651f88d62 100644 --- a/images/Makefile.rockchip +++ b/images/Makefile.rockchip @@ -38,6 +38,7 @@ FILE_barebox-rk3288-phycore-som.img = start_rk3288_phycore_som.pblb image-$(CONFIG_MACH_PHYTEC_SOM_RK3288) += barebox-rk3288-phycore-som.img $(call build_rockchip_image, CONFIG_MACH_RK3562_EVB2, start_rk3562_evb2, rockchip-rk3562-evb2/sdram-init.bin, rk3562-evb2) +$(call build_rockchip_image, CONFIG_MACH_RK3562_KICKPI_K3, start_rk3562_kickpi_k3, rockchip-rk3562-kickpi-k3/sdram-init.bin, rk3562-kickpi-k3) $(call build_rockchip_image, CONFIG_MACH_RK3568_EVB, start_rk3568_evb, rockchip-rk3568-evb/sdram-init.bin, rk3568-evb) $(call build_rockchip_image, CONFIG_MACH_RK3568_BPI_R2PRO, start_rk3568_bpi_r2pro, rockchip-rk3568-bpi-r2pro/sdram-init.bin, rk3568-bpi-r2pro) $(call build_rockchip_image, CONFIG_MACH_PINE64_PINETAB2, start_pinetab2_v0, pine64-pinetab2/sdram-init.bin, pinetab2-v0) -- 2.43.0 ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 07/14] pmdomain: rockchip: Add RK3562 power domain support 2026-01-30 5:16 [PATCH v2 00/14] ARM: rockchip: Add initial RK3562 SoC support Sohaib Mohamed ` (5 preceding siblings ...) 2026-01-30 5:16 ` [PATCH v2 06/14] ARM: rockchip: Add RK3562 KickPi K3 board support Sohaib Mohamed @ 2026-01-30 5:16 ` Sohaib Mohamed 2026-01-30 8:00 ` Ahmad Fatoum 2026-01-30 5:17 ` [PATCH v2 08/14] aiodev: rockchip_saradc: Add RK3562 support Sohaib Mohamed ` (6 subsequent siblings) 13 siblings, 1 reply; 23+ messages in thread From: Sohaib Mohamed @ 2026-01-30 5:16 UTC (permalink / raw) To: Sascha Hauer, BAREBOX; +Cc: Sohaib Mohamed Add basic power domain controller support for RK3562 SoC including GPU, NPU, VDPU, VEPU, RGA, VI, VO, and PHP domains with clock gating configurations. Note: This implementation does not handle nested power domain hierarchies if present on this SoC. Signed-off-by: Sohaib Mohamed <sohaib.amhmd@gmail.com> --- drivers/pmdomain/rockchip/pm-domains.c | 47 ++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rockchip/pm-domains.c index a30ff8fb22..4916515f27 100644 --- a/drivers/pmdomain/rockchip/pm-domains.c +++ b/drivers/pmdomain/rockchip/pm-domains.c @@ -32,6 +32,7 @@ #include <dt-bindings/power/rk3399-power.h> #include <dt-bindings/power/rk3568-power.h> #include <dt-bindings/power/rockchip,rk3576-power.h> +#include <dt-bindings/power/rockchip,rk3562-power.h> #include <dt-bindings/power/rk3588-power.h> #define readx_poll_timeout_atomic(op, addr, val, cond, poll_time, timeout_us) \ @@ -133,6 +134,21 @@ struct rockchip_pmu { .active_wakeup = wakeup, \ } +#define DOMAIN_M_G_SD(_name, pwr, status, req, idle, ack, g_mask, mem, wakeup, keepon) \ +{ \ + .name = _name, \ + .pwr_w_mask = (pwr) << 16, \ + .pwr_mask = (pwr), \ + .status_mask = (status), \ + .req_w_mask = (req) << 16, \ + .req_mask = (req), \ + .idle_mask = (idle), \ + .ack_mask = (ack), \ + .clk_ungate_mask = (g_mask), \ + .active_wakeup = wakeup, \ +} + + #define DOMAIN_M_O_R(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, wakeup, regulator) \ { \ .name = _name, \ @@ -202,6 +218,9 @@ struct rockchip_pmu { #define DOMAIN_RK3568(name, pwr, req, wakeup) \ DOMAIN_M(name, pwr, pwr, req, req, req, wakeup) +#define DOMAIN_RK3562(name, pwr, req, g_mask, mem, wakeup) \ + DOMAIN_M_G_SD(name, pwr, pwr, req, req, req, g_mask, mem, wakeup, false) + #define DOMAIN_RK3576(name, p_offset, pwr, status, r_status, r_offset, req, idle, g_mask, wakeup) \ DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_status, r_offset, req, idle, idle, g_mask, wakeup) @@ -1099,6 +1118,18 @@ static const struct rockchip_domain_info rk3399_pm_domains[] = { [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true), }; +static const struct rockchip_domain_info rk3562_pm_domains[] = { + /* name pwr req g_mask mem wakeup */ + [RK3562_PD_GPU] = DOMAIN_RK3562("gpu", BIT(0), BIT(1), BIT(1), 0, false), + [RK3562_PD_NPU] = DOMAIN_RK3562("npu", BIT(1), BIT(2), BIT(2), 0, false), + [RK3562_PD_VDPU] = DOMAIN_RK3562("vdpu", BIT(2), BIT(6), BIT(6), 0, false), + [RK3562_PD_VEPU] = DOMAIN_RK3562("vepu", BIT(3), BIT(7), BIT(7) | BIT(3), 0, false), + [RK3562_PD_RGA] = DOMAIN_RK3562("rga", BIT(4), BIT(5), BIT(5) | BIT(4), 0, false), + [RK3562_PD_VI] = DOMAIN_RK3562("vi", BIT(5), BIT(3), BIT(3), 0, false), + [RK3562_PD_VO] = DOMAIN_RK3562("vo", BIT(6), BIT(4), BIT(4), 16, false), + [RK3562_PD_PHP] = DOMAIN_RK3562("php", BIT(7), BIT(8), BIT(8), 0, false), +}; + static const struct rockchip_domain_info rk3568_pm_domains[] = { [RK3568_PD_NPU] = DOMAIN_RK3568("npu", BIT(1), BIT(2), false), [RK3568_PD_GPU] = DOMAIN_RK3568("gpu", BIT(0), BIT(1), false), @@ -1300,6 +1331,18 @@ static const struct rockchip_pmu_info rk3399_pmu = { .domain_info = rk3399_pm_domains, }; +static const struct rockchip_pmu_info rk3562_pmu = { + .pwr_offset = 0x210, + .status_offset = 0x230, + .req_offset = 0x110, + .idle_offset = 0x128, + .ack_offset = 0x120, + .clk_ungate_offset = 0x140, + + .num_domains = ARRAY_SIZE(rk3562_pm_domains), + .domain_info = rk3562_pm_domains, +}; + static const struct rockchip_pmu_info rk3568_pmu = { .pwr_offset = 0xa0, .status_offset = 0x98, @@ -1390,6 +1433,10 @@ static const struct of_device_id rockchip_pm_domain_dt_match[] = { .compatible = "rockchip,rk3366-power-controller", .data = (void *)&rk3366_pmu, }, + { + .compatible = "rockchip,rk3562-power-controller", + .data = (void *)&rk3562_pmu, + }, { .compatible = "rockchip,rk3368-power-controller", .data = (void *)&rk3368_pmu, -- 2.43.0 ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 07/14] pmdomain: rockchip: Add RK3562 power domain support 2026-01-30 5:16 ` [PATCH v2 07/14] pmdomain: rockchip: Add RK3562 power domain support Sohaib Mohamed @ 2026-01-30 8:00 ` Ahmad Fatoum 0 siblings, 0 replies; 23+ messages in thread From: Ahmad Fatoum @ 2026-01-30 8:00 UTC (permalink / raw) To: Sohaib Mohamed, Sascha Hauer, BAREBOX On 1/30/26 06:16, Sohaib Mohamed wrote: > Add basic power domain controller support for RK3562 SoC including > GPU, NPU, VDPU, VEPU, RGA, VI, VO, and PHP domains with clock gating > configurations. > > Note: This implementation does not handle nested power domain > hierarchies if present on this SoC. > > Signed-off-by: Sohaib Mohamed <sohaib.amhmd@gmail.com> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> > --- > drivers/pmdomain/rockchip/pm-domains.c | 47 ++++++++++++++++++++++++++++++++++ > 1 file changed, 47 insertions(+) > > diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rockchip/pm-domains.c > index a30ff8fb22..4916515f27 100644 > --- a/drivers/pmdomain/rockchip/pm-domains.c > +++ b/drivers/pmdomain/rockchip/pm-domains.c > @@ -32,6 +32,7 @@ > #include <dt-bindings/power/rk3399-power.h> > #include <dt-bindings/power/rk3568-power.h> > #include <dt-bindings/power/rockchip,rk3576-power.h> > +#include <dt-bindings/power/rockchip,rk3562-power.h> > #include <dt-bindings/power/rk3588-power.h> > > #define readx_poll_timeout_atomic(op, addr, val, cond, poll_time, timeout_us) \ > @@ -133,6 +134,21 @@ struct rockchip_pmu { > .active_wakeup = wakeup, \ > } > > +#define DOMAIN_M_G_SD(_name, pwr, status, req, idle, ack, g_mask, mem, wakeup, keepon) \ > +{ \ > + .name = _name, \ > + .pwr_w_mask = (pwr) << 16, \ > + .pwr_mask = (pwr), \ > + .status_mask = (status), \ > + .req_w_mask = (req) << 16, \ > + .req_mask = (req), \ > + .idle_mask = (idle), \ > + .ack_mask = (ack), \ > + .clk_ungate_mask = (g_mask), \ > + .active_wakeup = wakeup, \ > +} > + > + > #define DOMAIN_M_O_R(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, wakeup, regulator) \ > { \ > .name = _name, \ > @@ -202,6 +218,9 @@ struct rockchip_pmu { > #define DOMAIN_RK3568(name, pwr, req, wakeup) \ > DOMAIN_M(name, pwr, pwr, req, req, req, wakeup) > > +#define DOMAIN_RK3562(name, pwr, req, g_mask, mem, wakeup) \ > + DOMAIN_M_G_SD(name, pwr, pwr, req, req, req, g_mask, mem, wakeup, false) > + > #define DOMAIN_RK3576(name, p_offset, pwr, status, r_status, r_offset, req, idle, g_mask, wakeup) \ > DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_status, r_offset, req, idle, idle, g_mask, wakeup) > > @@ -1099,6 +1118,18 @@ static const struct rockchip_domain_info rk3399_pm_domains[] = { > [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true), > }; > > +static const struct rockchip_domain_info rk3562_pm_domains[] = { > + /* name pwr req g_mask mem wakeup */ > + [RK3562_PD_GPU] = DOMAIN_RK3562("gpu", BIT(0), BIT(1), BIT(1), 0, false), > + [RK3562_PD_NPU] = DOMAIN_RK3562("npu", BIT(1), BIT(2), BIT(2), 0, false), > + [RK3562_PD_VDPU] = DOMAIN_RK3562("vdpu", BIT(2), BIT(6), BIT(6), 0, false), > + [RK3562_PD_VEPU] = DOMAIN_RK3562("vepu", BIT(3), BIT(7), BIT(7) | BIT(3), 0, false), > + [RK3562_PD_RGA] = DOMAIN_RK3562("rga", BIT(4), BIT(5), BIT(5) | BIT(4), 0, false), > + [RK3562_PD_VI] = DOMAIN_RK3562("vi", BIT(5), BIT(3), BIT(3), 0, false), > + [RK3562_PD_VO] = DOMAIN_RK3562("vo", BIT(6), BIT(4), BIT(4), 16, false), > + [RK3562_PD_PHP] = DOMAIN_RK3562("php", BIT(7), BIT(8), BIT(8), 0, false), > +}; > + > static const struct rockchip_domain_info rk3568_pm_domains[] = { > [RK3568_PD_NPU] = DOMAIN_RK3568("npu", BIT(1), BIT(2), false), > [RK3568_PD_GPU] = DOMAIN_RK3568("gpu", BIT(0), BIT(1), false), > @@ -1300,6 +1331,18 @@ static const struct rockchip_pmu_info rk3399_pmu = { > .domain_info = rk3399_pm_domains, > }; > > +static const struct rockchip_pmu_info rk3562_pmu = { > + .pwr_offset = 0x210, > + .status_offset = 0x230, > + .req_offset = 0x110, > + .idle_offset = 0x128, > + .ack_offset = 0x120, > + .clk_ungate_offset = 0x140, > + > + .num_domains = ARRAY_SIZE(rk3562_pm_domains), > + .domain_info = rk3562_pm_domains, > +}; > + > static const struct rockchip_pmu_info rk3568_pmu = { > .pwr_offset = 0xa0, > .status_offset = 0x98, > @@ -1390,6 +1433,10 @@ static const struct of_device_id rockchip_pm_domain_dt_match[] = { > .compatible = "rockchip,rk3366-power-controller", > .data = (void *)&rk3366_pmu, > }, > + { > + .compatible = "rockchip,rk3562-power-controller", > + .data = (void *)&rk3562_pmu, > + }, > { > .compatible = "rockchip,rk3368-power-controller", > .data = (void *)&rk3368_pmu, > -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 08/14] aiodev: rockchip_saradc: Add RK3562 support 2026-01-30 5:16 [PATCH v2 00/14] ARM: rockchip: Add initial RK3562 SoC support Sohaib Mohamed ` (6 preceding siblings ...) 2026-01-30 5:16 ` [PATCH v2 07/14] pmdomain: rockchip: Add RK3562 power domain support Sohaib Mohamed @ 2026-01-30 5:17 ` Sohaib Mohamed 2026-01-30 8:01 ` Ahmad Fatoum 2026-01-30 5:17 ` [PATCH v2 09/14] phy: rockchip-inno-usb2: Add support for RK3562 PHY Sohaib Mohamed ` (5 subsequent siblings) 13 siblings, 1 reply; 23+ messages in thread From: Sohaib Mohamed @ 2026-01-30 5:17 UTC (permalink / raw) To: Sascha Hauer, BAREBOX; +Cc: Sohaib Mohamed The RK3562 has a SARADC v2 with 8 channels and 12 bit resolution. compile-tested Only. Signed-off-by: Sohaib Mohamed <sohaib.amhmd@gmail.com> --- drivers/aiodev/rockchip_saradc.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/aiodev/rockchip_saradc.c b/drivers/aiodev/rockchip_saradc.c index f1efab5233..d4cb1f4fbe 100644 --- a/drivers/aiodev/rockchip_saradc.c +++ b/drivers/aiodev/rockchip_saradc.c @@ -256,6 +256,12 @@ static int rockchip_saradc_probe(struct device *dev) return ret; } +static const struct rockchip_saradc_cfg rk3562_saradc_cfg = { + .num_bits = 12, + .num_channels = 8, + .read = rockchip_saradc_read_v2, +}; + static const struct rockchip_saradc_cfg rk3568_saradc_cfg = { .num_bits = 10, .num_channels = 8, @@ -276,6 +282,7 @@ static const struct rockchip_saradc_cfg rk3588_saradc_cfg = { }; static const struct of_device_id of_rockchip_saradc_match[] = { + { .compatible = "rockchip,rk3562-saradc", .data = &rk3562_saradc_cfg }, { .compatible = "rockchip,rk3568-saradc", .data = &rk3568_saradc_cfg }, { .compatible = "rockchip,rk3576-saradc", .data = &rk3576_saradc_cfg }, { .compatible = "rockchip,rk3588-saradc", .data = &rk3588_saradc_cfg }, -- 2.43.0 ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 08/14] aiodev: rockchip_saradc: Add RK3562 support 2026-01-30 5:17 ` [PATCH v2 08/14] aiodev: rockchip_saradc: Add RK3562 support Sohaib Mohamed @ 2026-01-30 8:01 ` Ahmad Fatoum 0 siblings, 0 replies; 23+ messages in thread From: Ahmad Fatoum @ 2026-01-30 8:01 UTC (permalink / raw) To: Sohaib Mohamed, Sascha Hauer, BAREBOX On 1/30/26 06:17, Sohaib Mohamed wrote: > The RK3562 has a SARADC v2 with 8 channels and 12 bit resolution. > compile-tested Only. > > Signed-off-by: Sohaib Mohamed <sohaib.amhmd@gmail.com> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> > --- > drivers/aiodev/rockchip_saradc.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/aiodev/rockchip_saradc.c b/drivers/aiodev/rockchip_saradc.c > index f1efab5233..d4cb1f4fbe 100644 > --- a/drivers/aiodev/rockchip_saradc.c > +++ b/drivers/aiodev/rockchip_saradc.c > @@ -256,6 +256,12 @@ static int rockchip_saradc_probe(struct device *dev) > return ret; > } > > +static const struct rockchip_saradc_cfg rk3562_saradc_cfg = { > + .num_bits = 12, > + .num_channels = 8, > + .read = rockchip_saradc_read_v2, > +}; > + > static const struct rockchip_saradc_cfg rk3568_saradc_cfg = { > .num_bits = 10, > .num_channels = 8, > @@ -276,6 +282,7 @@ static const struct rockchip_saradc_cfg rk3588_saradc_cfg = { > }; > > static const struct of_device_id of_rockchip_saradc_match[] = { > + { .compatible = "rockchip,rk3562-saradc", .data = &rk3562_saradc_cfg }, > { .compatible = "rockchip,rk3568-saradc", .data = &rk3568_saradc_cfg }, > { .compatible = "rockchip,rk3576-saradc", .data = &rk3576_saradc_cfg }, > { .compatible = "rockchip,rk3588-saradc", .data = &rk3588_saradc_cfg }, > -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 09/14] phy: rockchip-inno-usb2: Add support for RK3562 PHY 2026-01-30 5:16 [PATCH v2 00/14] ARM: rockchip: Add initial RK3562 SoC support Sohaib Mohamed ` (7 preceding siblings ...) 2026-01-30 5:17 ` [PATCH v2 08/14] aiodev: rockchip_saradc: Add RK3562 support Sohaib Mohamed @ 2026-01-30 5:17 ` Sohaib Mohamed 2026-01-30 8:01 ` Ahmad Fatoum 2026-01-30 5:17 ` [PATCH v2 10/14] rockchip-rng: Add RK3562 support Sohaib Mohamed ` (4 subsequent siblings) 13 siblings, 1 reply; 23+ messages in thread From: Sohaib Mohamed @ 2026-01-30 5:17 UTC (permalink / raw) To: Sascha Hauer, BAREBOX; +Cc: Sohaib Mohamed Add support for the RK3562 PHY variant. Signed-off-by: Sohaib Mohamed <sohaib.amhmd@gmail.com> --- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 52 ++++++++++++++++++++++++++- 1 file changed, 51 insertions(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index 9805537c34..6b57522090 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -394,7 +394,8 @@ static int rockchip_usb2phy_probe(struct device *dev) rphy->dev = dev; if (of_device_is_compatible(np, "rockchip,rv1108-usb2phy") || - of_device_is_compatible(np, "rockchip,rk3568-usb2phy")) + of_device_is_compatible(np, "rockchip,rk3568-usb2phy") || + of_device_is_compatible(np, "rockchip,rk3562-usb2phy")) rphy->grf_base = syscon_regmap_lookup_by_phandle(np, "rockchip,usbgrf"); else rphy->grf_base = syscon_node_to_regmap(dev->parent->of_node); @@ -857,6 +858,54 @@ static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = { { /* sentinel */ } }; +static const struct rockchip_usb2phy_cfg rk3562_phy_cfgs[] = { + { + .reg = 0xff740000, + .num_ports = 2, + .clkout_ctl = { 0x0108, 4, 4, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, + .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, + .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, + .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, + .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, + .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, + .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, + .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, + .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, + .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, + .ls_det_en = { 0x0110, 0, 0, 0, 1 }, + .ls_det_st = { 0x0114, 0, 0, 0, 1 }, + .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, + .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, + .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, + .utmi_ls = { 0x0120, 5, 4, 0, 1 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x0104, 8, 0, 0x1d2, 0x1d1 }, + .ls_det_en = { 0x0110, 1, 1, 0, 1 }, + .ls_det_st = { 0x0114, 1, 1, 0, 1 }, + .ls_det_clr = { 0x0118, 1, 1, 0, 1 }, + .utmi_ls = { 0x0120, 17, 16, 0, 1 }, + .utmi_hstdet = { 0x0120, 19, 19, 0, 1 } + } + }, + .chg_det = { + .cp_det = { 0x0120, 24, 24, 0, 1 }, + .dcp_det = { 0x0120, 23, 23, 0, 1 }, + .dp_det = { 0x0120, 25, 25, 0, 1 }, + .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, + .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, + .idp_src_en = { 0x0108, 9, 9, 0, 1 }, + .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, + .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, + .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, + }, + }, + { /* sentinel */ } +}; + static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = { { .reg = 0x100, @@ -1040,6 +1089,7 @@ static const struct of_device_id rockchip_usb2phy_dt_match[] = { { .compatible = "rockchip,rk322x-usb2phy", .data = &rk322x_phy_cfgs }, { .compatible = "rockchip,rk3308-usb2phy", .data = &rk3328_phy_cfgs }, { .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs }, + { .compatible = "rockchip,rk3562-usb2phy", .data = &rk3562_phy_cfgs }, { .compatible = "rockchip,rk3368-usb2phy", .data = &rk3368_phy_cfgs }, { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs }, { .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs }, -- 2.43.0 ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 09/14] phy: rockchip-inno-usb2: Add support for RK3562 PHY 2026-01-30 5:17 ` [PATCH v2 09/14] phy: rockchip-inno-usb2: Add support for RK3562 PHY Sohaib Mohamed @ 2026-01-30 8:01 ` Ahmad Fatoum 0 siblings, 0 replies; 23+ messages in thread From: Ahmad Fatoum @ 2026-01-30 8:01 UTC (permalink / raw) To: Sohaib Mohamed, Sascha Hauer, BAREBOX On 1/30/26 06:17, Sohaib Mohamed wrote: > Add support for the RK3562 PHY variant. > > Signed-off-by: Sohaib Mohamed <sohaib.amhmd@gmail.com> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> > --- > drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 52 ++++++++++++++++++++++++++- > 1 file changed, 51 insertions(+), 1 deletion(-) > > diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c > index 9805537c34..6b57522090 100644 > --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c > +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c > @@ -394,7 +394,8 @@ static int rockchip_usb2phy_probe(struct device *dev) > rphy->dev = dev; > > if (of_device_is_compatible(np, "rockchip,rv1108-usb2phy") || > - of_device_is_compatible(np, "rockchip,rk3568-usb2phy")) > + of_device_is_compatible(np, "rockchip,rk3568-usb2phy") || > + of_device_is_compatible(np, "rockchip,rk3562-usb2phy")) > rphy->grf_base = syscon_regmap_lookup_by_phandle(np, "rockchip,usbgrf"); > else > rphy->grf_base = syscon_node_to_regmap(dev->parent->of_node); > @@ -857,6 +858,54 @@ static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = { > { /* sentinel */ } > }; > > +static const struct rockchip_usb2phy_cfg rk3562_phy_cfgs[] = { > + { > + .reg = 0xff740000, > + .num_ports = 2, > + .clkout_ctl = { 0x0108, 4, 4, 1, 0 }, > + .port_cfgs = { > + [USB2PHY_PORT_OTG] = { > + .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, > + .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, > + .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, > + .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, > + .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, > + .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, > + .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, > + .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, > + .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, > + .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, > + .ls_det_en = { 0x0110, 0, 0, 0, 1 }, > + .ls_det_st = { 0x0114, 0, 0, 0, 1 }, > + .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, > + .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, > + .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, > + .utmi_ls = { 0x0120, 5, 4, 0, 1 }, > + }, > + [USB2PHY_PORT_HOST] = { > + .phy_sus = { 0x0104, 8, 0, 0x1d2, 0x1d1 }, > + .ls_det_en = { 0x0110, 1, 1, 0, 1 }, > + .ls_det_st = { 0x0114, 1, 1, 0, 1 }, > + .ls_det_clr = { 0x0118, 1, 1, 0, 1 }, > + .utmi_ls = { 0x0120, 17, 16, 0, 1 }, > + .utmi_hstdet = { 0x0120, 19, 19, 0, 1 } > + } > + }, > + .chg_det = { > + .cp_det = { 0x0120, 24, 24, 0, 1 }, > + .dcp_det = { 0x0120, 23, 23, 0, 1 }, > + .dp_det = { 0x0120, 25, 25, 0, 1 }, > + .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, > + .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, > + .idp_src_en = { 0x0108, 9, 9, 0, 1 }, > + .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, > + .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, > + .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, > + }, > + }, > + { /* sentinel */ } > +}; > + > static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = { > { > .reg = 0x100, > @@ -1040,6 +1089,7 @@ static const struct of_device_id rockchip_usb2phy_dt_match[] = { > { .compatible = "rockchip,rk322x-usb2phy", .data = &rk322x_phy_cfgs }, > { .compatible = "rockchip,rk3308-usb2phy", .data = &rk3328_phy_cfgs }, > { .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs }, > + { .compatible = "rockchip,rk3562-usb2phy", .data = &rk3562_phy_cfgs }, > { .compatible = "rockchip,rk3368-usb2phy", .data = &rk3368_phy_cfgs }, > { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs }, > { .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs }, > -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 10/14] rockchip-rng: Add RK3562 support 2026-01-30 5:16 [PATCH v2 00/14] ARM: rockchip: Add initial RK3562 SoC support Sohaib Mohamed ` (8 preceding siblings ...) 2026-01-30 5:17 ` [PATCH v2 09/14] phy: rockchip-inno-usb2: Add support for RK3562 PHY Sohaib Mohamed @ 2026-01-30 5:17 ` Sohaib Mohamed 2026-01-30 8:02 ` Ahmad Fatoum 2026-01-30 5:17 ` [PATCH v2 11/14] mci: sdhci: rockchip-dwcmshc: " Sohaib Mohamed ` (3 subsequent siblings) 13 siblings, 1 reply; 23+ messages in thread From: Sohaib Mohamed @ 2026-01-30 5:17 UTC (permalink / raw) To: Sascha Hauer, BAREBOX; +Cc: Sohaib Mohamed Add compatible string for RK3562 RNG support. Signed-off-by: Sohaib Mohamed <sohaib.amhmd@gmail.com> --- drivers/hw_random/rockchip-rng.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/hw_random/rockchip-rng.c b/drivers/hw_random/rockchip-rng.c index 8856a3883e..f1f4c4cb12 100644 --- a/drivers/hw_random/rockchip-rng.c +++ b/drivers/hw_random/rockchip-rng.c @@ -193,6 +193,10 @@ static const struct of_device_id rk_rng_dt_match[] = { .compatible = "rockchip,cryptov1-rng", .data = &rk_rng_v1_soc_data, }, + { + .compatible = "rockchip,rk3562-rng", + .data = &rk_rng_v2_soc_data, + }, { .compatible = "rockchip,rk3568-rng", .data = &rk_rng_v2_soc_data, -- 2.43.0 ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 10/14] rockchip-rng: Add RK3562 support 2026-01-30 5:17 ` [PATCH v2 10/14] rockchip-rng: Add RK3562 support Sohaib Mohamed @ 2026-01-30 8:02 ` Ahmad Fatoum 0 siblings, 0 replies; 23+ messages in thread From: Ahmad Fatoum @ 2026-01-30 8:02 UTC (permalink / raw) To: Sohaib Mohamed, Sascha Hauer, BAREBOX On 1/30/26 06:17, Sohaib Mohamed wrote: > Add compatible string for RK3562 RNG support. Nitpick: I'd have rather suggested hw_random as prefix, but I don't think you need to resend just for that. > > Signed-off-by: Sohaib Mohamed <sohaib.amhmd@gmail.com> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> > --- > drivers/hw_random/rockchip-rng.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/hw_random/rockchip-rng.c b/drivers/hw_random/rockchip-rng.c > index 8856a3883e..f1f4c4cb12 100644 > --- a/drivers/hw_random/rockchip-rng.c > +++ b/drivers/hw_random/rockchip-rng.c > @@ -193,6 +193,10 @@ static const struct of_device_id rk_rng_dt_match[] = { > .compatible = "rockchip,cryptov1-rng", > .data = &rk_rng_v1_soc_data, > }, > + { > + .compatible = "rockchip,rk3562-rng", > + .data = &rk_rng_v2_soc_data, > + }, > { > .compatible = "rockchip,rk3568-rng", > .data = &rk_rng_v2_soc_data, > -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 11/14] mci: sdhci: rockchip-dwcmshc: Add RK3562 support 2026-01-30 5:16 [PATCH v2 00/14] ARM: rockchip: Add initial RK3562 SoC support Sohaib Mohamed ` (9 preceding siblings ...) 2026-01-30 5:17 ` [PATCH v2 10/14] rockchip-rng: Add RK3562 support Sohaib Mohamed @ 2026-01-30 5:17 ` Sohaib Mohamed 2026-01-30 8:03 ` Ahmad Fatoum 2026-01-30 5:17 ` [PATCH v2 12/14] nvmem: rockchip-otp: " Sohaib Mohamed ` (2 subsequent siblings) 13 siblings, 1 reply; 23+ messages in thread From: Sohaib Mohamed @ 2026-01-30 5:17 UTC (permalink / raw) To: Sascha Hauer, BAREBOX; +Cc: Sohaib Mohamed Add compatible string for RK3562 DWCMSHC SDHCI controller. Signed-off-by: Sohaib Mohamed <sohaib.amhmd@gmail.com> --- drivers/mci/rockchip-dwcmshc-sdhci.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mci/rockchip-dwcmshc-sdhci.c b/drivers/mci/rockchip-dwcmshc-sdhci.c index c4c03f703a..0bc6824c80 100644 --- a/drivers/mci/rockchip-dwcmshc-sdhci.c +++ b/drivers/mci/rockchip-dwcmshc-sdhci.c @@ -352,6 +352,9 @@ static int rk_sdhci_probe(struct device *dev) } static __maybe_unused struct of_device_id rk_sdhci_compatible[] = { + { + .compatible = "rockchip,rk3562-dwcmshc" + }, { .compatible = "rockchip,rk3568-dwcmshc" }, { -- 2.43.0 ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 11/14] mci: sdhci: rockchip-dwcmshc: Add RK3562 support 2026-01-30 5:17 ` [PATCH v2 11/14] mci: sdhci: rockchip-dwcmshc: " Sohaib Mohamed @ 2026-01-30 8:03 ` Ahmad Fatoum 0 siblings, 0 replies; 23+ messages in thread From: Ahmad Fatoum @ 2026-01-30 8:03 UTC (permalink / raw) To: Sohaib Mohamed, Sascha Hauer, BAREBOX On 1/30/26 06:17, Sohaib Mohamed wrote: > Add compatible string for RK3562 DWCMSHC SDHCI controller. > > Signed-off-by: Sohaib Mohamed <sohaib.amhmd@gmail.com> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> > --- > drivers/mci/rockchip-dwcmshc-sdhci.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/mci/rockchip-dwcmshc-sdhci.c b/drivers/mci/rockchip-dwcmshc-sdhci.c > index c4c03f703a..0bc6824c80 100644 > --- a/drivers/mci/rockchip-dwcmshc-sdhci.c > +++ b/drivers/mci/rockchip-dwcmshc-sdhci.c > @@ -352,6 +352,9 @@ static int rk_sdhci_probe(struct device *dev) > } > > static __maybe_unused struct of_device_id rk_sdhci_compatible[] = { > + { > + .compatible = "rockchip,rk3562-dwcmshc" > + }, > { > .compatible = "rockchip,rk3568-dwcmshc" > }, { > -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 12/14] nvmem: rockchip-otp: Add RK3562 support 2026-01-30 5:16 [PATCH v2 00/14] ARM: rockchip: Add initial RK3562 SoC support Sohaib Mohamed ` (10 preceding siblings ...) 2026-01-30 5:17 ` [PATCH v2 11/14] mci: sdhci: rockchip-dwcmshc: " Sohaib Mohamed @ 2026-01-30 5:17 ` Sohaib Mohamed 2026-01-30 8:03 ` Ahmad Fatoum 2026-01-30 5:17 ` [PATCH v2 13/14] phy: rockchip: inno-dsidphy: " Sohaib Mohamed 2026-01-30 5:17 ` [PATCH v2 14/14] phy: rockchip: naneng-combphy: " Sohaib Mohamed 13 siblings, 1 reply; 23+ messages in thread From: Sohaib Mohamed @ 2026-01-30 5:17 UTC (permalink / raw) To: Sascha Hauer, BAREBOX; +Cc: Sohaib Mohamed Add RK3562 OTP support using rk3562-specific data configuration. Signed-off-by: Sohaib Mohamed <sohaib.amhmd@gmail.com> --- drivers/nvmem/rockchip-otp.c | 89 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/drivers/nvmem/rockchip-otp.c b/drivers/nvmem/rockchip-otp.c index 33b242c5bc..d2145bba52 100644 --- a/drivers/nvmem/rockchip-otp.c +++ b/drivers/nvmem/rockchip-otp.c @@ -51,6 +51,21 @@ #define OTPC_TIMEOUT 10000 +#define RK3562_NBYTES 2 + +/* RK3588 Register */ +#define RK3582_OTPC_AUTO_CTRL 0x04 +#define RK3582_OTPC_AUTO_EN 0x08 +#define RK3582_OTPC_INT_ST 0x84 +#define RK3582_OTPC_DOUT0 0x20 +#define RK3582_NO_SECURE_OFFSET 0x300 +#define RK3582_NBYTES 4 +#define RK3582_BURST_NUM 1 +#define RK3582_BURST_SHIFT 8 +#define RK3582_ADDR_SHIFT 16 +#define RK3582_AUTO_EN BIT(0) +#define RK3582_RD_DONE BIT(1) + #define RK3568_NBYTES 2 /* RK3588 Register */ @@ -183,6 +198,65 @@ static int px30_otp_read(void *context, unsigned int offset, return ret; } +static int rk3562_otp_read(void *context, unsigned int offset, void *val, + size_t bytes) +{ + struct rockchip_otp *otp = context; + unsigned int addr_start, addr_end, addr_offset, addr_len; + u32 out_value; + u8 *buf; + int ret = 0, i = 0; + + addr_start = rounddown(offset, RK3562_NBYTES) / RK3562_NBYTES; + addr_end = roundup(offset + bytes, RK3562_NBYTES) / RK3562_NBYTES; + addr_offset = offset % RK3562_NBYTES; + addr_len = addr_end - addr_start; + + buf = kzalloc(array3_size(addr_len, RK3562_NBYTES, sizeof(*buf)), + GFP_KERNEL); + if (!buf) + return -ENOMEM; + + ret = rockchip_otp_reset(otp); + if (ret) { + dev_err(otp->dev, "failed to reset otp phy\n"); + goto out; + } + + ret = rockchip_otp_ecc_enable(otp, false); + if (ret < 0) { + dev_err(otp->dev, "rockchip_otp_ecc_enable err\n"); + goto out; + } + + writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL); + udelay(5); + while (addr_len--) { + writel(addr_start++ | OTPC_USER_ADDR_MASK, + otp->base + OTPC_USER_ADDR); + writel(OTPC_USER_FSM_ENABLE | OTPC_USER_FSM_ENABLE_MASK, + otp->base + OTPC_USER_ENABLE); + ret = rockchip_otp_wait_status(otp, OTPC_INT_STATUS, OTPC_USER_DONE); + if (ret < 0) { + dev_err(otp->dev, "timeout during read setup\n"); + goto read_end; + } + out_value = readl(otp->base + OTPC_USER_Q); + memcpy(&buf[i], &out_value, RK3562_NBYTES); + i += RK3562_NBYTES; + } + + memcpy(val, buf + addr_offset, bytes); + +read_end: + writel(0x0 | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL); +out: + kfree(buf); + + return ret; +} + + static int rk3568_otp_read(void *context, unsigned int offset, void *val, size_t bytes) { @@ -328,6 +402,17 @@ static const struct rockchip_data px30_data = { .reg_read = px30_otp_read, }; +static const char * const rk3562_otp_clocks[] = { + "usr", "sbpi", "apb", "phy", +}; + +static const struct rockchip_data rk3562_data = { + .size = 0x80, + .clks = rk3562_otp_clocks, + .num_clks = ARRAY_SIZE(rk3562_otp_clocks), + .reg_read = rk3562_otp_read, +}; + static const char * const rk3568_otp_clocks[] = { "usr", "sbpi", "apb", "phy", }; @@ -366,6 +451,10 @@ static __maybe_unused const struct of_device_id rockchip_otp_match[] = { .compatible = "rockchip,rk3308-otp", .data = &px30_data, }, + { + .compatible = "rockchip,rk3562-otp", + .data = &rk3562_data, + }, { .compatible = "rockchip,rk3568-otp", .data = &rk3568_data, -- 2.43.0 ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 12/14] nvmem: rockchip-otp: Add RK3562 support 2026-01-30 5:17 ` [PATCH v2 12/14] nvmem: rockchip-otp: " Sohaib Mohamed @ 2026-01-30 8:03 ` Ahmad Fatoum 0 siblings, 0 replies; 23+ messages in thread From: Ahmad Fatoum @ 2026-01-30 8:03 UTC (permalink / raw) To: Sohaib Mohamed, Sascha Hauer, BAREBOX On 1/30/26 06:17, Sohaib Mohamed wrote: > Add RK3562 OTP support using rk3562-specific data configuration. > > Signed-off-by: Sohaib Mohamed <sohaib.amhmd@gmail.com> Acked-by: Ahmad Fatoum <a.fatoum@pengutronix.de> > --- > drivers/nvmem/rockchip-otp.c | 89 ++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 89 insertions(+) > > diff --git a/drivers/nvmem/rockchip-otp.c b/drivers/nvmem/rockchip-otp.c > index 33b242c5bc..d2145bba52 100644 > --- a/drivers/nvmem/rockchip-otp.c > +++ b/drivers/nvmem/rockchip-otp.c > @@ -51,6 +51,21 @@ > > #define OTPC_TIMEOUT 10000 > > +#define RK3562_NBYTES 2 > + > +/* RK3588 Register */ > +#define RK3582_OTPC_AUTO_CTRL 0x04 > +#define RK3582_OTPC_AUTO_EN 0x08 > +#define RK3582_OTPC_INT_ST 0x84 > +#define RK3582_OTPC_DOUT0 0x20 > +#define RK3582_NO_SECURE_OFFSET 0x300 > +#define RK3582_NBYTES 4 > +#define RK3582_BURST_NUM 1 > +#define RK3582_BURST_SHIFT 8 > +#define RK3582_ADDR_SHIFT 16 > +#define RK3582_AUTO_EN BIT(0) > +#define RK3582_RD_DONE BIT(1) > + > #define RK3568_NBYTES 2 > > /* RK3588 Register */ > @@ -183,6 +198,65 @@ static int px30_otp_read(void *context, unsigned int offset, > return ret; > } > > +static int rk3562_otp_read(void *context, unsigned int offset, void *val, > + size_t bytes) > +{ > + struct rockchip_otp *otp = context; > + unsigned int addr_start, addr_end, addr_offset, addr_len; > + u32 out_value; > + u8 *buf; > + int ret = 0, i = 0; > + > + addr_start = rounddown(offset, RK3562_NBYTES) / RK3562_NBYTES; > + addr_end = roundup(offset + bytes, RK3562_NBYTES) / RK3562_NBYTES; > + addr_offset = offset % RK3562_NBYTES; > + addr_len = addr_end - addr_start; > + > + buf = kzalloc(array3_size(addr_len, RK3562_NBYTES, sizeof(*buf)), > + GFP_KERNEL); > + if (!buf) > + return -ENOMEM; > + > + ret = rockchip_otp_reset(otp); > + if (ret) { > + dev_err(otp->dev, "failed to reset otp phy\n"); > + goto out; > + } > + > + ret = rockchip_otp_ecc_enable(otp, false); > + if (ret < 0) { > + dev_err(otp->dev, "rockchip_otp_ecc_enable err\n"); > + goto out; > + } > + > + writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL); > + udelay(5); > + while (addr_len--) { > + writel(addr_start++ | OTPC_USER_ADDR_MASK, > + otp->base + OTPC_USER_ADDR); > + writel(OTPC_USER_FSM_ENABLE | OTPC_USER_FSM_ENABLE_MASK, > + otp->base + OTPC_USER_ENABLE); > + ret = rockchip_otp_wait_status(otp, OTPC_INT_STATUS, OTPC_USER_DONE); > + if (ret < 0) { > + dev_err(otp->dev, "timeout during read setup\n"); > + goto read_end; > + } > + out_value = readl(otp->base + OTPC_USER_Q); > + memcpy(&buf[i], &out_value, RK3562_NBYTES); > + i += RK3562_NBYTES; > + } > + > + memcpy(val, buf + addr_offset, bytes); > + > +read_end: > + writel(0x0 | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL); > +out: > + kfree(buf); > + > + return ret; > +} > + > + > static int rk3568_otp_read(void *context, unsigned int offset, void *val, > size_t bytes) > { > @@ -328,6 +402,17 @@ static const struct rockchip_data px30_data = { > .reg_read = px30_otp_read, > }; > > +static const char * const rk3562_otp_clocks[] = { > + "usr", "sbpi", "apb", "phy", > +}; > + > +static const struct rockchip_data rk3562_data = { > + .size = 0x80, > + .clks = rk3562_otp_clocks, > + .num_clks = ARRAY_SIZE(rk3562_otp_clocks), > + .reg_read = rk3562_otp_read, > +}; > + > static const char * const rk3568_otp_clocks[] = { > "usr", "sbpi", "apb", "phy", > }; > @@ -366,6 +451,10 @@ static __maybe_unused const struct of_device_id rockchip_otp_match[] = { > .compatible = "rockchip,rk3308-otp", > .data = &px30_data, > }, > + { > + .compatible = "rockchip,rk3562-otp", > + .data = &rk3562_data, > + }, > { > .compatible = "rockchip,rk3568-otp", > .data = &rk3568_data, > -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 13/14] phy: rockchip: inno-dsidphy: Add RK3562 support 2026-01-30 5:16 [PATCH v2 00/14] ARM: rockchip: Add initial RK3562 SoC support Sohaib Mohamed ` (11 preceding siblings ...) 2026-01-30 5:17 ` [PATCH v2 12/14] nvmem: rockchip-otp: " Sohaib Mohamed @ 2026-01-30 5:17 ` Sohaib Mohamed 2026-01-30 8:04 ` Ahmad Fatoum 2026-01-30 5:17 ` [PATCH v2 14/14] phy: rockchip: naneng-combphy: " Sohaib Mohamed 13 siblings, 1 reply; 23+ messages in thread From: Sohaib Mohamed @ 2026-01-30 5:17 UTC (permalink / raw) To: Sascha Hauer, BAREBOX; +Cc: Sohaib Mohamed Add RK3562 DSI D-PHY support with max 2.5GHz data rate configuration. Signed-off-by: Sohaib Mohamed <sohaib.amhmd@gmail.com> --- drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c index 5a929dc972..161c9d7c0d 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c @@ -741,6 +741,9 @@ static const struct of_device_id inno_dsidphy_of_match[] = { }, { .compatible = "rockchip,rk3368-dsi-dphy", .data = &max_1ghz_video_phy_plat_data, + }, { + .compatible = "rockchip,rk3562-dsi-dphy", + .data = &max_2_5ghz_video_phy_plat_data, }, { .compatible = "rockchip,rk3568-dsi-dphy", .data = &max_2_5ghz_video_phy_plat_data, -- 2.43.0 ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 13/14] phy: rockchip: inno-dsidphy: Add RK3562 support 2026-01-30 5:17 ` [PATCH v2 13/14] phy: rockchip: inno-dsidphy: " Sohaib Mohamed @ 2026-01-30 8:04 ` Ahmad Fatoum 0 siblings, 0 replies; 23+ messages in thread From: Ahmad Fatoum @ 2026-01-30 8:04 UTC (permalink / raw) To: Sohaib Mohamed, Sascha Hauer, BAREBOX On 1/30/26 06:17, Sohaib Mohamed wrote: > Add RK3562 DSI D-PHY support with max 2.5GHz data rate configuration. > > Signed-off-by: Sohaib Mohamed <sohaib.amhmd@gmail.com> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> > --- > drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c > index 5a929dc972..161c9d7c0d 100644 > --- a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c > +++ b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c > @@ -741,6 +741,9 @@ static const struct of_device_id inno_dsidphy_of_match[] = { > }, { > .compatible = "rockchip,rk3368-dsi-dphy", > .data = &max_1ghz_video_phy_plat_data, > + }, { > + .compatible = "rockchip,rk3562-dsi-dphy", > + .data = &max_2_5ghz_video_phy_plat_data, > }, { > .compatible = "rockchip,rk3568-dsi-dphy", > .data = &max_2_5ghz_video_phy_plat_data, > -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 14/14] phy: rockchip: naneng-combphy: Add RK3562 support 2026-01-30 5:16 [PATCH v2 00/14] ARM: rockchip: Add initial RK3562 SoC support Sohaib Mohamed ` (12 preceding siblings ...) 2026-01-30 5:17 ` [PATCH v2 13/14] phy: rockchip: inno-dsidphy: " Sohaib Mohamed @ 2026-01-30 5:17 ` Sohaib Mohamed 2026-01-30 8:05 ` Ahmad Fatoum 13 siblings, 1 reply; 23+ messages in thread From: Sohaib Mohamed @ 2026-01-30 5:17 UTC (permalink / raw) To: Sascha Hauer, BAREBOX; +Cc: Sohaib Mohamed Add RK3562 naneng combphy support for PCIe and USB3 modes with SSC, CTLE, PLL configuration, and support for 24MHz/25MHz/100MHz reference clocks. NOTE: this commit is compile-tested Only. I tested only USB 2.0. Signed-off-by: Sohaib Mohamed <sohaib.amhmd@gmail.com> --- drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 161 +++++++++++++++++++++ 1 file changed, 161 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 7951a109f5..4a2e5f11ee 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -402,6 +402,163 @@ static int rockchip_combphy_probe(struct device *dev) return PTR_ERR_OR_ZERO(phy_provider); } +static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv) +{ + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; + unsigned long rate; + u32 val; + + switch (priv->type) { + case PHY_TYPE_PCIE: + /* Set SSC downward spread spectrum */ + rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, + PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT, + PHYREG32); + + rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); + break; + case PHY_TYPE_USB3: + /* Set SSC downward spread spectrum */ + rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, + PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT, + PHYREG32); + + /* Enable adaptive CTLE for USB3.0 Rx */ + rockchip_combphy_updatel(priv, PHYREG15_CTLE_EN, + PHYREG15_CTLE_EN, PHYREG15); + + /* Set PLL KVCO fine tuning signals */ + rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, + BIT(3), PHYREG33); + + /* Set PLL LPF R1 to su_trim[10:7]=1001 */ + writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); + + /* Set PLL input clock divider 1/2 */ + val = FIELD_PREP(PHYREG6_PLL_DIV_MASK, PHYREG6_PLL_DIV_2); + rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, val, PHYREG6); + + /* Set PLL loop divider */ + writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); + + /* Set PLL KVCO to min and set PLL charge pump current to max */ + writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); + + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); + rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); + break; + default: + dev_err(priv->dev, "incompatible PHY type\n"); + return -EINVAL; + } + + rate = clk_get_rate(priv->refclk); + + switch (rate) { + case REF_CLOCK_24MHz: + if (priv->type == PHY_TYPE_USB3) { + /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */ + val = FIELD_PREP(PHYREG15_SSC_CNT_MASK, + PHYREG15_SSC_CNT_VALUE); + rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK, + val, PHYREG15); + + writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); + } + break; + case REF_CLOCK_25MHz: + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); + break; + case REF_CLOCK_100MHz: + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); + if (priv->type == PHY_TYPE_PCIE) { + /* Gate_tx_pck_sel length select for L1ss support */ + rockchip_combphy_updatel(priv, PHYREG13_CKRCV_AMP0, + PHYREG13_CKRCV_AMP0, + PHYREG30); + /* PLL KVCO tuning fine */ + val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, + PHYREG33_PLL_KVCO_VALUE); + rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, + val, PHYREG33); + + /* Enable controlling random jitter, aka RMJ */ + writel(0x4, priv->mmio + PHYREG12); + + val = PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT; + rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, + val, PHYREG6); + + writel(0x32, priv->mmio + PHYREG18); + writel(0xf0, priv->mmio + PHYREG11); + } + break; + default: + dev_err(priv->dev, "Unsupported rate: %lu\n", rate); + return -EINVAL; + } + + if (priv->ext_refclk) { + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); + if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { + val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT; + val |= PHYREG13_CKRCV_AMP0; + rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, + PHYREG13); + + val = readl(priv->mmio + PHYREG14); + val |= PHYREG14_CKRCV_AMP1; + writel(val, priv->mmio + PHYREG14); + } + } + + if (priv->enable_ssc) { + val = readl(priv->mmio + PHYREG8); + val |= PHYREG8_SSC_EN; + writel(val, priv->mmio + PHYREG8); + } + + return 0; +} + +static const struct rockchip_combphy_grfcfg rk3562_combphy_grfcfgs = { + /* pipe-phy-grf */ + .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, + .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, + .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, + .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, + .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, + .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, + .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, + .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, + .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, + .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, + .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, + .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, + .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, + .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, + .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, + .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, + .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, + .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, + .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, +}; + +static const struct rockchip_combphy_cfg rk3562_combphy_cfgs = { + .num_phys = 2, + .phy_ids = { + 0xff750000 + }, + .grfcfg = &rk3562_combphy_grfcfgs, + .combphy_cfg = rk3562_combphy_cfg, +}; + + static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) { const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; @@ -1055,6 +1212,10 @@ static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = { }; static const struct of_device_id rockchip_combphy_of_match[] = { + { + .compatible = "rockchip,rk3562-naneng-combphy", + .data = &rk3562_combphy_cfgs, + }, { .compatible = "rockchip,rk3568-naneng-combphy", .data = &rk3568_combphy_cfgs, -- 2.43.0 ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 14/14] phy: rockchip: naneng-combphy: Add RK3562 support 2026-01-30 5:17 ` [PATCH v2 14/14] phy: rockchip: naneng-combphy: " Sohaib Mohamed @ 2026-01-30 8:05 ` Ahmad Fatoum 0 siblings, 0 replies; 23+ messages in thread From: Ahmad Fatoum @ 2026-01-30 8:05 UTC (permalink / raw) To: Sohaib Mohamed, Sascha Hauer, BAREBOX On 1/30/26 06:17, Sohaib Mohamed wrote: > Add RK3562 naneng combphy support for PCIe and USB3 modes with SSC, > CTLE, PLL configuration, and support for 24MHz/25MHz/100MHz reference > clocks. > NOTE: this commit is compile-tested Only. I tested only USB 2.0. > > Signed-off-by: Sohaib Mohamed <sohaib.amhmd@gmail.com> Acked-by: Ahmad Fatoum <a.fatoum@pengutronix.de> > --- > drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 161 +++++++++++++++++++++ > 1 file changed, 161 insertions(+) > > diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c > index 7951a109f5..4a2e5f11ee 100644 > --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c > +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c > @@ -402,6 +402,163 @@ static int rockchip_combphy_probe(struct device *dev) > return PTR_ERR_OR_ZERO(phy_provider); > } > > +static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv) > +{ > + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; > + unsigned long rate; > + u32 val; > + > + switch (priv->type) { > + case PHY_TYPE_PCIE: > + /* Set SSC downward spread spectrum */ > + rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, > + PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT, > + PHYREG32); > + > + rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); > + rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); > + rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); > + rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); > + break; > + case PHY_TYPE_USB3: > + /* Set SSC downward spread spectrum */ > + rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, > + PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT, > + PHYREG32); > + > + /* Enable adaptive CTLE for USB3.0 Rx */ > + rockchip_combphy_updatel(priv, PHYREG15_CTLE_EN, > + PHYREG15_CTLE_EN, PHYREG15); > + > + /* Set PLL KVCO fine tuning signals */ > + rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, > + BIT(3), PHYREG33); > + > + /* Set PLL LPF R1 to su_trim[10:7]=1001 */ > + writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); > + > + /* Set PLL input clock divider 1/2 */ > + val = FIELD_PREP(PHYREG6_PLL_DIV_MASK, PHYREG6_PLL_DIV_2); > + rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, val, PHYREG6); > + > + /* Set PLL loop divider */ > + writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); > + > + /* Set PLL KVCO to min and set PLL charge pump current to max */ > + writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); > + > + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); > + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); > + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); > + rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); > + break; > + default: > + dev_err(priv->dev, "incompatible PHY type\n"); > + return -EINVAL; > + } > + > + rate = clk_get_rate(priv->refclk); > + > + switch (rate) { > + case REF_CLOCK_24MHz: > + if (priv->type == PHY_TYPE_USB3) { > + /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */ > + val = FIELD_PREP(PHYREG15_SSC_CNT_MASK, > + PHYREG15_SSC_CNT_VALUE); > + rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK, > + val, PHYREG15); > + > + writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); > + } > + break; > + case REF_CLOCK_25MHz: > + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); > + break; > + case REF_CLOCK_100MHz: > + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); > + if (priv->type == PHY_TYPE_PCIE) { > + /* Gate_tx_pck_sel length select for L1ss support */ > + rockchip_combphy_updatel(priv, PHYREG13_CKRCV_AMP0, > + PHYREG13_CKRCV_AMP0, > + PHYREG30); > + /* PLL KVCO tuning fine */ > + val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, > + PHYREG33_PLL_KVCO_VALUE); > + rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, > + val, PHYREG33); > + > + /* Enable controlling random jitter, aka RMJ */ > + writel(0x4, priv->mmio + PHYREG12); > + > + val = PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT; > + rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, > + val, PHYREG6); > + > + writel(0x32, priv->mmio + PHYREG18); > + writel(0xf0, priv->mmio + PHYREG11); > + } > + break; > + default: > + dev_err(priv->dev, "Unsupported rate: %lu\n", rate); > + return -EINVAL; > + } > + > + if (priv->ext_refclk) { > + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); > + if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { > + val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT; > + val |= PHYREG13_CKRCV_AMP0; > + rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, > + PHYREG13); > + > + val = readl(priv->mmio + PHYREG14); > + val |= PHYREG14_CKRCV_AMP1; > + writel(val, priv->mmio + PHYREG14); > + } > + } > + > + if (priv->enable_ssc) { > + val = readl(priv->mmio + PHYREG8); > + val |= PHYREG8_SSC_EN; > + writel(val, priv->mmio + PHYREG8); > + } > + > + return 0; > +} > + > +static const struct rockchip_combphy_grfcfg rk3562_combphy_grfcfgs = { > + /* pipe-phy-grf */ > + .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, > + .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, > + .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, > + .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, > + .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, > + .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, > + .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, > + .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, > + .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, > + .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, > + .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, > + .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, > + .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, > + .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, > + .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, > + .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, > + .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, > + .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, > + .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, > +}; > + > +static const struct rockchip_combphy_cfg rk3562_combphy_cfgs = { > + .num_phys = 2, > + .phy_ids = { > + 0xff750000 > + }, > + .grfcfg = &rk3562_combphy_grfcfgs, > + .combphy_cfg = rk3562_combphy_cfg, > +}; > + > + > static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) > { > const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; > @@ -1055,6 +1212,10 @@ static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = { > }; > > static const struct of_device_id rockchip_combphy_of_match[] = { > + { > + .compatible = "rockchip,rk3562-naneng-combphy", > + .data = &rk3562_combphy_cfgs, > + }, > { > .compatible = "rockchip,rk3568-naneng-combphy", > .data = &rk3568_combphy_cfgs, > -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2026-01-30 8:05 UTC | newest] Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2026-01-30 5:16 [PATCH v2 00/14] ARM: rockchip: Add initial RK3562 SoC support Sohaib Mohamed 2026-01-30 5:16 ` [PATCH v2 01/14] " Sohaib Mohamed 2026-01-30 5:16 ` [PATCH v2 02/14] clk: rockchip: add RK3562 clock and reset driver support Sohaib Mohamed 2026-01-30 5:16 ` [PATCH v2 03/14] pinctrl: rockchip: sync driver with Linux Sohaib Mohamed 2026-01-30 5:16 ` [PATCH v2 04/14] ARM: boards: Rockchip: add RK3562-EVB2 support Sohaib Mohamed 2026-01-30 5:16 ` [PATCH v2 05/14] ARM: boards: Rockchip: Add device tree for kickpi k3 board Sohaib Mohamed 2026-01-30 5:16 ` [PATCH v2 06/14] ARM: rockchip: Add RK3562 KickPi K3 board support Sohaib Mohamed 2026-01-30 5:16 ` [PATCH v2 07/14] pmdomain: rockchip: Add RK3562 power domain support Sohaib Mohamed 2026-01-30 8:00 ` Ahmad Fatoum 2026-01-30 5:17 ` [PATCH v2 08/14] aiodev: rockchip_saradc: Add RK3562 support Sohaib Mohamed 2026-01-30 8:01 ` Ahmad Fatoum 2026-01-30 5:17 ` [PATCH v2 09/14] phy: rockchip-inno-usb2: Add support for RK3562 PHY Sohaib Mohamed 2026-01-30 8:01 ` Ahmad Fatoum 2026-01-30 5:17 ` [PATCH v2 10/14] rockchip-rng: Add RK3562 support Sohaib Mohamed 2026-01-30 8:02 ` Ahmad Fatoum 2026-01-30 5:17 ` [PATCH v2 11/14] mci: sdhci: rockchip-dwcmshc: " Sohaib Mohamed 2026-01-30 8:03 ` Ahmad Fatoum 2026-01-30 5:17 ` [PATCH v2 12/14] nvmem: rockchip-otp: " Sohaib Mohamed 2026-01-30 8:03 ` Ahmad Fatoum 2026-01-30 5:17 ` [PATCH v2 13/14] phy: rockchip: inno-dsidphy: " Sohaib Mohamed 2026-01-30 8:04 ` Ahmad Fatoum 2026-01-30 5:17 ` [PATCH v2 14/14] phy: rockchip: naneng-combphy: " Sohaib Mohamed 2026-01-30 8:05 ` Ahmad Fatoum
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