* [PATCH 0/3] ARM: boards: add support for tqma8mpxs boards
@ 2026-02-13 8:19 Fabian Pflug
2026-02-13 8:19 ` [PATCH 1/3] dts: arm64: freescale: add imx8mp-tqma8mpqs board Fabian Pflug
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Fabian Pflug @ 2026-02-13 8:19 UTC (permalink / raw)
To: BAREBOX; +Cc: Fabian Pflug
Extending the TQMA8MPxL board code with support for TQMA8MPxS, as they
share the same processor and a lot of the same codebasis, but differ in
small changes.
Both now have support for the different RAM configurations, but no ECC
support yet.
Signed-off-by: Fabian Pflug <f.pflug@pengutronix.de>
---
Fabian Pflug (3):
dts: arm64: freescale: add imx8mp-tqma8mpqs board
ARM: boards: tqma8mpxl: extend with support for xs
ARM: boards: tqma8mpxx: add no_ecc ram timings
Documentation/migration-guides/migration-master.md | 10 +
arch/arm/boards/Makefile | 2 +-
arch/arm/boards/tqma8mpxl/lowlevel.c | 113 ---
arch/arm/boards/{tqma8mpxl => tqma8mpxx}/Makefile | 0
arch/arm/boards/{tqma8mpxl => tqma8mpxx}/board.c | 17 +-
.../flash-header-tqma8mpxx.imxcfg} | 0
arch/arm/boards/tqma8mpxx/lowlevel.c | 196 ++++
.../{tqma8mpxl => tqma8mpxx}/lpddr4-timing.c | 763 +++++++++++++-
arch/arm/configs/imx_v8_defconfig | 2 +-
arch/arm/configs/multi_v8_defconfig | 2 +-
arch/arm/dts/Makefile | 2 +-
arch/arm/dts/imx8mp-tqma8mpqs-mba8mpxs.dts | 15 +
arch/arm/mach-imx/Kconfig | 5 +-
.../freescale/imx8mp-tqma8mpqs-mb-smarc-2.dts | 388 +++++++
dts/src/arm64/freescale/imx8mp-tqma8mpqs.dtsi | 1066 ++++++++++++++++++++
images/Makefile.imx | 2 +-
16 files changed, 2442 insertions(+), 141 deletions(-)
---
base-commit: 0024921364eb4c8bc8089fdc198440b0d67a239f
change-id: 20260213-v2026-01-0-topic-tqma8mpxs-bf32a1a3ecb5
Best regards,
--
Fabian Pflug <f.pflug@pengutronix.de>
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/3] dts: arm64: freescale: add imx8mp-tqma8mpqs board
2026-02-13 8:19 [PATCH 0/3] ARM: boards: add support for tqma8mpxs boards Fabian Pflug
@ 2026-02-13 8:19 ` Fabian Pflug
2026-02-13 12:07 ` Ahmad Fatoum
2026-02-13 8:19 ` [PATCH 2/3] ARM: boards: tqma8mpxl: extend with support for xs Fabian Pflug
2026-02-13 8:19 ` [PATCH 3/3] ARM: boards: tqma8mpxx: add no_ecc ram timings Fabian Pflug
2 siblings, 1 reply; 5+ messages in thread
From: Fabian Pflug @ 2026-02-13 8:19 UTC (permalink / raw)
To: BAREBOX; +Cc: Fabian Pflug
The TQMA8MPxS is another board from TQMA with the same processor, but a
different formfactor. Nevertheless could they share a lot of code.
This should be replaced with the code from kernel upstream, but I have
yet to find the correct patch.
Signed-off-by: Fabian Pflug <f.pflug@pengutronix.de>
---
.../freescale/imx8mp-tqma8mpqs-mb-smarc-2.dts | 388 +++++++
dts/src/arm64/freescale/imx8mp-tqma8mpqs.dtsi | 1066 ++++++++++++++++++++
2 files changed, 1454 insertions(+)
diff --git a/dts/src/arm64/freescale/imx8mp-tqma8mpqs-mb-smarc-2.dts b/dts/src/arm64/freescale/imx8mp-tqma8mpqs-mb-smarc-2.dts
new file mode 100644
index 0000000000..08e46e325e
--- /dev/null
+++ b/dts/src/arm64/freescale/imx8mp-tqma8mpqs-mb-smarc-2.dts
@@ -0,0 +1,388 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Paul Gerber
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+#include "imx8mp-tqma8mpqs.dtsi"
+
+/ {
+ model = "TQ-Systems i.MX8MPlus TQMa8MPxS on MB-SMARC-2";
+ compatible = "tq,imx8mp-tqma8mpqs-mb-smarc-2", "tq,imx8mp-tqma8mpqs", "fsl,imx8mp";
+ chassis-type = "embedded";
+
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ aliases {
+ ethernet0 = &eqos;
+ ethernet1 = &fec;
+ mmc0 = &usdhc3;
+ mmc1 = &usdhc2;
+ rtc0 = &pcf85063;
+ rtc1 = &snvs_rtc;
+ spi0 = &flexspi;
+ spi1 = &ecspi1;
+ spi2 = &ecspi2;
+ spi3 = &ecspi3;
+ };
+
+ backlight_lvds0: backlight-lvds0 {
+ compatible = "pwm-backlight";
+ pwms = <&pwm3 0 100000 0>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ enable-gpios = <&expander0 0 GPIO_ACTIVE_HIGH>;
+ power-supply = <®_12v0>;
+ status = "disabled";
+ };
+
+ backlight_lvds1: backlight-lvds1 {
+ compatible = "pwm-backlight";
+ pwms = <&pwm2 0 100000 0>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ enable-gpios = <&expander0 2 GPIO_ACTIVE_HIGH>;
+ power-supply = <®_12v0>;
+ status = "disabled";
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ label = "X6";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_out>;
+ };
+ };
+ };
+
+ panel_lvds0: panel-lvds0 {
+ /*
+ * Display is not fixed, so compatible has to be added from
+ * DT overlay
+ */
+ backlight = <&backlight_lvds0>;
+ power-supply = <®_lvds0>;
+ status = "disabled";
+
+ port {
+ panel_in_lvds0: endpoint {
+ remote-endpoint = <&ldb_lvds_ch0>;
+ };
+ };
+ };
+
+ panel_lvds1: panel-lvds1 {
+ /*
+ * Display is not fixed, so compatible has to be added from
+ * DT overlay
+ */
+ backlight = <&backlight_lvds1>;
+ power-supply = <®_lvds1>;
+ status = "disabled";
+
+ port {
+ panel_in_lvds1: endpoint {
+ remote-endpoint = <&ldb_lvds_ch1>;
+ };
+ };
+ };
+
+ reg_1v8: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_5v0: regulator-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_5V0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ reg_12v0: regulator-12v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "12V0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ };
+
+ reg_lvds0: regulator-lvds0 {
+ compatible = "regulator-fixed";
+ regulator-name = "LCD0_VDD_EN";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_lvds1: regulator-lvds1 {
+ compatible = "regulator-fixed";
+ regulator-name = "LCD1_VDD_EN";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&expander0 3 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0 0x38000000>;
+ alloc-ranges = <0 0x40000000 0 0x78000000>;
+ linux,cma-default;
+ };
+ };
+
+ sound {
+ compatible = "fsl,imx-audio-tlv320aic32x4";
+ model = "tqm-tlv320aic32";
+ audio-asrc = <&easrc>;
+ audio-cpu = <&sai5>;
+ audio-codec = <&tlv320aic3x04>;
+ audio-routing =
+ "IN3_L", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "IN1_L", "Line In Jack",
+ "IN1_R", "Line In Jack",
+ "Line Out Jack", "LOL",
+ "Line Out Jack", "LOR";
+ };
+
+ usb-connector {
+ compatible = "gpio-usb-b-connector", "usb-b-connector";
+ type = "micro";
+ label = "X4";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbcon0>;
+ id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+
+ port {
+ usb_dr_connector: endpoint {
+ remote-endpoint = <&usb3_dwc>;
+ };
+ };
+ };
+};
+
+&dp_bridge {
+ status = "okay";
+};
+
+&easrc {
+ status = "okay";
+};
+
+&ecspi1 {
+ status = "okay";
+};
+
+&eqos {
+ status = "okay";
+};
+
+ðphy0 {
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <0>;
+ default-state = "keep";
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <0>;
+ default-state = "keep";
+ };
+ };
+};
+
+ðphy3 {
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <0>;
+ default-state = "keep";
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <0>;
+ default-state = "keep";
+ };
+ };
+};
+
+&fec {
+ status = "okay";
+};
+
+&flexcan1 {
+ xceiver-supply = <®_3v3>;
+ status = "okay";
+};
+
+&flexcan2 {
+ xceiver-supply = <®_3v3>;
+ status = "okay";
+};
+
+&hdmi_pvi {
+ status = "okay";
+};
+
+&hdmi_tx {
+ status = "okay";
+
+ ports {
+ port@1 {
+ hdmi_tx_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+};
+
+&hdmi_tx_phy {
+ status = "okay";
+};
+
+&i2c1 {
+ tlv320aic3x04: audio-codec@18 {
+ compatible = "ti,tlv320aic32x4";
+ reg = <0x18>;
+ clock-names = "mclk";
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>;
+ iov-supply = <®_1v8>;
+ ldoin-supply = <®_3v3>;
+ };
+};
+
+&ldb_lvds_ch0 {
+ remote-endpoint = <&panel_in_lvds0>;
+};
+
+&ldb_lvds_ch1 {
+ remote-endpoint = <&panel_in_lvds1>;
+};
+
+&lcdif1 {
+ status = "okay";
+};
+
+&lcdif3 {
+ status = "okay";
+};
+
+&mipi_dsi {
+ status = "okay";
+};
+
+&pcie_phy {
+ fsl,clkreq-unsupported;
+ status = "okay";
+};
+
+&pcie {
+ status = "okay";
+};
+
+®_sdvmmc {
+ startup-delay-us = <100>;
+ off-on-delay-us = <12000>;
+ status = "okay";
+};
+
+&sai3 {
+ status = "okay";
+};
+
+&sai5 {
+ status = "okay";
+};
+
+&snvs_pwrkey {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart4 {
+ status = "okay";
+};
+
+&usb3_0 {
+ status = "okay";
+};
+
+&usb_dwc3_0 {
+ status = "okay";
+
+ port {
+ usb3_dwc: endpoint {
+ remote-endpoint = <&usb_dr_connector>;
+ };
+ };
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+ vmmc-supply = <®_sdvmmc>;
+ no-mmc;
+ no-sdio;
+ bus-width = <4>;
+ status = "okay";
+};
diff --git a/dts/src/arm64/freescale/imx8mp-tqma8mpqs.dtsi b/dts/src/arm64/freescale/imx8mp-tqma8mpqs.dtsi
new file mode 100644
index 0000000000..5cc568404d
--- /dev/null
+++ b/dts/src/arm64/freescale/imx8mp-tqma8mpqs.dtsi
@@ -0,0 +1,1066 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Paul Gerber
+ */
+
+#include <dt-bindings/net/ti-dp83867.h>
+#include "imx8mp.dtsi"
+
+/ {
+ model = "TQ-Systems i.MX8MPlus TQMa8MPxS";
+ compatible = "tq,imx8mp-tqma8mpqs", "fsl,imx8mp";
+
+ clk_dp: clk-dp {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ clk_xtal25: clk-xtal25 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0 0x80000000>;
+ };
+
+ reg_sdvmmc: regulator-sdvmmc {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdvmmc>;
+ regulator-name = "SDIO_PWR_EN";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&ldo5>;
+ status = "disabled";
+ };
+};
+
+&A53_0 {
+ cpu-supply = <&buck2>;
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, <&gpio5 12 GPIO_ACTIVE_LOW>;
+};
+
+/* GBE0 */
+&eqos {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos_phy>;
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,dp83867-rxctrl-strap-quirk;
+ ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+ reset-gpios = <&expander0 6 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <500000>;
+ reset-deassert-us = <50000>;
+ enet-phy-lane-no-swap;
+ interrupt-parent = <&gpio2>;
+ interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+ };
+
+ ethphy3: ethernet-phy@3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec_phy>;
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,dp83867-rxctrl-strap-quirk;
+ ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+ reset-gpios = <&expander0 7 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <500000>;
+ reset-deassert-us = <50000>;
+ enet-phy-lane-no-swap;
+ interrupt-parent = <&gpio2>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ };
+ };
+};
+
+/* GBE1 */
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy3>;
+ fsl,magic-packet;
+};
+
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+};
+
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+};
+
+&flexspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexspi0>;
+ status = "okay";
+
+ flash0: flash@0 {
+ reg = <0>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <66666666>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ };
+};
+
+&gpio1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio1>;
+
+ gpio-line-names = "SLEEP", "BATLOW#", "", "LID",
+ "", "GPIO10", "CHARGING#", "CHG_PRSNT#",
+ "PMIC_IRQ#", "ESPI_CS1_ALERT#", "USB1_OTG_ID", "USB2_OTG_ID",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+
+ pmic_irq_hog: pmic-irq-hog {
+ gpio-hog;
+ gpios = <8 0>;
+ input;
+ line-name = "PMIC_IRQ#";
+ };
+};
+
+&gpio2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hoggpio2>;
+
+ gpio-line-names = "", "", "", "",
+ "", "", "", "",
+ "", "", "PERST#", "PEWAKE#",
+ "SDIO_CD#", "", "", "",
+ "", "", "", "SDIO_PWR_EN",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+
+ enet0-int-hog {
+ gpio-hog;
+ gpios = <0 0>;
+ input;
+ line-name = "ENET0_INT#";
+ };
+
+ enet1-int-hog {
+ gpio-hog;
+ gpios = <1 0>;
+ input;
+ line-name = "ENET_INT#";
+ };
+
+ perst-hog {
+ gpio-hog;
+ gpios = <10 0>;
+ output-high;
+ line-name = "PERST#";
+ };
+
+ pewake-hog {
+ gpio-hog;
+ gpios = <11 0>;
+ input;
+ line-name = "PEWAKE#";
+ };
+
+ rtc-int-hog {
+ gpio-hog;
+ gpios = <27 0>;
+ input;
+ line-name = "RTC_INT#";
+ };
+};
+
+&gpio3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio3>;
+
+ gpio-line-names = "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "GPIO4",
+ "GPIO3", "", "", "",
+ "", "", "", "",
+ "TEMP_EVENT#", "", "", "";
+
+ temp-event--hog {
+ gpio-hog;
+ gpios = <28 0>;
+ input;
+ line-name = "TEMP_EVENT#";
+ };
+};
+
+&gpio4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio4>, <&pinctrl_sdp>, <&pinctrl_eepromwp>;
+
+ gpio-line-names = "", "GPIO8", "", "",
+ "GPIO9", "ESPI_RST#", "", "",
+ "", "", "", "",
+ "", "", "GBE0_SDP_DIR", "",
+ "GPIO7", "", "", "",
+ "", "", "", "",
+ "", "GPIO0", "GPIO1", "",
+ "GPIO2", "GPIO6", "", "";
+
+ /* EEPROM write control */
+ sw_en_hog: sw-en-hog {
+ gpio-hog;
+ gpios = <5 0>;
+ output-high;
+ line-name = "SW_EN";
+ };
+};
+
+&gpio5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio5>;
+
+ gpio-line-names = "", "", "", "",
+ "", "GPIO5", "", "",
+ "", "", "GPIO12", "GPIO11",
+ "", "GPIO13", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+
+ dp-hpd-int-hog {
+ gpio-hog;
+ gpios = <21 0>;
+ input;
+ line-name = "DP_HPD_INT";
+ };
+};
+
+&hdmi_tx {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hdmi>;
+};
+
+&i2c1 {
+ clock-frequency = <384000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ eeprom0: eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ pagesize = <32>;
+ read-only;
+ vcc-supply = <&buck5>;
+ };
+
+ pcf85063: rtc@51 {
+ compatible = "nxp,pcf85063a";
+ reg = <0x51>;
+ quartz-load-femtofarads = <7000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcf85063>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
+ };
+
+ eeprom1: eeprom@54 {
+ compatible = "atmel,24c64";
+ reg = <0x54>;
+ pagesize = <32>;
+ vcc-supply = <&buck5>;
+ };
+
+ /* protectable identification memory (part of M24C64-D @50) */
+ eeprom@58 {
+ compatible = "atmel,24c64d-wl";
+ reg = <0x58>;
+ size = <32>;
+ pagesize = <32>;
+ vcc-supply = <&buck5>;
+ };
+
+ /* protectable identification memory (part of M24C64-D @54) */
+ eeprom@5c {
+ compatible = "atmel,24c64d-wl";
+ reg = <0x5c>;
+ size = <32>;
+ pagesize = <32>;
+ vcc-supply = <&buck5>;
+ };
+
+ pcieclk: clock-generator@6a {
+ compatible = "renesas,9fgv0241";
+ reg = <0x6a>;
+ clocks = <&clk_xtal25>;
+ #clock-cells = <1>;
+ };
+
+ imu@6b {
+ compatible = "st,ism330dhcx";
+ reg = <0x6b>;
+ vdd-supply = <&buck4>;
+ vddio-supply = <&buck4>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <384000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ pmic: pmic@25 {
+ reg = <0x25>;
+ compatible = "nxp,pca9450c";
+
+ /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+
+ regulators {
+ /* V_0V85_SOC: 0.85 .. 0.95 */
+ buck1: BUCK1 {
+ regulator-name = "BUCK1";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <950000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ /* VDD_ARM */
+ buck2: BUCK2 {
+ regulator-name = "BUCK2";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ nxp,dvs-run-voltage = <950000>;
+ nxp,dvs-standby-voltage = <850000>;
+ regulator-ramp-delay = <3125>;
+ };
+
+ /* VCC3V3 -> VMMC, ... must not be changed */
+ buck4: BUCK4 {
+ regulator-name = "BUCK4";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */
+ buck5: BUCK5 {
+ regulator-name = "BUCK5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* V_1V1 -> RAM, ... must not be changed */
+ buck6: BUCK6 {
+ regulator-name = "BUCK6";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* V_1V8_SNVS */
+ ldo1: LDO1 {
+ regulator-name = "LDO1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* V_1V8_ANA */
+ ldo3: LDO3 {
+ regulator-name = "LDO3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* unused */
+ ldo4: LDO4 {
+ regulator-name = "LDO4";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ /* VCC SD IO - switched using SD2 VSELECT */
+ ldo5: LDO5 {
+ regulator-name = "LDO5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+ };
+
+ tmp1075: temperature-sensor@4a {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tmp1075>;
+ compatible = "ti,tmp1075";
+ reg = <0x4a>;
+ vs-supply = <&buck4>;
+ };
+
+ expander0: gpio@73 {
+ compatible = "nxp,pca9538";
+ reg = <0x73>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ vcc-supply = <&buck5>;
+ gpio-line-names = "LCD0_BKLT_EN", "LCD0_VDD_EN",
+ "LCD1_BKLT_EN", "LCD1_VDD_EN",
+ "DP_BRIDGE_EN", "HUB_RST#",
+ "ENET0_RESET#", "ENET1_RESET#";
+ };
+};
+
+&i2c3 {
+ clock-frequency = <384000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ dp_bridge: dp-bridge@f {
+ compatible = "toshiba,tc9595", "toshiba,tc358767";
+ reg = <0xf>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tc9595>;
+ clock-names = "ref";
+ clocks = <&clk_dp>;
+ reset-gpios = <&expander0 4 GPIO_ACTIVE_HIGH>;
+ toshiba,hpd-pin = <0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dsi_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ data-lanes = <1 2 3 4>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ endpoint {
+ toshiba,pre-emphasis = /bits/ 8 <1 1>;
+ };
+ };
+ };
+ };
+};
+
+&i2c4 {
+ clock-frequency = <384000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ pinctrl-1 = <&pinctrl_i2c4_gpio>;
+ scl-gpios = <&gpio2 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio2 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+&i2c6 {
+ clock-frequency = <384000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c6>;
+ pinctrl-1 = <&pinctrl_i2c6_gpio>;
+ scl-gpios = <&gpio2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio2 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+&mipi_dsi {
+ samsung,burst-clock-frequency = <1000000000>;
+ samsung,esc-clock-frequency = <10000000>;
+
+ ports {
+ port@1 {
+ reg = <1>;
+
+ dsi_out: endpoint {
+ remote-endpoint = <&dsi_in>;
+ data-lanes = <1 2 3 4>;
+ };
+ };
+ };
+};
+
+&pcie_phy {
+ fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
+ clock-names = "ref";
+ clocks = <&pcieclk 0>;
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+ <&clk IMX8MP_CLK_HSIO_AXI>,
+ <&clk IMX8MP_CLK_PCIE_ROOT>;
+ clock-names = "pcie", "pcie_bus", "pcie_aux";
+ assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
+ assigned-clock-rates = <10000000>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
+};
+
+&sai3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai3>;
+ assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <12288000>;
+};
+
+&sai5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai5>;
+ assigned-clocks = <&clk IMX8MP_CLK_SAI5>;
+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <12288000>;
+ fsl,sai-mclk-direction-output;
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ assigned-clocks = <&clk IMX8MP_CLK_UART1>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+ uart-has-rtscts;
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ assigned-clocks = <&clk IMX8MP_CLK_UART2>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+ rts-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
+ cts-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
+};
+
+&uart3 {
+ /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ assigned-clocks = <&clk IMX8MP_CLK_UART4>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+};
+
+&usb3_phy0 {
+ vbus-supply = <®_5v0>;
+ status = "okay";
+};
+
+&usb3_phy1 {
+ vbus-supply = <®_5v0>;
+ status = "okay";
+};
+
+&usb3_0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>;
+ fsl,over-current-active-low;
+ maximum-speed = "high-speed";
+};
+
+&usb3_1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>;
+ fsl,over-current-active-low;
+ status = "okay";
+};
+
+&usb_dwc3_0 {
+ /* dual role is implemented, but not a full featured OTG */
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+ maximum-speed = "high-speed";
+ dr_mode = "otg";
+ usb-role-switch;
+ role-switch-default-mode = "peripheral";
+};
+
+&usb_dwc3_1 {
+ dr_mode = "host";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ hub_2_0: hub@1 {
+ compatible = "usb451,8142";
+ reg = <1>;
+ peer-hub = <&hub_3_0>;
+ reset-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;
+ vdd-supply = <®_3v3>;
+ };
+
+ hub_3_0: hub@2 {
+ compatible = "usb451,8140";
+ reg = <2>;
+ peer-hub = <&hub_2_0>;
+ reset-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;
+ vdd-supply = <®_3v3>;
+ };
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ no-sdio;
+ no-sd;
+ vmmc-supply = <&buck4>;
+ vqmmc-supply = <&buck5>;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c0>,
+ <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x1c0>,
+ <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x1c0>,
+ <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c0>,
+ <MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x1c0>;
+ };
+
+ pinctrl_eepromwp: eepromwpgrp {
+ fsl,pins = <MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x00000144>;
+ };
+
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x40000044>,
+ <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x40000044>,
+ <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90>,
+ <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90>,
+ <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90>,
+ <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90>,
+ <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90>,
+ <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90>,
+ <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12>,
+ <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12>,
+ <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12>,
+ <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12>,
+ <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12>,
+ <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x14>;
+ };
+
+ pinctrl_eqos_event: eqosevtgrp {
+ fsl,pins = <MX8MP_IOMUXC_SAI2_MCLK__ENET_QOS_1588_EVENT3_IN 0x100>,
+ <MX8MP_IOMUXC_SAI2_TXFS__ENET_QOS_1588_EVENT3_OUT 0x1c0>;
+ };
+
+ pinctrl_eqos_phy: eqosphygrp {
+ fsl,pins = <MX8MP_IOMUXC_SD1_CLK__GPIO2_IO00 0x1c0>;
+ };
+
+ pinctrl_fec: fecgrp {
+ fsl,pins = <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90>,
+ <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90>,
+ <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90>,
+ <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90>,
+ <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90>,
+ <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90>,
+ <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12>,
+ <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12>,
+ <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x12>,
+ <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x12>,
+ <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x12>,
+ <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14>;
+ };
+
+ pinctrl_fec_event: fecevtgrp {
+ fsl,pins = <MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT 0x100>,
+ <MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x1c0>;
+ };
+
+ pinctrl_fec_phy: fecphygrp {
+ fsl,pins = <MX8MP_IOMUXC_SD1_CMD__GPIO2_IO01 0x1c0>;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x150>,
+ <MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x150>;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x150>,
+ <MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x150>;
+ };
+
+ pinctrl_flexspi0: flexspi0grp {
+ fsl,pins = <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x142>,
+ <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82>,
+ <MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x40000010>,
+ <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82>,
+ <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82>,
+ <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82>,
+ <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82>;
+ };
+
+ pinctrl_sdp: gbegrp {
+ fsl,pins = <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x10>,
+ <MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x10>;
+ };
+
+ pinctrl_gpio1: gpio1grp {
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x10>,
+ <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x10>,
+ <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x10>,
+ <MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x10>,
+ <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x10>,
+ <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x80>,
+ <MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x80>;
+ };
+
+ pinctrl_gpio3: gpio3grp {
+ fsl,pins = <MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x10>,
+ <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x10>;
+ };
+
+ pinctrl_gpio4: gpio4grp {
+ fsl,pins = <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x10>,
+ <MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x10>,
+ <MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x10>,
+ <MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10>,
+ <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x10>,
+ <MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x10>,
+ <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x10>,
+ <MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x10>;
+ };
+
+ pinctrl_gpio5: gpio5grp {
+ fsl,pins = <MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x10>,
+ <MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10 0x10>,
+ <MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x10>,
+ <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x10>;
+ };
+
+ pinctrl_hdmi: hdmigrp {
+ fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c2>,
+ <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c2>,
+ <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010>;
+ };
+
+ pinctrl_hoggpio2: hoggpio2grp {
+ fsl,pins = <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x140>;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001e2>,
+ <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001e2>;
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpiogrp {
+ fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001e2>,
+ <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001e2>;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001e2>,
+ <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001e2>;
+ };
+
+ pinctrl_i2c2_gpio: i2c2-gpiogrp {
+ fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001e2>,
+ <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001e2>;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001e2>,
+ <MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001e2>;
+ };
+
+ pinctrl_i2c3_gpio: i2c3-gpiogrp {
+ fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001e2>,
+ <MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001e2>;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <MX8MP_IOMUXC_SD1_DATA2__I2C4_SCL 0x400001e2>,
+ <MX8MP_IOMUXC_SD1_DATA3__I2C4_SDA 0x400001e2>;
+ };
+
+ pinctrl_i2c4_gpio: i2c4-gpiogrp {
+ fsl,pins = <MX8MP_IOMUXC_SD1_DATA2__GPIO2_IO04 0x400001e2>,
+ <MX8MP_IOMUXC_SD1_DATA3__GPIO2_IO05 0x400001e2>;
+ };
+
+ pinctrl_i2c6: i2c6grp {
+ fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 0x400001e2>,
+ <MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 0x400001e2>;
+ };
+
+ pinctrl_i2c6_gpio: i2c6-gpiogrp {
+ fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x400001e2>,
+ <MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x400001e2>;
+ };
+
+ pinctrl_pcf85063: pcf85063grp {
+ fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x80>;
+ };
+
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x60>,
+ <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x94>;
+ };
+
+ pinctrl_pmic: pmicirqgrp {
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x1c0>;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <MX8MP_IOMUXC_SPDIF_RX__PWM2_OUT 0x14>;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x14>;
+ };
+
+ pinctrl_sai3: sai3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x94
+ MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x94
+ MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x94
+ MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x94
+ >;
+ };
+
+ pinctrl_sai5: sai5grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI5_MCLK 0x94
+ MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 0x94
+ MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00 0x94
+ MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_TX_SYNC 0x94
+ MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI5_TX_BCLK 0x94
+ >;
+ };
+
+ pinctrl_sdvmmc: sdvmmcgrp {
+ fsl,pins = <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x10>;
+ };
+
+ pinctrl_tc9595: tc9595grp {
+ fsl,pins = <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x10>;
+ };
+
+ pinctrl_tmp1075: tmp1075grp {
+ fsl,pins = <MX8MP_IOMUXC_HDMI_CEC__GPIO3_IO28 0x140>;
+ };
+
+ /* DCE configuration */
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140>,
+ <MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140>,
+ <MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140>,
+ <MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140>;
+ };
+
+ /* DCE configuration */
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140>,
+ <MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140>,
+ <MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x140>,
+ <MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x140>;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x140>,
+ <MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x140>;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140>,
+ <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140>;
+ };
+
+ pinctrl_usb0: usb0grp {
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x1c0>,
+ <MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x1c0>;
+ };
+
+ pinctrl_usb1: usb1grp {
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x1c0>,
+ <MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x1c0>;
+ };
+
+ pinctrl_usbcon0: usb0congrp {
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c0>;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x192>,
+ <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d2>,
+ <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2>,
+ <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2>,
+ <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2>,
+ <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>,
+ <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>,
+ <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>,
+ <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
+ <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
+ <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
+ <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>,
+ <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>,
+ <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>,
+ <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
+ <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
+ <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
+ <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>,
+ <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
+ fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c0>,
+ <MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x1c0>;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>,
+ <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>,
+ <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>,
+ <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>,
+ <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>,
+ <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>,
+ <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>,
+ <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>,
+ <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>,
+ <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>,
+ <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x84>,
+ <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x84>;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>,
+ <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>,
+ <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>,
+ <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>,
+ <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>,
+ <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>,
+ <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>,
+ <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>,
+ <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>,
+ <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>,
+ <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x84>,
+ <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x84>;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>,
+ <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>,
+ <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>,
+ <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>,
+ <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>,
+ <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>,
+ <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>,
+ <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>,
+ <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>,
+ <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>,
+ <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x84>,
+ <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x84>;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x1c4>;
+ };
+};
--
2.47.3
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 2/3] ARM: boards: tqma8mpxl: extend with support for xs
2026-02-13 8:19 [PATCH 0/3] ARM: boards: add support for tqma8mpxs boards Fabian Pflug
2026-02-13 8:19 ` [PATCH 1/3] dts: arm64: freescale: add imx8mp-tqma8mpqs board Fabian Pflug
@ 2026-02-13 8:19 ` Fabian Pflug
2026-02-13 8:19 ` [PATCH 3/3] ARM: boards: tqma8mpxx: add no_ecc ram timings Fabian Pflug
2 siblings, 0 replies; 5+ messages in thread
From: Fabian Pflug @ 2026-02-13 8:19 UTC (permalink / raw)
To: BAREBOX; +Cc: Fabian Pflug
The TQMA8MPxS is another board from TQMA with the same processor, but a
different formfactor. Nevertheless they share a lot of code and can be
used from the same barebox resulting in the rename of tqma8mpxl to
tqma8mpxx.
Signed-off-by: Fabian Pflug <f.pflug@pengutronix.de>
---
Documentation/migration-guides/migration-master.md | 10 ++
arch/arm/boards/Makefile | 2 +-
arch/arm/boards/tqma8mpxl/lowlevel.c | 113 --------------
arch/arm/boards/{tqma8mpxl => tqma8mpxx}/Makefile | 0
arch/arm/boards/{tqma8mpxl => tqma8mpxx}/board.c | 17 +-
| 0
arch/arm/boards/tqma8mpxx/lowlevel.c | 172 +++++++++++++++++++++
.../{tqma8mpxl => tqma8mpxx}/lpddr4-timing.c | 0
arch/arm/configs/imx_v8_defconfig | 2 +-
arch/arm/configs/multi_v8_defconfig | 2 +-
arch/arm/dts/Makefile | 2 +-
arch/arm/dts/imx8mp-tqma8mpqs-mba8mpxs.dts | 15 ++
arch/arm/mach-imx/Kconfig | 5 +-
images/Makefile.imx | 2 +-
14 files changed, 214 insertions(+), 128 deletions(-)
diff --git a/Documentation/migration-guides/migration-master.md b/Documentation/migration-guides/migration-master.md
new file mode 100644
index 0000000000..0cf45d0713
--- /dev/null
+++ b/Documentation/migration-guides/migration-master.md
@@ -0,0 +1,10 @@
+:orphan:
+
+Boards
+------
+
+TQMA8MPxL
+^^^^^^^^^
+
+The config option has been renamed from MACH_TQ_MBA8MPXL to MACH_TQ_MBA8MPXX to
+accommodate the support for TQMA8MPxS boards with the same binary.
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index afc50051a2..ab4e74f592 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -75,7 +75,7 @@ obj-$(CONFIG_MACH_NXP_IMX8MN_EVK) += nxp-imx8mn-evk/
obj-$(CONFIG_MACH_NXP_IMX8MP_EVK) += nxp-imx8mp-evk/
obj-$(CONFIG_MACH_NXP_IMX93_FRDM) += nxp-imx93-frdm/
obj-$(CONFIG_MACH_CONGATEC_QMX8P_SOM) += congatec-qmx8p/
-obj-$(CONFIG_MACH_TQ_MBA8MPXL) += tqma8mpxl/
+obj-$(CONFIG_MACH_TQ_MBA8MPXX) += tqma8mpxx/
obj-$(CONFIG_MACH_PCA100) += phytec-phycard-imx27/
obj-$(CONFIG_MACH_PCM038) += phytec-phycore-imx27/
obj-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += phytec-som-am335x/
diff --git a/arch/arm/boards/tqma8mpxl/lowlevel.c b/arch/arm/boards/tqma8mpxl/lowlevel.c
deleted file mode 100644
index e0a0f17d3a..0000000000
--- a/arch/arm/boards/tqma8mpxl/lowlevel.c
+++ /dev/null
@@ -1,113 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-
-#include <io.h>
-#include <common.h>
-#include <firmware.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/sections.h>
-#include <asm/barebox-arm.h>
-#include <asm/barebox-arm-head.h>
-#include <linux/sizes.h>
-#include <mach/imx/atf.h>
-#include <mach/imx/xload.h>
-#include <mach/imx/esdctl.h>
-#include <mach/imx/generic.h>
-#include <mach/imx/imx8mp-regs.h>
-#include <mach/imx/iomux-mx8mp.h>
-#include <mach/imx/imx8m-ccm-regs.h>
-#include <mach/imx/debug_ll.h>
-#include <mfd/pca9450.h>
-#include <pbl/i2c.h>
-#include <pbl/pmic.h>
-#include <soc/imx8m/ddr.h>
-
-#define UART_PAD_CTRL MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \
- MX8MP_PAD_CTL_FSEL)
-
-#define I2C_PAD_CTRL MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \
- MX8MP_PAD_CTL_HYS | \
- MX8MP_PAD_CTL_PUE | \
- MX8MP_PAD_CTL_PE)
-
-static void setup_uart(void)
-{
- void __iomem *uart = IOMEM(MX8M_UART4_BASE_ADDR);
-
- imx8m_early_setup_uart_clock();
-
- imx8mp_setup_pad(MX8MP_PAD_UART4_TXD__UART4_DCE_TX | UART_PAD_CTRL);
- imx8mp_setup_pad(MX8MP_PAD_UART4_RXD__UART4_DCE_RX | UART_PAD_CTRL);
- imx8m_uart_setup(uart);
-
- pbl_set_putc(imx_uart_putc, uart);
-
- putc_ll('>');
-}
-
-static struct pmic_config pca9450_cfg[] = {
- /* BUCKxOUT_DVS0/1 control BUCK123 output */
- { PCA9450_BUCK123_DVS, 0x29 },
- /*
- * increase VDD_SOC to typical value 0.95V before first
- * DRAM access, set DVS1 to 0.85v for suspend.
- * Enable DVS control through PMIC_STBY_REQ and
- * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
- */
- { PCA9450_BUCK1OUT_DVS0, 0x1C },
- { PCA9450_BUCK1OUT_DVS1, 0x14 },
- { PCA9450_BUCK1CTRL, 0x59 },
- /*
- * Kernel uses OD/OD freq for SOC
- * To avoid timing risk from SOC to ARM,increase VDD_ARM to OD
- * voltage 0.95v
- */
- { PCA9450_BUCK2OUT_DVS0, 0x1C },
- /* set WDOG_B_CFG to cold reset */
- { PCA9450_RESET_CTRL, 0xA1 },
-};
-
-static void power_init_board(void)
-{
- struct pbl_i2c *i2c;
-
- imx8mp_setup_pad(MX8MP_PAD_I2C1_SCL__I2C1_SCL | I2C_PAD_CTRL);
- imx8mp_setup_pad(MX8MP_PAD_I2C1_SDA__I2C1_SDA | I2C_PAD_CTRL);
-
- imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1);
-
- i2c = imx8m_i2c_early_init(IOMEM(MX8MP_I2C1_BASE_ADDR));
-
- pmic_configure(i2c, 0x25, pca9450_cfg, ARRAY_SIZE(pca9450_cfg));
-}
-
-static __noreturn noinline void tqma8mpxl_start(void)
-{
- extern char __dtb_z_imx8mp_tqma8mpql_mba8mpxl_start[];
-
- setup_uart();
-
- if (current_el() == 3) {
- extern struct dram_timing_info dram_timing_2gb_no_ecc;
-
- imx8mp_early_clock_init();
-
- power_init_board();
-
- imx8mp_ddr_init(&dram_timing_2gb_no_ecc, DRAM_TYPE_LPDDR4);
-
- imx8mp_load_and_start_image_via_tfa();
- }
-
- imx8mp_barebox_entry(__dtb_z_imx8mp_tqma8mpql_mba8mpxl_start);
-}
-
-ENTRY_FUNCTION(start_tqma8mpxl, x0, x1, x2)
-{
- imx8mp_cpu_lowlevel_init();
-
- relocate_to_current_adr();
- setup_c();
-
- tqma8mpxl_start();
-}
diff --git a/arch/arm/boards/tqma8mpxl/Makefile b/arch/arm/boards/tqma8mpxx/Makefile
similarity index 100%
rename from arch/arm/boards/tqma8mpxl/Makefile
rename to arch/arm/boards/tqma8mpxx/Makefile
diff --git a/arch/arm/boards/tqma8mpxl/board.c b/arch/arm/boards/tqma8mpxx/board.c
similarity index 74%
rename from arch/arm/boards/tqma8mpxl/board.c
rename to arch/arm/boards/tqma8mpxx/board.c
index 459e180a57..34a7bd5f4f 100644
--- a/arch/arm/boards/tqma8mpxl/board.c
+++ b/arch/arm/boards/tqma8mpxx/board.c
@@ -16,7 +16,7 @@
#include <envfs.h>
#include <string.h>
-static int tqma8mpxl_probe(struct device *dev)
+static int tqma8mpxx_probe(struct device *dev)
{
const char *emmc, *sd;
int emmc_bbu_flag = 0;
@@ -43,15 +43,16 @@ static int tqma8mpxl_probe(struct device *dev)
return 0;
}
-static const struct of_device_id tqma8mpxl_of_match[] = {
+static const struct of_device_id tqma8mpxx_of_match[] = {
{ .compatible = "tq,imx8mp-tqma8mpql" },
+ { .compatible = "tq,imx8mp-tqma8mpqs" },
{ /* sentinel */ },
};
-BAREBOX_DEEP_PROBE_ENABLE(tqma8mpxl_of_match);
+BAREBOX_DEEP_PROBE_ENABLE(tqma8mpxx_of_match);
-static struct driver tqma8mpxl_board_driver = {
- .name = "board-tqma8mpxl",
- .probe = tqma8mpxl_probe,
- .of_compatible = DRV_OF_COMPAT(tqma8mpxl_of_match),
+static struct driver tqma8mpxx_board_driver = {
+ .name = "board-tqma8mpxx",
+ .probe = tqma8mpxx_probe,
+ .of_compatible = DRV_OF_COMPAT(tqma8mpxx_of_match),
};
-device_platform_driver(tqma8mpxl_board_driver);
+device_platform_driver(tqma8mpxx_board_driver);
diff --git a/arch/arm/boards/tqma8mpxl/flash-header-tqma8mpxl.imxcfg b/arch/arm/boards/tqma8mpxx/flash-header-tqma8mpxx.imxcfg
similarity index 100%
rename from arch/arm/boards/tqma8mpxl/flash-header-tqma8mpxl.imxcfg
rename to arch/arm/boards/tqma8mpxx/flash-header-tqma8mpxx.imxcfg
diff --git a/arch/arm/boards/tqma8mpxx/lowlevel.c b/arch/arm/boards/tqma8mpxx/lowlevel.c
new file mode 100644
index 0000000000..7d8bae9c4d
--- /dev/null
+++ b/arch/arm/boards/tqma8mpxx/lowlevel.c
@@ -0,0 +1,172 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <io.h>
+#include <common.h>
+#include <firmware.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/sections.h>
+#include <asm/barebox-arm.h>
+#include <asm/barebox-arm-head.h>
+#include <linux/sizes.h>
+#include <mach/imx/atf.h>
+#include <mach/imx/xload.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/generic.h>
+#include <mach/imx/imx8mp-regs.h>
+#include <mach/imx/iomux-mx8mp.h>
+#include <mach/imx/imx8m-ccm-regs.h>
+#include <mach/imx/debug_ll.h>
+#include <mfd/pca9450.h>
+#include <pbl/i2c.h>
+#include <pbl/pmic.h>
+#include <soc/imx8m/ddr.h>
+#include <boards/tq/tq_eeprom.h>
+
+#define UART_PAD_CTRL MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \
+ MX8MP_PAD_CTL_FSEL)
+
+#define I2C_PAD_CTRL MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \
+ MX8MP_PAD_CTL_HYS | \
+ MX8MP_PAD_CTL_PUE | \
+ MX8MP_PAD_CTL_PE)
+
+static void setup_uart(void *uart, iomux_v3_cfg_t tx_pad, iomux_v3_cfg_t rx_pad)
+{
+ imx8m_early_setup_uart_clock();
+
+ imx8mp_setup_pad(tx_pad | UART_PAD_CTRL);
+ imx8mp_setup_pad(rx_pad | UART_PAD_CTRL);
+ imx8m_uart_setup(uart);
+
+ pbl_set_putc(imx_uart_putc, uart);
+
+ putc_ll('>');
+}
+
+static struct pbl_i2c *tqma_i2c1_init(void)
+{
+ imx8mp_setup_pad(MX8MP_PAD_I2C1_SCL__I2C1_SCL | I2C_PAD_CTRL);
+ imx8mp_setup_pad(MX8MP_PAD_I2C1_SDA__I2C1_SDA | I2C_PAD_CTRL);
+
+ imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1);
+
+ return imx8m_i2c_early_init(IOMEM(MX8MP_I2C1_BASE_ADDR));
+}
+
+static struct pbl_i2c *tqma_i2c2_init(void)
+{
+ imx8mp_setup_pad(MX8MP_PAD_I2C2_SCL__I2C2_SCL | I2C_PAD_CTRL);
+ imx8mp_setup_pad(MX8MP_PAD_I2C2_SDA__I2C2_SDA | I2C_PAD_CTRL);
+
+ imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C2);
+
+ return imx8m_i2c_early_init(IOMEM(MX8MP_I2C2_BASE_ADDR));
+}
+
+static struct pmic_config pca9450_cfg[] = {
+ /* BUCKxOUT_DVS0/1 control BUCK123 output */
+ { PCA9450_BUCK123_DVS, 0x29 },
+ /*
+ * increase VDD_SOC to typical value 0.95V before first
+ * DRAM access, set DVS1 to 0.85v for suspend.
+ * Enable DVS control through PMIC_STBY_REQ and
+ * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
+ */
+ { PCA9450_BUCK1OUT_DVS0, 0x1C },
+ { PCA9450_BUCK1OUT_DVS1, 0x14 },
+ { PCA9450_BUCK1CTRL, 0x59 },
+ /*
+ * Kernel uses OD/OD freq for SOC
+ * To avoid timing risk from SOC to ARM,increase VDD_ARM to OD
+ * voltage 0.95v
+ */
+ { PCA9450_BUCK2OUT_DVS0, 0x1C },
+ /* set WDOG_B_CFG to cold reset */
+ { PCA9450_RESET_CTRL, 0xA1 },
+};
+
+static bool tqma_is_eeprom_valid(struct tq_eeprom *eeprom)
+{
+ int ramsize;
+
+ if (!*eeprom->serial || !*eeprom->id)
+ return false;
+ ramsize = tq_vard_ramsize(&eeprom->vard) / (SZ_1G);
+ if (ramsize != 1 && ramsize != 2 && ramsize != 4 && ramsize != 8)
+ return false;
+ return true;
+}
+
+static noinline void tqma8mpxx_start(void)
+{
+ extern char __dtb_z_imx8mp_tqma8mpql_mba8mpxl_start[];
+ extern char __dtb_z_imx8mp_tqma8mpqs_mba8mpxs_start[];
+
+ struct tq_eeprom *eeprom;
+ struct pbl_i2c *i2c;
+ void *boarddata;
+
+ i2c = tqma_i2c1_init();
+
+ /**
+ * The difference for the lowlevel code between xS and xL is:
+ * PMIC: xS on i2c2, xL on i2C1
+ * VARD: address 0x50 on xS, address 0x53 on xL.
+ * offset 0x1000 on xS, offset 0x0 on xL
+ */
+
+ eeprom = pbl_tq_read_eeprom(i2c, 0x50, 0x1000 | I2C_ADDR_16_BIT);
+ if (tqma_is_eeprom_valid(eeprom)) {
+ /* found xS board */
+ i2c = tqma_i2c2_init();
+ boarddata = __dtb_z_imx8mp_tqma8mpqs_mba8mpxs_start;
+ setup_uart(IOMEM(MX8M_UART3_BASE_ADDR),
+ MX8MP_PAD_SD1_DATA6__UART3_DCE_TX,
+ MX8MP_PAD_SD1_DATA7__UART3_DCE_RX);
+ } else {
+ eeprom = pbl_tq_read_eeprom(i2c, 0x53, 0);
+ if (!tqma_is_eeprom_valid(eeprom))
+ panic("Could not read VARD!\n");
+
+ /* found xL board */
+ boarddata = __dtb_z_imx8mp_tqma8mpql_mba8mpxl_start;
+ setup_uart(IOMEM(MX8M_UART4_BASE_ADDR),
+ MX8MP_PAD_UART4_TXD__UART4_DCE_TX,
+ MX8MP_PAD_UART4_RXD__UART4_DCE_RX);
+
+ }
+
+ if (current_el() == 3) {
+ extern struct dram_timing_info dram_timing_2gb_no_ecc;
+ int ramsize;
+
+ ramsize = tq_vard_ramsize(&eeprom->vard) / (SZ_1G);
+ if (ramsize != 2)
+ panic("RAMsize other then 2GB is not supported at the moment.\n");
+
+ imx8mp_early_clock_init();
+
+ pmic_configure(i2c, 0x25, pca9450_cfg, ARRAY_SIZE(pca9450_cfg));
+
+ imx8mp_ddr_init(&dram_timing_2gb_no_ecc, DRAM_TYPE_LPDDR4);
+
+ imx8mp_load_and_start_image_via_tfa();
+ }
+
+ tq_vard_show(&eeprom->vard);
+ printf("Serial: %s\n", eeprom->id);
+ printf("ID: %s\n", eeprom->serial);
+
+ imx8mp_barebox_entry(boarddata);
+}
+
+ENTRY_FUNCTION(start_tqma8mpxx, x0, x1, x2)
+{
+ imx8mp_cpu_lowlevel_init();
+
+ relocate_to_current_adr();
+ setup_c();
+
+ tqma8mpxx_start();
+}
diff --git a/arch/arm/boards/tqma8mpxl/lpddr4-timing.c b/arch/arm/boards/tqma8mpxx/lpddr4-timing.c
similarity index 100%
rename from arch/arm/boards/tqma8mpxl/lpddr4-timing.c
rename to arch/arm/boards/tqma8mpxx/lpddr4-timing.c
diff --git a/arch/arm/configs/imx_v8_defconfig b/arch/arm/configs/imx_v8_defconfig
index af071e4d83..e080a7db9b 100644
--- a/arch/arm/configs/imx_v8_defconfig
+++ b/arch/arm/configs/imx_v8_defconfig
@@ -12,7 +12,7 @@ CONFIG_MACH_PHYTEC_SOM_IMX8MQ=y
CONFIG_MACH_POLYHEX_DEBIX=y
CONFIG_MACH_PROTONIC_IMX8M=y
CONFIG_MACH_SKOV_IMX8MP=y
-CONFIG_MACH_TQ_MBA8MPXL=y
+CONFIG_MACH_TQ_MBA8MPXX=y
CONFIG_MACH_VARISCITE_DT8MCUSTOMBOARD_IMX8MP=y
CONFIG_MACH_ZII_IMX8MQ_DEV=y
CONFIG_MACH_PHYTEC_PHYCORE_IMX93=y
diff --git a/arch/arm/configs/multi_v8_defconfig b/arch/arm/configs/multi_v8_defconfig
index 6fe8ab3463..1553c47fab 100644
--- a/arch/arm/configs/multi_v8_defconfig
+++ b/arch/arm/configs/multi_v8_defconfig
@@ -21,7 +21,7 @@ CONFIG_MACH_PHYTEC_SOM_IMX8MQ=y
CONFIG_MACH_POLYHEX_DEBIX=y
CONFIG_MACH_PROTONIC_IMX8M=y
CONFIG_MACH_SKOV_IMX8MP=y
-CONFIG_MACH_TQ_MBA8MPXL=y
+CONFIG_MACH_TQ_MBA8MPXX=y
CONFIG_MACH_VARISCITE_DT8MCUSTOMBOARD_IMX8MP=y
CONFIG_MACH_ZII_IMX8MQ_DEV=y
CONFIG_MACH_PHYTEC_PHYCORE_IMX93=y
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index dd7482aa05..8dbe020e5d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -184,7 +184,7 @@ lwl-$(CONFIG_MACH_NXP_IMX8MP_EVK) += imx8mp-evk.dtb.o
lwl-$(CONFIG_MACH_NXP_IMX8MQ_EVK) += imx8mq-evk.dtb.o
lwl-$(CONFIG_MACH_NXP_IMX93_FRDM) += imx93-frdm.dtb.o
lwl-$(CONFIG_MACH_INNOCOMM_WB15) += imx8mm-innocomm-wb15-evk.dtb.o
-lwl-$(CONFIG_MACH_TQ_MBA8MPXL) += imx8mp-tqma8mpql-mba8mpxl.dtb.o
+lwl-$(CONFIG_MACH_TQ_MBA8MPXX) += imx8mp-tqma8mpql-mba8mpxl.dtb.o imx8mp-tqma8mpqs-mba8mpxs.dtb.o
lwl-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += tegra20-colibri-iris.dtb.o
lwl-$(CONFIG_MACH_TORADEX_COLIBRI_IMX6) += imx6dl-colibri-iris.dtb.o
lwl-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o
diff --git a/arch/arm/dts/imx8mp-tqma8mpqs-mba8mpxs.dts b/arch/arm/dts/imx8mp-tqma8mpqs-mba8mpxs.dts
new file mode 100644
index 0000000000..a3018af7a5
--- /dev/null
+++ b/arch/arm/dts/imx8mp-tqma8mpqs-mba8mpxs.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2026 Pengutronix, Fabian Pflug <kernel@pengutronix.de>
+ */
+
+/dts-v1/;
+
+#include <arm64/freescale/imx8mp-tqma8mpqs-mb-smarc-2.dts>
+#include "imx8mp.dtsi"
+
+&{pmic/regulators} {
+ barebox,allow-dummy-supply;
+};
+
+/delete-node/ &{/memory@40000000};
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index eb947e67fb..1e88c533f3 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -742,12 +742,13 @@ config MACH_SKOV_IMX8MP
select IMX8M_DRAM
select I2C_IMX_EARLY
-config MACH_TQ_MBA8MPXL
- bool "TQ i.MX8MP Dual/Quad on MBa8MPxL Board"
+config MACH_TQ_MBA8MPXX
+ bool "TQ i.MX8MP Dual/Quad on MBa8MPxL or MBa8MPxS Board"
select ARCH_IMX8MP
select FIRMWARE_IMX_LPDDR4_PMU_TRAIN
select FIRMWARE_IMX8MP_ATF
select ARM_SMCCC
+ select BOARD_TQ
select MCI_IMX_ESDHC_PBL
select IMX8M_DRAM
select I2C_IMX_EARLY
diff --git a/images/Makefile.imx b/images/Makefile.imx
index f66c0af6a4..0699f43fd7 100644
--- a/images/Makefile.imx
+++ b/images/Makefile.imx
@@ -505,7 +505,7 @@ $(call build_imx8m_habv4img, CONFIG_MACH_KARO_QSXP_ML81, start_karo_qsxp_ml81, k
$(call build_imx8m_habv4img, CONFIG_MACH_SKOV_IMX8MP, start_skov_imx8mp, skov-imx8mp/flash-header-skov-imx8mp, skov-imx8mp)
-$(call build_imx8m_habv4img, CONFIG_MACH_TQ_MBA8MPXL, start_tqma8mpxl, tqma8mpxl/flash-header-tqma8mpxl, tqma8mpxl)
+$(call build_imx8m_habv4img, CONFIG_MACH_TQ_MBA8MPXX, start_tqma8mpxx, tqma8mpxx/flash-header-tqma8mpxx, tqma8mpxx)
$(call build_imx8m_habv4img, CONFIG_MACH_POLYHEX_DEBIX, start_polyhex_debix, polyhex-debix/flash-header-polyhex-debix, polyhex-debix)
--
2.47.3
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 3/3] ARM: boards: tqma8mpxx: add no_ecc ram timings
2026-02-13 8:19 [PATCH 0/3] ARM: boards: add support for tqma8mpxs boards Fabian Pflug
2026-02-13 8:19 ` [PATCH 1/3] dts: arm64: freescale: add imx8mp-tqma8mpqs board Fabian Pflug
2026-02-13 8:19 ` [PATCH 2/3] ARM: boards: tqma8mpxl: extend with support for xs Fabian Pflug
@ 2026-02-13 8:19 ` Fabian Pflug
2 siblings, 0 replies; 5+ messages in thread
From: Fabian Pflug @ 2026-02-13 8:19 UTC (permalink / raw)
To: BAREBOX; +Cc: Fabian Pflug
Copied the RAM timings from [1] and [2] into a single file and removed
the duplicates to have a list of RAM-Timings for all known no-ecc
variants of the two boards tqma8mpxs and tqma8mpxl.
Print a warning if ECC is configured, since there seems to be only
inline ECC and no real ECC ram, it could possibly be used as non-ecc
memory, but the user should be warned about it.
Remove compile error for INLINE_ECC, as it it only present in tq-uboot
and not in barebox.
[1] https://github.com/tq-systems/u-boot-tqmaxx/tree/TQM-lf_v2024.04/board/tq/tqma8mpxl
[2] https://github.com/tq-systems/u-boot-tqmaxx/tree/TQM-lf_v2024.04/board/tq/tqma8mpxs
Signed-off-by: Fabian Pflug <f.pflug@pengutronix.de>
---
arch/arm/boards/tqma8mpxx/lowlevel.c | 36 +-
arch/arm/boards/tqma8mpxx/lpddr4-timing.c | 763 +++++++++++++++++++++++++++++-
2 files changed, 780 insertions(+), 19 deletions(-)
diff --git a/arch/arm/boards/tqma8mpxx/lowlevel.c b/arch/arm/boards/tqma8mpxx/lowlevel.c
index 7d8bae9c4d..aa0dec056f 100644
--- a/arch/arm/boards/tqma8mpxx/lowlevel.c
+++ b/arch/arm/boards/tqma8mpxx/lowlevel.c
@@ -31,6 +31,10 @@
MX8MP_PAD_CTL_PUE | \
MX8MP_PAD_CTL_PE)
+
+extern struct dram_timing_info *dram_timings_xs_no_ecc[];
+extern struct dram_timing_info *dram_timings_xl_no_ecc[];
+
static void setup_uart(void *uart, iomux_v3_cfg_t tx_pad, iomux_v3_cfg_t rx_pad)
{
imx8m_early_setup_uart_clock();
@@ -102,6 +106,7 @@ static noinline void tqma8mpxx_start(void)
{
extern char __dtb_z_imx8mp_tqma8mpql_mba8mpxl_start[];
extern char __dtb_z_imx8mp_tqma8mpqs_mba8mpxs_start[];
+ struct dram_timing_info **dram_timings;
struct tq_eeprom *eeprom;
struct pbl_i2c *i2c;
@@ -121,6 +126,7 @@ static noinline void tqma8mpxx_start(void)
/* found xS board */
i2c = tqma_i2c2_init();
boarddata = __dtb_z_imx8mp_tqma8mpqs_mba8mpxs_start;
+ dram_timings = dram_timings_xs_no_ecc;
setup_uart(IOMEM(MX8M_UART3_BASE_ADDR),
MX8MP_PAD_SD1_DATA6__UART3_DCE_TX,
MX8MP_PAD_SD1_DATA7__UART3_DCE_RX);
@@ -131,6 +137,7 @@ static noinline void tqma8mpxx_start(void)
/* found xL board */
boarddata = __dtb_z_imx8mp_tqma8mpql_mba8mpxl_start;
+ dram_timings = dram_timings_xl_no_ecc;
setup_uart(IOMEM(MX8M_UART4_BASE_ADDR),
MX8MP_PAD_UART4_TXD__UART4_DCE_TX,
MX8MP_PAD_UART4_RXD__UART4_DCE_RX);
@@ -138,18 +145,32 @@ static noinline void tqma8mpxx_start(void)
}
if (current_el() == 3) {
- extern struct dram_timing_info dram_timing_2gb_no_ecc;
- int ramsize;
+ unsigned long ramsize;
+ int index = -1;
- ramsize = tq_vard_ramsize(&eeprom->vard) / (SZ_1G);
- if (ramsize != 2)
- panic("RAMsize other then 2GB is not supported at the moment.\n");
+ ramsize = tq_vard_ramsize(&eeprom->vard);
+ switch (ramsize) {
+ case SZ_1G:
+ index = 0;
+ break;
+ case SZ_2G:
+ index = 1;
+ break;
+ case SZ_4G:
+ index = 2;
+ break;
+ case SZ_8G:
+ index = 3;
+ break;
+ default:
+ panic("RAMsize %lu is not supported.\n", ramsize);
+ }
imx8mp_early_clock_init();
pmic_configure(i2c, 0x25, pca9450_cfg, ARRAY_SIZE(pca9450_cfg));
- imx8mp_ddr_init(&dram_timing_2gb_no_ecc, DRAM_TYPE_LPDDR4);
+ imx8mp_ddr_init(dram_timings[index], DRAM_TYPE_LPDDR4);
imx8mp_load_and_start_image_via_tfa();
}
@@ -158,6 +179,9 @@ static noinline void tqma8mpxx_start(void)
printf("Serial: %s\n", eeprom->id);
printf("ID: %s\n", eeprom->serial);
+ if (tq_vard_has_ramecc(&eeprom->vard))
+ pr_err("ECC Configured, but treated as non ECC RAM\n");
+
imx8mp_barebox_entry(boarddata);
}
diff --git a/arch/arm/boards/tqma8mpxx/lpddr4-timing.c b/arch/arm/boards/tqma8mpxx/lpddr4-timing.c
index 85e21bf69d..b97736fbe8 100644
--- a/arch/arm/boards/tqma8mpxx/lpddr4-timing.c
+++ b/arch/arm/boards/tqma8mpxx/lpddr4-timing.c
@@ -4,19 +4,127 @@
*
* Generated code from MX8M_DDR_tool
*
- * Align with uboot version:
- * imx_v2019.04_5.4.x and above version
- * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga:
- * please replace #include <asm/arch/ddr.h> with #include <asm/arch/imx8m_ddr.h>
- *
- * TQMa8MPxL.2GByte.RAM-Timing.0004.xlsx / 2.0 GHz
*/
#include <common.h>
#include <soc/imx8m/ddr.h>
#include <soc/imx8m/lpddr4_define.h>
-static struct dram_cfg_param ddr_ddrc_cfg[] = {
+static struct dram_cfg_param ddr_ddrc_cfg_xx_1gb[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa1080020 },
+ { 0x3d400020, 0x1303 },
+ { 0x3d400024, 0x1e84800 },
+ { 0x3d400064, 0x7a00b4 },
+ { 0x3d400070, 0x7027f90 },
+ { 0x3d400074, 0x790 },
+ { 0x3d4000d0, 0xc00307a3 },
+ { 0x3d4000d4, 0xc50000 },
+ { 0x3d4000dc, 0xf4003f },
+ { 0x3d4000e0, 0x2b0000 },
+ { 0x3d4000e8, 0x550048 },
+ { 0x3d4000ec, 0x150048 },
+ { 0x3d400100, 0x201e222a },
+ { 0x3d400104, 0x8083f },
+ { 0x3d40010c, 0xe0e000 },
+ { 0x3d400110, 0x12040a12 },
+ { 0x3d400114, 0x2050f0f },
+ { 0x3d400118, 0x1010009 },
+ { 0x3d40011c, 0x502 },
+ { 0x3d400130, 0x20800 },
+ { 0x3d400134, 0xe100002 },
+ { 0x3d400138, 0xbc },
+ { 0x3d400144, 0xc80064 },
+ { 0x3d400180, 0x3e8001e },
+ { 0x3d400184, 0x3207a12 },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x49f820e },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x1f0e },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x1 },
+ { 0x3d4000f4, 0x799 },
+ { 0x3d400108, 0x9121b1c },
+ { 0x3d400200, 0x1f },
+ { 0x3d400208, 0x0 },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0xf070707 },
+ { 0x3d40021c, 0xf0f },
+ { 0x3d400250, 0x1705 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x4000030 },
+ { 0x3d400264, 0x900093e7 },
+ { 0x3d40026c, 0x2005574 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400404, 0x72ff },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x2100e07 },
+ { 0x3d400498, 0x620096 },
+ { 0x3d40049c, 0x1100e07 },
+ { 0x3d4004a0, 0xc8012c },
+ { 0x3d402020, 0x1001 },
+ { 0x3d402024, 0x30d400 },
+ { 0x3d402050, 0x20d000 },
+ { 0x3d402064, 0xc0012 },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x2b0000 },
+ { 0x3d4020e8, 0x550048 },
+ { 0x3d4020ec, 0x150048 },
+ { 0x3d402100, 0xa030305 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x302 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0x13 },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0x640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d4020f4, 0x599 },
+ { 0x3d403020, 0x1001 },
+ { 0x3d403024, 0xc3500 },
+ { 0x3d403050, 0x20d000 },
+ { 0x3d403064, 0x30005 },
+ { 0x3d4030dc, 0x840000 },
+ { 0x3d4030e0, 0x2b0000 },
+ { 0x3d4030e8, 0x550048 },
+ { 0x3d4030ec, 0x150048 },
+ { 0x3d403100, 0xa010102 },
+ { 0x3d403104, 0x30404 },
+ { 0x3d403108, 0x203060b },
+ { 0x3d40310c, 0x505000 },
+ { 0x3d403110, 0x2040202 },
+ { 0x3d403114, 0x2030202 },
+ { 0x3d403118, 0x1010004 },
+ { 0x3d40311c, 0x302 },
+ { 0x3d403130, 0x20300 },
+ { 0x3d403134, 0xa100002 },
+ { 0x3d403138, 0x5 },
+ { 0x3d403144, 0x50003 },
+ { 0x3d403180, 0x190004 },
+ { 0x3d403190, 0x3818200 },
+ { 0x3d403194, 0x80303 },
+ { 0x3d4031b4, 0x100 },
+ { 0x3d4030f4, 0x599 },
+ { 0x3d400028, 0x0 },
+};
+
+static struct dram_cfg_param ddr_ddrc_cfg_xl_2gb[] = {
/** Initialize DDRC registers **/
{ 0x3d400304, 0x1 },
{ 0x3d400030, 0x1 },
@@ -129,6 +237,348 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d400028, 0x0 },
};
+static struct dram_cfg_param ddr_ddrc_cfg_xs_2gb[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa1080020 },
+ { 0x3d400020, 0x1303 },
+ { 0x3d400024, 0x1e84800 },
+ { 0x3d400064, 0x7a0118 },
+ { 0x3d400070, 0x7027f90 },
+ { 0x3d400074, 0x790 },
+ { 0x3d4000d0, 0xc00307a3 },
+ { 0x3d4000d4, 0xc50000 },
+ { 0x3d4000dc, 0xf4003f },
+ { 0x3d4000e0, 0x2b0000 },
+ { 0x3d4000e8, 0x550048 },
+ { 0x3d4000ec, 0x150048 },
+ { 0x3d400100, 0x201e222a },
+ { 0x3d400104, 0x8083f },
+ { 0x3d40010c, 0xe0e000 },
+ { 0x3d400110, 0x12040a12 },
+ { 0x3d400114, 0x2050f0f },
+ { 0x3d400118, 0x1010009 },
+ { 0x3d40011c, 0x502 },
+ { 0x3d400130, 0x20800 },
+ { 0x3d400134, 0xe100002 },
+ { 0x3d400138, 0x120 },
+ { 0x3d400144, 0xc80064 },
+ { 0x3d400180, 0x3e8001e },
+ { 0x3d400184, 0x3207a12 },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x49f820e },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x1f0e },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x1 },
+ { 0x3d4000f4, 0x799 },
+ { 0x3d400108, 0x9121b1c },
+ { 0x3d400200, 0x1f },
+ { 0x3d400208, 0x0 },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+ { 0x3d40021c, 0xf0f },
+ { 0x3d400250, 0x1705 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x4000030 },
+ { 0x3d400264, 0x900093e7 },
+ { 0x3d40026c, 0x2005574 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400404, 0x72ff },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x2100e07 },
+ { 0x3d400498, 0x620096 },
+ { 0x3d40049c, 0x1100e07 },
+ { 0x3d4004a0, 0xc8012c },
+ { 0x3d402020, 0x1001 },
+ { 0x3d402024, 0x30d400 },
+ { 0x3d402050, 0x20d000 },
+ { 0x3d402064, 0xc001c },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x2b0000 },
+ { 0x3d4020e8, 0x550048 },
+ { 0x3d4020ec, 0x150048 },
+ { 0x3d402100, 0xa030305 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x302 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0x1d },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0x640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d4020f4, 0x599 },
+ { 0x3d403020, 0x1001 },
+ { 0x3d403024, 0xc3500 },
+ { 0x3d403050, 0x20d000 },
+ { 0x3d403064, 0x30007 },
+ { 0x3d4030dc, 0x840000 },
+ { 0x3d4030e0, 0x2b0000 },
+ { 0x3d4030e8, 0x550048 },
+ { 0x3d4030ec, 0x150048 },
+ { 0x3d403100, 0xa010102 },
+ { 0x3d403104, 0x30404 },
+ { 0x3d403108, 0x203060b },
+ { 0x3d40310c, 0x505000 },
+ { 0x3d403110, 0x2040202 },
+ { 0x3d403114, 0x2030202 },
+ { 0x3d403118, 0x1010004 },
+ { 0x3d40311c, 0x302 },
+ { 0x3d403130, 0x20300 },
+ { 0x3d403134, 0xa100002 },
+ { 0x3d403138, 0x8 },
+ { 0x3d403144, 0x50003 },
+ { 0x3d403180, 0x190004 },
+ { 0x3d403190, 0x3818200 },
+ { 0x3d403194, 0x80303 },
+ { 0x3d4031b4, 0x100 },
+ { 0x3d4030f4, 0x599 },
+ { 0x3d400028, 0x0 },
+};
+
+static struct dram_cfg_param ddr_ddrc_cfg_xx_4gb[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa3080020 },
+ { 0x3d400020, 0x1303 },
+ { 0x3d400024, 0x1e84800 },
+ { 0x3d400064, 0x7a0118 },
+ { 0x3d400070, 0x7027f90 },
+ { 0x3d400074, 0x790 },
+ { 0x3d4000d0, 0xc00307a3 },
+ { 0x3d4000d4, 0xc50000 },
+ { 0x3d4000dc, 0xf4003f },
+ { 0x3d4000e0, 0x2b0000 },
+ { 0x3d4000e8, 0x550048 },
+ { 0x3d4000ec, 0x150048 },
+ { 0x3d400100, 0x201e222a },
+ { 0x3d400104, 0x8083f },
+ { 0x3d40010c, 0xe0e000 },
+ { 0x3d400110, 0x12040a12 },
+ { 0x3d400114, 0x2050f0f },
+ { 0x3d400118, 0x1010009 },
+ { 0x3d40011c, 0x502 },
+ { 0x3d400130, 0x20800 },
+ { 0x3d400134, 0xe100002 },
+ { 0x3d400138, 0x120 },
+ { 0x3d400144, 0xc80064 },
+ { 0x3d400180, 0x3e8001e },
+ { 0x3d400184, 0x3207a12 },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x49f820e },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x1f0e },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x1 },
+ { 0x3d4000f4, 0x799 },
+ { 0x3d400108, 0x9121b1c },
+ { 0x3d400200, 0x17 },
+ { 0x3d400208, 0x0 },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+ { 0x3d40021c, 0xf0f },
+ { 0x3d400250, 0x1705 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x4000030 },
+ { 0x3d400264, 0x900093e7 },
+ { 0x3d40026c, 0x2005574 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400404, 0x72ff },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x2100e07 },
+ { 0x3d400498, 0x620096 },
+ { 0x3d40049c, 0x1100e07 },
+ { 0x3d4004a0, 0xc8012c },
+ { 0x3d402020, 0x1001 },
+ { 0x3d402024, 0x30d400 },
+ { 0x3d402050, 0x20d000 },
+ { 0x3d402064, 0xc001c },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x2b0000 },
+ { 0x3d4020e8, 0x550048 },
+ { 0x3d4020ec, 0x150048 },
+ { 0x3d402100, 0xa030305 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x302 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0x1d },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0x640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d4020f4, 0x599 },
+ { 0x3d403020, 0x1001 },
+ { 0x3d403024, 0xc3500 },
+ { 0x3d403050, 0x20d000 },
+ { 0x3d403064, 0x30007 },
+ { 0x3d4030dc, 0x840000 },
+ { 0x3d4030e0, 0x2b0000 },
+ { 0x3d4030e8, 0x550048 },
+ { 0x3d4030ec, 0x150048 },
+ { 0x3d403100, 0xa010102 },
+ { 0x3d403104, 0x30404 },
+ { 0x3d403108, 0x203060b },
+ { 0x3d40310c, 0x505000 },
+ { 0x3d403110, 0x2040202 },
+ { 0x3d403114, 0x2030202 },
+ { 0x3d403118, 0x1010004 },
+ { 0x3d40311c, 0x302 },
+ { 0x3d403130, 0x20300 },
+ { 0x3d403134, 0xa100002 },
+ { 0x3d403138, 0x8 },
+ { 0x3d403144, 0x50003 },
+ { 0x3d403180, 0x190004 },
+ { 0x3d403190, 0x3818200 },
+ { 0x3d403194, 0x80303 },
+ { 0x3d4031b4, 0x100 },
+ { 0x3d4030f4, 0x599 },
+ { 0x3d400028, 0x0 },
+};
+
+static struct dram_cfg_param ddr_ddrc_cfg_xx_8gb[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa3080020 },
+ { 0x3d400020, 0x1303 },
+ { 0x3d400024, 0x1e84800 },
+ { 0x3d400064, 0x7a017c },
+ { 0x3d400070, 0x7027f90 },
+ { 0x3d400074, 0x790 },
+ { 0x3d4000d0, 0xc00307a3 },
+ { 0x3d4000d4, 0xc50000 },
+ { 0x3d4000dc, 0xf4003f },
+ { 0x3d4000e0, 0x2b0000 },
+ { 0x3d4000e8, 0x550048 },
+ { 0x3d4000ec, 0x150048 },
+ { 0x3d400100, 0x201e222a },
+ { 0x3d400104, 0x8083f },
+ { 0x3d40010c, 0xe0e000 },
+ { 0x3d400110, 0x12040a12 },
+ { 0x3d400114, 0x2050f0f },
+ { 0x3d400118, 0x1010009 },
+ { 0x3d40011c, 0x502 },
+ { 0x3d400130, 0x20800 },
+ { 0x3d400134, 0xe100002 },
+ { 0x3d400138, 0x184 },
+ { 0x3d400144, 0xc80064 },
+ { 0x3d400180, 0x3e8001e },
+ { 0x3d400184, 0x3207a12 },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x49f820e },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x1f0e },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x1 },
+ { 0x3d4000f4, 0x799 },
+ { 0x3d400108, 0x9121b1c },
+ { 0x3d400200, 0x18 },
+ { 0x3d400208, 0x0 },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+ { 0x3d40021c, 0xf07 },
+ { 0x3d400250, 0x1705 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x4000030 },
+ { 0x3d400264, 0x900093e7 },
+ { 0x3d40026c, 0x2005574 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400404, 0x72ff },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x2100e07 },
+ { 0x3d400498, 0x620096 },
+ { 0x3d40049c, 0x1100e07 },
+ { 0x3d4004a0, 0xc8012c },
+ { 0x3d402020, 0x1001 },
+ { 0x3d402024, 0x30d400 },
+ { 0x3d402050, 0x20d000 },
+ { 0x3d402064, 0xc0026 },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x2b0000 },
+ { 0x3d4020e8, 0x550048 },
+ { 0x3d4020ec, 0x150048 },
+ { 0x3d402100, 0xa030305 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x302 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0x27 },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0x640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d4020f4, 0x599 },
+ { 0x3d403020, 0x1001 },
+ { 0x3d403024, 0xc3500 },
+ { 0x3d403050, 0x20d000 },
+ { 0x3d403064, 0x3000a },
+ { 0x3d4030dc, 0x840000 },
+ { 0x3d4030e0, 0x2b0000 },
+ { 0x3d4030e8, 0x550048 },
+ { 0x3d4030ec, 0x150048 },
+ { 0x3d403100, 0xa010102 },
+ { 0x3d403104, 0x30404 },
+ { 0x3d403108, 0x203060b },
+ { 0x3d40310c, 0x505000 },
+ { 0x3d403110, 0x2040202 },
+ { 0x3d403114, 0x2030202 },
+ { 0x3d403118, 0x1010004 },
+ { 0x3d40311c, 0x302 },
+ { 0x3d403130, 0x20300 },
+ { 0x3d403134, 0xa100002 },
+ { 0x3d403138, 0xa },
+ { 0x3d403144, 0x50003 },
+ { 0x3d403180, 0x190004 },
+ { 0x3d403190, 0x3818200 },
+ { 0x3d403194, 0x80303 },
+ { 0x3d4031b4, 0x100 },
+ { 0x3d4030f4, 0x599 },
+ { 0x3d400028, 0x0 },
+};
+
/* PHY Initialize Configuration */
static struct dram_cfg_param ddr_ddrphy_cfg[] = {
{ 0x100a0, 0x0 },
@@ -377,6 +827,44 @@ static struct dram_cfg_param ddr_fsp0_cfg[] = {
{ 0xd0000, 0x1 },
};
+static struct dram_cfg_param ddr_fsp0_4gb_8gb_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xfa0 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x303c },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x3ff4 },
+ { 0x5401a, 0x2b },
+ { 0x5401b, 0x4855 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x15 },
+ { 0x5401f, 0x3ff4 },
+ { 0x54020, 0x2b },
+ { 0x54021, 0x4855 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x15 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0xf400 },
+ { 0x54033, 0x2b3f },
+ { 0x54034, 0x5500 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1500 },
+ { 0x54038, 0xf400 },
+ { 0x54039, 0x2b3f },
+ { 0x5403a, 0x5500 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1500 },
+ { 0xd0000, 0x1 },
+};
+
/* P1 message block paremeter for training firmware */
static struct dram_cfg_param ddr_fsp1_cfg[] = {
{ 0xd0000, 0x0 },
@@ -417,6 +905,45 @@ static struct dram_cfg_param ddr_fsp1_cfg[] = {
{ 0xd0000, 0x1 },
};
+static struct dram_cfg_param ddr_fsp1_4gb_8gb_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x303c },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x2b },
+ { 0x5401b, 0x4855 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x15 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x2b },
+ { 0x54021, 0x4855 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x15 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x2b00 },
+ { 0x54034, 0x5500 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1500 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x2b00 },
+ { 0x5403a, 0x5500 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1500 },
+ { 0xd0000, 0x1 },
+};
+
/* P2 message block paremeter for training firmware */
static struct dram_cfg_param ddr_fsp2_cfg[] = {
{ 0xd0000, 0x0 },
@@ -457,6 +984,45 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = {
{ 0xd0000, 0x1 },
};
+static struct dram_cfg_param ddr_fsp2_4gb_8gb_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x102 },
+ { 0x54003, 0x64 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x303c },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x2b },
+ { 0x5401b, 0x4855 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x15 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x2b },
+ { 0x54021, 0x4855 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x15 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x2b00 },
+ { 0x54034, 0x5500 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1500 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x2b00 },
+ { 0x5403a, 0x5500 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1500 },
+ { 0xd0000, 0x1 },
+};
+
/* P0 2D message block paremeter for training firmware */
static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0xd0000, 0x0 },
@@ -497,6 +1063,45 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0xd0000, 0x1 },
};
+static struct dram_cfg_param ddr_fsp0_2d_4gb_8gb_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xfa0 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x303c },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x3ff4 },
+ { 0x5401a, 0x2b },
+ { 0x5401b, 0x4855 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x15 },
+ { 0x5401f, 0x3ff4 },
+ { 0x54020, 0x2b },
+ { 0x54021, 0x4855 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x15 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0xf400 },
+ { 0x54033, 0x2b3f },
+ { 0x54034, 0x5500 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1500 },
+ { 0x54038, 0xf400 },
+ { 0x54039, 0x2b3f },
+ { 0x5403a, 0x5500 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1500 },
+ { 0xd0000, 0x1 },
+};
+
/* DRAM PHY init engine image */
static struct dram_cfg_param ddr_phy_pie[] = {
{ 0xd0000, 0x0 },
@@ -1113,10 +1718,72 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
},
};
+static struct dram_fsp_msg ddr_dram_fsp_xs_4gb_msg[] = {
+ {
+ /* P0 4000mts 1D */
+ .drate = 4000,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_4gb_8gb_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_4gb_8gb_cfg),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_4gb_8gb_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_4gb_8gb_cfg),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_4gb_8gb_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_4gb_8gb_cfg),
+ },
+ {
+ /* P0 4000mts 2D */
+ .drate = 4000,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_4gb_8gb_msg[] = {
+ {
+ /* P0 4000mts 1D */
+ .drate = 4000,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_4gb_8gb_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_4gb_8gb_cfg),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_4gb_8gb_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_4gb_8gb_cfg),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_4gb_8gb_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_4gb_8gb_cfg),
+ },
+ {
+ /* P0 4000mts 2D */
+ .drate = 4000,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_4gb_8gb_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_4gb_8gb_cfg),
+ },
+};
+
/* ddr timing config params */
-struct dram_timing_info dram_timing_2gb_no_ecc = {
- .ddrc_cfg = ddr_ddrc_cfg,
- .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+struct dram_timing_info dram_timing_xx_1gb_no_ecc = {
+ .ddrc_cfg = ddr_ddrc_cfg_xx_1gb,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_xx_1gb),
.ddrphy_cfg = ddr_ddrphy_cfg,
.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
.fsp_msg = ddr_dram_fsp_msg,
@@ -1126,6 +1793,76 @@ struct dram_timing_info dram_timing_2gb_no_ecc = {
.fsp_table = { 4000, 400, 100, },
};
-#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
-#error
-#endif
+struct dram_timing_info dram_timing_xl_2gb_no_ecc = {
+ .ddrc_cfg = ddr_ddrc_cfg_xl_2gb,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_xl_2gb),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 4000, 400, 100, },
+};
+
+struct dram_timing_info dram_timing_xs_2gb_no_ecc = {
+ .ddrc_cfg = ddr_ddrc_cfg_xs_2gb,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_xs_2gb),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 4000, 400, 100, },
+};
+
+struct dram_timing_info dram_timing_xl_4gb_no_ecc = {
+ .ddrc_cfg = ddr_ddrc_cfg_xx_4gb,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_xx_4gb),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_4gb_8gb_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_4gb_8gb_msg),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 4000, 400, 100, },
+};
+
+struct dram_timing_info dram_timing_xs_4gb_no_ecc = {
+ .ddrc_cfg = ddr_ddrc_cfg_xx_4gb,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_xx_4gb),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_xs_4gb_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_xs_4gb_msg),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 4000, 400, 100, },
+};
+
+struct dram_timing_info dram_timing_xx_8gb_no_ecc = {
+ .ddrc_cfg = ddr_ddrc_cfg_xx_8gb,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_xx_8gb),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_4gb_8gb_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_4gb_8gb_msg),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 4000, 400, 100, },
+};
+
+struct dram_timing_info *dram_timings_xl_no_ecc[] = {
+ &dram_timing_xx_1gb_no_ecc,
+ &dram_timing_xl_2gb_no_ecc,
+ &dram_timing_xl_4gb_no_ecc,
+ &dram_timing_xx_8gb_no_ecc,
+};
+
+struct dram_timing_info *dram_timings_xs_no_ecc[] = {
+ &dram_timing_xx_1gb_no_ecc,
+ &dram_timing_xs_2gb_no_ecc,
+ &dram_timing_xs_4gb_no_ecc,
+ &dram_timing_xx_8gb_no_ecc,
+};
--
2.47.3
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/3] dts: arm64: freescale: add imx8mp-tqma8mpqs board
2026-02-13 8:19 ` [PATCH 1/3] dts: arm64: freescale: add imx8mp-tqma8mpqs board Fabian Pflug
@ 2026-02-13 12:07 ` Ahmad Fatoum
0 siblings, 0 replies; 5+ messages in thread
From: Ahmad Fatoum @ 2026-02-13 12:07 UTC (permalink / raw)
To: Fabian Pflug, BAREBOX
Hello Fabian,
On 2/13/26 9:19 AM, Fabian Pflug wrote:
> The TQMA8MPxS is another board from TQMA with the same processor, but a
> different formfactor. Nevertheless could they share a lot of code.
> This should be replaced with the code from kernel upstream, but I have
> yet to find the correct patch.
>
> Signed-off-by: Fabian Pflug <f.pflug@pengutronix.de>
We do not access patches against dts/ as it's synchronized 1:1 against
the device trees in Linux, see [1].
Please add the DTs to arch/arm/dts instead until they make it upstream.
[1]:
https://www.barebox.org/doc/latest/devicetree/index.html#upstream-device-trees
Thanks,
Ahmad
> ---
> .../freescale/imx8mp-tqma8mpqs-mb-smarc-2.dts | 388 +++++++
> dts/src/arm64/freescale/imx8mp-tqma8mpqs.dtsi | 1066 ++++++++++++++++++++
> 2 files changed, 1454 insertions(+)
>
> diff --git a/dts/src/arm64/freescale/imx8mp-tqma8mpqs-mb-smarc-2.dts b/dts/src/arm64/freescale/imx8mp-tqma8mpqs-mb-smarc-2.dts
> new file mode 100644
> index 0000000000..08e46e325e
> --- /dev/null
> +++ b/dts/src/arm64/freescale/imx8mp-tqma8mpqs-mb-smarc-2.dts
> @@ -0,0 +1,388 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> +/*
> + * Copyright 2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
> + * D-82229 Seefeld, Germany.
> + * Author: Paul Gerber
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/leds/common.h>
> +#include <dt-bindings/phy/phy-imx8-pcie.h>
> +#include "imx8mp-tqma8mpqs.dtsi"
> +
> +/ {
> + model = "TQ-Systems i.MX8MPlus TQMa8MPxS on MB-SMARC-2";
> + compatible = "tq,imx8mp-tqma8mpqs-mb-smarc-2", "tq,imx8mp-tqma8mpqs", "fsl,imx8mp";
> + chassis-type = "embedded";
> +
> + chosen {
> + stdout-path = &uart3;
> + };
> +
> + aliases {
> + ethernet0 = &eqos;
> + ethernet1 = &fec;
> + mmc0 = &usdhc3;
> + mmc1 = &usdhc2;
> + rtc0 = &pcf85063;
> + rtc1 = &snvs_rtc;
> + spi0 = &flexspi;
> + spi1 = &ecspi1;
> + spi2 = &ecspi2;
> + spi3 = &ecspi3;
> + };
> +
> + backlight_lvds0: backlight-lvds0 {
> + compatible = "pwm-backlight";
> + pwms = <&pwm3 0 100000 0>;
> + brightness-levels = <0 4 8 16 32 64 128 255>;
> + default-brightness-level = <7>;
> + enable-gpios = <&expander0 0 GPIO_ACTIVE_HIGH>;
> + power-supply = <®_12v0>;
> + status = "disabled";
> + };
> +
> + backlight_lvds1: backlight-lvds1 {
> + compatible = "pwm-backlight";
> + pwms = <&pwm2 0 100000 0>;
> + brightness-levels = <0 4 8 16 32 64 128 255>;
> + default-brightness-level = <7>;
> + enable-gpios = <&expander0 2 GPIO_ACTIVE_HIGH>;
> + power-supply = <®_12v0>;
> + status = "disabled";
> + };
> +
> + hdmi-connector {
> + compatible = "hdmi-connector";
> + label = "X6";
> + type = "a";
> +
> + port {
> + hdmi_connector_in: endpoint {
> + remote-endpoint = <&hdmi_tx_out>;
> + };
> + };
> + };
> +
> + panel_lvds0: panel-lvds0 {
> + /*
> + * Display is not fixed, so compatible has to be added from
> + * DT overlay
> + */
> + backlight = <&backlight_lvds0>;
> + power-supply = <®_lvds0>;
> + status = "disabled";
> +
> + port {
> + panel_in_lvds0: endpoint {
> + remote-endpoint = <&ldb_lvds_ch0>;
> + };
> + };
> + };
> +
> + panel_lvds1: panel-lvds1 {
> + /*
> + * Display is not fixed, so compatible has to be added from
> + * DT overlay
> + */
> + backlight = <&backlight_lvds1>;
> + power-supply = <®_lvds1>;
> + status = "disabled";
> +
> + port {
> + panel_in_lvds1: endpoint {
> + remote-endpoint = <&ldb_lvds_ch1>;
> + };
> + };
> + };
> +
> + reg_1v8: regulator-1v8 {
> + compatible = "regulator-fixed";
> + regulator-name = "1V8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + reg_3v3: regulator-3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "3V3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + reg_5v0: regulator-5v0 {
> + compatible = "regulator-fixed";
> + regulator-name = "VCC_5V0";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-always-on;
> + };
> +
> + reg_12v0: regulator-12v0 {
> + compatible = "regulator-fixed";
> + regulator-name = "12V0";
> + regulator-min-microvolt = <12000000>;
> + regulator-max-microvolt = <12000000>;
> + regulator-always-on;
> + };
> +
> + reg_lvds0: regulator-lvds0 {
> + compatible = "regulator-fixed";
> + regulator-name = "LCD0_VDD_EN";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + reg_lvds1: regulator-lvds1 {
> + compatible = "regulator-fixed";
> + regulator-name = "LCD1_VDD_EN";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&expander0 3 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + /* global autoconfigured region for contiguous allocations */
> + linux,cma {
> + compatible = "shared-dma-pool";
> + reusable;
> + size = <0 0x38000000>;
> + alloc-ranges = <0 0x40000000 0 0x78000000>;
> + linux,cma-default;
> + };
> + };
> +
> + sound {
> + compatible = "fsl,imx-audio-tlv320aic32x4";
> + model = "tqm-tlv320aic32";
> + audio-asrc = <&easrc>;
> + audio-cpu = <&sai5>;
> + audio-codec = <&tlv320aic3x04>;
> + audio-routing =
> + "IN3_L", "Mic Jack",
> + "Mic Jack", "Mic Bias",
> + "IN1_L", "Line In Jack",
> + "IN1_R", "Line In Jack",
> + "Line Out Jack", "LOL",
> + "Line Out Jack", "LOR";
> + };
> +
> + usb-connector {
> + compatible = "gpio-usb-b-connector", "usb-b-connector";
> + type = "micro";
> + label = "X4";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usbcon0>;
> + id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
> +
> + port {
> + usb_dr_connector: endpoint {
> + remote-endpoint = <&usb3_dwc>;
> + };
> + };
> + };
> +};
> +
> +&dp_bridge {
> + status = "okay";
> +};
> +
> +&easrc {
> + status = "okay";
> +};
> +
> +&ecspi1 {
> + status = "okay";
> +};
> +
> +&eqos {
> + status = "okay";
> +};
> +
> +ðphy0 {
> + leds {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + led@1 {
> + reg = <1>;
> + color = <LED_COLOR_ID_GREEN>;
> + function = LED_FUNCTION_LAN;
> + function-enumerator = <0>;
> + default-state = "keep";
> + };
> +
> + led@2 {
> + reg = <2>;
> + color = <LED_COLOR_ID_AMBER>;
> + function = LED_FUNCTION_LAN;
> + function-enumerator = <0>;
> + default-state = "keep";
> + };
> + };
> +};
> +
> +ðphy3 {
> + leds {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + led@1 {
> + reg = <1>;
> + color = <LED_COLOR_ID_GREEN>;
> + function = LED_FUNCTION_LAN;
> + function-enumerator = <0>;
> + default-state = "keep";
> + };
> +
> + led@2 {
> + reg = <2>;
> + color = <LED_COLOR_ID_AMBER>;
> + function = LED_FUNCTION_LAN;
> + function-enumerator = <0>;
> + default-state = "keep";
> + };
> + };
> +};
> +
> +&fec {
> + status = "okay";
> +};
> +
> +&flexcan1 {
> + xceiver-supply = <®_3v3>;
> + status = "okay";
> +};
> +
> +&flexcan2 {
> + xceiver-supply = <®_3v3>;
> + status = "okay";
> +};
> +
> +&hdmi_pvi {
> + status = "okay";
> +};
> +
> +&hdmi_tx {
> + status = "okay";
> +
> + ports {
> + port@1 {
> + hdmi_tx_out: endpoint {
> + remote-endpoint = <&hdmi_connector_in>;
> + };
> + };
> + };
> +};
> +
> +&hdmi_tx_phy {
> + status = "okay";
> +};
> +
> +&i2c1 {
> + tlv320aic3x04: audio-codec@18 {
> + compatible = "ti,tlv320aic32x4";
> + reg = <0x18>;
> + clock-names = "mclk";
> + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>;
> + iov-supply = <®_1v8>;
> + ldoin-supply = <®_3v3>;
> + };
> +};
> +
> +&ldb_lvds_ch0 {
> + remote-endpoint = <&panel_in_lvds0>;
> +};
> +
> +&ldb_lvds_ch1 {
> + remote-endpoint = <&panel_in_lvds1>;
> +};
> +
> +&lcdif1 {
> + status = "okay";
> +};
> +
> +&lcdif3 {
> + status = "okay";
> +};
> +
> +&mipi_dsi {
> + status = "okay";
> +};
> +
> +&pcie_phy {
> + fsl,clkreq-unsupported;
> + status = "okay";
> +};
> +
> +&pcie {
> + status = "okay";
> +};
> +
> +®_sdvmmc {
> + startup-delay-us = <100>;
> + off-on-delay-us = <12000>;
> + status = "okay";
> +};
> +
> +&sai3 {
> + status = "okay";
> +};
> +
> +&sai5 {
> + status = "okay";
> +};
> +
> +&snvs_pwrkey {
> + status = "okay";
> +};
> +
> +&uart1 {
> + status = "okay";
> +};
> +
> +&uart2 {
> + status = "okay";
> +};
> +
> +&uart4 {
> + status = "okay";
> +};
> +
> +&usb3_0 {
> + status = "okay";
> +};
> +
> +&usb_dwc3_0 {
> + status = "okay";
> +
> + port {
> + usb3_dwc: endpoint {
> + remote-endpoint = <&usb_dr_connector>;
> + };
> + };
> +};
> +
> +&usdhc2 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
> + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
> + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
> + wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
> + vmmc-supply = <®_sdvmmc>;
> + no-mmc;
> + no-sdio;
> + bus-width = <4>;
> + status = "okay";
> +};
> diff --git a/dts/src/arm64/freescale/imx8mp-tqma8mpqs.dtsi b/dts/src/arm64/freescale/imx8mp-tqma8mpqs.dtsi
> new file mode 100644
> index 0000000000..5cc568404d
> --- /dev/null
> +++ b/dts/src/arm64/freescale/imx8mp-tqma8mpqs.dtsi
> @@ -0,0 +1,1066 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> +/*
> + * Copyright 2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
> + * D-82229 Seefeld, Germany.
> + * Author: Paul Gerber
> + */
> +
> +#include <dt-bindings/net/ti-dp83867.h>
> +#include "imx8mp.dtsi"
> +
> +/ {
> + model = "TQ-Systems i.MX8MPlus TQMa8MPxS";
> + compatible = "tq,imx8mp-tqma8mpqs", "fsl,imx8mp";
> +
> + clk_dp: clk-dp {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <26000000>;
> + };
> +
> + clk_xtal25: clk-xtal25 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <25000000>;
> + };
> +
> + memory@40000000 {
> + device_type = "memory";
> + reg = <0x0 0x40000000 0 0x80000000>;
> + };
> +
> + reg_sdvmmc: regulator-sdvmmc {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_sdvmmc>;
> + regulator-name = "SDIO_PWR_EN";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + vin-supply = <&ldo5>;
> + status = "disabled";
> + };
> +};
> +
> +&A53_0 {
> + cpu-supply = <&buck2>;
> +};
> +
> +&ecspi1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ecspi1>;
> + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, <&gpio5 12 GPIO_ACTIVE_LOW>;
> +};
> +
> +/* GBE0 */
> +&eqos {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_eqos>;
> + phy-mode = "rgmii-id";
> + phy-handle = <ðphy0>;
> +
> + mdio {
> + compatible = "snps,dwmac-mdio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy0: ethernet-phy@0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_eqos_phy>;
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0>;
> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
> + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
> + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> + ti,dp83867-rxctrl-strap-quirk;
> + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
> + reset-gpios = <&expander0 6 GPIO_ACTIVE_LOW>;
> + reset-assert-us = <500000>;
> + reset-deassert-us = <50000>;
> + enet-phy-lane-no-swap;
> + interrupt-parent = <&gpio2>;
> + interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
> + };
> +
> + ethphy3: ethernet-phy@3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_fec_phy>;
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <3>;
> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
> + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
> + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> + ti,dp83867-rxctrl-strap-quirk;
> + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
> + reset-gpios = <&expander0 7 GPIO_ACTIVE_LOW>;
> + reset-assert-us = <500000>;
> + reset-deassert-us = <50000>;
> + enet-phy-lane-no-swap;
> + interrupt-parent = <&gpio2>;
> + interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
> + };
> + };
> +};
> +
> +/* GBE1 */
> +&fec {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_fec>;
> + phy-mode = "rgmii-id";
> + phy-handle = <ðphy3>;
> + fsl,magic-packet;
> +};
> +
> +&flexcan1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan1>;
> +};
> +
> +&flexcan2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan2>;
> +};
> +
> +&flexspi {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexspi0>;
> + status = "okay";
> +
> + flash0: flash@0 {
> + reg = <0>;
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <66666666>;
> + spi-tx-bus-width = <4>;
> + spi-rx-bus-width = <4>;
> +
> + partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + };
> + };
> +};
> +
> +&gpio1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpio1>;
> +
> + gpio-line-names = "SLEEP", "BATLOW#", "", "LID",
> + "", "GPIO10", "CHARGING#", "CHG_PRSNT#",
> + "PMIC_IRQ#", "ESPI_CS1_ALERT#", "USB1_OTG_ID", "USB2_OTG_ID",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "";
> +
> + pmic_irq_hog: pmic-irq-hog {
> + gpio-hog;
> + gpios = <8 0>;
> + input;
> + line-name = "PMIC_IRQ#";
> + };
> +};
> +
> +&gpio2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_hoggpio2>;
> +
> + gpio-line-names = "", "", "", "",
> + "", "", "", "",
> + "", "", "PERST#", "PEWAKE#",
> + "SDIO_CD#", "", "", "",
> + "", "", "", "SDIO_PWR_EN",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "";
> +
> + enet0-int-hog {
> + gpio-hog;
> + gpios = <0 0>;
> + input;
> + line-name = "ENET0_INT#";
> + };
> +
> + enet1-int-hog {
> + gpio-hog;
> + gpios = <1 0>;
> + input;
> + line-name = "ENET_INT#";
> + };
> +
> + perst-hog {
> + gpio-hog;
> + gpios = <10 0>;
> + output-high;
> + line-name = "PERST#";
> + };
> +
> + pewake-hog {
> + gpio-hog;
> + gpios = <11 0>;
> + input;
> + line-name = "PEWAKE#";
> + };
> +
> + rtc-int-hog {
> + gpio-hog;
> + gpios = <27 0>;
> + input;
> + line-name = "RTC_INT#";
> + };
> +};
> +
> +&gpio3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpio3>;
> +
> + gpio-line-names = "", "", "", "",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "GPIO4",
> + "GPIO3", "", "", "",
> + "", "", "", "",
> + "TEMP_EVENT#", "", "", "";
> +
> + temp-event--hog {
> + gpio-hog;
> + gpios = <28 0>;
> + input;
> + line-name = "TEMP_EVENT#";
> + };
> +};
> +
> +&gpio4 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpio4>, <&pinctrl_sdp>, <&pinctrl_eepromwp>;
> +
> + gpio-line-names = "", "GPIO8", "", "",
> + "GPIO9", "ESPI_RST#", "", "",
> + "", "", "", "",
> + "", "", "GBE0_SDP_DIR", "",
> + "GPIO7", "", "", "",
> + "", "", "", "",
> + "", "GPIO0", "GPIO1", "",
> + "GPIO2", "GPIO6", "", "";
> +
> + /* EEPROM write control */
> + sw_en_hog: sw-en-hog {
> + gpio-hog;
> + gpios = <5 0>;
> + output-high;
> + line-name = "SW_EN";
> + };
> +};
> +
> +&gpio5 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpio5>;
> +
> + gpio-line-names = "", "", "", "",
> + "", "GPIO5", "", "",
> + "", "", "GPIO12", "GPIO11",
> + "", "GPIO13", "", "",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "",
> + "", "", "", "";
> +
> + dp-hpd-int-hog {
> + gpio-hog;
> + gpios = <21 0>;
> + input;
> + line-name = "DP_HPD_INT";
> + };
> +};
> +
> +&hdmi_tx {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_hdmi>;
> +};
> +
> +&i2c1 {
> + clock-frequency = <384000>;
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&pinctrl_i2c1>;
> + pinctrl-1 = <&pinctrl_i2c1_gpio>;
> + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + status = "okay";
> +
> + eeprom0: eeprom@50 {
> + compatible = "atmel,24c64";
> + reg = <0x50>;
> + pagesize = <32>;
> + read-only;
> + vcc-supply = <&buck5>;
> + };
> +
> + pcf85063: rtc@51 {
> + compatible = "nxp,pcf85063a";
> + reg = <0x51>;
> + quartz-load-femtofarads = <7000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pcf85063>;
> + interrupt-parent = <&gpio2>;
> + interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
> + };
> +
> + eeprom1: eeprom@54 {
> + compatible = "atmel,24c64";
> + reg = <0x54>;
> + pagesize = <32>;
> + vcc-supply = <&buck5>;
> + };
> +
> + /* protectable identification memory (part of M24C64-D @50) */
> + eeprom@58 {
> + compatible = "atmel,24c64d-wl";
> + reg = <0x58>;
> + size = <32>;
> + pagesize = <32>;
> + vcc-supply = <&buck5>;
> + };
> +
> + /* protectable identification memory (part of M24C64-D @54) */
> + eeprom@5c {
> + compatible = "atmel,24c64d-wl";
> + reg = <0x5c>;
> + size = <32>;
> + pagesize = <32>;
> + vcc-supply = <&buck5>;
> + };
> +
> + pcieclk: clock-generator@6a {
> + compatible = "renesas,9fgv0241";
> + reg = <0x6a>;
> + clocks = <&clk_xtal25>;
> + #clock-cells = <1>;
> + };
> +
> + imu@6b {
> + compatible = "st,ism330dhcx";
> + reg = <0x6b>;
> + vdd-supply = <&buck4>;
> + vddio-supply = <&buck4>;
> + };
> +};
> +
> +&i2c2 {
> + clock-frequency = <384000>;
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&pinctrl_i2c2>;
> + pinctrl-1 = <&pinctrl_i2c2_gpio>;
> + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + status = "okay";
> +
> + pmic: pmic@25 {
> + reg = <0x25>;
> + compatible = "nxp,pca9450c";
> +
> + /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pmic>;
> + interrupt-parent = <&gpio1>;
> + interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
> +
> + regulators {
> + /* V_0V85_SOC: 0.85 .. 0.95 */
> + buck1: BUCK1 {
> + regulator-name = "BUCK1";
> + regulator-min-microvolt = <850000>;
> + regulator-max-microvolt = <950000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <3125>;
> + };
> +
> + /* VDD_ARM */
> + buck2: BUCK2 {
> + regulator-name = "BUCK2";
> + regulator-min-microvolt = <850000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-boot-on;
> + regulator-always-on;
> + nxp,dvs-run-voltage = <950000>;
> + nxp,dvs-standby-voltage = <850000>;
> + regulator-ramp-delay = <3125>;
> + };
> +
> + /* VCC3V3 -> VMMC, ... must not be changed */
> + buck4: BUCK4 {
> + regulator-name = "BUCK4";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */
> + buck5: BUCK5 {
> + regulator-name = "BUCK5";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + /* V_1V1 -> RAM, ... must not be changed */
> + buck6: BUCK6 {
> + regulator-name = "BUCK6";
> + regulator-min-microvolt = <1100000>;
> + regulator-max-microvolt = <1100000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + /* V_1V8_SNVS */
> + ldo1: LDO1 {
> + regulator-name = "LDO1";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + /* V_1V8_ANA */
> + ldo3: LDO3 {
> + regulator-name = "LDO3";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + /* unused */
> + ldo4: LDO4 {
> + regulator-name = "LDO4";
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + /* VCC SD IO - switched using SD2 VSELECT */
> + ldo5: LDO5 {
> + regulator-name = "LDO5";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + };
> + };
> + };
> +
> + tmp1075: temperature-sensor@4a {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_tmp1075>;
> + compatible = "ti,tmp1075";
> + reg = <0x4a>;
> + vs-supply = <&buck4>;
> + };
> +
> + expander0: gpio@73 {
> + compatible = "nxp,pca9538";
> + reg = <0x73>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + vcc-supply = <&buck5>;
> + gpio-line-names = "LCD0_BKLT_EN", "LCD0_VDD_EN",
> + "LCD1_BKLT_EN", "LCD1_VDD_EN",
> + "DP_BRIDGE_EN", "HUB_RST#",
> + "ENET0_RESET#", "ENET1_RESET#";
> + };
> +};
> +
> +&i2c3 {
> + clock-frequency = <384000>;
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&pinctrl_i2c3>;
> + pinctrl-1 = <&pinctrl_i2c3_gpio>;
> + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + status = "okay";
> +
> + dp_bridge: dp-bridge@f {
> + compatible = "toshiba,tc9595", "toshiba,tc358767";
> + reg = <0xf>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_tc9595>;
> + clock-names = "ref";
> + clocks = <&clk_dp>;
> + reset-gpios = <&expander0 4 GPIO_ACTIVE_HIGH>;
> + toshiba,hpd-pin = <0>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + dsi_in: endpoint {
> + remote-endpoint = <&dsi_out>;
> + data-lanes = <1 2 3 4>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> +
> + endpoint {
> + toshiba,pre-emphasis = /bits/ 8 <1 1>;
> + };
> + };
> + };
> + };
> +};
> +
> +&i2c4 {
> + clock-frequency = <384000>;
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&pinctrl_i2c4>;
> + pinctrl-1 = <&pinctrl_i2c4_gpio>;
> + scl-gpios = <&gpio2 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio2 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + status = "okay";
> +};
> +
> +&i2c6 {
> + clock-frequency = <384000>;
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&pinctrl_i2c6>;
> + pinctrl-1 = <&pinctrl_i2c6_gpio>;
> + scl-gpios = <&gpio2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio2 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + status = "okay";
> +};
> +
> +&mipi_dsi {
> + samsung,burst-clock-frequency = <1000000000>;
> + samsung,esc-clock-frequency = <10000000>;
> +
> + ports {
> + port@1 {
> + reg = <1>;
> +
> + dsi_out: endpoint {
> + remote-endpoint = <&dsi_in>;
> + data-lanes = <1 2 3 4>;
> + };
> + };
> + };
> +};
> +
> +&pcie_phy {
> + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
> + clock-names = "ref";
> + clocks = <&pcieclk 0>;
> +};
> +
> +&pcie {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pcie>;
> + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
> + <&clk IMX8MP_CLK_HSIO_AXI>,
> + <&clk IMX8MP_CLK_PCIE_ROOT>;
> + clock-names = "pcie", "pcie_bus", "pcie_aux";
> + assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
> + assigned-clock-rates = <10000000>;
> + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
> +};
> +
> +&pwm2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm2>;
> +};
> +
> +&pwm3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm3>;
> +};
> +
> +&sai3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_sai3>;
> + assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
> + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
> + assigned-clock-rates = <12288000>;
> +};
> +
> +&sai5 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_sai5>;
> + assigned-clocks = <&clk IMX8MP_CLK_SAI5>;
> + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
> + assigned-clock-rates = <12288000>;
> + fsl,sai-mclk-direction-output;
> +};
> +
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1>;
> + assigned-clocks = <&clk IMX8MP_CLK_UART1>;
> + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
> + uart-has-rtscts;
> +};
> +
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart2>;
> + assigned-clocks = <&clk IMX8MP_CLK_UART2>;
> + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
> + rts-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
> + cts-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
> +};
> +
> +&uart3 {
> + /* console */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart3>;
> + status = "okay";
> +};
> +
> +&uart4 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart4>;
> + assigned-clocks = <&clk IMX8MP_CLK_UART4>;
> + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
> +};
> +
> +&usb3_phy0 {
> + vbus-supply = <®_5v0>;
> + status = "okay";
> +};
> +
> +&usb3_phy1 {
> + vbus-supply = <®_5v0>;
> + status = "okay";
> +};
> +
> +&usb3_0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usb0>;
> + fsl,over-current-active-low;
> + maximum-speed = "high-speed";
> +};
> +
> +&usb3_1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usb1>;
> + fsl,over-current-active-low;
> + status = "okay";
> +};
> +
> +&usb_dwc3_0 {
> + /* dual role is implemented, but not a full featured OTG */
> + hnp-disable;
> + srp-disable;
> + adp-disable;
> + maximum-speed = "high-speed";
> + dr_mode = "otg";
> + usb-role-switch;
> + role-switch-default-mode = "peripheral";
> +};
> +
> +&usb_dwc3_1 {
> + dr_mode = "host";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "okay";
> +
> + hub_2_0: hub@1 {
> + compatible = "usb451,8142";
> + reg = <1>;
> + peer-hub = <&hub_3_0>;
> + reset-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;
> + vdd-supply = <®_3v3>;
> + };
> +
> + hub_3_0: hub@2 {
> + compatible = "usb451,8140";
> + reg = <2>;
> + peer-hub = <&hub_2_0>;
> + reset-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;
> + vdd-supply = <®_3v3>;
> + };
> +};
> +
> +&usdhc3 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc3>;
> + pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
> + pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
> + bus-width = <8>;
> + non-removable;
> + no-sdio;
> + no-sd;
> + vmmc-supply = <&buck4>;
> + vqmmc-supply = <&buck5>;
> + status = "okay";
> +};
> +
> +&wdog1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_wdog>;
> + fsl,ext-reset-output;
> + status = "okay";
> +};
> +
> +&iomuxc {
> + pinctrl_ecspi1: ecspi1grp {
> + fsl,pins = <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c0>,
> + <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x1c0>,
> + <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x1c0>,
> + <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c0>,
> + <MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x1c0>;
> + };
> +
> + pinctrl_eepromwp: eepromwpgrp {
> + fsl,pins = <MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x00000144>;
> + };
> +
> + pinctrl_eqos: eqosgrp {
> + fsl,pins = <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x40000044>,
> + <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x40000044>,
> + <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90>,
> + <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90>,
> + <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90>,
> + <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90>,
> + <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90>,
> + <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90>,
> + <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12>,
> + <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12>,
> + <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12>,
> + <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12>,
> + <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12>,
> + <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x14>;
> + };
> +
> + pinctrl_eqos_event: eqosevtgrp {
> + fsl,pins = <MX8MP_IOMUXC_SAI2_MCLK__ENET_QOS_1588_EVENT3_IN 0x100>,
> + <MX8MP_IOMUXC_SAI2_TXFS__ENET_QOS_1588_EVENT3_OUT 0x1c0>;
> + };
> +
> + pinctrl_eqos_phy: eqosphygrp {
> + fsl,pins = <MX8MP_IOMUXC_SD1_CLK__GPIO2_IO00 0x1c0>;
> + };
> +
> + pinctrl_fec: fecgrp {
> + fsl,pins = <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90>,
> + <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90>,
> + <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90>,
> + <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90>,
> + <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90>,
> + <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90>,
> + <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12>,
> + <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12>,
> + <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x12>,
> + <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x12>,
> + <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x12>,
> + <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14>;
> + };
> +
> + pinctrl_fec_event: fecevtgrp {
> + fsl,pins = <MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT 0x100>,
> + <MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x1c0>;
> + };
> +
> + pinctrl_fec_phy: fecphygrp {
> + fsl,pins = <MX8MP_IOMUXC_SD1_CMD__GPIO2_IO01 0x1c0>;
> + };
> +
> + pinctrl_flexcan1: flexcan1grp {
> + fsl,pins = <MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x150>,
> + <MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x150>;
> + };
> +
> + pinctrl_flexcan2: flexcan2grp {
> + fsl,pins = <MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x150>,
> + <MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x150>;
> + };
> +
> + pinctrl_flexspi0: flexspi0grp {
> + fsl,pins = <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x142>,
> + <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82>,
> + <MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x40000010>,
> + <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82>,
> + <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82>,
> + <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82>,
> + <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82>;
> + };
> +
> + pinctrl_sdp: gbegrp {
> + fsl,pins = <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x10>,
> + <MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x10>;
> + };
> +
> + pinctrl_gpio1: gpio1grp {
> + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x10>,
> + <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x10>,
> + <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x10>,
> + <MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x10>,
> + <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x10>,
> + <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x80>,
> + <MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x80>;
> + };
> +
> + pinctrl_gpio3: gpio3grp {
> + fsl,pins = <MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x10>,
> + <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x10>;
> + };
> +
> + pinctrl_gpio4: gpio4grp {
> + fsl,pins = <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x10>,
> + <MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x10>,
> + <MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x10>,
> + <MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10>,
> + <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x10>,
> + <MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x10>,
> + <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x10>,
> + <MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x10>;
> + };
> +
> + pinctrl_gpio5: gpio5grp {
> + fsl,pins = <MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x10>,
> + <MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10 0x10>,
> + <MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x10>,
> + <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x10>;
> + };
> +
> + pinctrl_hdmi: hdmigrp {
> + fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c2>,
> + <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c2>,
> + <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010>;
> + };
> +
> + pinctrl_hoggpio2: hoggpio2grp {
> + fsl,pins = <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x140>;
> + };
> +
> + pinctrl_i2c1: i2c1grp {
> + fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001e2>,
> + <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001e2>;
> + };
> +
> + pinctrl_i2c1_gpio: i2c1-gpiogrp {
> + fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001e2>,
> + <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001e2>;
> + };
> +
> + pinctrl_i2c2: i2c2grp {
> + fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001e2>,
> + <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001e2>;
> + };
> +
> + pinctrl_i2c2_gpio: i2c2-gpiogrp {
> + fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001e2>,
> + <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001e2>;
> + };
> +
> + pinctrl_i2c3: i2c3grp {
> + fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001e2>,
> + <MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001e2>;
> + };
> +
> + pinctrl_i2c3_gpio: i2c3-gpiogrp {
> + fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001e2>,
> + <MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001e2>;
> + };
> +
> + pinctrl_i2c4: i2c4grp {
> + fsl,pins = <MX8MP_IOMUXC_SD1_DATA2__I2C4_SCL 0x400001e2>,
> + <MX8MP_IOMUXC_SD1_DATA3__I2C4_SDA 0x400001e2>;
> + };
> +
> + pinctrl_i2c4_gpio: i2c4-gpiogrp {
> + fsl,pins = <MX8MP_IOMUXC_SD1_DATA2__GPIO2_IO04 0x400001e2>,
> + <MX8MP_IOMUXC_SD1_DATA3__GPIO2_IO05 0x400001e2>;
> + };
> +
> + pinctrl_i2c6: i2c6grp {
> + fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 0x400001e2>,
> + <MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 0x400001e2>;
> + };
> +
> + pinctrl_i2c6_gpio: i2c6-gpiogrp {
> + fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x400001e2>,
> + <MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x400001e2>;
> + };
> +
> + pinctrl_pcf85063: pcf85063grp {
> + fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x80>;
> + };
> +
> + pinctrl_pcie: pciegrp {
> + fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x60>,
> + <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x94>;
> + };
> +
> + pinctrl_pmic: pmicirqgrp {
> + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x1c0>;
> + };
> +
> + pinctrl_pwm2: pwm2grp {
> + fsl,pins = <MX8MP_IOMUXC_SPDIF_RX__PWM2_OUT 0x14>;
> + };
> +
> + pinctrl_pwm3: pwm3grp {
> + fsl,pins = <MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x14>;
> + };
> +
> + pinctrl_sai3: sai3grp {
> + fsl,pins = <
> + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x94
> + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x94
> + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x94
> + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x94
> + >;
> + };
> +
> + pinctrl_sai5: sai5grp {
> + fsl,pins = <
> + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI5_MCLK 0x94
> + MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 0x94
> + MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00 0x94
> + MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_TX_SYNC 0x94
> + MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI5_TX_BCLK 0x94
> + >;
> + };
> +
> + pinctrl_sdvmmc: sdvmmcgrp {
> + fsl,pins = <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x10>;
> + };
> +
> + pinctrl_tc9595: tc9595grp {
> + fsl,pins = <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x10>;
> + };
> +
> + pinctrl_tmp1075: tmp1075grp {
> + fsl,pins = <MX8MP_IOMUXC_HDMI_CEC__GPIO3_IO28 0x140>;
> + };
> +
> + /* DCE configuration */
> + pinctrl_uart1: uart1grp {
> + fsl,pins = <MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140>,
> + <MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140>,
> + <MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140>,
> + <MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140>;
> + };
> +
> + /* DCE configuration */
> + pinctrl_uart2: uart2grp {
> + fsl,pins = <MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140>,
> + <MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140>,
> + <MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x140>,
> + <MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x140>;
> + };
> +
> + pinctrl_uart3: uart3grp {
> + fsl,pins = <MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x140>,
> + <MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x140>;
> + };
> +
> + pinctrl_uart4: uart4grp {
> + fsl,pins = <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140>,
> + <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140>;
> + };
> +
> + pinctrl_usb0: usb0grp {
> + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x1c0>,
> + <MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x1c0>;
> + };
> +
> + pinctrl_usb1: usb1grp {
> + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x1c0>,
> + <MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x1c0>;
> + };
> +
> + pinctrl_usbcon0: usb0congrp {
> + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c0>;
> + };
> +
> + pinctrl_usdhc2: usdhc2grp {
> + fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x192>,
> + <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d2>,
> + <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2>,
> + <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2>,
> + <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2>,
> + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>,
> + <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
> + };
> +
> + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
> + fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>,
> + <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>,
> + <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
> + <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
> + <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
> + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>,
> + <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
> + };
> +
> + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
> + fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>,
> + <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>,
> + <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
> + <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
> + <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
> + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>,
> + <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
> + };
> +
> + pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
> + fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c0>,
> + <MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x1c0>;
> + };
> +
> + pinctrl_usdhc3: usdhc3grp {
> + fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>,
> + <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>,
> + <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>,
> + <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>,
> + <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>,
> + <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>,
> + <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>,
> + <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>,
> + <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>,
> + <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>,
> + <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x84>,
> + <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x84>;
> + };
> +
> + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
> + fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>,
> + <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>,
> + <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>,
> + <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>,
> + <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>,
> + <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>,
> + <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>,
> + <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>,
> + <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>,
> + <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>,
> + <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x84>,
> + <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x84>;
> + };
> +
> + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
> + fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>,
> + <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>,
> + <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>,
> + <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>,
> + <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>,
> + <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>,
> + <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>,
> + <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>,
> + <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>,
> + <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>,
> + <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x84>,
> + <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x84>;
> + };
> +
> + pinctrl_wdog: wdoggrp {
> + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x1c4>;
> + };
> +};
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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2026-02-13 8:19 [PATCH 0/3] ARM: boards: add support for tqma8mpxs boards Fabian Pflug
2026-02-13 8:19 ` [PATCH 1/3] dts: arm64: freescale: add imx8mp-tqma8mpqs board Fabian Pflug
2026-02-13 12:07 ` Ahmad Fatoum
2026-02-13 8:19 ` [PATCH 2/3] ARM: boards: tqma8mpxl: extend with support for xs Fabian Pflug
2026-02-13 8:19 ` [PATCH 3/3] ARM: boards: tqma8mpxx: add no_ecc ram timings Fabian Pflug
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