[PATCH 0/4] ARM: i.MX8: add DDRC-ECC support

[Steffen Trumtrar <s.trumtrar@pengutronix.de>]

The i.MX8 DDRC controller supports using inline ECC with the DDR RAM.
Inline ECC reduces the usable RAM size by 1/8: 7/8 RAM is for data and
1/8 RAM is for the ECC bits. Also, measuring random memory writes in
linux with

    stress-ng --memthrash 4 --memthrash-method chunk1 -t 1m --metrics

shows a performance decrease by ~10%.

If a board wants to support ECC, the lpddr4 RAM settings in the
according lpddr4-timing-* must be adapted to enable and configure the
ECC registers.
Also, a board_dram_ecc_scrub() function must be provided, so that the
RAM is initialized on startup.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
David Jander (3):
      arm: mach-imx: esdctl.c: Add support for imx8mp inline ECC
      drivers: ddr: imx8m: ddr_init.c: support ECC scrubbing
      arm: boards: protonic-imx8ml: Add ECC + scrubbing

Steffen Trumtrar (1):
      ARM: i.MX: esdctl: fix spelling of ad(d)ress

 .../boards/protonic-imx8m/lpddr4-timing-prt8ml.c   | 25 ++++++-
 arch/arm/dts/imx8mp-prt8ml.dts                     | 10 ++-
 arch/arm/mach-imx/Kconfig                          |  8 ++
 arch/arm/mach-imx/esdctl.c                         | 86 ++++++++++++++++++++--
 drivers/ddr/imx/imx8m_ddr_init.c                   | 73 ++++++++++++++++++
 include/soc/imx8m/ddr.h                            | 11 +++
 6 files changed, 203 insertions(+), 10 deletions(-)
---
base-commit: f4122cb473bf8ca2d3d84cf7cd3c981d1da3309f
change-id: 20260304-v2026-02-0-topic-imx8-ecc-9206fee1f037

Best regards,
-- 
Steffen Trumtrar <s.trumtrar@pengutronix.de>