[PATCH 4/4] arm: boards: protonic-imx8ml: Add ECC + scrubbing

[Steffen Trumtrar <s.trumtrar@pengutronix.de>]

From: David Jander <david@protonic.nl>

Enable ECC settings in DDRC and add inline ECC scrub on the 3 memory
regions.
The scrubbing is a simpler version than the one generated with
mscale_ddr_tool from NXP. This is much faster and seems to work equally
well.
Documentation of this procedure is nowhere to be found unfortunately, so
proving that it is correct is impossible beyond simply testing it.

Start up time increases by ~800ms with ECC scrubbing enabled.

Signed-off-by: David Jander <david@protonic.nl>
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
 .../boards/protonic-imx8m/lpddr4-timing-prt8ml.c   | 25 +++++++++++++++++++++-
 arch/arm/dts/imx8mp-prt8ml.dts                     | 10 ++++++++-
 2 files changed, 33 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boards/protonic-imx8m/lpddr4-timing-prt8ml.c b/arch/arm/boards/protonic-imx8m/lpddr4-timing-prt8ml.c
index 913db8786f..550641b462 100644
--- a/arch/arm/boards/protonic-imx8m/lpddr4-timing-prt8ml.c
+++ b/arch/arm/boards/protonic-imx8m/lpddr4-timing-prt8ml.c
@@ -15,6 +15,12 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d400020, 0x1303 },
 	{ 0x3d400024, 0x1e84800 },
 	{ 0x3d400064, 0x7a017c },
+#ifdef CONFIG_IMX8MP_DRAM_ECC
+	{ 0x3d400070, 0x01027f54 },
+#else
+	{ 0x3d400070, 0x01027f10 },
+#endif
+	{ 0x3d400074, 0x000007b0 },
 	{ 0x3d4000d0, 0xc00307a3 },
 	{ 0x3d4000d4, 0xc50000 },
 	{ 0x3d4000dc, 0xf4003f },
@@ -47,12 +53,21 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
 
 	{ 0x3d4000f4, 0xc99 },
 	{ 0x3d400108, 0x9121c1c },
+#ifdef CONFIG_IMX8MP_DRAM_ECC
+	{ 0x3d400200, 0x13 },
+	{ 0x3d400204, 0x00050505 },
+	{ 0x3d40020c, 0x13131300 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400214, 0x04040404 },
+	{ 0x3d400218, 0x68040404 },
+#else
 	{ 0x3d400200, 0x16 },
 	{ 0x3d40020c, 0x0 },
-	{ 0x3d400210, 0x1f1f },
 	{ 0x3d400204, 0x80808 },
+	{ 0x3d400210, 0x1f1f },
 	{ 0x3d400214, 0x7070707 },
 	{ 0x3d400218, 0x68070707 },
+#endif
 	{ 0x3d40021c, 0xf08 },
 	{ 0x3d400250, 0x00001705 },
 	{ 0x3d400254, 0x2c },
@@ -1119,3 +1134,11 @@ struct dram_timing_info prt8ml_dram_timing = {
 	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
 	.fsp_table = { 4000, 400, 100, },
 };
+
+void board_dram_ecc_scrub(void)
+{
+	ddrc_inline_ecc_scrub(0x00000000, 0x1bffffff);
+	ddrc_inline_ecc_scrub(0x20000000, 0x3bffffff);
+	ddrc_inline_ecc_scrub(0x40000000, 0x5bffffff);
+	ddrc_inline_ecc_scrub_end(0x0, 0x5fffffff);
+}
diff --git a/arch/arm/dts/imx8mp-prt8ml.dts b/arch/arm/dts/imx8mp-prt8ml.dts
index 15c3e710ae..b23d64f2d1 100644
--- a/arch/arm/dts/imx8mp-prt8ml.dts
+++ b/arch/arm/dts/imx8mp-prt8ml.dts
@@ -20,8 +20,16 @@ environment-emmc {
 			status = "disabled";
 		};
 	};
-};
 
+	/* Minimum contiguous memory region is 1792MiB
+	 * The probe function of the ddrc will either expand this
+	 * to 6GiB (without ECC) or 5.25GiB (with inline ECC, in 3 regions).
+	 */
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x0 0x40000000 0x0 0x70000000>;
+	};
+};
 
 &usdhc2 {
 	#address-cells = <1>;

-- 
2.52.0