[PATCH master] ARM: i.MX8: esdctl: fix breakage for multi-SoC i.MX8M

[Ahmad Fatoum <a.fatoum@pengutronix.de>]

Only the i.MX8MP supports ECC out of the i.MX8M* family, so checking
DDRC_ECCCFG0 on the other SoCs is incorrect.

Guard the check behind a cpu_is_mx8mp(), which expands to 0 if
CONFIG_ARCH_IMX8MP is not defined and to
imx_cpu_type == IMX_CPU_IMX8MP otherwise.

Fixes: 0651254b9450 ("arm: mach-imx: esdctl.c: Add support for imx8mp inline ECC")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/mach-imx/esdctl.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
index 605d5efe9bde..788459076aa2 100644
--- a/arch/arm/mach-imx/esdctl.c
+++ b/arch/arm/mach-imx/esdctl.c
@@ -14,6 +14,7 @@
 #include <linux/bitfield.h>
 #include <asm/barebox-arm.h>
 #include <asm/memory.h>
+#include <mach/imx/generic.h>
 #include <mach/imx/esdctl.h>
 #include <mach/imx/esdctl-v4.h>
 #include <mach/imx/imx6-mmdc.h>
@@ -1151,7 +1152,11 @@ resource_size_t imx8m_barebox_earlymem_size(unsigned buswidth)
 {
 	resource_size_t size;
 
-	if (imx_esdctl_ecc_enabled(IOMEM(MX8M_DDRC_CTL_BASE_ADDR)))
+	/* NOTE: This expects that imx_set_cpu_type() has been called beforehand,
+	 * which the common entry points in atf.c all do. If this didn't happen,
+	 * we assume ECC to not be available, which is a safe bet.
+	 */
+	if (cpu_is_mx8mp() && imx_esdctl_ecc_enabled(IOMEM(MX8M_DDRC_CTL_BASE_ADDR)))
 		size = imx8m_ddrc_ecc_sdram_size(NULL, NULL, buswidth);
 	else
 		size = imx8m_ddrc_sdram_size(buswidth);
-- 
2.47.3