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X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.whiteo.stw.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-5.1 required=4.0 tests=AWL,BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.2 Subject: [PATCH] ARM: i.MX8M: enable MMU in PBL around fw-external BL32 verify X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.whiteo.stw.pengutronix.de) The BL32 fw-external blob is loaded into DRAM by the PBL and then SHA-256-verified inside get_builtin_firmware_ext(). The verify runs in PBL phase 1 with the MMU off and D-cache cold, walking ~720 KiB through uncached DRAM accesses; on a Cortex-A53 this costs around 2 s of pre-BL31 wall-clock on every boot. The verify is the only thing anchoring the BL32 content to the signed PBL: HABv4 on i.MX8M only signs and loads what fits in on-chip SRAM (= the PBL), and BL31/BL32 reach DRAM via PBL-driven copies, so skipping the SHA-256 would be a security regression. Turn on MMU + D-cache once the DRAM is populated and right before the SHA-256 verify + BL31/BL32 memcpy run, and drop the MMU again right before the BL31 entry (BL31 expects MMU off). Mirrors the Rockchip handling in commits f2ae1a4a85 ("ARM: rockchip: atf: enable MMU in PBL") and a0ef3a1b5c ("ARM: rockchip: atf: pass correct memsize to mmu_early_enable()"). Measured on i.MX8MM and i.MX8MP (Cortex-A53, ~720 KiB BL32 blob): the BL32 verify drops from ~2 s to ~300 ms (generic-C SHA-256 in both cases, the difference is the D-cache state) and the BL31 early-init also benefits from the warm cache (~200 ms saved). Assisted-by: Claude:claude-opus-4-7 Signed-off-by: Johannes Schneider --- --- a/arch/arm/mach-imx/atf.c +++ b/arch/arm/mach-imx/atf.c @@ -20,6 +20,7 @@ #include #include #include +#include static void imx_adjust_optee_memory(void **bl32, void **bl32_image, size_t *bl32_size) { @@ -187,6 +188,9 @@ "r" (tfa_dest - 16) : "cc"); + /* BL31 expects MMU off. */ + mmu_disable(); + /* * If enabled the bl_params are passed via x0 to the TF-A, except for * the i.MX8MQ which doesn't support bl_params yet. @@ -284,6 +288,12 @@ imx8m_setup_snvs(); imx8mm_load_bl33(bl33); + /* Cache DRAM for the BL32 verify + BL31/BL32 memcpy that follow. */ + mmu_early_enable(MX8M_DDR_CSD1_BASE_ADDR, + imx8m_barebox_earlymem_size(32), + MX8M_DDR_CSD1_BASE_ADDR + + imx8m_barebox_earlymem_size(32) - OPTEE_SIZE); + if (IS_ENABLED(CONFIG_FIRMWARE_IMX8MM_OPTEE)) { get_builtin_firmware_ext(imx8mm_bl32_bin, bl33, &bl32, &bl32_size); get_builtin_firmware(imx8mm_bl31_bin_optee, &bl31, &bl31_size); @@ -349,6 +359,12 @@ imx8m_setup_snvs(); imx8mp_load_bl33(bl33); + /* Cache DRAM for the BL32 verify + BL31/BL32 memcpy that follow. */ + mmu_early_enable(MX8M_DDR_CSD1_BASE_ADDR, + imx8m_barebox_earlymem_size(32), + MX8M_DDR_CSD1_BASE_ADDR + + imx8m_barebox_earlymem_size(32) - OPTEE_SIZE); + if (IS_ENABLED(CONFIG_FIRMWARE_IMX8MP_OPTEE)) { get_builtin_firmware_ext(imx8mp_bl32_bin, bl33, &bl32, &bl32_size); get_builtin_firmware(imx8mp_bl31_bin_optee, &bl31, &bl31_size); @@ -414,6 +430,12 @@ imx8m_setup_snvs(); imx8mn_load_bl33(bl33); + /* Cache DRAM for the BL32 verify + BL31/BL32 memcpy that follow. */ + mmu_early_enable(MX8M_DDR_CSD1_BASE_ADDR, + imx8m_barebox_earlymem_size(16), + MX8M_DDR_CSD1_BASE_ADDR + + imx8m_barebox_earlymem_size(16) - OPTEE_SIZE); + if (IS_ENABLED(CONFIG_FIRMWARE_IMX8MN_OPTEE)) { get_builtin_firmware_ext(imx8mn_bl32_bin, bl33, &bl32, &bl32_size); get_builtin_firmware(imx8mn_bl31_bin_optee, &bl31, &bl31_size); @@ -473,6 +495,12 @@ imx8m_setup_snvs(); imx8mq_load_bl33(bl33); + /* Cache DRAM for the BL32 verify + BL31/BL32 memcpy that follow. */ + mmu_early_enable(MX8M_DDR_CSD1_BASE_ADDR, + imx8m_barebox_earlymem_size(32), + MX8M_DDR_CSD1_BASE_ADDR + + imx8m_barebox_earlymem_size(32) - OPTEE_SIZE); + if (IS_ENABLED(CONFIG_FIRMWARE_IMX8MQ_OPTEE)) { get_builtin_firmware_ext(imx8mq_bl32_bin, bl33, &bl32, &bl32_size); get_builtin_firmware(imx8mq_bl31_bin_optee, &bl31, &bl31_size);