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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: h7pFOdPoranGW67ZFzCJh12pbW8nNKRv2kzenfaiREeRM09MKGk39EcnqMU855lGiVZQZrVFc4t2QjS5N/Vhi5ARLB5o33wF/UIbMm2PRqyAo8novt9C6jA0WuPUAPEKfCbR0xJXzBSbrNqbW4MNJWOqf2iMakdvm6LqfZ3vtQAEPhZkEb6KPaIDFp6fU9KB5L904BKQH5o8wmzsIMgqzXx+VPsgRuifDVbEtjM8DxU+neMAh4CRe9ocBt5ri6YwdmT4jGhMYn8YQncUpHO7qq04Z76gC8kjVh3xgDtnh18CkOUUsgrtjX+AP9zu4fHKkC4DqwCOJ7Xf17UbCIcbI7J32FxoB+CPDIVXIiSDTgWiJJXvkz8LQob5d2sAsDtJz9vwou7IPuR4S/fAjmflTQcK0IDk8aTwkxbKchSietZnmvzJj+OzUW1GQPfN+R/z X-OriginatorOrg: leica-geosystems.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jun 2026 13:01:57.4308 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2b188312-2799-49aa-2aaa-08ded1279b6c X-MS-Exchange-CrossTenant-Id: 1b16ab3e-b8f6-4fe3-9f3e-2db7fe549f6a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=1b16ab3e-b8f6-4fe3-9f3e-2db7fe549f6a;Ip=[193.8.40.99];Helo=[hexagon.com] X-MS-Exchange-CrossTenant-AuthSource: AMS0EPF000001B1.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS5PR06MB8837 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260623_060204_763735_D6692A5B X-CRM114-Status: GOOD ( 16.64 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.whiteo.stw.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-5.2 required=4.0 tests=AWL,BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.2 Subject: Re: [RFC] mci: imx-esdhc-pbl: enable ADMA2 for i.MX8M BL33 loads X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.whiteo.stw.pengutronix.de) Hoi Sascha, On Mon, Jun 22, 2026 at 09:11:30 +0200, Sascha Hauer wrote: > > > > Motivation > > ---------- > > Current PBL i.MX8M BL33 load is SDMA-based with the SDHCI boundary-restart > > loop in sdhci_transfer_data_dma(). For a 32 KiB BL33 transfer at the default > > 4 KiB SDMA boundary that's eight kicks-and-restarts. Measured on a custom > > i.MX8MM board: > > > > Boot timeline (from power-on): > > BootROM: 1 ms > > PBL-init: 3 ms > > DDR-training: 262 ms > > PBL-load: 819 ms > > PBL-pre-load: 168 ms > > load_bl33: 645 ms <-- (SDMA, ~5 MiB/s effective) > > PBL-post-load: 5 ms > > BL31-early: 114 ms > > BL31-platform: 15 ms > > BL31-runtime: 98 ms > > thru-OPTEE: 98 ms > > post-OPTEE: 0 ms > > barebox: 5654 ms > > kernel-init: 111 ms > > > > barebox's own runtime imx-esdhc.c driver uses ADMA2 for the same controller > > and gets the FIT image off the same eMMC at expected speed. ADMA2 in PBL > > should match. > > You lost me here. ADMA(2) usage is gated behind the SDHCI_USE_ADMA which > is set in sdhci_setup_adma(). Only the Rockchip driver calls this > currently, so imx-esdhc should use SDMA also in barebox proper. You're right, and my cover letter was wrong :-S To be precise about who uses what: Linux sdhci-esdhc-imx : ADMA2 + HS400ES @ 200 MHz barebox-proper : SDMA (sdhci_transfer_data_dma(), SDHCI_USE_ADMA unset) barebox PBL : PIO (esdhc_use_pio_mode() is true in PBL) I wrote that *barebox*-proper uses ADMA2 - that was the mistake; it is *Linux* that does. barebox-proper uses SDMA, and nothing on i.MX uses ADMA2. > So you have patches in your tree I haven't seen yet? No, nothing unpublished. The ADMA2 reference I was comparing against is Linux's sdhci-esdhc-imx, not anything in barebox. Linux drives ADMA2 + HS400ES at 200 MHz on the exact board this RFC targets (USDHC3 -> eMMC): # dmesg | grep mmc2 mmc2: SDHCI controller on 30b60000.mmc using ADMA mmc2: new HS400 Enhanced strobe MMC card at address 0001 mmcblk2: mmc2:0001 IM032G 9.70 GiB # cat /sys/kernel/debug/mmc2/ios clock: 200000000 Hz bus width: 3 (8 bits) timing spec: 10 (mmc HS400 enhanced strobe) signal voltage: 1 (1.80 V) so it is a PBL bring-up gap, not a silicon limit. On our i.MX8MM board, PBL load_bl33 takes ~640 ms in PIO - and this is what i'm trying to lower ... somehow. One step up would be SDMA, but that has the problem of the SDMA boundary field colliding with the 13-bit BLKSIZE, so the boundary cannot be raised far enough and the engine would end up restarting every 4K (~340 stops for a 1.5 MB read, which makes SDMA ~= PIO ?). Therefore i directly "aimed high" at ADMA2, to avoid round-trips and load everthing in one go - but there it hangs in ST_TFR (RFC body) -> what might i be missing or have overlooked? Gruß, Johannes