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Sat, 4 Jul 2026 14:26:30 +0200 From: Johannes Schneider To: barebox@lists.infradead.org Cc: Johannes Schneider Subject: [PATCH v2 09/11] dma: provide the streaming DMA API in the PBL (opt-in via PBL_HAS_DMA) Date: Sat, 4 Jul 2026 12:26:26 +0000 Message-ID: <20260704122628.3326142-10-johannes.schneider@leica-geosystems.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260704122628.3326142-1-johannes.schneider@leica-geosystems.com> References: <20260704122628.3326142-1-johannes.schneider@leica-geosystems.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-OriginalArrivalTime: 04 Jul 2026 12:26:30.0385 (UTC) FILETIME=[57A95E10:01DD0BB0] X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DB1PEPF000509EA:EE_|AS1PR06MB8539:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: 3ec2da3f-21c1-4ef9-dc74-08ded9c77d0f X-SET-LOWER-SCL-SCANNER: YES X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|23010399003|1800799024|36860700016|11063799006|56012099006|22082099003|18002099003; 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Content preview: The PBL has always gotten no-op dma_map_single()/dma_sync_single_for_*()/ dma_unmap_single() stubs, on the assumption that DMA buffers live in uncached memory because the MMU is only turned on in bare [...] Content analysis details: (-2.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a01:111:f403:c200:0:0:0:1 listed in] [list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 DMARC_PASS DMARC pass policy X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-Rspamd-Server: mx1 X-Rspamd-Queue-Id: BA83820269E X-Spamd-Result: default: False [-6.41 / 15.00]; BAYES_HAM(-3.00)[100.00%]; DWL_DNSWL_MED(-2.00)[infradead.org:dkim]; MID_CONTAINS_FROM(1.00)[]; ARC_ALLOW(-1.00)[microsoft.com:s=arcselector10001:i=1]; DMARC_POLICY_ALLOW(-0.50)[leica-geosystems.com,reject]; RCVD_DKIM_ARC_DNSWL_MED(-0.50)[]; R_MISSING_CHARSET(0.50)[]; R_SPF_ALLOW(-0.20)[+mx:c]; RCVD_IN_DNSWL_MED(-0.20)[2607:7c80:54:3::133:from]; R_DKIM_ALLOW(-0.20)[lists.infradead.org:s=bombadil.20210309,leica-geosystems.com:s=selector1]; MAILLIST(-0.20)[mailman]; MIME_GOOD(-0.10)[text/plain]; HAS_LIST_UNSUB(-0.01)[]; FROM_NEQ_ENVFROM(0.00)[johannes.schneider@leica-geosystems.com,barebox-bounces@lists.infradead.org]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; FORGED_SENDER_MAILLIST(0.00)[]; RCVD_IN_DNSWL_NONE(0.00)[2a01:111:f403:c200::1:received]; RECEIVED_HELO_LOCALHOST(0.00)[]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; RCPT_COUNT_TWO(0.00)[2]; NEURAL_HAM(-0.00)[-1.000]; DKIM_TRACE(0.00)[lists.infradead.org:+,leica-geosystems.com:+]; ASN(0.00)[asn:7247, ipnet:2607:7c80:54::/48, country:US]; RCVD_COUNT_FIVE(0.00)[6]; RCVD_TLS_LAST(0.00)[]; TAGGED_FROM(0.00)[lore=pengutronix.de]; FROM_HAS_DN(0.00)[] X-Rspamd-Action: no action X-Stat-Signature: gc5rdretun5mb5w1i93yt1q8fqcxqok1 The PBL has always gotten no-op dma_map_single()/dma_sync_single_for_*()/ dma_unmap_single() stubs, on the assumption that DMA buffers live in uncached memory because the MMU is only turned on in barebox_arm_entry(). That assumption breaks the moment a PBL DMA user runs with the MMU (and thus the D-cache) on -- which is the direction the i.MX8M PBL is moving in for a fast, warm-cache next-stage load. Add an opt-in CONFIG_PBL_HAS_DMA that routes the PBL through the same real dma_map/dma_sync implementation (drivers/dma/map.c) and arch cache maintenance (arch_sync_dma_for_*) that barebox proper uses, rather than the stubs. It is a plain selectable bool: boards/drivers that do PBL DMA with the MMU on select it; everyone else is byte-for-byte unchanged and keeps the stubs. On ARM this also builds dma_$(S64_32).o (arch_sync_dma_for_device) for the PBL; arch_sync_dma_for_cpu and the dma_{inv,flush}_range cache ops already come in via the PBL-linked mmu-common.o / mmu_$(S64_32).o. No functional change unless PBL_HAS_DMA is selected. Assisted-by: Claude Opus 4.8 (1M context) Signed-off-by: Johannes Schneider --- Notes: v2: - New patch. Adds the dma_map/dma_sync cache-maintenance infrastructure the PBL was missing, behind an opt-in CONFIG_PBL_HAS_DMA (Sascha). arch/arm/cpu/Makefile | 1 + common/Kconfig | 12 ++++++++++++ drivers/dma/Makefile | 1 + include/dma.h | 7 ++++--- 4 files changed, 18 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile index 467ef17bfd..d1e94d9a13 100644 --- a/arch/arm/cpu/Makefile +++ b/arch/arm/cpu/Makefile @@ -7,6 +7,7 @@ pbl-$(CONFIG_ARM_EXCEPTIONS_PBL) += exceptions_$(S64_32).o interrupts_$(S64_32). obj-pbl-$(CONFIG_MMU) += mmu-common.o obj-pbl-$(CONFIG_MMU) += mmu_$(S64_32).o obj-$(CONFIG_MMU) += dma_$(S64_32).o +pbl-$(CONFIG_PBL_HAS_DMA) += dma_$(S64_32).o obj-pbl-y += lowlevel_$(S64_32).o obj-pbl-$(CONFIG_CPU_32v7) += hyp.o AFLAGS_hyp.o :=-Wa,-march=armv7-a -Wa,-mcpu=all diff --git a/common/Kconfig b/common/Kconfig index 2c75844be9..055f169431 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -87,6 +87,18 @@ config HAS_DMA Drivers that depend on a DMA implementation can depend on this config, so that you don't get a compilation error. +config PBL_HAS_DMA + bool + depends on HAS_DMA && MMU + help + Make the streaming DMA API -- dma_map_single(), + dma_sync_single_for_cpu()/_for_device() and dma_unmap_single() -- + available in the PBL, backed by the same arch_sync_dma_for_*() cache + maintenance barebox proper uses. Without this the PBL only gets no-op + stubs that assume DMA buffers live in uncached memory, which is only + true while the MMU (and thus the D-cache) is off. A PBL DMA user that + runs with the MMU on must select this so its transfers stay coherent. + config GENERIC_GPIO bool diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 66f9dc2756..c941b69c89 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_DMADEVICES) += dma-devices.o obj-$(CONFIG_HAS_DMA) += map.o +pbl-$(CONFIG_PBL_HAS_DMA) += map.o obj-$(CONFIG_DMA_API_DEBUG) += debug.o obj-$(CONFIG_MXS_APBH_DMA) += apbh_dma.o obj-$(CONFIG_OF_DMA_COHERENCY) += of_fixups.o diff --git a/include/dma.h b/include/dma.h index 60937a69aa..2a6f3d804a 100644 --- a/include/dma.h +++ b/include/dma.h @@ -102,7 +102,7 @@ void arch_sync_dma_for_device(void *vaddr, size_t size, enum dma_data_direction dir); #endif -#if IN_PROPER +#if IN_PROPER || IS_ENABLED(CONFIG_PBL_HAS_DMA) void dma_sync_single_for_cpu(struct device *dev, dma_addr_t address, size_t size, enum dma_data_direction dir); @@ -116,8 +116,9 @@ void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, enum dma_data_direction dir); #else /* - * assumes buffers are in coherent/uncached memory, e.g. because - * MMU is only enabled in barebox_arm_entry which hasn't run yet. + * PBL without CONFIG_PBL_HAS_DMA: assumes buffers are in coherent/uncached + * memory, e.g. because the MMU is only enabled in barebox_arm_entry which + * hasn't run yet. Select PBL_HAS_DMA to get real cache maintenance instead. */ static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t address, size_t size, enum dma_data_direction dir) -- 2.43.0