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Sat, 4 Jul 2026 14:26:30 +0200 From: Johannes Schneider To: barebox@lists.infradead.org Cc: Johannes Schneider , "Claude Opus 4 . 8" Subject: [PATCH v2 08/11] ARM: i.MX8M: enable the MMU before the PBL eMMC load Date: Sat, 4 Jul 2026 12:26:25 +0000 Message-ID: <20260704122628.3326142-9-johannes.schneider@leica-geosystems.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260704122628.3326142-1-johannes.schneider@leica-geosystems.com> References: <20260704122628.3326142-1-johannes.schneider@leica-geosystems.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-OriginalArrivalTime: 04 Jul 2026 12:26:30.0354 (UTC) FILETIME=[57A4A320:01DD0BB0] X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DB1PEPF000509EA:EE_|VI1PR06MB6397:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: 143d47eb-f315-400f-d4f2-08ded9c77ccd X-SET-LOWER-SCL-SCANNER: YES X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700016|1800799024|23010399003|11063799006|56012099006|22082099003|18002099003; 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The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: The i.MX8MM/8MP PBL reads the next stage from eMMC with the MMU off, so the PIO copy and the CPU's writes to DRAM are uncached and slow: on an i.MX8MM loading the ~1.6 MB next stage took ~713 ms. Move the imx8m_mmu_early_enable() up to before imx8m{m,p}_load_bl33() so the copy runs against a warm D-cache. Measured on i.MX8MM: load_bl33 713 ms -> 241 ms. The MMU then stays on for the BL32 verif [...] Content analysis details: (-2.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a01:111:f403:c201:0:0:0:1 listed in] [list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 DMARC_PASS DMARC pass policy X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-Rspamd-Server: mx1 X-Rspamd-Queue-Id: 41D6E2026BE X-Spamd-Result: default: False [-6.41 / 15.00]; BAYES_HAM(-3.00)[99.99%]; DWL_DNSWL_MED(-2.00)[infradead.org:dkim]; MID_CONTAINS_FROM(1.00)[]; ARC_ALLOW(-1.00)[microsoft.com:s=arcselector10001:i=1]; DMARC_POLICY_ALLOW(-0.50)[leica-geosystems.com,reject]; RCVD_DKIM_ARC_DNSWL_MED(-0.50)[]; R_MISSING_CHARSET(0.50)[]; R_SPF_ALLOW(-0.20)[+mx:c]; RCVD_IN_DNSWL_MED(-0.20)[2607:7c80:54:3::133:from]; R_DKIM_ALLOW(-0.20)[lists.infradead.org:s=bombadil.20210309,leica-geosystems.com:s=selector1]; MAILLIST(-0.20)[mailman]; MIME_GOOD(-0.10)[text/plain]; HAS_LIST_UNSUB(-0.01)[]; FROM_NEQ_ENVFROM(0.00)[johannes.schneider@leica-geosystems.com,barebox-bounces@lists.infradead.org]; RCVD_IN_DNSWL_NONE(0.00)[2a01:111:f403:c201::1:received]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; RECEIVED_HELO_LOCALHOST(0.00)[]; FORGED_SENDER_MAILLIST(0.00)[]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; RCVD_TLS_LAST(0.00)[]; RCPT_COUNT_THREE(0.00)[3]; ASN(0.00)[asn:7247, ipnet:2607:7c80:54::/48, country:US]; NEURAL_HAM(-0.00)[-1.000]; DKIM_TRACE(0.00)[lists.infradead.org:+,leica-geosystems.com:+]; TAGGED_FROM(0.00)[lore=pengutronix.de]; RCVD_COUNT_FIVE(0.00)[6]; FROM_HAS_DN(0.00)[] X-Rspamd-Action: no action X-Stat-Signature: t91hf88gb43kwytyf1doybkgwxxa73q9 The i.MX8MM/8MP PBL reads the next stage from eMMC with the MMU off, so the PIO copy and the CPU's writes to DRAM are uncached and slow: on an i.MX8MM loading the ~1.6 MB next stage took ~713 ms. Move the imx8m_mmu_early_enable() up to before imx8m{m,p}_load_bl33() so the copy runs against a warm D-cache. Measured on i.MX8MM: load_bl33 713 ms -> 241 ms. The MMU then stays on for the BL32 verify + BL31/BL32 memcpy that follow, so this replaces the post-load enable for these two SoCs. Signed-off-by: Johannes Schneider Assisted-by: Claude Opus 4.8 (1M context) --- Notes: v2: - New patch. The maintainer-suggested DMA-free speedup: enable the MMU before the PBL eMMC load so PIO runs warm-cached, split out so it stands on its own (Sascha). arch/arm/mach-imx/atf.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-imx/atf.c b/arch/arm/mach-imx/atf.c index 0f57a204b7..4b6f7ce5e1 100644 --- a/arch/arm/mach-imx/atf.c +++ b/arch/arm/mach-imx/atf.c @@ -299,10 +299,10 @@ __noreturn void __imx8mm_load_and_start_image_via_tfa(void *fdt, void *bl33) imx8mm_init_scratch_space(); imx8m_save_bootrom_log(); imx8m_setup_snvs(); - imx8mm_load_bl33(bl33); - /* Cache DRAM for the BL32 verify + BL31/BL32 memcpy that follow. */ + /* MMU on before the load: PIO runs warm-cached; also serves the verify. */ imx8m_mmu_early_enable(); + imx8mm_load_bl33(bl33); if (IS_ENABLED(CONFIG_FIRMWARE_IMX8MM_OPTEE)) { get_builtin_firmware_ext(imx8mm_bl32_bin, bl33, &bl32); @@ -365,10 +365,10 @@ __noreturn void __imx8mp_load_and_start_image_via_tfa(void *fdt, void *bl33) imx8mp_init_scratch_space(); imx8m_save_bootrom_log(); imx8m_setup_snvs(); - imx8mp_load_bl33(bl33); - /* Cache DRAM for the BL32 verify + BL31/BL32 memcpy that follow. */ + /* MMU on before the load: PIO runs warm-cached; also serves the verify. */ imx8m_mmu_early_enable(); + imx8mp_load_bl33(bl33); if (IS_ENABLED(CONFIG_FIRMWARE_IMX8MP_OPTEE)) { get_builtin_firmware_ext(imx8mp_bl32_bin, bl33, &bl32); -- 2.43.0