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The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: From: Sascha Hauer clk: imx: pll14xx: Use register defines consistently The driver has defines for the registers, but they are mostly unused. Use the defines consistently throughout the driver. While at it rename DIV_CT [...] Content analysis details: (-2.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.0 DMARC_MISSING Missing DMARC policy X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ahmad Fatoum Sender: "barebox" X-Spamd-Result: default: False [-54.91 / 15.00]; RECEIVED_AUTHENTICATED_BY_MX1(-50.00)[]; BAYES_HAM(-3.00)[100.00%]; DWL_DNSWL_MED(-2.00)[infradead.org:dkim]; MID_CONTAINS_FROM(1.00)[]; ARC_REJECT(1.00)[signature check failed: fail, {[1] = sig:pengutronix.de:reject}]; KNOWN_LIST_ID(-1.00)[barebox.lists.infradead.org]; RCVD_DKIM_ARC_DNSWL_MED(-0.50)[]; R_MISSING_CHARSET(0.50)[]; MAILLIST(-0.20)[mailman]; RCVD_IN_DNSWL_MED(-0.20)[2607:7c80:54:3::133:from]; R_DKIM_ALLOW(-0.20)[lists.infradead.org:s=bombadil.20210309]; R_SPF_ALLOW(-0.20)[+mx:c]; MIME_GOOD(-0.10)[text/plain]; HAS_LIST_UNSUB(-0.01)[]; MIME_TRACE(0.00)[0:+]; RCPT_COUNT_TWO(0.00)[2]; RECEIVED_HELO_LOCALHOST(0.00)[]; ARC_SIGNED(0.00)[pengutronix.de:s=20260414:i=2]; RCVD_COUNT_THREE(0.00)[4]; TO_DN_SOME(0.00)[]; DMARC_NA(0.00)[pengutronix.de]; R_DKIM_REJECT(0.00)[pengutronix.de:s=20260414]; TAGGED_FROM(0.00)[lore=pengutronix.de]; NEURAL_HAM(-0.00)[-1.000]; FROM_NEQ_ENVFROM(0.00)[a.fatoum@pengutronix.de,barebox-bounces@lists.infradead.org]; FROM_HAS_DN(0.00)[]; RCVD_TLS_LAST(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; DKIM_MIXED(0.00)[]; ASN(0.00)[asn:7247, ipnet:2607:7c80:54::/48, country:US]; DKIM_TRACE(0.00)[lists.infradead.org:+,pengutronix.de:-]; FORGED_SENDER_MAILLIST(0.00)[] X-Rspamd-Action: no action X-Rspamd-Server: mx1 X-Rspamd-Queue-Id: 214CB200231 X-Stat-Signature: 5tzbx4mqm4r11ceygwyum4ph4dfdq5p8 From: Sascha Hauer clk: imx: pll14xx: Use register defines consistently The driver has defines for the registers, but they are mostly unused. Use the defines consistently throughout the driver. While at it rename DIV_CTL to DIV_CTL0 because that's the name in the reference manual. Signed-off-by: Sascha Hauer [ ahmad: ported from Linux 485b4ff57c27, s/(readl|writel)_relaxed/\1/ ] Signed-off-by: Ahmad Fatoum --- drivers/clk/imx/clk-pll14xx.c | 49 ++++++++++++++++++----------------- 1 file changed, 25 insertions(+), 24 deletions(-) diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index 8a773f19f807..c1d5a6b88f41 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -19,7 +19,8 @@ #include "clk.h" #define GNRL_CTL 0x0 -#define DIV_CTL 0x4 +#define DIV_CTL0 0x4 +#define DIV_CTL1 0x8 #define LOCK_STATUS BIT(31) #define LOCK_SEL_MASK BIT(29) #define CLKE_MASK BIT(11) @@ -118,7 +119,7 @@ static unsigned long clk_pll1416x_recalc_rate(struct clk_hw *hw, u32 mdiv, pdiv, sdiv, pll_div; u64 fvco = parent_rate; - pll_div = readl(pll->base + 4); + pll_div = readl(pll->base + DIV_CTL0); mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT; sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; @@ -137,8 +138,8 @@ static unsigned long clk_pll1443x_recalc_rate(struct clk_hw *hw, short int kdiv; u64 fvco = parent_rate; - pll_div_ctl0 = readl(pll->base + 4); - pll_div_ctl1 = readl(pll->base + 8); + pll_div_ctl0 = readl(pll->base + DIV_CTL0); + pll_div_ctl1 = readl(pll->base + DIV_CTL1); mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT; sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; @@ -168,7 +169,7 @@ static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll) { u32 val; - return readl_poll_timeout(pll->base, val, val & LOCK_STATUS, + return readl_poll_timeout(pll->base + GNRL_CTL, val, val & LOCK_STATUS, LOCK_TIMEOUT_US); } @@ -187,32 +188,32 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, return -EINVAL; } - tmp = readl(pll->base + 4); + tmp = readl(pll->base + DIV_CTL0); if (!clk_pll14xx_mp_change(rate, tmp)) { tmp &= ~(SDIV_MASK) << SDIV_SHIFT; tmp |= rate->sdiv << SDIV_SHIFT; - writel(tmp, pll->base + 4); + writel(tmp, pll->base + DIV_CTL0); return 0; } /* Bypass clock and set lock to pll output lock */ - tmp = readl(pll->base); + tmp = readl(pll->base + GNRL_CTL); tmp |= LOCK_SEL_MASK; - writel(tmp, pll->base); + writel(tmp, pll->base + GNRL_CTL); /* Enable RST */ tmp &= ~RST_MASK; - writel(tmp, pll->base); + writel(tmp, pll->base + GNRL_CTL); /* Enable BYPASS */ tmp |= BYPASS_MASK; - writel(tmp, pll->base); + writel(tmp, pll->base + GNRL_CTL); div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | (rate->sdiv << SDIV_SHIFT); - writel(div_val, pll->base + 0x4); + writel(div_val, pll->base + DIV_CTL0); /* * According to SPEC, t3 - t2 need to be greater than @@ -224,7 +225,7 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, /* Disable RST */ tmp |= RST_MASK; - writel(tmp, pll->base); + writel(tmp, pll->base + GNRL_CTL); /* Wait Lock */ ret = clk_pll14xx_wait_lock(pll); @@ -233,7 +234,7 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, /* Bypass */ tmp &= ~BYPASS_MASK; - writel(tmp, pll->base); + writel(tmp, pll->base + GNRL_CTL); return 0; } @@ -269,32 +270,32 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, return -EINVAL; } - tmp = readl(pll->base + 4); + tmp = readl(pll->base + DIV_CTL0); if (!clk_pll14xx_mp_change(rate, tmp)) { tmp &= ~(SDIV_MASK) << SDIV_SHIFT; tmp |= rate->sdiv << SDIV_SHIFT; - writel(tmp, pll->base + 4); + writel(tmp, pll->base + DIV_CTL0); tmp = rate->kdiv << KDIV_SHIFT; - writel(tmp, pll->base + 8); + writel(tmp, pll->base + DIV_CTL1); return 0; } /* Enable RST */ - tmp = readl(pll->base); + tmp = readl(pll->base + GNRL_CTL); tmp &= ~RST_MASK; - writel(tmp, pll->base); + writel(tmp, pll->base + GNRL_CTL); /* Enable BYPASS */ tmp |= BYPASS_MASK; - writel(tmp, pll->base); + writel(tmp, pll->base + GNRL_CTL); div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | (rate->sdiv << SDIV_SHIFT); - writel(div_val, pll->base + 0x4); - writel(rate->kdiv << KDIV_SHIFT, pll->base + 0x8); + writel(div_val, pll->base + DIV_CTL0); + writel(rate->kdiv << KDIV_SHIFT, pll->base + DIV_CTL1); /* * According to SPEC, t3 - t2 need to be greater than @@ -306,7 +307,7 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, /* Disable RST */ tmp |= RST_MASK; - writel(tmp, pll->base); + writel(tmp, pll->base + GNRL_CTL); /* Wait Lock*/ ret = clk_pll14xx_wait_lock(pll); @@ -315,7 +316,7 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, /* Bypass */ tmp &= ~BYPASS_MASK; - writel(tmp, pll->base); + writel(tmp, pll->base + GNRL_CTL); return 0; } -- 2.47.3