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The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: While clk_pll1416x_early_set_rate() programs the dividers, waits for the lock and clears the bypass, it doesn't actually ungate the clock. Therefore, the i.MX8M early clock init sets the CLKE bit by hand afterwards, but it does so only for the ARM PLL. SYS_PLL3 is reconfigured without CLKE being touched, because it works out, because it' [...] Content analysis details: (-2.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.0 DMARC_MISSING Missing DMARC policy X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-Spamd-Result: default: False [-58.91 / 15.00]; RECEIVED_AUTHENTICATED_BY_MX1(-50.00)[]; BAYES_HAM(-3.00)[100.00%]; DWL_DNSWL_MED(-2.00)[infradead.org:dkim]; ARC_ALLOW_TRUSTED(-2.00)[pengutronix.de:s=20260414:i=1]; KNOWN_LIST_ID(-1.00)[barebox.lists.infradead.org]; ARC_ALLOW(-1.00)[pengutronix.de:s=20260414:i=1]; MID_CONTAINS_FROM(1.00)[]; RCVD_DKIM_ARC_DNSWL_MED(-0.50)[]; R_MISSING_CHARSET(0.50)[]; R_DKIM_ALLOW(-0.20)[lists.infradead.org:s=bombadil.20210309,pengutronix.de:s=20260414]; R_SPF_ALLOW(-0.20)[+mx:c]; MAILLIST(-0.20)[mailman]; RCVD_IN_DNSWL_MED(-0.20)[2607:7c80:54:3::133:from]; MIME_GOOD(-0.10)[text/plain]; HAS_LIST_UNSUB(-0.01)[]; RCPT_COUNT_TWO(0.00)[2]; ARC_SIGNED(0.00)[pengutronix.de:s=20260414:i=2]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; FROM_HAS_DN(0.00)[]; DMARC_NA(0.00)[pengutronix.de]; RCVD_COUNT_THREE(0.00)[4]; NEURAL_HAM(-0.00)[-1.000]; RCVD_TLS_LAST(0.00)[]; ASN(0.00)[asn:7247, ipnet:2607:7c80:54::/48, country:US]; RCVD_VIA_SMTP_AUTH(0.00)[]; RECEIVED_HELO_LOCALHOST(0.00)[]; DKIM_TRACE(0.00)[lists.infradead.org:+,pengutronix.de:+]; TAGGED_FROM(0.00)[lore=pengutronix.de]; FROM_NEQ_ENVFROM(0.00)[a.fatoum@pengutronix.de,barebox-bounces@lists.infradead.org]; FORGED_SENDER_MAILLIST(0.00)[] X-Rspamd-Action: no action X-Rspamd-Server: mx1 X-Rspamd-Queue-Id: E2BAE202303 X-Stat-Signature: biiyirkx6xm4yh6wj75qtdyuubh4rmfw While clk_pll1416x_early_set_rate() programs the dividers, waits for the lock and clears the bypass, it doesn't actually ungate the clock. Therefore, the i.MX8M early clock init sets the CLKE bit by hand afterwards, but it does so only for the ARM PLL. SYS_PLL3 is reconfigured without CLKE being touched, because it works out, because it's set at reset and BootROM doesn't clear it. U-Boot's intpll_configure() sets CLKE at the end instead. As we are going to align the early init with U-Boot for easier comparison in future, let's rename our function to clk_pll1416x_early_configure() and have it also ungate the clock. Signed-off-by: Ahmad Fatoum --- arch/arm/mach-imx/imx8m.c | 11 ++++------- drivers/clk/imx/clk-pll14xx.c | 14 +++++++++++--- include/soc/imx8m/clk-early.h | 4 ++-- 3 files changed, 17 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c index 6286ab7344bc..3b2833a07ec2 100644 --- a/arch/arm/mach-imx/imx8m.c +++ b/arch/arm/mach-imx/imx8m.c @@ -116,8 +116,8 @@ static void __imx8m_early_clock_init(int cpu_type) pll3_freq = 750000000UL; /* Configure SYS_PLL3 */ - clk_pll1416x_early_set_rate(ana + IMX8MM_CCM_ANALOG_SYS_PLL3_GEN_CTRL, - pll3_freq, 25000000UL); + clk_pll1416x_early_configure(ana + IMX8MM_CCM_ANALOG_SYS_PLL3_GEN_CTRL, + pll3_freq, 25000000UL); if (cpu_type == IMX_CPU_IMX8MP) { /* 8MP ROM already set NOC to 800Mhz, only need to configure NOC_IO clk to 600Mhz */ @@ -131,11 +131,8 @@ static void __imx8m_early_clock_init(int cpu_type) IMX8M_CCM_TARGET_ROOTn_MUX(2)); /* Configure ARM PLL to 1.2GHz */ - clk_pll1416x_early_set_rate(ana + IMX8MM_CCM_ANALOG_ARM_PLL_GEN_CTRL, - 1200000000UL, 25000000UL); - - clrsetbits_le32(ana + IMX8MM_CCM_ANALOG_ARM_PLL_GEN_CTRL, 0, - INTPLL_CLKE_MASK); + clk_pll1416x_early_configure(ana + IMX8MM_CCM_ANALOG_ARM_PLL_GEN_CTRL, + 1200000000UL, 25000000UL); clrsetbits_le32(ccm + IMX8M_CCM_TARGET_ROOTn(IMX8M_ARM_A53_CLK_ROOT), IMX8M_CCM_TARGET_ROOTn_MUX(7), diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index 8a773f19f807..a0213c60516d 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -238,8 +238,8 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, return 0; } -int clk_pll1416x_early_set_rate(void __iomem *base, unsigned long drate, - unsigned long prate) +int clk_pll1416x_early_configure(void __iomem *base, unsigned long drate, + unsigned long prate) { struct clk_pll14xx pll = { .hw.clk = { @@ -249,8 +249,16 @@ int clk_pll1416x_early_set_rate(void __iomem *base, unsigned long drate, .rate_table = imx_pll1416x_tbl, .rate_count = ARRAY_SIZE(imx_pll1416x_tbl), }; + int ret; - return clk_pll1416x_set_rate(&pll.hw, drate, prate); + ret = clk_pll1416x_set_rate(&pll.hw, drate, prate); + if (ret) + return ret; + + /* enable the PLL output */ + setbits_le32(base + GNRL_CTL, CLKE_MASK); + + return 0; } static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, diff --git a/include/soc/imx8m/clk-early.h b/include/soc/imx8m/clk-early.h index c2034e54f070..2430521d7a2e 100644 --- a/include/soc/imx8m/clk-early.h +++ b/include/soc/imx8m/clk-early.h @@ -3,7 +3,7 @@ #ifndef __SOC_IMX8M_CLK_EARLY_H #define __SOC_IMX8M_CLK_EARLY_H -int clk_pll1416x_early_set_rate(void __iomem *base, unsigned long drate, - unsigned long prate); +int clk_pll1416x_early_configure(void __iomem *base, unsigned long drate, + unsigned long prate); #endif /* __SOC_IMX8M_CLK_EARLY_H */ -- 2.47.3