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The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: barebox never touches NOC_CLK_ROOT on the i.MX8MM and i.MX8MN in the PBL, so early startup uses the ROM's setting: sys_pll1_800m with a post divider of 2, i.e. 400MHz. barebox proper later reparents NOC to sys_pll3_out as requested by the upstream device tree, but the assigned rate is 0 and clk-conf only switches the mux, so the ROM's divider stays and NOC runs at h [...] Content analysis details: (-2.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.0 DMARC_MISSING Missing DMARC policy X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-Spamd-Result: default: False [-58.91 / 15.00]; RECEIVED_AUTHENTICATED_BY_MX1(-50.00)[]; BAYES_HAM(-3.00)[99.99%]; DWL_DNSWL_MED(-2.00)[infradead.org:dkim]; ARC_ALLOW_TRUSTED(-2.00)[pengutronix.de:s=20260414:i=1]; KNOWN_LIST_ID(-1.00)[barebox.lists.infradead.org]; MID_CONTAINS_FROM(1.00)[]; ARC_ALLOW(-1.00)[pengutronix.de:s=20260414:i=1]; RCVD_DKIM_ARC_DNSWL_MED(-0.50)[]; R_MISSING_CHARSET(0.50)[]; RCVD_IN_DNSWL_MED(-0.20)[2607:7c80:54:3::133:from]; R_SPF_ALLOW(-0.20)[+mx:c]; MAILLIST(-0.20)[mailman]; R_DKIM_ALLOW(-0.20)[lists.infradead.org:s=bombadil.20210309,pengutronix.de:s=20260414]; MIME_GOOD(-0.10)[text/plain]; HAS_LIST_UNSUB(-0.01)[]; RECEIVED_HELO_LOCALHOST(0.00)[]; RCVD_COUNT_THREE(0.00)[4]; DMARC_NA(0.00)[pengutronix.de]; ARC_SIGNED(0.00)[pengutronix.de:s=20260414:i=2]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; DKIM_TRACE(0.00)[lists.infradead.org:+,pengutronix.de:+]; TAGGED_FROM(0.00)[lore=pengutronix.de]; FROM_NEQ_ENVFROM(0.00)[a.fatoum@pengutronix.de,barebox-bounces@lists.infradead.org]; FROM_HAS_DN(0.00)[]; RCVD_TLS_LAST(0.00)[]; NEURAL_HAM(-0.00)[-1.000]; ASN(0.00)[asn:7247, ipnet:2607:7c80:54::/48, country:US]; RCVD_VIA_SMTP_AUTH(0.00)[]; RCPT_COUNT_THREE(0.00)[3]; FORGED_SENDER_MAILLIST(0.00)[] X-Rspamd-Action: no action X-Rspamd-Server: mx1 X-Rspamd-Queue-Id: BF52E201F18 X-Stat-Signature: 1xtm8ejjca713opmjssiurohaagsr8iy barebox never touches NOC_CLK_ROOT on the i.MX8MM and i.MX8MN in the PBL, so early startup uses the ROM's setting: sys_pll1_800m with a post divider of 2, i.e. 400MHz. barebox proper later reparents NOC to sys_pll3_out as requested by the upstream device tree, but the assigned rate is 0 and clk-conf only switches the mux, so the ROM's divider stays and NOC runs at half the SYS_PLL3 rate: 300MHz instead of 600MHz on the i.MX8MN. This was observed to make an L2 cache miss about 10% more costly. U-Boot's clock_init() instead writes NOC_CLK_ROOT in full: undivided sys_pll3_out, i.e. 750MHz on the i.MX8MM and 600MHz on the i.MX8MN, both within the 800MHz maximum of the root. Let's do the same in barebox. Reported-by: Niels de Koeijer Signed-off-by: Ahmad Fatoum --- arch/arm/mach-imx/imx8m.c | 5 +++++ include/mach/imx/imx8m-ccm-regs.h | 1 + 2 files changed, 6 insertions(+) diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c index 3b2833a07ec2..533e2877237f 100644 --- a/arch/arm/mach-imx/imx8m.c +++ b/arch/arm/mach-imx/imx8m.c @@ -124,6 +124,11 @@ static void __imx8m_early_clock_init(int cpu_type) imx8m_clock_set_target_val(IMX8M_NOC_IO_CLK_ROOT, IMX8M_CCM_TARGET_ROOTn_ENABLE | IMX8M_CCM_TARGET_ROOTn_MUX(2)); + } else { + /* NOC from undivided sys_pll3_out */ + imx8m_clock_set_target_val(IMX8M_NOC_CLK_ROOT, + IMX8M_CCM_TARGET_ROOTn_ENABLE | + IMX8M_CCM_TARGET_ROOTn_MUX(2)); } clrsetbits_le32(ccm + IMX8M_CCM_TARGET_ROOTn(IMX8M_ARM_A53_CLK_ROOT), diff --git a/include/mach/imx/imx8m-ccm-regs.h b/include/mach/imx/imx8m-ccm-regs.h index 035cd13ed694..42d0c485f25b 100644 --- a/include/mach/imx/imx8m-ccm-regs.h +++ b/include/mach/imx/imx8m-ccm-regs.h @@ -22,6 +22,7 @@ * Applications Processor Reference Manual */ #define IMX8M_ARM_A53_CLK_ROOT 0 +#define IMX8M_NOC_CLK_ROOT 26 #define IMX8M_NOC_IO_CLK_ROOT 27 #define IMX8M_DRAM_SEL_CFG 48 #define IMX8M_DRAM_ALT_CLK_ROOT 64 -- 2.47.3