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The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: barebox derives the 200MHz dram_apb clock from sys_pll1_800m divided by 4, while U-Boot's clock_init() selects sys_pll2_200m, which needs no divider. Let's do the same, so both can be compared side by [...] Content analysis details: (-2.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.0 DMARC_MISSING Missing DMARC policy X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-Spamd-Result: default: False [-58.91 / 15.00]; RECEIVED_AUTHENTICATED_BY_MX1(-50.00)[]; BAYES_HAM(-3.00)[99.99%]; DWL_DNSWL_MED(-2.00)[infradead.org:dkim]; ARC_ALLOW_TRUSTED(-2.00)[pengutronix.de:s=20260414:i=1]; KNOWN_LIST_ID(-1.00)[barebox.lists.infradead.org]; ARC_ALLOW(-1.00)[pengutronix.de:s=20260414:i=1]; MID_CONTAINS_FROM(1.00)[]; RCVD_DKIM_ARC_DNSWL_MED(-0.50)[]; R_MISSING_CHARSET(0.50)[]; R_DKIM_ALLOW(-0.20)[lists.infradead.org:s=bombadil.20210309,pengutronix.de:s=20260414]; R_SPF_ALLOW(-0.20)[+mx:c]; MAILLIST(-0.20)[mailman]; RCVD_IN_DNSWL_MED(-0.20)[2607:7c80:54:3::133:from]; MIME_GOOD(-0.10)[text/plain]; HAS_LIST_UNSUB(-0.01)[]; RCPT_COUNT_TWO(0.00)[2]; ARC_SIGNED(0.00)[pengutronix.de:s=20260414:i=2]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; FROM_HAS_DN(0.00)[]; DMARC_NA(0.00)[pengutronix.de]; RCVD_COUNT_THREE(0.00)[4]; NEURAL_HAM(-0.00)[-1.000]; RCVD_TLS_LAST(0.00)[]; ASN(0.00)[asn:7247, ipnet:2607:7c80:54::/48, country:US]; RCVD_VIA_SMTP_AUTH(0.00)[]; RECEIVED_HELO_LOCALHOST(0.00)[]; DKIM_TRACE(0.00)[lists.infradead.org:+,pengutronix.de:+]; TAGGED_FROM(0.00)[lore=pengutronix.de]; FROM_NEQ_ENVFROM(0.00)[a.fatoum@pengutronix.de,barebox-bounces@lists.infradead.org]; FORGED_SENDER_MAILLIST(0.00)[] X-Rspamd-Action: no action X-Rspamd-Server: mx1 X-Rspamd-Queue-Id: 48DC0200758 X-Stat-Signature: emicgmodggz1fddkenbxewk97wo97yxi barebox derives the 200MHz dram_apb clock from sys_pll1_800m divided by 4, while U-Boot's clock_init() selects sys_pll2_200m, which needs no divider. Let's do the same, so both can be compared side by side. Move the DRAM clock setup below the code enabling the SYS_PLL2 outputs, where U-Boot has it as well. This is ordering only: all SYS_PLL2 outputs are enabled at reset already. No functional change: imx8m_ddr_init() reconfigures DRAM_APB_CLK_ROOT via ddrphy_init_set_dfi_clk() before the DDRC is first accessed, so the value set here is overwritten before any register access uses it. Signed-off-by: Ahmad Fatoum --- arch/arm/mach-imx/imx8m.c | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c index 66a3b376ed94..23a920ffae2e 100644 --- a/arch/arm/mach-imx/imx8m.c +++ b/arch/arm/mach-imx/imx8m.c @@ -59,20 +59,6 @@ static void __imx8m_early_clock_init(int cpu_type) void __iomem *ana = IOMEM(MX8M_ANATOP_BASE_ADDR); u32 val; - imx8m_ccgr_clock_disable(IMX8M_CCM_CCGR_DDR1); - - imx8m_clock_set_target_val(IMX8M_DRAM_ALT_CLK_ROOT, - IMX8M_CCM_TARGET_ROOTn_ENABLE | - IMX8M_CCM_TARGET_ROOTn_MUX(1)); - - /* change the clock source of dram_apb_clk_root: source 4 800MHz /4 = 200MHz */ - imx8m_clock_set_target_val(IMX8M_DRAM_APB_CLK_ROOT, - IMX8M_CCM_TARGET_ROOTn_ENABLE | - IMX8M_CCM_TARGET_ROOTn_MUX(4) | - IMX8M_CCM_TARGET_ROOTn_POST_DIV(4 - 1)); - - imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_DDR1); - /* * The gate is not exported to clk tree, so configure them here. * According to ANAMIX SPEC @@ -96,6 +82,19 @@ static void __imx8m_early_clock_init(int cpu_type) INTPLL_DIV20_CLKE_MASK; writel(val, ana + IMX8MM_CCM_ANALOG_SYS_PLL2_GEN_CTRL); + imx8m_ccgr_clock_disable(IMX8M_CCM_CCGR_DDR1); + + imx8m_clock_set_target_val(IMX8M_DRAM_ALT_CLK_ROOT, + IMX8M_CCM_TARGET_ROOTn_ENABLE | + IMX8M_CCM_TARGET_ROOTn_MUX(1)); + + /* change the clock source of dram_apb_clk_root: source 1 sys_pll2_200m */ + imx8m_clock_set_target_val(IMX8M_DRAM_APB_CLK_ROOT, + IMX8M_CCM_TARGET_ROOTn_ENABLE | + IMX8M_CCM_TARGET_ROOTn_MUX(1)); + + imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_DDR1); + if (cpu_type != IMX_CPU_IMX8MP) { /* 8MP ROM already set GIC to 400Mhz, system_pll1_800m with div = 2 */ /* For everything else, config GIC to sys_pll2_100m */ -- 2.47.3