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The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: The clocks configured in __imx8m_early_clock_init() now match U-Boot's clock_init(), but are written in a different order: DRAM first, then GIC, SYS_PLL3, NOC and the ARM PLL last. U-Boot sets up the ARM PLL right after enabling the SYS_PLL1/2 outputs, then SYS_PLL3 and its NOC consumer, the GIC root and the DRAM clocks last. Reorder to the same sequence, so the two can be compa [...] Content analysis details: (-2.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.0 DMARC_MISSING Missing DMARC policy X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-Spamd-Result: default: False [-58.91 / 15.00]; RECEIVED_AUTHENTICATED_BY_MX1(-50.00)[]; BAYES_HAM(-3.00)[99.99%]; DWL_DNSWL_MED(-2.00)[infradead.org:dkim]; ARC_ALLOW_TRUSTED(-2.00)[pengutronix.de:s=20260414:i=1]; KNOWN_LIST_ID(-1.00)[barebox.lists.infradead.org]; ARC_ALLOW(-1.00)[pengutronix.de:s=20260414:i=1]; MID_CONTAINS_FROM(1.00)[]; RCVD_DKIM_ARC_DNSWL_MED(-0.50)[]; R_MISSING_CHARSET(0.50)[]; R_DKIM_ALLOW(-0.20)[lists.infradead.org:s=bombadil.20210309,pengutronix.de:s=20260414]; R_SPF_ALLOW(-0.20)[+mx:c]; MAILLIST(-0.20)[mailman]; RCVD_IN_DNSWL_MED(-0.20)[2607:7c80:54:3::133:from]; MIME_GOOD(-0.10)[text/plain]; HAS_LIST_UNSUB(-0.01)[]; RCPT_COUNT_TWO(0.00)[2]; ARC_SIGNED(0.00)[pengutronix.de:s=20260414:i=2]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; FROM_HAS_DN(0.00)[]; DMARC_NA(0.00)[pengutronix.de]; RCVD_COUNT_THREE(0.00)[4]; NEURAL_HAM(-0.00)[-1.000]; RCVD_TLS_LAST(0.00)[]; ASN(0.00)[asn:7247, ipnet:2607:7c80:54::/48, country:US]; RCVD_VIA_SMTP_AUTH(0.00)[]; RECEIVED_HELO_LOCALHOST(0.00)[]; DKIM_TRACE(0.00)[lists.infradead.org:+,pengutronix.de:+]; TAGGED_FROM(0.00)[lore=pengutronix.de]; FROM_NEQ_ENVFROM(0.00)[a.fatoum@pengutronix.de,barebox-bounces@lists.infradead.org]; FORGED_SENDER_MAILLIST(0.00)[] X-Rspamd-Action: no action X-Rspamd-Server: mx1 X-Rspamd-Queue-Id: 3ABD4201F18 X-Stat-Signature: zombyiuo76ij1za3k9rsc5rkjiakohsr The clocks configured in __imx8m_early_clock_init() now match U-Boot's clock_init(), but are written in a different order: DRAM first, then GIC, SYS_PLL3, NOC and the ARM PLL last. U-Boot sets up the ARM PLL right after enabling the SYS_PLL1/2 outputs, then SYS_PLL3 and its NOC consumer, the GIC root and the DRAM clocks last. Reorder to the same sequence, so the two can be compared side by side. The remaining differences are: - barebox doesn't touch the NAND_USDHC_BUS and watchdog roots or the TEMP_SENSOR and SEC_DEBUG gates in the PBL - NXP's downstream U-Boot additionally configures the display clocks in clock_init() (VIDEO_PLL at 594MHz, the DISPLAY_AXI/APB and MIPI DSI roots, DISPMIX gate) These are skipped as both barebox and Linux will configure these clocks if needed before using them. Every root and gate ends up with the same value, and each source is enabled before a root is switched to it in either order. No functional change. Assisted-by: Claude:fable-5.1 Signed-off-by: Ahmad Fatoum --- arch/arm/mach-imx/imx8m.c | 83 +++++++++++++++++++-------------------- 1 file changed, 40 insertions(+), 43 deletions(-) diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c index 23a920ffae2e..b9f8906d6ed2 100644 --- a/arch/arm/mach-imx/imx8m.c +++ b/arch/arm/mach-imx/imx8m.c @@ -82,6 +82,46 @@ static void __imx8m_early_clock_init(int cpu_type) INTPLL_DIV20_CLKE_MASK; writel(val, ana + IMX8MM_CCM_ANALOG_SYS_PLL2_GEN_CTRL); + /* Configure ARM at 1.2GHz */ + imx8m_clock_set_target_val(IMX8M_ARM_A53_CLK_ROOT, + IMX8M_CCM_TARGET_ROOTn_ENABLE | + IMX8M_CCM_TARGET_ROOTn_MUX(2)); + + clk_pll1416x_early_configure(ana + IMX8MM_CCM_ANALOG_ARM_PLL_GEN_CTRL, + 1200000000UL, 25000000UL); + + /* Bypass the A53 root and feed the cores from arm_pll_out directly */ + imx8m_clock_set_target_val(IMX8M_CORE_SEL_CFG, + IMX8M_CCM_TARGET_ROOTn_MUX(1)); + + if (cpu_type == IMX_CPU_IMX8MN || cpu_type == IMX_CPU_IMX8MP) + pll3_freq = 600000000UL; + else + pll3_freq = 750000000UL; + + /* Configure SYS_PLL3 */ + clk_pll1416x_early_configure(ana + IMX8MM_CCM_ANALOG_SYS_PLL3_GEN_CTRL, + pll3_freq, 25000000UL); + + if (cpu_type == IMX_CPU_IMX8MP) { + /* NOC_IO from sys_pll3_out, barebox proper sets NOC and GIC */ + imx8m_clock_set_target_val(IMX8M_NOC_IO_CLK_ROOT, + IMX8M_CCM_TARGET_ROOTn_ENABLE | + IMX8M_CCM_TARGET_ROOTn_MUX(2)); + } else { + /* NOC from undivided sys_pll3_out */ + imx8m_clock_set_target_val(IMX8M_NOC_CLK_ROOT, + IMX8M_CCM_TARGET_ROOTn_ENABLE | + IMX8M_CCM_TARGET_ROOTn_MUX(2)); + + /* config GIC to sys_pll2_100m */ + imx8m_ccgr_clock_disable(IMX8M_CCM_CCGR_GIC); + imx8m_clock_set_target_val(IMX8M_GIC_CLK_ROOT, + IMX8M_CCM_TARGET_ROOTn_ENABLE | + IMX8M_CCM_TARGET_ROOTn_MUX(3)); + imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_GIC); + } + imx8m_ccgr_clock_disable(IMX8M_CCM_CCGR_DDR1); imx8m_clock_set_target_val(IMX8M_DRAM_ALT_CLK_ROOT, @@ -94,49 +134,6 @@ static void __imx8m_early_clock_init(int cpu_type) IMX8M_CCM_TARGET_ROOTn_MUX(1)); imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_DDR1); - - if (cpu_type != IMX_CPU_IMX8MP) { - /* 8MP ROM already set GIC to 400Mhz, system_pll1_800m with div = 2 */ - /* For everything else, config GIC to sys_pll2_100m */ - imx8m_ccgr_clock_disable(IMX8M_CCM_CCGR_GIC); - imx8m_clock_set_target_val(IMX8M_GIC_CLK_ROOT, - IMX8M_CCM_TARGET_ROOTn_ENABLE | - IMX8M_CCM_TARGET_ROOTn_MUX(3)); - imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_GIC); - } - - if (cpu_type == IMX_CPU_IMX8MN || cpu_type == IMX_CPU_IMX8MP) - pll3_freq = 600000000UL; - else - pll3_freq = 750000000UL; - - /* Configure SYS_PLL3 */ - clk_pll1416x_early_configure(ana + IMX8MM_CCM_ANALOG_SYS_PLL3_GEN_CTRL, - pll3_freq, 25000000UL); - - if (cpu_type == IMX_CPU_IMX8MP) { - /* 8MP ROM already set NOC to 800Mhz, only need to configure NOC_IO clk to 600Mhz */ - imx8m_clock_set_target_val(IMX8M_NOC_IO_CLK_ROOT, - IMX8M_CCM_TARGET_ROOTn_ENABLE | - IMX8M_CCM_TARGET_ROOTn_MUX(2)); - } else { - /* NOC from undivided sys_pll3_out */ - imx8m_clock_set_target_val(IMX8M_NOC_CLK_ROOT, - IMX8M_CCM_TARGET_ROOTn_ENABLE | - IMX8M_CCM_TARGET_ROOTn_MUX(2)); - } - - imx8m_clock_set_target_val(IMX8M_ARM_A53_CLK_ROOT, - IMX8M_CCM_TARGET_ROOTn_ENABLE | - IMX8M_CCM_TARGET_ROOTn_MUX(2)); - - /* Configure ARM PLL to 1.2GHz */ - clk_pll1416x_early_configure(ana + IMX8MM_CCM_ANALOG_ARM_PLL_GEN_CTRL, - 1200000000UL, 25000000UL); - - /* Bypass the A53 root and feed the cores from arm_pll_out directly */ - imx8m_clock_set_target_val(IMX8M_CORE_SEL_CFG, - IMX8M_CCM_TARGET_ROOTn_MUX(1)); } void imx8mm_early_clock_init(void) -- 2.47.3