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The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: The image of the first stage boot loader on the Agilex 5 is limited to approximately 256k. The SRAM is actually 512k, but there is some handoff data at the send of the SRAM, which must not be overridd [...] Content analysis details: (-2.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.0 DMARC_MISSING Missing DMARC policy X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-Spamd-Result: default: False [-60.81 / 15.00]; RECEIVED_AUTHENTICATED_BY_MX1(-50.00)[]; BAYES_HAM(-3.00)[100.00%]; ARC_ALLOW_TRUSTED(-2.00)[pengutronix.de:s=20260414:i=1]; DWL_DNSWL_MED(-2.00)[infradead.org:dkim]; KNOWN_LIST_ID(-1.00)[barebox.lists.infradead.org]; ARC_ALLOW(-1.00)[pengutronix.de:s=20260414:i=1]; RCVD_IN_DNSWL_MED(-0.60)[2a0a:edc0:0:1101:1d::54:received,2607:7c80:54:3::133:from,2a0a:edc0:0:c01:1d::a2:received]; RCVD_DKIM_ARC_DNSWL_MED(-0.50)[]; R_DKIM_ALLOW(-0.20)[lists.infradead.org:s=bombadil.20210309,pengutronix.de:s=20260414]; MAILLIST(-0.20)[mailman]; R_SPF_ALLOW(-0.20)[+mx:c]; MIME_GOOD(-0.10)[text/plain]; HAS_LIST_UNSUB(-0.01)[]; RECEIVED_HELO_LOCALHOST(0.00)[]; RCVD_COUNT_THREE(0.00)[4]; DMARC_NA(0.00)[pengutronix.de]; FORGED_SENDER(0.00)[m.tretter@pengutronix.de,barebox-bounces@lists.infradead.org]; RCVD_TLS_LAST(0.00)[]; MIME_TRACE(0.00)[0:+]; FORWARDED(0.00)[barebox@lists.infradead.org]; TO_DN_ALL(0.00)[]; RCPT_COUNT_THREE(0.00)[3]; DKIM_TRACE(0.00)[lists.infradead.org:+,pengutronix.de:+]; FORGED_SENDER_FORWARDING(0.00)[]; FROM_NEQ_ENVFROM(0.00)[m.tretter@pengutronix.de,barebox-bounces@lists.infradead.org]; FROM_HAS_DN(0.00)[]; TAGGED_FROM(0.00)[lore=pengutronix.de]; NEURAL_HAM(-0.00)[-1.000]; RCVD_VIA_SMTP_AUTH(0.00)[]; MID_RHS_MATCH_FROM(0.00)[]; ARC_SIGNED(0.00)[pengutronix.de:s=20260414:i=2]; ASN(0.00)[asn:7247, ipnet:2607:7c80:54::/48, country:US]; FORGED_SENDER_MAILLIST(0.00)[] X-Rspamd-Action: no action X-Rspamd-Server: mx1 X-Rspamd-Queue-Id: 6C04B201D41 X-Stat-Signature: gg5de9qcq179kg81dricjs3o11d9jjc8 The image of the first stage boot loader on the Agilex 5 is limited to approximately 256k. The SRAM is actually 512k, but there is some handoff data at the send of the SRAM, which must not be overridden. There are some size checks, but due to compression of the FSBL image, it's the possible image size cannot be determined reliably. The barebox PBL and a full featured barebox proper are easily larger than the allowed size. Compression of the piggy data may even be counter productive, since the entire FSBL image is compressed again when creating the boot image. Add support to remove the piggy data from the FSBL image, and load the second stage (consisting of a barebox PBL and barebox proper) from flash in the PBL. Patches 1-4 rework the Cadence QSPI NOR flash driver to be available in the PBL via the pbl_bio abstraction. Patches 5-9 extend the Agilex 5 support to initialize the flash driver in the PBL and chain load an SSBL as bl33 instead of copying the currently running barebox. The patches also add the infrastructure to build the PBL without piggy data and device tree. Patches 10-11 enable the xload support in the Arrow AXE5 Eagle board. Signed-off-by: Michael Tretter --- Michael Tretter (11): mtd: spi-nor: drop requirement for device field mtd: spi-nor: enable module in PBL mtd: spi-nor: cadence: extract common part for use in PBL mtd: spi-nor: cadence: add a PBL driver arm: socfpga: agilex5: add bl33 xload support arm: socfpga: agilex5: separate load and start of bl33 arm: socfpga: agilex5: enable xload for bl33 arm: socfpga: agilex5: initialize QSPI flash in PBL arm: socfpga: agilex5: add agilex5_barebox_entry_xload arm: socfpga: axe5-eagle: move lowlevel init to separate function arm: socfpga: axe5-eagle: build FSBL without piggy data arch/arm/boards/arrow-axe5-eagle/lowlevel.c | 31 +- arch/arm/mach-socfpga/Kconfig | 43 +- arch/arm/mach-socfpga/Makefile | 3 + arch/arm/mach-socfpga/agilex5-xload.c | 74 +++ arch/arm/mach-socfpga/atf.c | 83 ++- drivers/mtd/spi-nor/Kconfig | 3 + drivers/mtd/spi-nor/Makefile | 5 +- drivers/mtd/spi-nor/cadence-quadspi-common.c | 615 +++++++++++++++++++++ drivers/mtd/spi-nor/cadence-quadspi-pbl.c | 104 ++++ drivers/mtd/spi-nor/cadence-quadspi.c | 794 +-------------------------- drivers/mtd/spi-nor/cadence-quadspi.h | 216 ++++++++ drivers/mtd/spi-nor/spi-nor.c | 3 +- images/Makefile.socfpga | 5 + include/mach/socfpga/generic.h | 16 + include/pbl/mtd.h | 26 + 15 files changed, 1210 insertions(+), 811 deletions(-) --- base-commit: 70421fc4591e6b4b9c7172ca72b60ef1868ecc5c change-id: 20261007-socfpga-agilex5-xload-f3f89721453b Best regards, -- Michael Tretter