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Wed, 07 Oct 2026 12:55:48 +0200 From: Michael Tretter Date: Wed, 07 Oct 2026 12:55:56 +0200 Subject: [PATCH 11/11] arm: socfpga: axe5-eagle: build FSBL without piggy data MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261007-socfpga-agilex5-xload-v1-11-f8fb2d2819da@pengutronix.de> References: <20261007-socfpga-agilex5-xload-v1-0-f8fb2d2819da@pengutronix.de> In-Reply-To: <20261007-socfpga-agilex5-xload-v1-0-f8fb2d2819da@pengutronix.de> To: Sascha Hauer , BAREBOX Cc: Michael Tretter X-Mailer: b4 0.14.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261007_041501_646321_9590B52F X-CRM114-Status: GOOD ( 14.16 ) X-Spam-Score: -2.1 (--) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Add xload support to the Arrow AXE5 Eagle board and remove the piggy data from the FSBL. The load address and size are set via the barebox configuration, because they depend on the partition layout in flash, which is configured when configuring the flash image in Quartus. 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The load address and size are set via the barebox configuration, because they depend on the partition layout in flash, which is configured when configuring the flash image in Quartus. Signed-off-by: Michael Tretter --- arch/arm/boards/arrow-axe5-eagle/lowlevel.c | 24 ++++++++++++++++++++++ arch/arm/mach-socfpga/Kconfig | 32 ++++++++++++++++++++++++++++- images/Makefile.socfpga | 5 +++++ 3 files changed, 60 insertions(+), 1 deletion(-) diff --git a/arch/arm/boards/arrow-axe5-eagle/lowlevel.c b/arch/arm/boards/arrow-axe5-eagle/lowlevel.c index bf98515f28d8..7b7f699655a1 100644 --- a/arch/arm/boards/arrow-axe5-eagle/lowlevel.c +++ b/arch/arm/boards/arrow-axe5-eagle/lowlevel.c @@ -13,6 +13,11 @@ extern char __dtb_z_socfpga_agilex5_axe5_eagle_start[]; +static struct socfpga_barebox_part axe5_eagle_barebox_part = { + .nor_offset = CONFIG_MACH_SOCFPGA_ARROW_AXE5_EAGLE_XLOAD_ADDR, + .nor_size = CONFIG_MACH_SOCFPGA_ARROW_AXE5_EAGLE_XLOAD_SIZE, +}; + static void axe5_eagle_lowlevel_init(void) { void __iomem *uart = IOMEM(SOCFPGA_UART_BASE(0)); @@ -30,6 +35,14 @@ static noinline void axe5_eagle_continue(void) agilex5_barebox_entry(__dtb_z_socfpga_agilex5_axe5_eagle_start); } +static noinline void axe5_eagle_continue_xload(void) +{ + axe5_eagle_lowlevel_init(); + + agilex5_set_barebox_part(&axe5_eagle_barebox_part); + agilex5_barebox_entry_xload(); +} + ENTRY_FUNCTION_AGILEX5(start_socfpga_agilex5_axe5_eagle) { if (current_el() == 3) @@ -40,3 +53,14 @@ ENTRY_FUNCTION_AGILEX5(start_socfpga_agilex5_axe5_eagle) axe5_eagle_continue(); } + +ENTRY_FUNCTION_AGILEX5(start_socfpga_agilex5_axe5_eagle_xload) +{ + if (current_el() == 3) + socfpga_agilex5_cpu_lowlevel_init(); + + relocate_to_current_adr(); + setup_c(); + + axe5_eagle_continue_xload(); +} diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 55d7b12200c9..915bae352b0e 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -79,10 +79,40 @@ if 64BIT comment "Agilex 5 boards" -config MACH_SOCFPGA_ARROW_AXE5_EAGLE +menuconfig MACH_SOCFPGA_ARROW_AXE5_EAGLE bool "Arrow AXE5 Eagle" select ARCH_SOCFPGA_AGILEX5 +config MACH_SOCFPGA_ARROW_AXE5_EAGLE_XLOAD + bool "Build Arrow AXE5 Eagle FSBL without piggy data" + depends on MACH_SOCFPGA_ARROW_AXE5_EAGLE + select SOCFPGA_AGILEX5_XLOAD + select SPI_CADENCE_QUADSPI_PBL + help + This option reduces the binary size of the FSBL and makes it + independent of the enabled features of the SSBL, but requires SSBL + xload support. + +config MACH_SOCFPGA_ARROW_AXE5_EAGLE_XLOAD_ADDR + depends on MACH_SOCFPGA_ARROW_AXE5_EAGLE_XLOAD + prompt "Start address of the Arrow AXE5 SSBL on flash" + hex + default 0x01000000 + help + barebox tries to load an SSBL from this address in the QSPI flash. + + Keep this address in sync with your QSPI image configuration. + +config MACH_SOCFPGA_ARROW_AXE5_EAGLE_XLOAD_SIZE + depends on MACH_SOCFPGA_ARROW_AXE5_EAGLE_XLOAD + prompt "Maximum size of the Arrow AXE5 SSBL on flash" + hex + default 0x00400000 + help + The maximum size of the SSBL in the QSPI flash. + + Keep this size in sync with your QSPI image configuration. + endif comment "board features" diff --git a/images/Makefile.socfpga b/images/Makefile.socfpga index ec1bce5079c9..38bb27ac0e58 100644 --- a/images/Makefile.socfpga +++ b/images/Makefile.socfpga @@ -96,8 +96,13 @@ FILE_barebox-socfpga-socrates.img = start_socfpga_socrates.pblb socfpga-barebox-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += barebox-socfpga-socrates.img # ----------------------- Agilex5 based boards --------------------------- +#ifdef MACH_SOCFPGA_ARROW_AXE5_EAGLE_XLOAD +pblb-$(CONFIG_MACH_SOCFPGA_ARROW_AXE5_EAGLE) += start_socfpga_agilex5_axe5_eagle_xload +FILE_barebox-socfpga-agilex5-axe5-eagle.img = start_socfpga_agilex5_axe5_eagle_xload.pblb.hex +#else pblb-$(CONFIG_MACH_SOCFPGA_ARROW_AXE5_EAGLE) += start_socfpga_agilex5_axe5_eagle FILE_barebox-socfpga-agilex5-axe5-eagle.img = start_socfpga_agilex5_axe5_eagle.pblb.hex +#endif socfpga-barebox-$(CONFIG_MACH_SOCFPGA_ARROW_AXE5_EAGLE) += barebox-socfpga-agilex5-axe5-eagle.img pblb-$(CONFIG_MACH_SOCFPGA_ARROW_AXE5_EAGLE) += start_socfpga_agilex5_axe5_eagle -- 2.47.3