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Wed, 07 Oct 2026 12:55:47 +0200 From: Michael Tretter Date: Wed, 07 Oct 2026 12:55:49 +0200 Subject: [PATCH 04/11] mtd: spi-nor: cadence: add a PBL driver MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261007-socfpga-agilex5-xload-v1-4-f8fb2d2819da@pengutronix.de> References: <20261007-socfpga-agilex5-xload-v1-0-f8fb2d2819da@pengutronix.de> In-Reply-To: <20261007-socfpga-agilex5-xload-v1-0-f8fb2d2819da@pengutronix.de> To: Sascha Hauer , BAREBOX Cc: Michael Tretter X-Mailer: b4 0.14.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261007_115552_360357_51AC6EBB X-CRM114-Status: GOOD ( 18.05 ) X-Spam-Score: -0.2 (/) X-Spam-Report: Spam detection software, running on the system "desiato.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Integrate the Cadence QSPI driver with read-only support into the PBL with a pbl_bio abstraction. This allows to load additional binaries and firmware from the flash while still in the PBL without req [...] Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.0 DMARC_MISSING Missing DMARC policy X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-Spamd-Result: default: False [-61.01 / 15.00]; RECEIVED_AUTHENTICATED_BY_MX1(-50.00)[]; BAYES_HAM(-3.00)[100.00%]; DWL_DNSWL_MED(-2.00)[infradead.org:dkim]; ARC_ALLOW_TRUSTED(-2.00)[pengutronix.de:s=20260414:i=1]; ARC_ALLOW(-1.00)[pengutronix.de:s=20260414:i=1]; KNOWN_LIST_ID(-1.00)[barebox.lists.infradead.org]; RCVD_IN_DNSWL_MED(-0.80)[2a0a:edc0:0:1101:1d::54:received,2a0a:edc0:0:c01:1d::a2:received,2607:7c80:54:3::133:from,2001:8b0:10b:1:d65d:64ff:fe57:4e05:received]; RCVD_DKIM_ARC_DNSWL_MED(-0.50)[]; MAILLIST(-0.20)[mailman]; R_DKIM_ALLOW(-0.20)[lists.infradead.org:s=bombadil.20210309,pengutronix.de:s=20260414]; R_SPF_ALLOW(-0.20)[+mx:c]; MIME_GOOD(-0.10)[text/plain]; HAS_LIST_UNSUB(-0.01)[]; RCVD_TLS_LAST(0.00)[]; FORWARDED(0.00)[barebox@bombadil.infradead.org]; TO_DN_ALL(0.00)[]; FORGED_SENDER(0.00)[m.tretter@pengutronix.de,barebox-bounces@lists.infradead.org]; DMARC_NA(0.00)[pengutronix.de]; TAGGED_FROM(0.00)[lore=pengutronix.de]; MIME_TRACE(0.00)[0:+]; RECEIVED_HELO_LOCALHOST(0.00)[]; RCPT_COUNT_THREE(0.00)[3]; DKIM_MIXED(0.00)[]; FORGED_SENDER_FORWARDING(0.00)[]; RCVD_COUNT_FIVE(0.00)[5]; FROM_NEQ_ENVFROM(0.00)[m.tretter@pengutronix.de,barebox-bounces@lists.infradead.org]; FROM_HAS_DN(0.00)[]; R_DKIM_REJECT(0.00)[infradead.org:s=desiato.20200630]; NEURAL_HAM(-0.00)[-1.000]; RCVD_VIA_SMTP_AUTH(0.00)[]; DKIM_TRACE(0.00)[lists.infradead.org:+,infradead.org:-,pengutronix.de:+]; MID_RHS_MATCH_FROM(0.00)[]; ARC_SIGNED(0.00)[pengutronix.de:s=20260414:i=2]; ASN(0.00)[asn:7247, ipnet:2607:7c80:54::/48, country:US]; FORGED_SENDER_MAILLIST(0.00)[] X-Rspamd-Action: no action X-Rspamd-Server: mx1 X-Rspamd-Queue-Id: BB04B201E69 X-Stat-Signature: ty79mt7qjoup9gggsy64yka7fa6cornn Integrate the Cadence QSPI driver with read-only support into the PBL with a pbl_bio abstraction. This allows to load additional binaries and firmware from the flash while still in the PBL without requiring a full barebox proper. Signed-off-by: Michael Tretter --- drivers/mtd/spi-nor/Kconfig | 3 + drivers/mtd/spi-nor/Makefile | 1 + drivers/mtd/spi-nor/cadence-quadspi-pbl.c | 104 ++++++++++++++++++++++++++++++ include/pbl/mtd.h | 26 ++++++++ 4 files changed, 134 insertions(+) diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig index b34c69203ec2..e703ce707c5b 100644 --- a/drivers/mtd/spi-nor/Kconfig +++ b/drivers/mtd/spi-nor/Kconfig @@ -26,6 +26,9 @@ config SPI_CADENCE_QUADSPI help This enables support for the Cadence Quad SPI controller and NOR flash. +config SPI_CADENCE_QUADSPI_PBL + bool + config SPI_SYNOPSYS_OCTALSPI_NOR tristate "Synopsys DesignWare Octal SPI controller" help diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile index ed73a95ec6b9..9e229a37ddfb 100644 --- a/drivers/mtd/spi-nor/Makefile +++ b/drivers/mtd/spi-nor/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only obj-pbl-$(CONFIG_MTD_SPI_NOR) += spi-nor.o obj-$(CONFIG_SPI_CADENCE_QUADSPI) += cadence-quadspi.o cadence-quadspi-common.o +pbl-$(CONFIG_SPI_CADENCE_QUADSPI_PBL) += cadence-quadspi-pbl.o cadence-quadspi-common.o obj-$(CONFIG_SPI_SYNOPSYS_OCTALSPI_NOR) += dw-ospi-nor.o diff --git a/drivers/mtd/spi-nor/cadence-quadspi-pbl.c b/drivers/mtd/spi-nor/cadence-quadspi-pbl.c new file mode 100644 index 000000000000..b2bb00d15dc7 --- /dev/null +++ b/drivers/mtd/spi-nor/cadence-quadspi-pbl.c @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include + +#include "cadence-quadspi.h" + +static void cqspi_write(struct spi_nor *nor, loff_t to, + size_t len, size_t *retlen, const u_char *buf) +{ +} + +static int cqspi_get_flash_pdata(struct cqspi_st *cqspi, + struct cqspi_flash_pdata *f_pdata) +{ + void __iomem *reg_base = cqspi->iobase; + + f_pdata->block_size = (readl(reg_base + CQSPI_REG_SIZE) >> + CQSPI_REG_SIZE_BLOCK_LSB) & + CQSPI_REG_SIZE_BLOCK_MASK; + cqspi->no_reconfig = true; + + return 0; +} + +static int cqspi_setup_flash(struct cqspi_st *cqspi, + struct cqspi_flash_pdata *f_pdata) +{ + const struct spi_nor_hwcaps hwcaps = { + .mask = SNOR_HWCAPS_READ | + SNOR_HWCAPS_READ_FAST | + SNOR_HWCAPS_READ_1_1_2 | + SNOR_HWCAPS_READ_1_1_4 | + SNOR_HWCAPS_PP, + }; + struct spi_nor *nor; + struct mtd_info *mtd; + int ret; + + ret = cqspi_get_flash_pdata(cqspi, f_pdata); + if (ret) + return ret; + + nor = &f_pdata->nor; + mtd = &f_pdata->mtd; + + nor->mtd = mtd; + + nor->priv = cqspi; + nor->read_reg = cqspi_read_reg; + nor->write_reg = cqspi_write_reg; + nor->read = cqspi_read; + nor->write = cqspi_write; + + return spi_nor_scan(nor, NULL, &hwcaps, false); +} + +static int cqspi_bio_read(struct pbl_bio *bio, off_t start, + void *buf, unsigned int nblocks) +{ + struct cqspi_st *cqspi = bio->priv; + struct spi_nor *nor = &cqspi->f_pdata[0].nor; + int ret; + size_t count = 0; + + ret = nor->read(nor, start, nblocks, &count, buf); + if (ret) + return ret; + + return count; +} + +static struct cqspi_st cqspi; + +int cqspi_bio_init(struct pbl_bio *bio, + void __iomem *iobase, void __iomem *ahb_base, + unsigned int master_ref_clk, + struct cadence_qspi_platform_data *qspi_pdata) +{ + cqspi.master_ref_clk_hz = master_ref_clk; + cqspi.iobase = iobase; + cqspi.ahb_base = ahb_base; + + cqspi_wait_idle(&cqspi); + cqspi_controller_init(&cqspi); + + cqspi.current_cs = -1; + cqspi.sclk = 0; + + cqspi.is_decoded_cs = qspi_pdata->is_decoded_cs; + cqspi.fifo_depth = qspi_pdata->fifo_depth; + + cqspi_setup_flash(&cqspi, &cqspi.f_pdata[0]); + + bio->priv = &cqspi; + bio->read = cqspi_bio_read; + + return 0; +} diff --git a/include/pbl/mtd.h b/include/pbl/mtd.h new file mode 100644 index 000000000000..f58b61d29997 --- /dev/null +++ b/include/pbl/mtd.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __PBL_MTD_H__ +#define __PBL_MTD_H__ + +#include + +struct pbl_bio; + +#include + +#ifdef CONFIG_SPI_CADENCE_QUADSPI_PBL +int cqspi_bio_init(struct pbl_bio *bio, + void __iomem *iobase, void __iomem *ahb_base, + unsigned int master_ref_clk, + struct cadence_qspi_platform_data *qspi_pdata); +#else +static inline int cqspi_bio_init(struct pbl_bio *bio, + void __iomem *iobase, void __iomem *ahb_base, + unsigned int master_ref_clk, + struct cadence_qspi_platform_data *qspi_pdata) +{ + return -ENOSYS; +} +#endif + +#endif /* __PBL_MTD_H__ */ -- 2.47.3