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Wed, 07 Oct 2026 12:55:48 +0200 From: Michael Tretter Date: Wed, 07 Oct 2026 12:55:50 +0200 Subject: [PATCH 05/11] arm: socfpga: agilex5: add bl33 xload support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261007-socfpga-agilex5-xload-v1-5-f8fb2d2819da@pengutronix.de> References: <20261007-socfpga-agilex5-xload-v1-0-f8fb2d2819da@pengutronix.de> In-Reply-To: <20261007-socfpga-agilex5-xload-v1-0-f8fb2d2819da@pengutronix.de> To: Sascha Hauer , BAREBOX Cc: Michael Tretter X-Mailer: b4 0.14.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261007_035557_805150_3DCEDB8A X-CRM114-Status: GOOD ( 17.55 ) X-Spam-Score: -2.1 (--) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: The size of the FSBL on Agilex 5 is limited by the size of the available SRAM (512k), but there are additional limits imposed by the tooling which limit the possible size of the FSBL to about 256k. Add xload support to the Agilex 5 PBL to optionally xload a barebox image as bl33 from another boot medium. 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Add xload support to the Agilex 5 PBL to optionally xload a barebox image as bl33 from another boot medium. Signed-off-by: Michael Tretter --- arch/arm/mach-socfpga/Kconfig | 11 ++++++ arch/arm/mach-socfpga/Makefile | 3 ++ arch/arm/mach-socfpga/agilex5-xload.c | 74 +++++++++++++++++++++++++++++++++++ include/mach/socfpga/generic.h | 15 +++++++ 4 files changed, 103 insertions(+) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index a836711e6c40..55d7b12200c9 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -92,4 +92,15 @@ config ARCH_SOCFPGA_XLOAD depends on ARCH_SOCFPGA_CYCLONE5 prompt "Build SoCFPGA preloader image" +config SOCFPGA_AGILEX5_XLOAD + bool + depends on ARCH_SOCFPGA_AGILEX5 + prompt "Support SSBL xloading on Agilex 5" + help + On Agilex 5, the FSBL binary is limited to a size of ~256k. Enable + XLOAD support to load the SSBL from a separate medium and allow + larger bootloader images. + + Note that the SSBL loading has to be configured in the board code. + endmenu diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 6a8117874136..f061d82f01dd 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -22,6 +22,9 @@ pbl-$(CONFIG_ARCH_SOCFPGA_AGILEX5) += soc64-system-manager.o \ agilex5-secreg.o \ agilex5-clock-manager.o \ atf.o +ifdef CONFIG_SOCFPGA_AGILEX5_XLOAD +pbl-$(CONFIG_ARCH_SOCFPGA_AGILEX5) += agilex5-xload.o +endif obj-$(CONFIG_ARCH_SOCFPGA_AGILEX5) += secure_reg_helper.o \ smc_api.o diff --git a/arch/arm/mach-socfpga/agilex5-xload.c b/arch/arm/mach-socfpga/agilex5-xload.c new file mode 100644 index 000000000000..9e55252c04cc --- /dev/null +++ b/arch/arm/mach-socfpga/agilex5-xload.c @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include +#include +#include +#include +#include +#include + +static inline u32 barebox_arm_size(const char *head) +{ + return *(u32 *)(head + ARM_HEAD_SIZE_OFFSET); +} + +const struct socfpga_barebox_part *barebox_part; + +void agilex5_set_barebox_part(struct socfpga_barebox_part *part) +{ + barebox_part = part; +} + +static ssize_t agilex5_bl33_read(struct pbl_bio *bio, void *bl33, + off_t offs, size_t max) +{ + const off_t step = ARM_HEAD_SIZE; + u32 size = 0; + int ret; + + ret = pbl_bio_read(bio, offs, bl33, step); + if (ret < 0) + return ret; + if (is_barebox_arm_head(bl33)) + size = barebox_arm_size(bl33); + if (size == 0) { + pr_err("cannot find bl33 at offset 0x%08lx)\n", offs); + return -EIO; + } + if (size > max) { + pr_err("bl33 size (%u) larger than partition\n", size); + return -EINVAL; + } + + pr_info("bl33 found at 0x%08lx, size %u\n", offs, size); + + ret = pbl_bio_read(bio, offs + step, bl33 + step, size - step); + if (ret < size - step) { + pr_warn("failed to read bl33 from flash: %d\n", ret); + return ret; + } + + pr_debug("read bl33 to %p from %lx (%u bytes)\n", bl33, offs, size); + + return size; +} + +int agilex5_xload_bl33(struct pbl_bio *bio, void *bl33) +{ + ssize_t size; + + if (!bio) { + pr_warn("source device for SSBL is not configured\n"); + return -ENODEV; + } + if (!barebox_part) { + pr_warn("source partition for SSBL is not configured\n"); + return -ENODEV; + } + size = agilex5_bl33_read(bio, bl33, + barebox_part->nor_offset, + barebox_part->nor_size); + if (size < 0) + return size; + + return 0; +} diff --git a/include/mach/socfpga/generic.h b/include/mach/socfpga/generic.h index 6c99a17e81f1..16e117f4206c 100644 --- a/include/mach/socfpga/generic.h +++ b/include/mach/socfpga/generic.h @@ -134,4 +134,19 @@ struct socfpga_barebox_part { /* Partition/device for xloader to load main bootloader from */ extern const struct socfpga_barebox_part *barebox_part; +struct pbl_bio; +#ifdef CONFIG_SOCFPGA_AGILEX5_XLOAD +void agilex5_set_barebox_part(struct socfpga_barebox_part *part); +int agilex5_xload_bl33(struct pbl_bio *bio, void *bl33); +#else +static inline void agilex5_set_barebox_part(struct socfpga_barebox_part *part) +{ +} + +static inline int agilex5_xload_bl33(struct pbl_bio *bio, void *bl33) +{ + return -ENODEV; +} +#endif + #endif /* __MACH_SOCFPGA_GENERIC_H */ -- 2.47.3