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The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: OpenSBI starts the HiFive images like a kernel, so they use the supervisor mode head. Both boards hand the first 128M of DRAM to barebox proper, so that goes into the new SiFive SoC defaults and the b [...] Content analysis details: (-1.9 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a0a:edc0:2:b01:1d:0:0:104 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.0 DMARC_MISSING Missing DMARC policy X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-Rspamd-Server: mx1 X-Rspamd-Queue-Id: 9B5D3201CE0 X-Spamd-Result: default: False [-6.11 / 15.00]; BAYES_HAM(-3.00)[100.00%]; DWL_DNSWL_MED(-2.00)[infradead.org:dkim]; MID_CONTAINS_FROM(1.00)[]; KNOWN_LIST_ID(-1.00)[barebox.lists.infradead.org]; RCVD_DKIM_ARC_DNSWL_MED(-0.50)[]; R_MISSING_CHARSET(0.50)[]; RCVD_IN_DNSWL_MED(-0.40)[2607:7c80:54:3::133:from,2a0a:edc0:0:900:1d::77:received]; MAILLIST(-0.20)[mailman]; R_DKIM_ALLOW(-0.20)[lists.infradead.org:s=bombadil.20210309]; R_SPF_ALLOW(-0.20)[+mx:c]; MIME_GOOD(-0.10)[text/plain]; HAS_LIST_UNSUB(-0.01)[]; DMARC_NA(0.00)[barebox.org]; TO_DN_SOME(0.00)[]; MIME_TRACE(0.00)[0:+]; ARC_NA(0.00)[]; RCVD_IN_DNSWL_NONE(0.00)[2a0a:edc0:2:b01:1d::104:received]; ARC_SIGNED(0.00)[pengutronix.de:s=20260414:i=1]; RECEIVED_HELO_LOCALHOST(0.00)[]; TAGGED_FROM(0.00)[lore=pengutronix.de]; RCVD_TLS_LAST(0.00)[]; NEURAL_HAM(-0.00)[-1.000]; FORGED_SENDER_MAILLIST(0.00)[]; RCVD_COUNT_THREE(0.00)[3]; ASN(0.00)[asn:7247, ipnet:2607:7c80:54::/48, country:US]; DKIM_TRACE(0.00)[lists.infradead.org:+]; RCPT_COUNT_THREE(0.00)[4]; FROM_HAS_DN(0.00)[]; FROM_NEQ_ENVFROM(0.00)[a.fatoum@barebox.org,barebox-bounces@lists.infradead.org] X-Rspamd-Action: no action X-Stat-Signature: csc5gn79rrehir1rg5py3a1io1chkjsm OpenSBI starts the HiFive images like a kernel, so they use the supervisor mode head. Both boards hand the first 128M of DRAM to barebox proper, so that goes into the new SiFive SoC defaults and the boards only add their built-in device tree. The '>' is now printed by the stage dispatch. Assisted-by: Claude:fable-5.1 Signed-off-by: Ahmad Fatoum --- arch/riscv/boards/hifive/lowlevel.c | 30 ++++++++------------------- include/mach/sifive/entry.h | 32 +++++++++++++++++++++++++++++ 2 files changed, 41 insertions(+), 21 deletions(-) create mode 100644 include/mach/sifive/entry.h diff --git a/arch/riscv/boards/hifive/lowlevel.c b/arch/riscv/boards/hifive/lowlevel.c index 5e8969bef1da..ab60c7e96a78 100644 --- a/arch/riscv/boards/hifive/lowlevel.c +++ b/arch/riscv/boards/hifive/lowlevel.c @@ -1,26 +1,14 @@ // SPDX-License-Identifier: GPL-2.0-only -#include -#include -#include +#include -static __always_inline void start_hifive(unsigned long hartid, void *fdt) -{ - putc_ll('>'); +extern char __dtb_z_hifive_unmatched_a00_start[]; +extern char __dtb_z_hifive_unleashed_a00_start[]; - barebox_riscv_supervisor_entry(0x80000000, SZ_128M, hartid, fdt); -} +ENTRY_POINT(FU740, start_hifive_unmatched) + .second_stage.board_data = __dtb_z_hifive_unmatched_a00_start, +ENTRY_POINT_END -ENTRY_FUNCTION(start_hifive_unmatched, a0, a1, a2) -{ - extern char __dtb_z_hifive_unmatched_a00_start[]; - - start_hifive(a0, __dtb_z_hifive_unmatched_a00_start + get_runtime_offset()); -} - -ENTRY_FUNCTION(start_hifive_unleashed, a0, a1, a2) -{ - extern char __dtb_z_hifive_unleashed_a00_start[]; - - start_hifive(a0, __dtb_z_hifive_unleashed_a00_start + get_runtime_offset()); -} +ENTRY_POINT(FU540, start_hifive_unleashed) + .second_stage.board_data = __dtb_z_hifive_unleashed_a00_start, +ENTRY_POINT_END diff --git a/include/mach/sifive/entry.h b/include/mach/sifive/entry.h new file mode 100644 index 000000000000..04529099dcf4 --- /dev/null +++ b/include/mach/sifive/entry.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MACH_SIFIVE_ENTRY_H +#define __MACH_SIFIVE_ENTRY_H + +#include +#include +#include + +#define SIFIVE_DRAM_BASE 0x80000000 + +/* + * OpenSBI starts the image in supervisor mode in DRAM. Every board has + * at least 128M, boards with more can raise mem_minsz. OpenSBI leaves + * the UART set up, so there's no console and the PBL uses DEBUG_LL. + */ +#define PBL_SOC_SIFIVE_DEFAULTS(soc) \ + .soc_type = SOC_TYPE_##soc, \ + .second_stage = { \ + .stacktop = SIFIVE_DRAM_BASE + SZ_128M, \ + .mem_start = SIFIVE_DRAM_BASE, \ + .mem_minsz = SZ_128M, \ + .soc_chainload = pbl_stage_barebox_entry, \ + } + +#define PBL_SOC_FU540_HEAD __barebox_pbl_head_v1_supervisor +#define PBL_SOC_FU540_DEFAULTS PBL_SOC_SIFIVE_DEFAULTS(FU540) + +#define PBL_SOC_FU740_HEAD __barebox_pbl_head_v1_supervisor +#define PBL_SOC_FU740_DEFAULTS PBL_SOC_SIFIVE_DEFAULTS(FU740) + +#endif -- 2.47.3