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The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: The driver selects software Hamming ECC before nand_scan(), but rawnand_dt_init() unconditionally overwrites chip->ecc.algo with the device tree setting. None of the Kirkwood device trees has an ECC p [...] Content analysis details: (-2.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 DMARC_PASS DMARC pass policy X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-Rspamd-Server: mx1 X-Rspamd-Queue-Id: ECDA2202BAB X-Spamd-Result: default: False [-7.91 / 15.00]; BAYES_HAM(-3.00)[100.00%]; DWL_DNSWL_MED(-2.00)[infradead.org:dkim]; KNOWN_LIST_ID(-1.00)[barebox.lists.infradead.org]; RCVD_DKIM_ARC_DNSWL_MED(-0.50)[]; DMARC_POLICY_ALLOW(-0.50)[puzzle.ch,reject]; R_SPF_ALLOW(-0.20)[+mx:c]; R_DKIM_ALLOW(-0.20)[lists.infradead.org:s=bombadil.20210309,puzzle.ch:s=20211230,puzzle.ch:s=20211209]; RCVD_IN_DNSWL_MED(-0.20)[2607:7c80:54:3::133:from]; MAILLIST(-0.20)[mailman]; MIME_GOOD(-0.10)[text/plain]; HAS_LIST_UNSUB(-0.01)[]; RECEIVED_HELO_LOCALHOST(0.00)[]; RCVD_COUNT_THREE(0.00)[3]; FROM_HAS_DN(0.00)[]; FORWARDED(0.00)[barebox@lists.infradead.org]; MIME_TRACE(0.00)[0:+]; ARC_NA(0.00)[]; FORGED_SENDER(0.00)[grzeschik@puzzle.ch,barebox-bounces@lists.infradead.org]; RCVD_TLS_LAST(0.00)[]; TAGGED_FROM(0.00)[lore=pengutronix.de]; FORGED_SENDER_FORWARDING(0.00)[]; ASN(0.00)[asn:7247, ipnet:2607:7c80:54::/48, country:US]; MID_RHS_MATCH_FROM(0.00)[]; NEURAL_HAM(-0.00)[-1.000]; TO_DN_ALL(0.00)[]; MISSING_XM_UA(0.00)[]; DKIM_TRACE(0.00)[lists.infradead.org:+,puzzle.ch:+]; RCPT_COUNT_THREE(0.00)[3]; FROM_NEQ_ENVFROM(0.00)[grzeschik@puzzle.ch,barebox-bounces@lists.infradead.org]; ARC_SIGNED(0.00)[pengutronix.de:s=20260414:i=1]; FORGED_SENDER_MAILLIST(0.00)[] X-Rspamd-Action: no action X-Stat-Signature: 6cmzw5ggzg3daexjde7rf1sutrby9tdw The driver selects software Hamming ECC before nand_scan(), but rawnand_dt_init() unconditionally overwrites chip->ecc.algo with the device tree setting. None of the Kirkwood device trees has an ECC property, so the algorithm ends up as NAND_ECC_ALGO_UNKNOWN and probing fails: WARNING: at drivers/mtd/nand/raw/nand_base.c:5783/nand_set_ecc_soft_ops()! WARNING: Unsupported ECC algorithm! leaving all boards with an orion NAND controller without NAND. Do the same as the Linux orion_nand driver: keep the software engine as default before scanning, and pick the Hamming algorithm in ->attach_chip(), which runs after the device tree has been parsed, if neither the device tree nor anything else chose one. Assisted-by: Claude:claude-opus-5-5 Signed-off-by: Michael Grzeschik --- drivers/mtd/nand/raw/nand_orion.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/nand_orion.c b/drivers/mtd/nand/raw/nand_orion.c index c7fa4a08e9..68797b9b38 100644 --- a/drivers/mtd/nand/raw/nand_orion.c +++ b/drivers/mtd/nand/raw/nand_orion.c @@ -73,6 +73,19 @@ static void orion_nand_read_buf(struct nand_chip *chip, uint8_t *buf, int len) buf[i++] = readb(io_base); } +static int orion_nand_attach_chip(struct nand_chip *chip) +{ + if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT && + chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) + chip->ecc.algo = NAND_ECC_ALGO_HAMMING; + + return 0; +} + +static const struct nand_controller_ops orion_nand_controller_ops = { + .attach_chip = orion_nand_attach_chip, +}; + static int orion_nand_probe(struct device *dev) { struct resource *iores; @@ -117,8 +130,13 @@ static int orion_nand_probe(struct device *dev) chip->legacy.IO_ADDR_R = chip->legacy.IO_ADDR_W = io_base; chip->legacy.cmd_ctrl = orion_nand_cmd_ctrl; chip->legacy.read_buf = orion_nand_read_buf; + /* + * The default ECC engine is software. The algorithm is set in + * ->attach_chip(), after rawnand_dt_init() has overwritten it with the + * (usually absent) device tree setting. + */ chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; - chip->ecc.algo = NAND_ECC_ALGO_HAMMING; + chip->legacy.dummy_controller.ops = &orion_nand_controller_ops; WARN(width > 16, "%d bit bus width out of range", width); if (width == 16) -- 2.53.0