Re: [PATCH v2 2/4] arm: mach-imx: esdctl.c: Add support for imx8mp inline ECC

[Ahmad Fatoum <a.fatoum@pengutronix.de>]

On 3/9/26 8:46 AM, Steffen Trumtrar wrote:
> From: David Jander <david@protonic.nl>
> 
> This adds support for detecting the use of inline ECC and compute the
> correct memory bank(s) in that case.
> In case inline ECC is active the memory map is modified as follows:
> The total memory size is reduced to 7/8th of the raw memory size.
> If a reduced-address-space type RAM is used (0.75, 1.5, 3, 6... GiB), then
> the whole address space is split up into 3 equal parts, separated by 1/3rd
> of the raw address space, but each 7/8th that size.
> The ECC area at the end of each part is not addressable and must be
> excluded from the map.
> 
> Signed-off-by: David Jander <david@protonic.nl>
> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
> ---
>  arch/arm/mach-imx/Kconfig  |  8 +++++
>  arch/arm/mach-imx/esdctl.c | 77 +++++++++++++++++++++++++++++++++++++++++++++-
>  2 files changed, 84 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index d244c57580..08b0a955c6 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -1026,6 +1026,14 @@ config HABV3_IMG_CRT_DER
>  
>  endif
>  
> +config IMX8MP_DRAM_ECC
> +	bool
> +	depends on ARCH_IMX8MP
> +	help
> +	  The i.MX8MP SoC supports ECC on the LPDDR4 memory. Select Y to enable
> +	  this feature. The total amount of memory available will be reduced by
> +	  1/8th.

Help text doesn't reflect reality anymore after removal of the prompt.
Suggestion:

This option is selected by boards that make use of the inline ECC
support for LPDDR4 memory on i.MX8MP SoCs. For board images that
configure ECC, the total amount of memory available will be reduced by
1/8th.
Boards that don't explicitly make use of it are not affected.

> +static resource_size_t imx8mp_ddrc_sdram_size(void __iomem *ddrc,
> +		unsigned int *chunks, resource_size_t *stride)
> +{
> +	resource_size_t size = imx8m_ddrc_sdram_size(ddrc, 32);
> +	const bool reduced_address_space = FIELD_GET(
> +		DDRC_ADDRMAP6_LPDDR4_6GB_12GB_24GB, readl(ddrc + DDRC_ADDRMAP(6)));
> +
> +	/* ECC devides the accessible address space into 1 or 3 contiguous

divides


> +static int imx8mp_ddrc_add_mem(void *mmdcbase, const struct imx_esdctl_data *data)
> +{
> +	unsigned int chunks;
> +	unsigned long base;
> +	resource_size_t chunksize = 0, stride = 0;
> +	int ret = -ENOMEM;
> +	int i;
> +	char name[5];
> +
> +	chunksize = imx8mp_ddrc_sdram_size(mmdcbase, &chunks, &stride);
> +
> +	base = data->base0;
> +	for (i = 0; i < chunks; i++) {
> +		snprintf(name, 5, "ram%d", i);

sizeof(name)

>  static __maybe_unused const struct imx_esdctl_data imx9_data = {
>  	.base0 = MX9_DDR_CSD1_BASE_ADDR,
>  	.add_mem = imx9_ddrc_add_mem,
> @@ -822,6 +885,12 @@ static __maybe_unused struct of_device_id imx_esdctl_dt_ids[] = {
>  	}, {
>  		.compatible = "fsl,imx8mn-ddrc",
>  		.data = &imx8mn_data
> +	}, {
> +		.compatible = "fsl,imx8mp-ddrc",
> +		.data = &imx8mp_data
> +	}, {
> +		.compatible = "fsl,imx8mq-ddrc",
> +		.data = &imx8mp_data

Are you sure that the original i.MX8M Quad supports ECC?

>  	}, {
>  		.compatible = "fsl,imx93-ddrc",
>  		.data = &imx9_data
> @@ -1000,9 +1069,15 @@ void __noreturn vf610_barebox_entry(void *boarddata)
>  
>  resource_size_t imx8m_barebox_earlymem_size(unsigned buswidth)
>  {
> +	unsigned int chunks;
> +	resource_size_t stride = 0;

Drop and just pass NULL as pointer?

>  	resource_size_t size;
>  
> -	size = imx8m_ddrc_sdram_size(IOMEM(MX8M_DDRC_CTL_BASE_ADDR), buswidth);
> +	if (imx_esdctl_ecc_enabled(IOMEM(MX8M_DDRC_CTL_BASE_ADDR)))
> +		size = imx8mp_ddrc_sdram_size(IOMEM(MX8M_DDRC_CTL_BASE_ADDR), &chunks,
> +				&stride);
> +	else
> +		size = imx8m_ddrc_sdram_size(IOMEM(MX8M_DDRC_CTL_BASE_ADDR), buswidth);
>  	/*
>  	 * We artificially limit detected memory size to force malloc
>  	 * pool placement to be within 4GiB address space, so as to
> 

Cheers,
Ahmad

-- 
Pengutronix e.K.                  |                             |
Steuerwalder Str. 21              | http://www.pengutronix.de/  |
31137 Hildesheim, Germany         | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686  | Fax:   +49-5121-206917-5555 |