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[130.180.211.218]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3a073e5cffasm14105707f8f.96.2025.04.29.06.09.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 29 Apr 2025 06:09:22 -0700 (PDT) Message-ID: <29d7fbb7-52ec-40a4-9f12-2fb6286b94ba@linaro.org> Date: Tue, 29 Apr 2025 15:09:21 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird To: Ahmad Fatoum Cc: barebox@lists.infradead.org References: <20250422052635.3423961-1-a.fatoum@pengutronix.de> <20250422052635.3423961-3-a.fatoum@pengutronix.de> <080c0462-8e25-4255-9e91-9d8b47cd4a0e@pengutronix.de> Content-Language: en-US From: Daniel Lezcano In-Reply-To: <080c0462-8e25-4255-9e91-9d8b47cd4a0e@pengutronix.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250429_060925_282565_8AE3B3B5 X-CRM114-Status: GOOD ( 15.00 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.whiteo.stw.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-4.8 required=4.0 tests=AWL,BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: Re: [PATCH 2/9] clocksource: ti-dm: make available in PBL X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.whiteo.stw.pengutronix.de) On 29/04/2025 11:31, Ahmad Fatoum wrote: > Hello Daniel, > > On 4/29/25 11:08, Daniel Lezcano wrote: >> On Tue, Apr 22, 2025 at 07:26:28AM +0200, Ahmad Fatoum wrote: >>> +int omap_dmtimer_init(void __iomem *mmio_start, unsigned clk_speed) >>> +{ >>> + base = mmio_start; >>> + >>> + dmtimer_cs.mult = clocksource_hz2mult(clk_speed, dmtimer_cs.shift); >>> + >>> + /* Enable counter */ >>> + writel(0x3, base + TCLR); >>> + >>> + return init_clock(&dmtimer_cs); >>> +} >> >> Can you take the opportunity to fix the function prototype with the correct types 'u32' ? > > Why is u32 more correct than unsigned? The value is not written to a > register, but instead used as input to computing the multiplier. It is to match the call to clocksource_hz2mult() which has a u32 as parameter. >> And replacing the litteral 0x3 with a macro ? > > Sure thing. > > Thanks, > Ahmad > >> >>> + >>> static int omap_dmtimer_probe(struct device *dev) >>> { >>> struct resource *iores; >>> @@ -90,12 +102,7 @@ static int omap_dmtimer_probe(struct device *dev) >>> if (clk_speed < 0) >>> return clk_speed; >>> >>> - dmtimer_cs.mult = clocksource_hz2mult(clk_speed, dmtimer_cs.shift); >>> - >>> - /* Enable counter */ >>> - writel(0x3, base + TCLR); >>> - >>> - return init_clock(&dmtimer_cs); >>> + return omap_dmtimer_init(IOMEM(iores->start), clk_speed); >>> } >>> >>> static int am335x_get_clock(struct device *dev) >>> diff --git a/include/mach/omap/am33xx-clock.h b/include/mach/omap/am33xx-clock.h >>> index af47a0f3e77a..b064337ac4f8 100644 >>> --- a/include/mach/omap/am33xx-clock.h >>> +++ b/include/mach/omap/am33xx-clock.h >>> @@ -191,4 +191,7 @@ void am33xx_pll_init(int mpupll_M, int ddrpll_M); >>> void am33xx_enable_ddr_clocks(void); >>> int am33xx_get_osc_clock(void); >>> >>> +int omap_dmtimer_init(void __iomem *mmio_start, >>> + unsigned clk_speed); >>> + >>> #endif /* endif _AM33XX_CLOCKS_H_ */ >>> -- >>> 2.39.5 >>> >>> >>> >> > -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog