Re: [PATCH 2/3] arch/arm/boards/avnet-zedboard/lowlevel.c: added SDIO clk frequency configuration

[Ahmad Fatoum <a.fatoum@pengutronix.de>]

Hi,

On 07.07.25 07:53, Gwenhael Goavec-Merou wrote:
> From: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
> 
> As mentionned in [1] MMC sometime fails to be initialized/ is not
> working with this type of error:
> 
> arasan-sdhci e0100000.mmc@e0100000.of: registered as mmc0
> malloc space: 0x17e00000 -> 0x1fdfffff (size 128 MiB)
> arasan-sdhci e0100000.mmc@e0100000.of: error while transferring data for command 6
> arasan-sdhci e0100000.mmc@e0100000.of: state = 0x01ff0202 , interrupt = 0x00208000
> mmc0: Card's startup fails with -74
> barebox-environment chosen:environment-sd.of: probe failed: No such file or directory
> environment load /dev/env0: No such file or directory
> 
> This patch adds SDIO clck configuration allowing to have a valid MMC
> clock frequency.
> 
> [1] https://lore.barebox.org/barebox/VI1PR02MB4429606E3B06D0F53D2B4175AB4DA@VI1PR02MB4429.eurprd02.prod.outlook.com/T/#m1cb8598da4741c0b7a41944e1aecef373dd74319

Same comment as on v1, I'd suggest as commit message title:

  ARM: zynq: zed: add SDIO clk frequency configuration


I am wondering why this is needed when we seem to have a clock driver for
the platform, but your workaround looks ok:

Acked-by: Ahmad Fatoum <a.fatoum@pengutronix.de>

Thanks,
Ahmad

> 
> Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
> ---
>  arch/arm/boards/avnet-zedboard/lowlevel.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/boards/avnet-zedboard/lowlevel.c b/arch/arm/boards/avnet-zedboard/lowlevel.c
> index 605aab783a..b7a98f5a82 100644
> --- a/arch/arm/boards/avnet-zedboard/lowlevel.c
> +++ b/arch/arm/boards/avnet-zedboard/lowlevel.c
> @@ -241,6 +241,7 @@ static void avnet_zedboard_ps7_init(void)
>  	/* poor mans clkctrl */
>  	writel(0x00001403, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_UART_CLK_CTRL);
>  	writel(0x00000101, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_LQSPI_CLK_CTRL);
> +	writel(0x00001401, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_SDIO_CLK_CTRL);
>  
>  	/* GEM0 */
>  	writel(0x00000001, 0xf8000138);


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