[PATCH] mtd: nand-mxs: Gate ENFC_CLK_ROOT clock off before changing nand clock rate

[PATCH] mtd: nand-mxs: Gate ENFC_CLK_ROOT clock off before changing nand clock rate

[Dmitry Lavnikevich]

This fixes NAND initialization issue which appears occasionally on
some i.MX6 SoCs (particulary was observed on phyCARD-i.MX6 with
i.MX6Solo).

Signed-off-by: Dmitry Lavnikevich <d.lavnikevich@sam-solutions.com>
---
 arch/arm/mach-imx/include/mach/clock-imx6.h |  4 ++++
 drivers/mtd/nand/nand_mxs.c                 | 12 ++++++++++++
 2 files changed, 16 insertions(+)

diff --git a/arch/arm/mach-imx/include/mach/clock-imx6.h b/arch/arm/mach-imx/include/mach/clock-imx6.h
index 8e5e9d9..ffa889d 100644
--- a/arch/arm/mach-imx/include/mach/clock-imx6.h
+++ b/arch/arm/mach-imx/include/mach/clock-imx6.h
@@ -344,4 +344,8 @@
 #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS			(1 << 2)
 #define MXC_CCM_CGPR_PMIC_DELAY_SCALER			(1)
 
+/* Define the bits in register CCGR2 */
+#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET		14
+#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK		(3 << 14)
+
 #endif				/* __ARCH_ARM_MACH_MX6_CRM_REGS_H__ */
diff --git a/drivers/mtd/nand/nand_mxs.c b/drivers/mtd/nand/nand_mxs.c
index d5428bc..9ebddb3 100644
--- a/drivers/mtd/nand/nand_mxs.c
+++ b/drivers/mtd/nand/nand_mxs.c
@@ -34,6 +34,8 @@
 #include <stmp-device.h>
 #include <asm/mmu.h>
 #include <mach/generic.h>
+#include <mach/clock-imx6.h>
+#include <mach/imx6-regs.h>
 
 #define	MX28_BLOCK_SFTRST				(1 << 31)
 #define	MX28_BLOCK_CLKGATE				(1 << 30)
@@ -1254,6 +1256,7 @@ static int mxs_nand_probe(struct device_d *dev)
 	struct nand_chip *nand;
 	struct mtd_info *mtd;
 	enum gpmi_type type;
+	u32 val;
 	int err;
 
 	err = dev_get_drvdata(dev, (unsigned long *)&type);
@@ -1277,7 +1280,16 @@ static int mxs_nand_probe(struct device_d *dev)
 		return PTR_ERR(nand_info->clk);
 
 	if (mxs_nand_is_imx6(nand_info)) {
+		val = readl(MXC_CCM_CCGR2);
+		val &= ~MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK;
+		writel(val, MXC_CCM_CCGR2);
+
 		clk_set_rate(nand_info->clk, 96000000);
+
+		val = readl(MXC_CCM_CCGR2);
+		val |= MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK;
+		writel(val, MXC_CCM_CCGR2);
+
 		clk_enable(nand_info->clk);
 		nand_info->dma_channel_base = 0;
 	} else {
-- 
2.1.3


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Re: [PATCH] mtd: nand-mxs: Gate ENFC_CLK_ROOT clock off before changing nand clock rate

[Sascha Hauer]

On Mon, Nov 17, 2014 at 12:58:34AM +0300, Dmitry Lavnikevich wrote:
> This fixes NAND initialization issue which appears occasionally on
> some i.MX6 SoCs (particulary was observed on phyCARD-i.MX6 with
> i.MX6Solo).
> 
> Signed-off-by: Dmitry Lavnikevich <d.lavnikevich@sam-solutions.com>

Applied, thanks

Sascha

> ---
>  arch/arm/mach-imx/include/mach/clock-imx6.h |  4 ++++
>  drivers/mtd/nand/nand_mxs.c                 | 12 ++++++++++++
>  2 files changed, 16 insertions(+)
> 
> diff --git a/arch/arm/mach-imx/include/mach/clock-imx6.h b/arch/arm/mach-imx/include/mach/clock-imx6.h
> index 8e5e9d9..ffa889d 100644
> --- a/arch/arm/mach-imx/include/mach/clock-imx6.h
> +++ b/arch/arm/mach-imx/include/mach/clock-imx6.h
> @@ -344,4 +344,8 @@
>  #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS			(1 << 2)
>  #define MXC_CCM_CGPR_PMIC_DELAY_SCALER			(1)
>  
> +/* Define the bits in register CCGR2 */
> +#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET		14
> +#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK		(3 << 14)
> +
>  #endif				/* __ARCH_ARM_MACH_MX6_CRM_REGS_H__ */
> diff --git a/drivers/mtd/nand/nand_mxs.c b/drivers/mtd/nand/nand_mxs.c
> index d5428bc..9ebddb3 100644
> --- a/drivers/mtd/nand/nand_mxs.c
> +++ b/drivers/mtd/nand/nand_mxs.c
> @@ -34,6 +34,8 @@
>  #include <stmp-device.h>
>  #include <asm/mmu.h>
>  #include <mach/generic.h>
> +#include <mach/clock-imx6.h>
> +#include <mach/imx6-regs.h>
>  
>  #define	MX28_BLOCK_SFTRST				(1 << 31)
>  #define	MX28_BLOCK_CLKGATE				(1 << 30)
> @@ -1254,6 +1256,7 @@ static int mxs_nand_probe(struct device_d *dev)
>  	struct nand_chip *nand;
>  	struct mtd_info *mtd;
>  	enum gpmi_type type;
> +	u32 val;
>  	int err;
>  
>  	err = dev_get_drvdata(dev, (unsigned long *)&type);
> @@ -1277,7 +1280,16 @@ static int mxs_nand_probe(struct device_d *dev)
>  		return PTR_ERR(nand_info->clk);
>  
>  	if (mxs_nand_is_imx6(nand_info)) {
> +		val = readl(MXC_CCM_CCGR2);
> +		val &= ~MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK;
> +		writel(val, MXC_CCM_CCGR2);
> +
>  		clk_set_rate(nand_info->clk, 96000000);
> +
> +		val = readl(MXC_CCM_CCGR2);
> +		val |= MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK;
> +		writel(val, MXC_CCM_CCGR2);
> +
>  		clk_enable(nand_info->clk);
>  		nand_info->dma_channel_base = 0;
>  	} else {
> -- 
> 2.1.3
> 
> 
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> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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Re: [PATCH] mtd: nand-mxs: Gate ENFC_CLK_ROOT clock off before changing nand clock rate

[Sascha Hauer]

On Mon, Nov 17, 2014 at 12:58:34AM +0300, Dmitry Lavnikevich wrote:
> This fixes NAND initialization issue which appears occasionally on
> some i.MX6 SoCs (particulary was observed on phyCARD-i.MX6 with
> i.MX6Solo).
> 
> Signed-off-by: Dmitry Lavnikevich <d.lavnikevich@sam-solutions.com>

I had to revert this one. It breaks compilation on i.MX28. Looking
closer at it reveals this is the wrong approach.

>  	if (mxs_nand_is_imx6(nand_info)) {
> +		val = readl(MXC_CCM_CCGR2);
> +		val &= ~MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK;
> +		writel(val, MXC_CCM_CCGR2);
> +
>  		clk_set_rate(nand_info->clk, 96000000);
> +
> +		val = readl(MXC_CCM_CCGR2);
> +		val |= MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK;
> +		writel(val, MXC_CCM_CCGR2);
> +
>  		clk_enable(nand_info->clk);

First of all please look at the kernel driver. It uses a clock of 22MHz
normally and 100 or 80MHz for EDO mode, which seems to require setup of
other registers. So it might be that there's something else that makes
trouble here.

The clk API is for abstracting the clock providers from its consumers.
It's unnecessary to directly fiddle with the clock registers in the nand
driver. Instead of passing the enfc_podf to the nand controller
arch/arm/mach-imx/clk-imx6.c should be changed to pass the gate to the
controller and here. In the final enabling of all the gates in
clk-imx6.c clear MXC_CCM_CCGR2[14..15] and enable the clock here after
setting the rate.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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Re: [PATCH] mtd: nand-mxs: Gate ENFC_CLK_ROOT clock off before changing nand clock rate

[Dmitry Lavnikevich]

>> 	if (mxs_nand_is_imx6(nand_info)) {
>> +		val = readl(MXC_CCM_CCGR2);
>> +		val &= ~MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK;
>> +		writel(val, MXC_CCM_CCGR2);
>> +
>> 		clk_set_rate(nand_info->clk, 96000000);
>> +
>> +		val = readl(MXC_CCM_CCGR2);
>> +		val |= MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK;
>> +		writel(val, MXC_CCM_CCGR2);
>> +
>> 		clk_enable(nand_info->clk);
> 
> First of all please look at the kernel driver. It uses a clock of 22MHz
> normally and 100 or 80MHz for EDO mode, which seems to require setup of
> other registers. So it might be that there's something else that makes
> trouble here.

I have looked in kernel driver but didn’t found anything related to this issue.
This solution was ported from similar clock initialisation in u-boot.

> The clk API is for abstracting the clock providers from its consumers.
> It's unnecessary to directly fiddle with the clock registers in the nand
> driver. Instead of passing the enfc_podf to the nand controller
> arch/arm/mach-imx/clk-imx6.c should be changed to pass the gate to the
> controller and here. In the final enabling of all the gates in
> clk-imx6.c clear MXC_CCM_CCGR2[14..15] and enable the clock here after
> setting the rate.

so if I understood correctly

* I should both set enfc clock rate and enable it in clk-imx6.c while
clock is gated off. For this I should create gated clock like:

clks[enfc] = imx_clk_gate2("enfc", "enfc_pred", base + 0x70, 14);

for which I should implement the imx_clk_gate2() itself for operating on two-bits gate
clocks (I see such function in kernel clk code).

* Setting clock rate and enabling it in nand_mxs.c becomes unnecessary
and can be removed.

Am I right?

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