Fwd: [PATCH 2/3] ARM: socfpga: Enclustra SA2: enable USB1 HS

Fwd: [PATCH 2/3] ARM: socfpga: Enclustra SA2: enable USB1 HS

[David Picard]

-------- Message transféré --------
Sujet : 	[PATCH 2/3] ARM: socfpga: Enclustra SA2: enable USB1 HS
Date : 	Wed, 04 Mar 2026 14:51:24 +0100
De : 	David Picard <david.picard@clermont.in2p3.fr>
Pour : 	David Picard <david.picard@clermont.in2p3.fr>



Enable high-speed USB 2.0 USB1 controller on Enclustra
Mercury+ SA2 module.
---
arch/arm/configs/socfpga_defconfig | 6 ++++++
arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi | 7 +++++++
2 files changed, 13 insertions(+)

diff --git a/arch/arm/configs/socfpga_defconfig 
b/arch/arm/configs/socfpga_defconfig
index 37555a6297..8f9e34d459 100644
--- a/arch/arm/configs/socfpga_defconfig
+++ b/arch/arm/configs/socfpga_defconfig
@@ -86,6 +86,10 @@ CONFIG_MTD_NAND_DENALI=y
CONFIG_MTD_NAND_DENALI_DT=y
CONFIG_MTD_SPI_NOR=y
CONFIG_SPI_CADENCE_QUADSPI=y
+CONFIG_USB_HOST=y
+CONFIG_USB_DWC2_HOST=y
+CONFIG_USB_EHCI=y
+CONFIG_USB_ULPI=y
CONFIG_MCI=y
CONFIG_MCI_DW=y
CONFIG_LED=y
@@ -103,6 +107,8 @@ CONFIG_FIRMWARE_ALTERA_SOCFPGA=y
CONFIG_FPGA=y
CONFIG_FPGA_BRIDGE=y
CONFIG_SOCFPGA_FPGA_BRIDGE=y
+CONFIG_GENERIC_PHY=y
+CONFIG_USB_NOP_XCEIV=y
CONFIG_FS_EXT4=y
CONFIG_FS_TFTP=y
CONFIG_FS_NFS=y
diff --git a/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi 
b/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi
index 6334573a77..cd33b38d2b 100644
--- a/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi
@@ -8,6 +8,7 @@
*/
#include <arm/intel/socfpga/socfpga_cyclone5.dtsi>
+#include <dt-bindings/gpio/gpio.h>
/ {
barebox,deep-probe;
@@ -205,6 +206,12 @@ Reference:
};
};
+&usbphy0 {
+ /* HPS_GPIO0, active low */
+ reset-gpios = <&porta 0 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
&usb1 {
status = "okay";
dr_mode = "host";

-- 
2.43.0