* [PATCH 01/12] ARM omap: Add omap signGP tool and possibility to build ift images
2011-04-11 14:39 OMAP4 support Sascha Hauer
@ 2011-04-11 14:39 ` Sascha Hauer
2011-04-11 14:39 ` [PATCH 02/12] mci omap: hsmmc is also found on the omap3 Sascha Hauer
` (10 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Sascha Hauer @ 2011-04-11 14:39 UTC (permalink / raw)
To: barebox
The tool is needed to build images suitable for omap processors
to load from mmc or nand.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/Makefile | 8 +
arch/arm/mach-omap/Kconfig | 4 +
scripts/Makefile | 1 +
scripts/omap_signGP.c | 313 ++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 326 insertions(+), 0 deletions(-)
create mode 100644 scripts/omap_signGP.c
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 108bd5e..fa1677c 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -134,6 +134,14 @@ ifeq ($(machine-y),netx)
KBUILD_IMAGE := barebox.netx
endif
+barebox.bin.ift: barebox.bin
+ @echo " IFT " $@
+ $(Q)scripts/omap_signGP barebox.bin $(TEXT_BASE) 1
+
+ifeq ($(CONFIG_OMAP_BUILD_IFT),y)
+KBUILD_IMAGE := barebox.bin.ift
+endif
+
all: $(KBUILD_IMAGE)
archprepare: maketools
diff --git a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig
index d171a6f..351c469 100644
--- a/arch/arm/mach-omap/Kconfig
+++ b/arch/arm/mach-omap/Kconfig
@@ -83,6 +83,10 @@ config OMAP_GPMC
Controller(GPMC). GPMC allows you to configure devices such as NOR,
NAND, OneNAND etc.
+config OMAP_BUILD_IFT
+ prompt "build ift binary"
+ bool
+
config ARCH_TEXT_BASE
hex
default 0x80e80000 if MACH_OMAP343xSDP
diff --git a/scripts/Makefile b/scripts/Makefile
index be8e3e0..d6ea48c 100644
--- a/scripts/Makefile
+++ b/scripts/Makefile
@@ -9,6 +9,7 @@ hostprogs-y += bin2c
hostprogs-y += mkimage
hostprogs-y += bareboxenv
hostprogs-$(CONFIG_ARCH_NETX) += gen_netx_image
+hostprogs-$(CONFIG_ARCH_OMAP) += omap_signGP
always := $(hostprogs-y) $(hostprogs-m)
diff --git a/scripts/omap_signGP.c b/scripts/omap_signGP.c
new file mode 100644
index 0000000..d20d357
--- /dev/null
+++ b/scripts/omap_signGP.c
@@ -0,0 +1,313 @@
+/**
+ * signGP.c - Read the x-load.bin file and write out the x-load.bin.ift file
+ *
+ * The signed image is the original pre-pended with the size of the image
+ * and the load address. If not entered on command line, file name is
+ * assumed to be x-load.bin in current directory and load address is
+ * 0x40200800.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdio.h>
+#include <errno.h>
+#include <stdlib.h>
+#include <fcntl.h>
+#include <sys/stat.h>
+#include <string.h>
+#include <malloc.h>
+#include <linux/types.h>
+
+#undef CH_WITH_CHRAM
+struct chsettings {
+ __u32 section_key;
+ __u8 valid;
+ __u8 version;
+ __u16 reserved;
+ __u32 flags;
+} __attribute__ ((__packed__));
+
+/* __u32 cm_clksel_core;
+ __u32 reserved1;
+ __u32 cm_autoidle_dpll_mpu;
+ __u32 cm_clksel_dpll_mpu;
+ __u32 cm_div_m2_dpll_mpu;
+ __u32 cm_autoidle_dpll_core;
+ __u32 cm_clksel_dpll_core;
+ __u32 cm_div_m2_dpll_core;
+ __u32 cm_div_m3_dpll_core;
+ __u32 cm_div_m4_dpll_core;
+ __u32 cm_div_m5_dpll_core;
+ __u32 cm_div_m6_dpll_core;
+ __u32 cm_div_m7_dpll_core;
+ __u32 cm_autoidle_dpll_per;
+ __u32 cm_clksel_dpll_per;
+ __u32 cm_div_m2_dpll_per;
+ __u32 cm_div_m3_dpll_per;
+ __u32 cm_div_m4_dpll_per;
+ __u32 cm_div_m5_dpll_per;
+ __u32 cm_div_m6_dpll_per;
+ __u32 cm_div_m7_dpll_per;
+ __u32 cm_autoidle_dpll_usb;
+ __u32 cm_clksel_dpll_usb;
+ __u32 cm_div_m2_dpll_usb;
+}*/
+
+struct gp_header {
+ __u32 size;
+ __u32 load_addr;
+} __attribute__ ((__packed__));
+
+struct ch_toc {
+ __u32 section_offset;
+ __u32 section_size;
+ __u8 unused[12];
+ __u8 section_name[12];
+} __attribute__ ((__packed__));
+
+struct chram {
+ /* CHRAM */
+ __u32 section_key_chr;
+ __u8 section_disable_chr;
+ __u8 pad_chr[3];
+ /* EMIF1 */
+ __u32 config_emif1;
+ __u32 refresh_emif1;
+ __u32 tim1_emif1;
+ __u32 tim2_emif1;
+ __u32 tim3_emif1;
+ __u32 pwrControl_emif1;
+ __u32 phy_cntr1_emif1;
+ __u32 phy_cntr2_emif1;
+ __u8 modereg1_emif1;
+ __u8 modereg2_emif1;
+ __u8 modereg3_emif1;
+ __u8 pad_emif1;
+ /* EMIF2 */
+ __u32 config_emif2;
+ __u32 refresh_emif2;
+ __u32 tim1_emif2;
+ __u32 tim2_emif2;
+ __u32 tim3_emif2;
+ __u32 pwrControl_emif2;
+ __u32 phy_cntr1_emif2;
+ __u32 phy_cntr2_emif2;
+ __u8 modereg1_emif2;
+ __u8 modereg2_emif2;
+ __u8 modereg3_emif2;
+ __u8 pad_emif2;
+
+ __u32 dmm_lisa_map;
+ __u8 flags;
+ __u8 pad[3];
+} __attribute__ ((__packed__));
+
+
+struct ch_chsettings_chram {
+ struct ch_toc toc_chsettings;
+ struct ch_toc toc_chram;
+ struct ch_toc toc_terminator;
+ struct chsettings section_chsettings;
+ struct chram section_chram;
+ __u8 padding1[512 -
+ (sizeof(struct ch_toc) * 3 +
+ sizeof(struct chsettings) + sizeof(struct chram))];
+ /* struct gp_header gpheader; */
+} __attribute__ ((__packed__));
+
+struct ch_chsettings_nochram {
+ struct ch_toc toc_chsettings;
+ struct ch_toc toc_terminator;
+ struct chsettings section_chsettings;
+ __u8 padding1[512 -
+ (sizeof(struct ch_toc) * 2 +
+ sizeof(struct chsettings))];
+ /* struct gp_header gpheader; */
+} __attribute__ ((__packed__));
+
+
+#ifdef CH_WITH_CHRAM
+static const struct ch_chsettings_chram config_header = {
+ /* CHSETTINGS TOC */
+ {sizeof(struct ch_toc) * 4,
+ sizeof(struct chsettings),
+ "",
+ {"CHSETTINGS"}
+ },
+ /* CHRAM TOC */
+ {sizeof(struct ch_toc) * 4 + sizeof(struct chsettings),
+ sizeof(struct chram),
+ "",
+ {"CHRAM"}
+ },
+ /* toc terminator */
+ {0xFFFFFFFF,
+ 0xFFFFFFFF,
+ {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF},
+ {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF}
+ },
+ /* CHSETTINGS section */
+ {
+ 0xC0C0C0C1,
+ 0,
+ 1,
+ 0,
+ 0},
+ /* CHRAM section */
+ {
+ 0xc0c0c0c2,
+ 0x01,
+ {0x00, 0x00, 0x00},
+
+ /* EMIF1 */
+ 0x80800eb2,
+ 0x00000010,
+ 0x110d1624,
+ 0x3058161b,
+ 0x030060b2,
+ 0x00000200,
+ 0x901ff416,
+ 0x00000000,
+ 0x23,
+ 0x01,
+ 0x02,
+ 0x00,
+
+ /* EMIF2 */
+ 0x80800eb2,
+ 0x000002ba,
+ 0x110d1624,
+ 0x3058161b,
+ 0x03006542,
+ 0x00000200,
+ 0x901ff416,
+ 0x00000000,
+ 0x23,
+ 0x01,
+ 0x02,
+ 0x00,
+
+ /* LISA map */
+ 0x80700100,
+ 0x05,
+ {0x00, 0x00, 0x00},
+ },
+ ""
+};
+#else
+static struct ch_chsettings_nochram config_header
+ __attribute__((section(".config_header"))) = {
+ /* CHSETTINGS TOC */
+ {(sizeof(struct ch_toc)) * 2,
+ sizeof(struct chsettings),
+ "",
+ {"CHSETTINGS"}
+ },
+ /* toc terminator */
+ {0xFFFFFFFF,
+ 0xFFFFFFFF,
+ {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF},
+ {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF}
+ },
+ /* CHSETTINGS section */
+ {
+ 0xC0C0C0C1,
+ 0,
+ 1,
+ 0,
+ 0},
+ ""
+};
+#endif
+
+
+#define err(...) do { int save_errno = errno; \
+ fprintf(stderr, __VA_ARGS__); \
+ errno = save_errno; \
+ } while (0);
+#define pdie(func, ...) do { perror(func); exit(1); } while (0);
+
+int main(int argc, char *argv[])
+{
+ int i;
+ char ifname[FILENAME_MAX], ofname[FILENAME_MAX], ch;
+ FILE *ifile, *ofile;
+ unsigned long loadaddr, len;
+ struct stat sinfo;
+ int ch_add = 0;
+
+
+ /* Default to x-load.bin and 0x40200800. */
+ strcpy(ifname, "x-load.bin");
+ loadaddr = 0x40200800;
+
+ if ((argc == 2) || (argc == 3) || (argc == 4))
+ strcpy(ifname, argv[1]);
+
+ if ((argc == 3) || (argc == 4))
+ loadaddr = strtoul(argv[2], NULL, 16);
+
+ if (argc == 4)
+ ch_add = strtoul(argv[3], NULL, 16);
+
+ /* Form the output file name. */
+ strcpy(ofname, ifname);
+ strcat(ofname, ".ift");
+
+ /* Open the input file. */
+ ifile = fopen(ifname, "rb");
+ if (ifile == NULL) {
+ err("Cannot open %s\n", ifname);
+ pdie("fopen");
+ }
+
+ /* Get file length. */
+ stat(ifname, &sinfo);
+ len = sinfo.st_size;
+
+ /* Open the output file and write it. */
+ ofile = fopen(ofname, "wb");
+ if (ofile == NULL) {
+ fclose(ifile);
+ err("Cannot open %s\n", ofname);
+ pdie("fopen");
+ }
+
+ if (ch_add)
+ if (fwrite(&config_header, 1, 512, ofile) <= 0)
+ pdie("fwrite");
+
+ if (fwrite(&len, 1, 4, ofile) <= 0)
+ pdie("fwrite");
+ if (fwrite(&loadaddr, 1, 4, ofile) <= 0)
+ pdie("fwrite");
+ for (i = 0; i < len; i++) {
+ if (fread(&ch, 1, 1, ifile) <= 0)
+ pdie("fread");
+ if (fwrite(&ch, 1, 1, ofile) <= 0)
+ pdie("fwrite");
+ }
+
+ if (fclose(ifile))
+ perror("warning: fclose");
+ if (fclose(ofile))
+ perror("warning: fclose");
+
+ return 0;
+}
--
1.7.2.3
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^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 02/12] mci omap: hsmmc is also found on the omap3
2011-04-11 14:39 OMAP4 support Sascha Hauer
2011-04-11 14:39 ` [PATCH 01/12] ARM omap: Add omap signGP tool and possibility to build ift images Sascha Hauer
@ 2011-04-11 14:39 ` Sascha Hauer
2011-04-11 14:39 ` [PATCH 03/12] ARM omap: make sr32 a static inline function Sascha Hauer
` (9 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Sascha Hauer @ 2011-04-11 14:39 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/mci/Kconfig | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/mci/Kconfig b/drivers/mci/Kconfig
index cfed72f..5d8adbd 100644
--- a/drivers/mci/Kconfig
+++ b/drivers/mci/Kconfig
@@ -68,7 +68,7 @@ config MCI_IMX_ESDHC_PIO
config MCI_OMAP_HSMMC
bool "OMAP HSMMC"
- depends on ARCH_OMAP4
+ depends on ARCH_OMAP4 || ARCH_OMAP3
help
Enable this entry to add support to read and write SD cards on a
OMAP4 based system.
--
1.7.2.3
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^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 03/12] ARM omap: make sr32 a static inline function
2011-04-11 14:39 OMAP4 support Sascha Hauer
2011-04-11 14:39 ` [PATCH 01/12] ARM omap: Add omap signGP tool and possibility to build ift images Sascha Hauer
2011-04-11 14:39 ` [PATCH 02/12] mci omap: hsmmc is also found on the omap3 Sascha Hauer
@ 2011-04-11 14:39 ` Sascha Hauer
2011-04-11 14:39 ` [PATCH 04/12] ARM omap: Add omap4 support Sascha Hauer
` (8 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Sascha Hauer @ 2011-04-11 14:39 UTC (permalink / raw)
To: barebox
This generates smaller code.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-omap/include/mach/syslib.h | 23 ++++++++++++++++++++++-
arch/arm/mach-omap/syslib.c | 20 --------------------
2 files changed, 22 insertions(+), 21 deletions(-)
diff --git a/arch/arm/mach-omap/include/mach/syslib.h b/arch/arm/mach-omap/include/mach/syslib.h
index c89f50b..6a7044a 100644
--- a/arch/arm/mach-omap/include/mach/syslib.h
+++ b/arch/arm/mach-omap/include/mach/syslib.h
@@ -30,9 +30,30 @@
*/
#ifndef __ASM_ARCH_OMAP_SYSLIB_H_
#define __ASM_ARCH_OMAP_SYSLIB_H_
+#include <asm/io.h>
/** System Independent functions */
-void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value);
+
+/**
+ * @brief clear & set a value in a bit range for a 32 bit address
+ *
+ * @param[in] addr Address to set/read from
+ * @param[in] start_bit Where to put the value
+ * @param[in] num_bits number of bits the value should be set
+ * @param[in] value the value to set
+ *
+ * @return void
+ */
+static inline void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
+{
+ u32 tmp, msk = 0;
+ msk = 1 << num_bits;
+ --msk;
+ tmp = readl(addr) & ~(msk << start_bit);
+ tmp |= value << start_bit;
+ writel(tmp, addr);
+}
+
u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound);
void sdelay(unsigned long loops);
diff --git a/arch/arm/mach-omap/syslib.c b/arch/arm/mach-omap/syslib.c
index 2b25dc1..677de6a 100644
--- a/arch/arm/mach-omap/syslib.c
+++ b/arch/arm/mach-omap/syslib.c
@@ -53,26 +53,6 @@ void sdelay(unsigned long loops)
}
/**
- * @brief clear & set a value in a bit range for a 32 bit address
- *
- * @param[in] addr Address to set/read from
- * @param[in] start_bit Where to put the value
- * @param[in] num_bits number of bits the value should be set
- * @param[in] value the value to set
- *
- * @return void
- */
-void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
-{
- u32 tmp, msk = 0;
- msk = 1 << num_bits;
- --msk;
- tmp = readl(addr) & ~(msk << start_bit);
- tmp |= value << start_bit;
- writel(tmp, addr);
-}
-
-/**
* @brief common routine to allow waiting for changes in volatile regs.
*
* @param[in] read_bit_mask the bit mask to read
--
1.7.2.3
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^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 04/12] ARM omap: Add omap4 support
2011-04-11 14:39 OMAP4 support Sascha Hauer
` (2 preceding siblings ...)
2011-04-11 14:39 ` [PATCH 03/12] ARM omap: make sr32 a static inline function Sascha Hauer
@ 2011-04-11 14:39 ` Sascha Hauer
2011-04-11 14:39 ` [PATCH 05/12] ARM omap: add xload helper functions Sascha Hauer
` (7 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Sascha Hauer @ 2011-04-11 14:39 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-omap/Kconfig | 13 +-
arch/arm/mach-omap/Makefile | 1 +
arch/arm/mach-omap/gpio.c | 18 +
arch/arm/mach-omap/include/mach/omap4-clock.h | 320 ++++++++++++++++++
arch/arm/mach-omap/include/mach/omap4-mux.h | 344 +++++++++++++++++++
arch/arm/mach-omap/include/mach/omap4-silicon.h | 179 ++++++++++
arch/arm/mach-omap/include/mach/silicon.h | 3 +
arch/arm/mach-omap/omap4_clock.c | 380 +++++++++++++++++++++
arch/arm/mach-omap/omap4_generic.c | 406 +++++++++++++++++++++++
9 files changed, 1663 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-omap/include/mach/omap4-clock.h
create mode 100644 arch/arm/mach-omap/include/mach/omap4-mux.h
create mode 100644 arch/arm/mach-omap/include/mach/omap4-silicon.h
create mode 100644 arch/arm/mach-omap/omap4_clock.c
create mode 100644 arch/arm/mach-omap/omap4_generic.c
diff --git a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig
index 351c469..df83b17 100644
--- a/arch/arm/mach-omap/Kconfig
+++ b/arch/arm/mach-omap/Kconfig
@@ -38,6 +38,14 @@ config ARCH_OMAP3
help
Say Y here if you are using Texas Instrument's OMAP343x based platform
+config ARCH_OMAP4
+ bool "OMAP4"
+ select CPU_V7
+ select GENERIC_GPIO
+ select OMAP_CLOCK_SOURCE_S32K
+ help
+ Say Y here if you are using Texas Instrument's OMAP4 based platform
+
endchoice
### Generic Clock configurations to be enabled by Mach - invisible to enable.
@@ -76,7 +84,7 @@ config OMAP3_COPY_CLOCK_SRAM
config OMAP_GPMC
prompt "Support for GPMC configuration"
bool
- depends on (ARCH_OMAP2 || ARCH_OMAP3)
+ depends on (ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP4)
default y
help
Enable this if you use Texas Instrument's General purpose Memory
@@ -106,6 +114,7 @@ config MACH_OMAP343xSDP
select MACH_HAS_LOWLEVEL_INIT
select OMAP_CLOCK_ALL
select HAS_OMAP_NAND
+ depends on ARCH_OMAP3
help
Say Y here if you are using SDP343x platform
@@ -114,6 +123,7 @@ config MACH_BEAGLE
select MACH_HAS_LOWLEVEL_INIT
select OMAP_CLOCK_ALL
select HAS_OMAP_NAND
+ depends on ARCH_OMAP3
help
Say Y here if you are using Beagle Board
@@ -122,6 +132,7 @@ config MACH_OMAP3EVM
select MACH_HAS_LOWLEVEL_INIT
select OMAP_CLOCK_ALL
select HAS_OMAP_NAND
+ depends on ARCH_OMAP3
help
Say Y here if you are using OMAP3EVM
diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile
index 13c327c..9c31456 100644
--- a/arch/arm/mach-omap/Makefile
+++ b/arch/arm/mach-omap/Makefile
@@ -22,6 +22,7 @@
obj-$(CONFIG_ARCH_OMAP) += syslib.o
obj-$(CONFIG_OMAP_CLOCK_SOURCE_S32K) += s32k_clksource.o
obj-$(CONFIG_ARCH_OMAP3) += omap3_core.o omap3_generic.o
+obj-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o
obj-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock_core.o omap3_clock.o
obj-$(CONFIG_OMAP_GPMC) += gpmc.o devices-gpmc-nand.o
obj-y += omap-uart.o gpio.o
diff --git a/arch/arm/mach-omap/gpio.c b/arch/arm/mach-omap/gpio.c
index 68b7890..b0bd805 100644
--- a/arch/arm/mach-omap/gpio.c
+++ b/arch/arm/mach-omap/gpio.c
@@ -58,6 +58,24 @@ static void __iomem *gpio_bank[] = {
};
#endif
+#ifdef CONFIG_ARCH_OMAP4
+
+#define OMAP_GPIO_OE 0x0134
+#define OMAP_GPIO_DATAIN 0x0138
+#define OMAP_GPIO_DATAOUT 0x013c
+#define OMAP_GPIO_CLEARDATAOUT 0x0190
+#define OMAP_GPIO_SETDATAOUT 0x0194
+
+static void __iomem *gpio_bank[] = {
+ (void *)0x4a310000,
+ (void *)0x48055000,
+ (void *)0x48057000,
+ (void *)0x48059000,
+ (void *)0x4805b000,
+ (void *)0x4805d000,
+};
+#endif
+
static inline void __iomem *get_gpio_base(int gpio)
{
return gpio_bank[gpio >> 5];
diff --git a/arch/arm/mach-omap/include/mach/omap4-clock.h b/arch/arm/mach-omap/include/mach/omap4-clock.h
new file mode 100644
index 0000000..0a31d09
--- /dev/null
+++ b/arch/arm/mach-omap/include/mach/omap4-clock.h
@@ -0,0 +1,320 @@
+ /* PRCM */
+#define CM_SYS_CLKSEL 0x4a306110
+
+#define CM_SYS_CLKSEL_19M2 0x4
+#define CM_SYS_CLKSEL_38M4 0x7
+
+/* PRM.CKGEN module registers */
+#define CM_ABE_PLL_REF_CLKSEL 0x4a30610c
+
+
+/* PRM.WKUP_CM module registers */
+#define CM_WKUP_CLKSTCTRL 0x4a307800
+#define CM_WKUP_L4WKUP_CLKCTRL 0x4a307820
+#define CM_WKUP_WDT1_CLKCTRL 0x4a307828
+#define CM_WKUP_WDT2_CLKCTRL 0x4a307830
+#define CM_WKUP_GPIO1_CLKCTRL 0x4a307838
+#define CM_WKUP_TIMER1_CLKCTRL 0x4a307840
+#define CM_WKUP_TIMER12_CLKCTRL 0x4a307848
+#define CM_WKUP_SYNCTIMER_CLKCTRL 0x4a307850
+#define CM_WKUP_USIM_CLKCTRL 0x4a307858
+#define CM_WKUP_SARRAM_CLKCTRL 0x4a307860
+#define CM_WKUP_KEYBOARD_CLKCTRL 0x4a307878
+#define CM_WKUP_RTC_CLKCTRL 0x4a307880
+#define CM_WKUP_BANDGAP_CLKCTRL 0x4a307888
+
+/* CM1.CKGEN module registers */
+#define CM_CLKSEL_CORE 0x4a004100
+#define CM_CLKSEL_ABE 0x4a004108
+#define CM_DLL_CTRL 0x4a004110
+#define CM_CLKMODE_DPLL_CORE 0x4a004120
+#define CM_IDLEST_DPLL_CORE 0x4a004124
+#define CM_AUTOIDLE_DPLL_CORE 0x4a004128
+#define CM_CLKSEL_DPLL_CORE 0x4a00412c
+#define CM_DIV_M2_DPLL_CORE 0x4a004130
+#define CM_DIV_M3_DPLL_CORE 0x4a004134
+#define CM_DIV_M4_DPLL_CORE 0x4a004138
+#define CM_DIV_M5_DPLL_CORE 0x4a00413c
+#define CM_DIV_M6_DPLL_CORE 0x4a004140
+#define CM_DIV_M7_DPLL_CORE 0x4a004144
+#define CM_SSC_DELTAMSTEP_DPLL_CORE 0x4a004148
+#define CM_SSC_MODFREQDIV_DPLL_CORE 0x4a00414c
+#define CM_EMU_OVERRIDE_DPLL_CORE 0x4a004150
+#define CM_CLKMODE_DPLL_MPU 0x4a004160
+#define CM_IDLEST_DPLL_MPU 0x4a004164
+#define CM_AUTOIDLE_DPLL_MPU 0x4a004168
+#define CM_CLKSEL_DPLL_MPU 0x4a00416c
+#define CM_DIV_M2_DPLL_MPU 0x4a004170
+#define CM_SSC_DELTAMSTEP_DPLL_MPU 0x4a004188
+#define CM_SSC_MODFREQDIV_DPLL_MPU 0x4a00418c
+#define CM_BYPCLK_DPLL_MPU 0x4a00419c
+#define CM_CLKMODE_DPLL_IVA 0x4a0041a0
+#define CM_IDLEST_DPLL_IVA 0x4a0041a4
+#define CM_AUTOIDLE_DPLL_IVA 0x4a0041a8
+#define CM_CLKSEL_DPLL_IVA 0x4a0041ac
+#define CM_DIV_M4_DPLL_IVA 0x4a0041b8
+#define CM_DIV_M5_DPLL_IVA 0x4a0041bc
+#define CM_SSC_DELTAMSTEP_DPLL_IVA 0x4a0041c8
+#define CM_SSC_MODFREQDIV_DPLL_IVA 0x4a0041cc
+#define CM_BYPCLK_DPLL_IVA 0x4a0041dc
+#define CM_CLKMODE_DPLL_ABE 0x4a0041e0
+#define CM_IDLEST_DPLL_ABE 0x4a0041e4
+#define CM_AUTOIDLE_DPLL_ABE 0x4a0041e8
+#define CM_CLKSEL_DPLL_ABE 0x4a0041ec
+#define CM_DIV_M2_DPLL_ABE 0x4a0041f0
+#define CM_DIV_M3_DPLL_ABE 0x4a0041f4
+#define CM_SSC_DELTAMSTEP_DPLL_ABE 0x4a004208
+#define CM_SSC_MODFREQDIV_DPLL_ABE 0x4a00420c
+#define CM_CLKMODE_DPLL_DDRPHY 0x4a004220
+#define CM_IDLEST_DPLL_DDRPHY 0x4a004224
+#define CM_AUTOIDLE_DPLL_DDRPHY 0x4a004228
+#define CM_CLKSEL_DPLL_DDRPHY 0x4a00422c
+#define CM_DIV_M2_DPLL_DDRPHY 0x4a004230
+#define CM_DIV_M4_DPLL_DDRPHY 0x4a004238
+#define CM_DIV_M5_DPLL_DDRPHY 0x4a00423c
+#define CM_DIV_M6_DPLL_DDRPHY 0x4a004240
+#define CM_SSC_DELTAMSTEP_DPLL_DDRPHY 0x4a004248
+
+/* CM1.ABE register offsets */
+#define CM1_ABE_CLKSTCTRL 0x4a004500
+#define CM1_ABE_L4ABE_CLKCTRL 0x4a004520
+#define CM1_ABE_AESS_CLKCTRL 0x4a004528
+#define CM1_ABE_PDM_CLKCTRL 0x4a004530
+#define CM1_ABE_DMIC_CLKCTRL 0x4a004538
+#define CM1_ABE_MCASP_CLKCTRL 0x4a004540
+#define CM1_ABE_MCBSP1_CLKCTRL 0x4a004548
+#define CM1_ABE_MCBSP2_CLKCTRL 0x4a004550
+#define CM1_ABE_MCBSP3_CLKCTRL 0x4a004558
+#define CM1_ABE_SLIMBUS_CLKCTRL 0x4a004560
+#define CM1_ABE_TIMER5_CLKCTRL 0x4a004568
+#define CM1_ABE_TIMER6_CLKCTRL 0x4a004570
+#define CM1_ABE_TIMER7_CLKCTRL 0x4a004578
+#define CM1_ABE_TIMER8_CLKCTRL 0x4a004580
+#define CM1_ABE_WDT3_CLKCTRL 0x4a004588
+
+/* CM1.DSP register offsets */
+#define DSP_CLKSTCTRL 0x4a004400
+#define DSP_DSP_CLKCTRL 0x4a004420
+
+/* CM2.CKGEN module registers */
+#define CM_CLKSEL_DUCATI_ISS_ROOT 0x4a008100
+#define CM_CLKSEL_USB_60MHz 0x4a008104
+#define CM_SCALE_FCLK 0x4a008108
+#define CM_CORE_DVFS_PERF1 0x4a008110
+#define CM_CORE_DVFS_PERF2 0x4a008114
+#define CM_CORE_DVFS_PERF3 0x4a008118
+#define CM_CORE_DVFS_PERF4 0x4a00811c
+#define CM_CORE_DVFS_CURRENT 0x4a008124
+#define CM_IVA_DVFS_PERF_TESLA 0x4a008128
+#define CM_IVA_DVFS_PERF_IVAHD 0x4a00812c
+#define CM_IVA_DVFS_PERF_ABE 0x4a008130
+#define CM_IVA_DVFS_CURRENT 0x4a008138
+#define CM_CLKMODE_DPLL_PER 0x4a008140
+#define CM_IDLEST_DPLL_PER 0x4a008144
+#define CM_AUTOIDLE_DPLL_PER 0x4a008148
+#define CM_CLKSEL_DPLL_PER 0x4a00814c
+#define CM_DIV_M2_DPLL_PER 0x4a008150
+#define CM_DIV_M3_DPLL_PER 0x4a008154
+#define CM_DIV_M4_DPLL_PER 0x4a008158
+#define CM_DIV_M5_DPLL_PER 0x4a00815c
+#define CM_DIV_M6_DPLL_PER 0x4a008160
+#define CM_DIV_M7_DPLL_PER 0x4a008164
+#define CM_SSC_DELTAMSTEP_DPLL_PER 0x4a008168
+#define CM_SSC_MODFREQDIV_DPLL_PER 0x4a00816c
+#define CM_EMU_OVERRIDE_DPLL_PER 0x4a008170
+#define CM_CLKMODE_DPLL_USB 0x4a008180
+#define CM_IDLEST_DPLL_USB 0x4a008184
+#define CM_AUTOIDLE_DPLL_USB 0x4a008188
+#define CM_CLKSEL_DPLL_USB 0x4a00818c
+#define CM_DIV_M2_DPLL_USB 0x4a008190
+#define CM_SSC_DELTAMSTEP_DPLL_USB 0x4a0081a8
+#define CM_SSC_MODFREQDIV_DPLL_USB 0x4a0081ac
+#define CM_CLKDCOLDO_DPLL_USB 0x4a0081b4
+#define CM_CLKMODE_DPLL_UNIPRO 0x4a0081c0
+#define CM_IDLEST_DPLL_UNIPRO 0x4a0081c4
+#define CM_AUTOIDLE_DPLL_UNIPRO 0x4a0081c8
+#define CM_CLKSEL_DPLL_UNIPRO 0x4a0081cc
+#define CM_DIV_M2_DPLL_UNIPRO 0x4a0081d0
+#define CM_SSC_DELTAMSTEP_DPLL_UNIPRO 0x4a0081e8
+#define CM_SSC_MODFREQDIV_DPLL_UNIPRO 0x4a0081ec
+
+/* CM2.CORE module registers */
+#define CM_L3_1_CLKSTCTRL 0x4a008700
+#define CM_L3_1_DYNAMICDEP 0x4a008708
+#define CM_L3_1_L3_1_CLKCTRL 0x4a008720
+#define CM_L3_2_CLKSTCTRL 0x4a008800
+#define CM_L3_2_DYNAMICDEP 0x4a008808
+#define CM_L3_2_L3_2_CLKCTRL 0x4a008820
+#define CM_L3_2_GPMC_CLKCTRL 0x4a008828
+#define CM_L3_2_OCMC_RAM_CLKCTRL 0x4a008830
+#define CM_DUCATI_CLKSTCTRL 0x4a008900
+#define CM_DUCATI_STATICDEP 0x4a008904
+#define CM_DUCATI_DYNAMICDEP 0x4a008908
+#define CM_DUCATI_DUCATI_CLKCTRL 0x4a008920
+#define CM_SDMA_CLKSTCTRL 0x4a008a00
+#define CM_SDMA_STATICDEP 0x4a008a04
+#define CM_SDMA_DYNAMICDEP 0x4a008a08
+#define CM_SDMA_SDMA_CLKCTRL 0x4a008a20
+#define CM_MEMIF_CLKSTCTRL 0x4a008b00
+#define CM_MEMIF_DMM_CLKCTRL 0x4a008b20
+#define CM_MEMIF_EMIF_FW_CLKCTRL 0x4a008b28
+#define CM_MEMIF_EMIF_1_CLKCTRL 0x4a008b30
+#define CM_MEMIF_EMIF_2_CLKCTRL 0x4a008b38
+#define CM_MEMIF_DLL_CLKCTRL 0x4a008b40
+#define CM_MEMIF_EMIF_H1_CLKCTRL 0x4a008b50
+#define CM_MEMIF_EMIF_H2_CLKCTRL 0x4a008b58
+#define CM_MEMIF_DLL_H_CLKCTRL 0x4a008b60
+#define CM_D2D_CLKSTCTRL 0x4a008c00
+#define CM_D2D_STATICDEP 0x4a008c04
+#define CM_D2D_DYNAMICDEP 0x4a008c08
+#define CM_D2D_SAD2D_CLKCTRL 0x4a008c20
+#define CM_D2D_MODEM_ICR_CLKCTRL 0x4a008c28
+#define CM_D2D_SAD2D_FW_CLKCTRL 0x4a008c30
+#define CM_L4CFG_CLKSTCTRL 0x4a008d00
+#define CM_L4CFG_DYNAMICDEP 0x4a008d08
+#define CM_L4CFG_L4_CFG_CLKCTRL 0x4a008d20
+#define CM_L4CFG_HW_SEM_CLKCTRL 0x4a008d28
+#define CM_L4CFG_MAILBOX_CLKCTRL 0x4a008d30
+#define CM_L4CFG_SAR_ROM_CLKCTRL 0x4a008d38
+#define CM_L3INSTR_CLKSTCTRL 0x4a008e00
+#define CM_L3INSTR_L3_3_CLKCTRL 0x4a008e20
+#define CM_L3INSTR_L3_INSTR_CLKCTRL 0x4a008e28
+#define CM_L3INSTR_OCP_WP1_CLKCTRL 0x4a008e40
+
+/* CM2.L4PER register offsets */
+#define CM_L4PER_CLKSTCTRL 0x4a009400
+#define CM_L4PER_DYNAMICDEP 0x4a009408
+#define CM_L4PER_ADC_CLKCTRL 0x4a009420
+#define CM_L4PER_DMTIMER10_CLKCTRL 0x4a009428
+#define CM_L4PER_DMTIMER11_CLKCTRL 0x4a009430
+#define CM_L4PER_DMTIMER2_CLKCTRL 0x4a009438
+#define CM_L4PER_DMTIMER3_CLKCTRL 0x4a009440
+#define CM_L4PER_DMTIMER4_CLKCTRL 0x4a009448
+#define CM_L4PER_DMTIMER9_CLKCTRL 0x4a009450
+#define CM_L4PER_ELM_CLKCTRL 0x4a009458
+#define CM_L4PER_GPIO2_CLKCTRL 0x4a009460
+#define CM_L4PER_GPIO3_CLKCTRL 0x4a009468
+#define CM_L4PER_GPIO4_CLKCTRL 0x4a009470
+#define CM_L4PER_GPIO5_CLKCTRL 0x4a009478
+#define CM_L4PER_GPIO6_CLKCTRL 0x4a009480
+#define CM_L4PER_HDQ1W_CLKCTRL 0x4a009488
+#define CM_L4PER_HECC1_CLKCTRL 0x4a009490
+#define CM_L4PER_HECC2_CLKCTRL 0x4a009498
+#define CM_L4PER_I2C1_CLKCTRL 0x4a0094a0
+#define CM_L4PER_I2C2_CLKCTRL 0x4a0094a8
+#define CM_L4PER_I2C3_CLKCTRL 0x4a0094b0
+#define CM_L4PER_I2C4_CLKCTRL 0x4a0094b8
+#define CM_L4PER_L4PER_CLKCTRL 0x4a0094c0
+#define CM_L4PER_MCASP2_CLKCTRL 0x4a0094d0
+#define CM_L4PER_MCASP3_CLKCTRL 0x4a0094d8
+#define CM_L4PER_MCBSP4_CLKCTRL 0x4a0094e0
+#define CM_L4PER_MGATE_CLKCTRL 0x4a0094e8
+#define CM_L4PER_MCSPI1_CLKCTRL 0x4a0094f0
+#define CM_L4PER_MCSPI2_CLKCTRL 0x4a0094f8
+#define CM_L4PER_MCSPI3_CLKCTRL 0x4a009500
+#define CM_L4PER_MCSPI4_CLKCTRL 0x4a009508
+#define CM_L4PER_MMCSD3_CLKCTRL 0x4a009520
+#define CM_L4PER_MMCSD4_CLKCTRL 0x4a009528
+#define CM_L4PER_MSPROHG_CLKCTRL 0x4a009530
+#define CM_L4PER_SLIMBUS2_CLKCTRL 0x4a009538
+#define CM_L4PER_UART1_CLKCTRL 0x4a009540
+#define CM_L4PER_UART2_CLKCTRL 0x4a009548
+#define CM_L4PER_UART3_CLKCTRL 0x4a009550
+#define CM_L4PER_UART4_CLKCTRL 0x4a009558
+#define CM_L4PER_MMCSD5_CLKCTRL 0x4a009560
+#define CM_L4PER_I2C5_CLKCTRL 0x4a009568
+#define CM_L4SEC_CLKSTCTRL 0x4a009580
+#define CM_L4SEC_STATICDEP 0x4a009584
+#define CM_L4SEC_DYNAMICDEP 0x4a009588
+#define CM_L4SEC_AES1_CLKCTRL 0x4a0095a0
+#define CM_L4SEC_AES2_CLKCTRL 0x4a0095a8
+#define CM_L4SEC_DES3DES_CLKCTRL 0x4a0095b0
+#define CM_L4SEC_PKAEIP29_CLKCTRL 0x4a0095b8
+#define CM_L4SEC_RNG_CLKCTRL 0x4a0095c0
+#define CM_L4SEC_SHA2MD51_CLKCTRL 0x4a0095c8
+#define CM_L4SEC_CRYPTODMA_CLKCTRL 0x4a0095d8
+
+/* CM2.IVAHD */
+#define IVAHD_CLKSTCTRL 0x4a008f00
+#define IVAHD_IVAHD_CLKCTRL 0x4a008f20
+#define IVAHD_SL2_CLKCTRL 0x4a008f28
+
+/* CM2.L3INIT */
+#define CM_L3INIT_HSMMC1_CLKCTRL 0x4a009328
+#define CM_L3INIT_HSMMC2_CLKCTRL 0x4a009330
+#define CM_L3INIT_HSI_CLKCTRL 0x4a009338
+#define CM_L3INIT_UNIPRO1_CLKCTRL 0x4a009340
+#define CM_L3INIT_HSUSBHOST_CLKCTRL 0x4a009358
+#define CM_L3INIT_HSUSBOTG_CLKCTRL 0x4a009360
+#define CM_L3INIT_HSUSBTLL_CLKCTRL 0x4a009368
+#define CM_L3INIT_P1500_CLKCTRL 0x4a009378
+#define CM_L3INIT_FSUSB_CLKCTRL 0x4a0093d0
+#define CM_L3INIT_USBPHY_CLKCTRL 0x4a0093e0
+
+/* CM2.CAM */
+#define CM_CAM_CLKSTCTRL 0x4a009000
+#define CM_CAM_ISS_CLKCTRL 0x4a009020
+#define CM_CAM_FDIF_CLKCTRL 0x4a009028
+
+/* CM2.DSS */
+#define CM_DSS_CLKSTCTRL 0x4a009100
+#define CM_DSS_DSS_CLKCTRL 0x4a009120
+#define CM_DSS_DEISS_CLKCTRL 0x4a009128
+
+/* CM2.SGX */
+#define CM_SGX_CLKSTCTRL 0x4a009200
+#define CM_SGX_SGX_CLKCTRL 0x4a009220
+
+#define PLL_STOP 1 /* PER & IVA */
+#define PLL_MN_POWER_BYPASS 4
+#define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */
+#define PLL_FAST_RELOCK_BYPASS 6 /* CORE */
+#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */
+
+/* Used to index into DPLL parameter tables */
+struct dpll_param {
+ unsigned int m;
+ unsigned int n;
+ unsigned int m2;
+ unsigned int m3;
+ unsigned int m4;
+ unsigned int m5;
+ unsigned int m6;
+ unsigned int m7;
+};
+
+#define OMAP4_MPU_DPLL_PARAM_19M2 {0x34, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
+#define OMAP4_MPU_DPLL_PARAM_19M2_MPU600 {0x7d, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
+#define OMAP4_MPU_DPLL_PARAM_19M2_MPU1000 {0x69, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
+#define OMAP4_MPU_DPLL_PARAM_38M4 {0x1a, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
+#define OMAP4_MPU_DPLL_PARAM_38M4_MPU600 {0x7d, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
+#define OMAP4_MPU_DPLL_PARAM_38M4_MPU1000 {0x69, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
+
+#define OMAP4_IVA_DPLL_PARAM_19M2 {0x61, 0x01, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00}
+#define OMAP4_IVA_DPLL_PARAM_38M4 {0x61, 0x03, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00}
+
+#define OMAP4_PER_DPLL_PARAM_19M2 {0x28, 0x00, 0x08, 0x06, 0x0c, 0x09, 0x04, 0x05}
+#define OMAP4_PER_DPLL_PARAM_38M4 {0x14, 0x00, 0x08, 0x06, 0x0c, 0x09, 0x04, 0x05}
+
+#define OMAP4_ABE_DPLL_PARAM_19M2 {0x80, 0x18, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00}
+#define OMAP4_ABE_DPLL_PARAM_38M4 {0x40, 0x18, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00}
+
+#define OMAP4_USB_DPLL_PARAM_19M2 {0x32, 0x0, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0}
+#define OMAP4_USB_DPLL_PARAM_38M4 {0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0}
+
+#define OMAP4_CORE_DPLL_PARAM_19M2_DDR200 {0x7d, 0x02, 0x02, 0x05, 0x08, 0x04, 0x06, 0x05}
+#define OMAP4_CORE_DPLL_PARAM_19M2_DDR333 {0x410, 0x09, 0x03, 0x0c, 0x14, 0x0a, 0x0f, 0x0c}
+#define OMAP4_CORE_DPLL_PARAM_19M2_DDR400 {0x7d, 0x02, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05}
+#define OMAP4_CORE_DPLL_PARAM_38M4_DDR200 {0x7d, 0x05, 0x02, 0x05, 0x08, 0x04, 0x06, 0x05}
+#define OMAP4_CORE_DPLL_PARAM_38M4_DDR400 {0x7d, 0x05, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05}
+
+void omap4_configure_mpu_dpll(const struct dpll_param *dpll_param);
+void omap4_configure_iva_dpll(const struct dpll_param *dpll_param);
+void omap4_configure_per_dpll(const struct dpll_param *dpll_param);
+void omap4_configure_abe_dpll(const struct dpll_param *dpll_param);
+void omap4_configure_usb_dpll(const struct dpll_param *dpll_param);
+void omap4_configure_core_dpll_no_lock(const struct dpll_param *param);
+void omap4_lock_core_dpll(void);
+void omap4_lock_core_dpll_shadow(const struct dpll_param *param);
+void omap4_enable_all_clocks(void);
+
diff --git a/arch/arm/mach-omap/include/mach/omap4-mux.h b/arch/arm/mach-omap/include/mach/omap4-mux.h
new file mode 100644
index 0000000..019574b
--- /dev/null
+++ b/arch/arm/mach-omap/include/mach/omap4-mux.h
@@ -0,0 +1,344 @@
+/*
+ * (C) Copyright 2004-2009
+ * Texas Instruments Incorporated
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Aneesh V <aneesh@ti.com>
+ * Balaji Krishnamoorthy <balajitk@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _MUX_OMAP4_H_
+#define _MUX_OMAP4_H_
+
+#include <asm/types.h>
+
+struct pad_conf_entry {
+
+ u16 offset;
+
+ u16 val;
+
+} __attribute__ ((packed));
+
+#ifdef CONFIG_OFF_PADCONF
+#define OFF_PD (1 << 12)
+#define OFF_PU (3 << 12)
+#define OFF_OUT_PTD (0 << 10)
+#define OFF_OUT_PTU (2 << 10)
+#define OFF_IN (1 << 10)
+#define OFF_OUT (0 << 10)
+#define OFF_EN (1 << 9)
+#else
+#define OFF_PD (0 << 12)
+#define OFF_PU (0 << 12)
+#define OFF_OUT_PTD (0 << 10)
+#define OFF_OUT_PTU (0 << 10)
+#define OFF_IN (0 << 10)
+#define OFF_OUT (0 << 10)
+#define OFF_EN (0 << 9)
+#endif
+
+#define IEN (1 << 8)
+#define IDIS (0 << 8)
+#define PTU (3 << 3)
+#define PTD (1 << 3)
+#define EN (1 << 3)
+#define DIS (0 << 3)
+
+#define M0 0
+#define M1 1
+#define M2 2
+#define M3 3
+#define M4 4
+#define M5 5
+#define M6 6
+#define M7 7
+
+#define SAFE_MODE M7
+
+#ifdef CONFIG_OFF_PADCONF
+#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN)
+#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN)
+#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN)
+#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN)
+#else
+#define OFF_IN_PD 0
+#define OFF_IN_PU 0
+#define OFF_OUT_PD 0
+#define OFF_OUT_PU 0
+#endif
+
+#define CORE_REVISION 0x0000
+#define CORE_HWINFO 0x0004
+#define CORE_SYSCONFIG 0x0010
+#define GPMC_AD0 0x0040
+#define GPMC_AD1 0x0042
+#define GPMC_AD2 0x0044
+#define GPMC_AD3 0x0046
+#define GPMC_AD4 0x0048
+#define GPMC_AD5 0x004A
+#define GPMC_AD6 0x004C
+#define GPMC_AD7 0x004E
+#define GPMC_AD8 0x0050
+#define GPMC_AD9 0x0052
+#define GPMC_AD10 0x0054
+#define GPMC_AD11 0x0056
+#define GPMC_AD12 0x0058
+#define GPMC_AD13 0x005A
+#define GPMC_AD14 0x005C
+#define GPMC_AD15 0x005E
+#define GPMC_A16 0x0060
+#define GPMC_A17 0x0062
+#define GPMC_A18 0x0064
+#define GPMC_A19 0x0066
+#define GPMC_A20 0x0068
+#define GPMC_A21 0x006A
+#define GPMC_A22 0x006C
+#define GPMC_A23 0x006E
+#define GPMC_A24 0x0070
+#define GPMC_A25 0x0072
+#define GPMC_NCS0 0x0074
+#define GPMC_NCS1 0x0076
+#define GPMC_NCS2 0x0078
+#define GPMC_NCS3 0x007A
+#define GPMC_NWP 0x007C
+#define GPMC_CLK 0x007E
+#define GPMC_NADV_ALE 0x0080
+#define GPMC_NOE 0x0082
+#define GPMC_NWE 0x0084
+#define GPMC_NBE0_CLE 0x0086
+#define GPMC_NBE1 0x0088
+#define GPMC_WAIT0 0x008A
+#define GPMC_WAIT1 0x008C
+#define C2C_DATA11 0x008E
+#define C2C_DATA12 0x0090
+#define C2C_DATA13 0x0092
+#define C2C_DATA14 0x0094
+#define C2C_DATA15 0x0096
+#define HDMI_HPD 0x0098
+#define HDMI_CEC 0x009A
+#define HDMI_DDC_SCL 0x009C
+#define HDMI_DDC_SDA 0x009E
+#define CSI21_DX0 0x00A0
+#define CSI21_DY0 0x00A2
+#define CSI21_DX1 0x00A4
+#define CSI21_DY1 0x00A6
+#define CSI21_DX2 0x00A8
+#define CSI21_DY2 0x00AA
+#define CSI21_DX3 0x00AC
+#define CSI21_DY3 0x00AE
+#define CSI21_DX4 0x00B0
+#define CSI21_DY4 0x00B2
+#define CSI22_DX0 0x00B4
+#define CSI22_DY0 0x00B6
+#define CSI22_DX1 0x00B8
+#define CSI22_DY1 0x00BA
+#define CAM_SHUTTER 0x00BC
+#define CAM_STROBE 0x00BE
+#define CAM_GLOBALRESET 0x00C0
+#define USBB1_ULPITLL_CLK 0x00C2
+#define USBB1_ULPITLL_STP 0x00C4
+#define USBB1_ULPITLL_DIR 0x00C6
+#define USBB1_ULPITLL_NXT 0x00C8
+#define USBB1_ULPITLL_DAT0 0x00CA
+#define USBB1_ULPITLL_DAT1 0x00CC
+#define USBB1_ULPITLL_DAT2 0x00CE
+#define USBB1_ULPITLL_DAT3 0x00D0
+#define USBB1_ULPITLL_DAT4 0x00D2
+#define USBB1_ULPITLL_DAT5 0x00D4
+#define USBB1_ULPITLL_DAT6 0x00D6
+#define USBB1_ULPITLL_DAT7 0x00D8
+#define USBB1_HSIC_DATA 0x00DA
+#define USBB1_HSIC_STROBE 0x00DC
+#define USBC1_ICUSB_DP 0x00DE
+#define USBC1_ICUSB_DM 0x00E0
+#define SDMMC1_CLK 0x00E2
+#define SDMMC1_CMD 0x00E4
+#define SDMMC1_DAT0 0x00E6
+#define SDMMC1_DAT1 0x00E8
+#define SDMMC1_DAT2 0x00EA
+#define SDMMC1_DAT3 0x00EC
+#define SDMMC1_DAT4 0x00EE
+#define SDMMC1_DAT5 0x00F0
+#define SDMMC1_DAT6 0x00F2
+#define SDMMC1_DAT7 0x00F4
+#define ABE_MCBSP2_CLKX 0x00F6
+#define ABE_MCBSP2_DR 0x00F8
+#define ABE_MCBSP2_DX 0x00FA
+#define ABE_MCBSP2_FSX 0x00FC
+#define ABE_MCBSP1_CLKX 0x00FE
+#define ABE_MCBSP1_DR 0x0100
+#define ABE_MCBSP1_DX 0x0102
+#define ABE_MCBSP1_FSX 0x0104
+#define ABE_PDM_UL_DATA 0x0106
+#define ABE_PDM_DL_DATA 0x0108
+#define ABE_PDM_FRAME 0x010A
+#define ABE_PDM_LB_CLK 0x010C
+#define ABE_CLKS 0x010E
+#define ABE_DMIC_CLK1 0x0110
+#define ABE_DMIC_DIN1 0x0112
+#define ABE_DMIC_DIN2 0x0114
+#define ABE_DMIC_DIN3 0x0116
+#define UART2_CTS 0x0118
+#define UART2_RTS 0x011A
+#define UART2_RX 0x011C
+#define UART2_TX 0x011E
+#define HDQ_SIO 0x0120
+#define I2C1_SCL 0x0122
+#define I2C1_SDA 0x0124
+#define I2C2_SCL 0x0126
+#define I2C2_SDA 0x0128
+#define I2C3_SCL 0x012A
+#define I2C3_SDA 0x012C
+#define I2C4_SCL 0x012E
+#define I2C4_SDA 0x0130
+#define MCSPI1_CLK 0x0132
+#define MCSPI1_SOMI 0x0134
+#define MCSPI1_SIMO 0x0136
+#define MCSPI1_CS0 0x0138
+#define MCSPI1_CS1 0x013A
+#define MCSPI1_CS2 0x013C
+#define MCSPI1_CS3 0x013E
+#define UART3_CTS_RCTX 0x0140
+#define UART3_RTS_SD 0x0142
+#define UART3_RX_IRRX 0x0144
+#define UART3_TX_IRTX 0x0146
+#define SDMMC5_CLK 0x0148
+#define SDMMC5_CMD 0x014A
+#define SDMMC5_DAT0 0x014C
+#define SDMMC5_DAT1 0x014E
+#define SDMMC5_DAT2 0x0150
+#define SDMMC5_DAT3 0x0152
+#define MCSPI4_CLK 0x0154
+#define MCSPI4_SIMO 0x0156
+#define MCSPI4_SOMI 0x0158
+#define MCSPI4_CS0 0x015A
+#define UART4_RX 0x015C
+#define UART4_TX 0x015E
+#define USBB2_ULPITLL_CLK 0x0160
+#define USBB2_ULPITLL_STP 0x0162
+#define USBB2_ULPITLL_DIR 0x0164
+#define USBB2_ULPITLL_NXT 0x0166
+#define USBB2_ULPITLL_DAT0 0x0168
+#define USBB2_ULPITLL_DAT1 0x016A
+#define USBB2_ULPITLL_DAT2 0x016C
+#define USBB2_ULPITLL_DAT3 0x016E
+#define USBB2_ULPITLL_DAT4 0x0170
+#define USBB2_ULPITLL_DAT5 0x0172
+#define USBB2_ULPITLL_DAT6 0x0174
+#define USBB2_ULPITLL_DAT7 0x0176
+#define USBB2_HSIC_DATA 0x0178
+#define USBB2_HSIC_STROBE 0x017A
+#define UNIPRO_TX0 0x017C
+#define UNIPRO_TY0 0x017E
+#define UNIPRO_TX1 0x0180
+#define UNIPRO_TY1 0x0182
+#define UNIPRO_TX2 0x0184
+#define UNIPRO_TY2 0x0186
+#define UNIPRO_RX0 0x0188
+#define UNIPRO_RY0 0x018A
+#define UNIPRO_RX1 0x018C
+#define UNIPRO_RY1 0x018E
+#define UNIPRO_RX2 0x0190
+#define UNIPRO_RY2 0x0192
+#define USBA0_OTG_CE 0x0194
+#define USBA0_OTG_DP 0x0196
+#define USBA0_OTG_DM 0x0198
+#define FREF_CLK1_OUT 0x019A
+#define FREF_CLK2_OUT 0x019C
+#define SYS_NIRQ1 0x019E
+#define SYS_NIRQ2 0x01A0
+#define SYS_BOOT0 0x01A2
+#define SYS_BOOT1 0x01A4
+#define SYS_BOOT2 0x01A6
+#define SYS_BOOT3 0x01A8
+#define SYS_BOOT4 0x01AA
+#define SYS_BOOT5 0x01AC
+#define DPM_EMU0 0x01AE
+#define DPM_EMU1 0x01B0
+#define DPM_EMU2 0x01B2
+#define DPM_EMU3 0x01B4
+#define DPM_EMU4 0x01B6
+#define DPM_EMU5 0x01B8
+#define DPM_EMU6 0x01BA
+#define DPM_EMU7 0x01BC
+#define DPM_EMU8 0x01BE
+#define DPM_EMU9 0x01C0
+#define DPM_EMU10 0x01C2
+#define DPM_EMU11 0x01C4
+#define DPM_EMU12 0x01C6
+#define DPM_EMU13 0x01C8
+#define DPM_EMU14 0x01CA
+#define DPM_EMU15 0x01CC
+#define DPM_EMU16 0x01CE
+#define DPM_EMU17 0x01D0
+#define DPM_EMU18 0x01D2
+#define DPM_EMU19 0x01D4
+#define WAKEUPEVENT_0 0x01D8
+#define WAKEUPEVENT_1 0x01DC
+#define WAKEUPEVENT_2 0x01E0
+#define WAKEUPEVENT_3 0x01E4
+#define WAKEUPEVENT_4 0x01E8
+#define WAKEUPEVENT_5 0x01EC
+#define WAKEUPEVENT_6 0x01F0
+
+#define WKUP_REVISION 0x0000
+#define WKUP_HWINFO 0x0004
+#define WKUP_SYSCONFIG 0x0010
+#define PAD0_SIM_IO 0x0040
+#define PAD1_SIM_CLK 0x0042
+#define PAD0_SIM_RESET 0x0044
+#define PAD1_SIM_CD 0x0046
+#define PAD0_SIM_PWRCTRL 0x0048
+#define PAD1_SR_SCL 0x004A
+#define PAD0_SR_SDA 0x004C
+#define PAD1_FREF_XTAL_IN 0x004E
+#define PAD0_FREF_SLICER_IN 0x0050
+#define PAD1_FREF_CLK_IOREQ 0x0052
+#define PAD0_FREF_CLK0_OUT 0x0054
+#define PAD1_FREF_CLK3_REQ 0x0056
+#define PAD0_FREF_CLK3_OUT 0x0058
+#define PAD1_FREF_CLK4_REQ 0x005A
+#define PAD0_FREF_CLK4_OUT 0x005C
+#define PAD1_SYS_32K 0x005E
+#define PAD0_SYS_NRESPWRON 0x0060
+#define PAD1_SYS_NRESWARM 0x0062
+#define PAD0_SYS_PWR_REQ 0x0064
+#define PAD1_SYS_PWRON_RESET 0x0066
+#define PAD0_SYS_BOOT6 0x0068
+#define PAD1_SYS_BOOT7 0x006A
+#define PAD0_JTAG_NTRST 0x006C
+#define PAD1_JTAG_TCK 0x006D
+#define PAD0_JTAG_RTCK 0x0070
+#define PAD1_JTAG_TMS_TMSC 0x0072
+#define PAD0_JTAG_TDI 0x0074
+#define PAD1_JTAG_TDO 0x0076
+#define PADCONF_WAKEUPEVENT_0 0x007C
+#define CONTROL_SMART1NOPMIO_PADCONF_0 0x05A0
+#define CONTROL_SMART1NOPMIO_PADCONF_1 0x05A4
+#define PADCONF_MODE 0x05A8
+#define CONTROL_XTAL_OSCILLATOR 0x05AC
+#define CONTROL_CONTROL_I2C_2 0x0604
+#define CONTROL_CONTROL_JTAG 0x0608
+#define CONTROL_CONTROL_SYS 0x060C
+#define CONTROL_SPARE_RW 0x0614
+#define CONTROL_SPARE_R 0x0618
+#define CONTROL_SPARE_R_C0 0x061C
+
+#endif /* _MUX_OMAP4_H_ */
diff --git a/arch/arm/mach-omap/include/mach/omap4-silicon.h b/arch/arm/mach-omap/include/mach/omap4-silicon.h
new file mode 100644
index 0000000..db0dfdf
--- /dev/null
+++ b/arch/arm/mach-omap/include/mach/omap4-silicon.h
@@ -0,0 +1,179 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Authors:
+ * Aneesh V <aneesh@ti.com>
+ *
+ * Derived from OMAP3 work by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _OMAP4_H_
+#define _OMAP4_H_
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+/*
+ * L4 Peripherals - L4 Wakeup and L4 Core now
+ */
+#define OMAP44XX_L4_CORE_BASE 0x4A000000
+#define OMAP44XX_WAKEUP_L4_IO_BASE 0x4A300000
+#define OMAP44XX_L4_WKUP_BASE 0x4A300000
+#define OMAP44XX_L4_PER_BASE 0x48000000
+
+/* EMIF and DMM registers */
+#define OMAP44XX_EMIF1_BASE 0x4c000000
+#define OMAP44XX_EMIF2_BASE 0x4d000000
+
+#define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000
+#define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000
+
+
+/* CONTROL */
+#define OMAP44XX_CTRL_BASE (OMAP44XX_L4_CORE_BASE + 0x2000)
+#define OMAP44XX_CONTROL_PADCONF_CORE (OMAP44XX_L4_CORE_BASE + 0x100000)
+#define OMAP44XX_CONTROL_PADCONF_WKUP (OMAP44XX_L4_CORE_BASE + 0x31E000)
+
+/* PRM */
+#define OMAP44XX_PRM_VC_VAL_BYPASS (OMAP44XX_WAKEUP_L4_IO_BASE + 0x7ba0)
+#define OMAP44XX_PRM_VC_CFG_I2C_MODE (OMAP44XX_WAKEUP_L4_IO_BASE + 0x7ba8)
+#define OMAP44XX_PRM_VC_CFG_I2C_CLK (OMAP44XX_WAKEUP_L4_IO_BASE + 0x7bac)
+
+/* IRQ */
+#define OMAP44XX_PRM_IRQSTATUS_MPU_A9 (OMAP44XX_WAKEUP_L4_IO_BASE + 0x6010)
+
+/* UART */
+#define OMAP44XX_UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000)
+#define OMAP44XX_UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000)
+#define OMAP44XX_UART3_BASE (OMAP44XX_L4_PER_BASE + 0x20000)
+
+/* General Purpose Timers */
+#define OMAP44XX_GPT1_BASE (OMAP44XX_L4_WKUP_BASE + 0x18000)
+#define OMAP44XX_GPT2_BASE (OMAP44XX_L4_PER_BASE + 0x32000)
+#define OMAP44XX_GPT3_BASE (OMAP44XX_L4_PER_BASE + 0x34000)
+
+/* Watchdog Timer2 - MPU watchdog */
+#define OMAP44XX_WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000)
+
+#define OMAP44XX_SCRM_BASE 0x4a30a000
+#define OMAP44XX_SCRM_ALTCLKSRC (OMAP44XX_SCRM_BASE + 0x110)
+#define OMAP44XX_SCRM_AUXCLK1 (OMAP44XX_SCRM_BASE + 0x314)
+#define OMAP44XX_SCRM_AUXCLK3 (OMAP44XX_SCRM_BASE + 0x31c)
+
+/* 32KTIMER */
+#define OMAP_32KTIMER_BASE (OMAP44XX_L4_WKUP_BASE + 0x4000)
+
+/* GPMC */
+#define OMAP_GPMC_BASE 0x50000000
+
+/* DMM */
+#define OMAP44XX_DMM_BASE 0x4E000000
+#define DMM_LISA_MAP_BASE (OMAP44XX_DMM_BASE + 0x40)
+#define DMM_LISA_MAP_SYS_SIZE_MASK (7 << 20)
+#define DMM_LISA_MAP_SYS_SIZE_SHIFT 20
+#define DMM_LISA_MAP_SYS_ADDR_MASK (0xFF << 24)
+/*
+ * Hardware Register Details
+ */
+
+/* Watchdog Timer */
+#define WD_UNLOCK1 0xAAAA
+#define WD_UNLOCK2 0x5555
+
+/* GP Timer */
+#define TCLR_ST (0x1 << 0)
+#define TCLR_AR (0x1 << 1)
+#define TCLR_PRE (0x1 << 5)
+
+/*
+ * PRCM
+ */
+
+/* PRM */
+#define PRM_BASE 0x4A306000
+#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00)
+
+#define PRM_RSTCTRL PRM_DEVICE_BASE
+#define PRM_RSTCTRL_RESET 0x01
+
+#ifndef __ASSEMBLY__
+
+struct s32ktimer {
+ unsigned char res[0x10];
+ unsigned int s32k_cr; /* 0x10 */
+};
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Non-secure SRAM Addresses
+ * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
+ * at 0x40304000(EMU base) so that our code works for both EMU and GP
+ */
+#define NON_SECURE_SRAM_START 0x40304000
+#define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */
+/* base address for indirect vectors (internal boot mode) */
+#define SRAM_ROM_VECT_BASE 0x4030D000
+/* Temporary SRAM stack used while low level init is done */
+#define LOW_LEVEL_SRAM_STACK NON_SECURE_SRAM_END
+
+/*
+ * OMAP4 real hardware:
+ * TODO: Change this to the IDCODE in the hw regsiter
+ */
+#define CPU_OMAP4430_ES10 1
+#define CPU_OMAP4430_ES20 2
+
+#define CM_DLL_CTRL 0x4a004110
+#define CM_MEMIF_EMIF_1_CLKCTRL 0x4a008b30
+#define CM_MEMIF_EMIF_2_CLKCTRL 0x4a008b38
+
+/* Silicon revisions */
+#define OMAP4430_SILICON_ID_INVALID 0
+#define OMAP4430_ES1_0 1
+#define OMAP4430_ES2_0 2
+#define OMAP4430_ES2_1 3
+#define OMAP4430_ES2_2 4
+
+struct ddr_regs {
+ u32 tim1;
+ u32 tim2;
+ u32 tim3;
+ u32 phy_ctrl_1;
+ u32 ref_ctrl;
+ u32 config_init;
+ u32 config_final;
+ u32 zq_config;
+ u8 mr1;
+ u8 mr2;
+};
+
+struct dpll_param;
+
+void omap4_ddr_init(const struct ddr_regs *, const struct dpll_param *);
+void omap4_power_i2c_send(u32);
+unsigned int omap4_revision(void);
+
+#endif
diff --git a/arch/arm/mach-omap/include/mach/silicon.h b/arch/arm/mach-omap/include/mach/silicon.h
index 22daa5c..c2f0c41 100644
--- a/arch/arm/mach-omap/include/mach/silicon.h
+++ b/arch/arm/mach-omap/include/mach/silicon.h
@@ -25,6 +25,9 @@
#ifdef CONFIG_ARCH_OMAP3
#include <mach/omap3-silicon.h>
#endif
+#ifdef CONFIG_ARCH_OMAP4
+#include <mach/omap4-silicon.h>
+#endif
/* If Architecture specific init functions are present */
#ifdef CONFIG_ARCH_HAS_LOWLEVEL_INIT
diff --git a/arch/arm/mach-omap/omap4_clock.c b/arch/arm/mach-omap/omap4_clock.c
new file mode 100644
index 0000000..23a77d0
--- /dev/null
+++ b/arch/arm/mach-omap/omap4_clock.c
@@ -0,0 +1,380 @@
+#include <common.h>
+#include <mach/syslib.h>
+#include <asm/io.h>
+#include <mach/omap4-clock.h>
+
+#define LDELAY 12000000
+
+void omap4_configure_mpu_dpll(const struct dpll_param *dpll_param)
+{
+ /* Unlock the MPU dpll */
+ sr32(CM_CLKMODE_DPLL_MPU, 0, 3, PLL_MN_POWER_BYPASS);
+ wait_on_value((1 << 0), 0, CM_IDLEST_DPLL_MPU, LDELAY);
+
+ sr32(CM_AUTOIDLE_DPLL_MPU, 0, 3, 0x0); /* Disable DPLL autoidle */
+
+ /* Set M,N,M2 values */
+ sr32(CM_CLKSEL_DPLL_MPU, 8, 11, dpll_param->m);
+ sr32(CM_CLKSEL_DPLL_MPU, 0, 6, dpll_param->n);
+ sr32(CM_DIV_M2_DPLL_MPU, 0, 5, dpll_param->m2);
+ sr32(CM_DIV_M2_DPLL_MPU, 8, 1, 0x1);
+
+ /* Lock the mpu dpll */
+ sr32(CM_CLKMODE_DPLL_MPU, 0, 3, PLL_LOCK | 0x10);
+ wait_on_value((1 << 0), 1, CM_IDLEST_DPLL_MPU, LDELAY);
+}
+
+void omap4_configure_iva_dpll(const struct dpll_param *dpll_param)
+{
+ /* Unlock the IVA dpll */
+ sr32(CM_CLKMODE_DPLL_IVA, 0, 3, PLL_MN_POWER_BYPASS);
+ wait_on_value((1 << 0), 0, CM_IDLEST_DPLL_IVA, LDELAY);
+
+ /* CM_BYPCLK_DPLL_IVA = CORE_X2_CLK/2 */
+ sr32(CM_BYPCLK_DPLL_IVA, 0, 2, 0x1);
+
+ sr32(CM_AUTOIDLE_DPLL_IVA, 0, 3, 0x0); /* Disable DPLL autoidle */
+
+ /* Set M,N,M4,M5 */
+ sr32(CM_CLKSEL_DPLL_IVA, 8, 11, dpll_param->m);
+ sr32(CM_CLKSEL_DPLL_IVA, 0, 7, dpll_param->n);
+ sr32(CM_DIV_M4_DPLL_IVA, 0, 5, dpll_param->m4);
+ sr32(CM_DIV_M4_DPLL_IVA, 8, 1, 0x1);
+ sr32(CM_DIV_M5_DPLL_IVA, 0, 5, dpll_param->m5);
+ sr32(CM_DIV_M5_DPLL_IVA, 8, 1, 0x1);
+
+ /* Lock the iva dpll */
+ sr32(CM_CLKMODE_DPLL_IVA, 0, 3, PLL_LOCK);
+ wait_on_value((1 << 0), 1, CM_IDLEST_DPLL_IVA, LDELAY);
+}
+
+void omap4_configure_per_dpll(const struct dpll_param *dpll_param)
+{
+ /* Unlock the PER dpll */
+ sr32(CM_CLKMODE_DPLL_PER, 0, 3, PLL_MN_POWER_BYPASS);
+ wait_on_value((1 << 0), 0, CM_IDLEST_DPLL_PER, LDELAY);
+
+ /* Disable autoidle */
+ sr32(CM_AUTOIDLE_DPLL_PER, 0, 3, 0x0);
+
+ sr32(CM_CLKSEL_DPLL_PER, 8, 11, dpll_param->m);
+ sr32(CM_CLKSEL_DPLL_PER, 0, 6, dpll_param->n);
+ sr32(CM_DIV_M2_DPLL_PER, 0, 5, dpll_param->m2);
+ sr32(CM_DIV_M3_DPLL_PER, 0, 5, dpll_param->m3);
+ sr32(CM_DIV_M4_DPLL_PER, 0, 5, dpll_param->m4);
+ sr32(CM_DIV_M5_DPLL_PER, 0, 5, dpll_param->m5);
+ sr32(CM_DIV_M6_DPLL_PER, 0, 5, dpll_param->m6);
+ sr32(CM_DIV_M7_DPLL_PER, 0, 5, dpll_param->m7);
+
+ sr32(CM_DIV_M2_DPLL_PER, 8, 1, 0x1);
+ sr32(CM_DIV_M3_DPLL_PER, 8, 1, 0x1);
+ sr32(CM_DIV_M4_DPLL_PER, 8, 1, 0x1);
+ sr32(CM_DIV_M5_DPLL_PER, 8, 1, 0x1);
+ sr32(CM_DIV_M6_DPLL_PER, 8, 1, 0x1);
+ sr32(CM_DIV_M7_DPLL_PER, 8, 1, 0x1);
+
+ /* Lock the per dpll */
+ sr32(CM_CLKMODE_DPLL_PER, 0, 3, PLL_LOCK);
+ wait_on_value((1 << 0), 1, CM_IDLEST_DPLL_PER, LDELAY);
+
+ return;
+}
+
+void omap4_configure_abe_dpll(const struct dpll_param *dpll_param)
+{
+ /* Select sys_clk as ref clk for ABE dpll */
+ sr32(CM_ABE_PLL_REF_CLKSEL, 0, 32, 0x0);
+
+ /* Unlock the ABE dpll */
+ sr32(CM_CLKMODE_DPLL_ABE, 0, 3, PLL_MN_POWER_BYPASS);
+ wait_on_value((1 << 0), 0, CM_IDLEST_DPLL_ABE, LDELAY);
+
+ /* Disable autoidle */
+ sr32(CM_AUTOIDLE_DPLL_ABE, 0, 3, 0x0);
+
+ sr32(CM_CLKSEL_DPLL_ABE, 8, 11, dpll_param->m);
+ sr32(CM_CLKSEL_DPLL_ABE, 0, 6, dpll_param->n);
+
+ /* Force DPLL CLKOUTHIF to stay enabled */
+ sr32(CM_DIV_M2_DPLL_ABE, 0, 32, 0x500);
+ sr32(CM_DIV_M2_DPLL_ABE, 0, 5, dpll_param->m2);
+ sr32(CM_DIV_M2_DPLL_ABE, 8, 1, 0x1);
+ /* Force DPLL CLKOUTHIF to stay enabled */
+ sr32(CM_DIV_M3_DPLL_ABE, 0, 32, 0x100);
+ sr32(CM_DIV_M3_DPLL_ABE, 0, 5, dpll_param->m3);
+ sr32(CM_DIV_M3_DPLL_ABE, 8, 1, 0x1);
+
+ /* Lock the abe dpll */
+ sr32(CM_CLKMODE_DPLL_ABE, 0, 3, PLL_LOCK);
+ wait_on_value((1 << 0), 1, CM_IDLEST_DPLL_ABE, LDELAY);
+
+ return;
+}
+
+void omap4_configure_usb_dpll(const struct dpll_param *dpll_param)
+{
+ /* Select the 60Mhz clock 480/8 = 60*/
+ sr32(CM_CLKSEL_USB_60MHz, 0, 32, 0x1);
+
+ /* Unlock the USB dpll */
+ sr32(CM_CLKMODE_DPLL_USB, 0, 3, PLL_MN_POWER_BYPASS);
+ wait_on_value((1 << 0), 0, CM_IDLEST_DPLL_USB, LDELAY);
+
+ /* Disable autoidle */
+ sr32(CM_AUTOIDLE_DPLL_USB, 0, 3, 0x0);
+
+ sr32(CM_CLKSEL_DPLL_USB, 8, 11, dpll_param->m);
+ sr32(CM_CLKSEL_DPLL_USB, 0, 6, dpll_param->n);
+
+ /* Force DPLL CLKOUT to stay active */
+ sr32(CM_DIV_M2_DPLL_USB, 0, 32, 0x100);
+ sr32(CM_DIV_M2_DPLL_USB, 0, 5, dpll_param->m2);
+ sr32(CM_DIV_M2_DPLL_USB, 8, 1, 0x1);
+ sr32(CM_CLKDCOLDO_DPLL_USB, 8, 1, 0x1);
+
+ /* Lock the usb dpll */
+ sr32(CM_CLKMODE_DPLL_USB, 0, 3, PLL_LOCK);
+ wait_on_value((1 << 0), 1, CM_IDLEST_DPLL_USB, LDELAY);
+
+ /* force enable the CLKDCOLDO clock */
+ sr32(CM_CLKDCOLDO_DPLL_USB, 0, 32, 0x100);
+
+ return;
+}
+
+void omap4_configure_core_dpll_no_lock(const struct dpll_param *param)
+{
+ /* CORE_CLK=CORE_X2_CLK/2, L3_CLK=CORE_CLK/2, L4_CLK=L3_CLK/2 */
+ sr32(CM_CLKSEL_CORE, 0, 32, 0x110);
+
+ /* Unlock the CORE dpll */
+ sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_MN_POWER_BYPASS);
+ wait_on_value((1 << 0), 0, CM_IDLEST_DPLL_CORE, LDELAY);
+
+ /* Disable autoidle */
+ sr32(CM_AUTOIDLE_DPLL_CORE, 0, 3, 0x0);
+
+ sr32(CM_CLKSEL_DPLL_CORE, 8, 11, param->m);
+ sr32(CM_CLKSEL_DPLL_CORE, 0, 6, param->n);
+ sr32(CM_DIV_M2_DPLL_CORE, 0, 5, param->m2);
+ sr32(CM_DIV_M3_DPLL_CORE, 0, 5, param->m3);
+ sr32(CM_DIV_M4_DPLL_CORE, 0, 5, param->m4);
+ sr32(CM_DIV_M5_DPLL_CORE, 0, 5, param->m5);
+ sr32(CM_DIV_M6_DPLL_CORE, 0, 5, param->m6);
+ sr32(CM_DIV_M7_DPLL_CORE, 0, 5, param->m7);
+
+ sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1);
+ sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1);
+ sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1);
+ sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1);
+ sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x0);
+ sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1);
+}
+
+void omap4_lock_core_dpll(void)
+{
+ /* Lock the core dpll */
+ sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_LOCK);
+ wait_on_value((1 << 0), 1, CM_IDLEST_DPLL_CORE, LDELAY);
+
+ return;
+}
+
+void omap4_lock_core_dpll_shadow(const struct dpll_param *param)
+{
+ /* Lock the core dpll using freq update method */
+ *(volatile int*)0x4A004120 = 10; //(CM_CLKMODE_DPLL_CORE)
+
+ /* CM_SHADOW_FREQ_CONFIG1: DLL_OVERRIDE = 1(hack), DLL_RESET = 1,
+ * DPLL_CORE_M2_DIV =1, DPLL_CORE_DPLL_EN = 0x7, FREQ_UPDATE = 1
+ */
+ *(volatile int*)0x4A004260 = 0x70D | (param->m2 << 11);
+
+ /* Wait for Freq_Update to get cleared: CM_SHADOW_FREQ_CONFIG1 */
+ while( ( (*(volatile int*)0x4A004260) & 0x1) == 0x1 );
+
+ /* Wait for DPLL to Lock : CM_IDLEST_DPLL_CORE */
+ wait_on_value((1 << 0), 1, CM_IDLEST_DPLL_CORE, LDELAY);
+}
+
+void omap4_enable_all_clocks(void)
+{
+ /* Enable Ducati clocks */
+ sr32(CM_DUCATI_DUCATI_CLKCTRL, 0, 32, 0x1);
+ sr32(CM_DUCATI_CLKSTCTRL, 0, 32, 0x2);
+
+ wait_on_value((1 << 8), (1 << 8), CM_DUCATI_CLKSTCTRL, LDELAY);
+
+ /* Enable ivahd and sl2 clocks */
+ sr32(IVAHD_IVAHD_CLKCTRL, 0, 32, 0x1);
+ sr32(IVAHD_SL2_CLKCTRL, 0, 32, 0x1);
+ sr32(IVAHD_CLKSTCTRL, 0, 32, 0x2);
+
+ wait_on_value((1 << 8), (1 << 8), IVAHD_CLKSTCTRL, LDELAY);
+
+ /* Enable Tesla clocks */
+ sr32(DSP_DSP_CLKCTRL, 0, 32, 0x1);
+ sr32(DSP_CLKSTCTRL, 0, 32, 0x2);
+
+ wait_on_value((1 << 8), (1 << 8), DSP_CLKSTCTRL, LDELAY);
+
+ /* wait for tesla to become accessible */
+
+ /* ABE clocks */
+ sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x3);
+ sr32(CM1_ABE_AESS_CLKCTRL, 0, 32, 0x2);
+ sr32(CM1_ABE_PDM_CLKCTRL, 0, 32, 0x2);
+ sr32(CM1_ABE_DMIC_CLKCTRL, 0, 32, 0x2);
+ sr32(CM1_ABE_MCASP_CLKCTRL, 0, 32, 0x2);
+ sr32(CM1_ABE_MCBSP1_CLKCTRL, 0, 32, 0x08000002);
+ sr32(CM1_ABE_MCBSP2_CLKCTRL, 0, 32, 0x08000002);
+ sr32(CM1_ABE_MCBSP3_CLKCTRL, 0, 32, 0x08000002);
+ sr32(CM1_ABE_SLIMBUS_CLKCTRL, 0, 32, 0xf02);
+ sr32(CM1_ABE_TIMER5_CLKCTRL, 0, 32, 0x2);
+ sr32(CM1_ABE_TIMER6_CLKCTRL, 0, 32, 0x2);
+ sr32(CM1_ABE_TIMER7_CLKCTRL, 0, 32, 0x2);
+ sr32(CM1_ABE_TIMER8_CLKCTRL, 0, 32, 0x2);
+ sr32(CM1_ABE_WDT3_CLKCTRL, 0, 32, 0x2);
+ /* Disable sleep transitions */
+ sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x0);
+
+ /* L4PER clocks */
+ sr32(CM_L4PER_CLKSTCTRL, 0, 32, 0x2);
+ sr32(CM_L4PER_DMTIMER10_CLKCTRL, 0, 32, 0x2);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_DMTIMER10_CLKCTRL, LDELAY);
+ sr32(CM_L4PER_DMTIMER11_CLKCTRL, 0, 32, 0x2);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_DMTIMER11_CLKCTRL, LDELAY);
+ sr32(CM_L4PER_DMTIMER2_CLKCTRL, 0, 32, 0x2);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_DMTIMER2_CLKCTRL, LDELAY);
+ sr32(CM_L4PER_DMTIMER3_CLKCTRL, 0, 32, 0x2);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_DMTIMER3_CLKCTRL, LDELAY);
+ sr32(CM_L4PER_DMTIMER4_CLKCTRL, 0, 32, 0x2);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_DMTIMER4_CLKCTRL, LDELAY);
+ sr32(CM_L4PER_DMTIMER9_CLKCTRL, 0, 32, 0x2);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_DMTIMER9_CLKCTRL, LDELAY);
+
+ /* GPIO clocks */
+ sr32(CM_L4PER_GPIO2_CLKCTRL, 0, 32, 0x1);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO2_CLKCTRL, LDELAY);
+ sr32(CM_L4PER_GPIO3_CLKCTRL, 0, 32, 0x1);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO3_CLKCTRL, LDELAY);
+ sr32(CM_L4PER_GPIO4_CLKCTRL, 0, 32, 0x1);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO4_CLKCTRL, LDELAY);
+ sr32(CM_L4PER_GPIO5_CLKCTRL, 0, 32, 0x1);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO5_CLKCTRL, LDELAY);
+ sr32(CM_L4PER_GPIO6_CLKCTRL, 0, 32, 0x1);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO6_CLKCTRL, LDELAY);
+
+ sr32(CM_L4PER_HDQ1W_CLKCTRL, 0, 32, 0x2);
+
+ /* I2C clocks */
+ sr32(CM_L4PER_I2C1_CLKCTRL, 0, 32, 0x2);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_I2C1_CLKCTRL, LDELAY);
+ sr32(CM_L4PER_I2C2_CLKCTRL, 0, 32, 0x2);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_I2C2_CLKCTRL, LDELAY);
+ sr32(CM_L4PER_I2C3_CLKCTRL, 0, 32, 0x2);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_I2C3_CLKCTRL, LDELAY);
+ sr32(CM_L4PER_I2C4_CLKCTRL, 0, 32, 0x2);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_I2C4_CLKCTRL, LDELAY);
+
+ sr32(CM_L4PER_MCBSP4_CLKCTRL, 0, 32, 0x2);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_MCBSP4_CLKCTRL, LDELAY);
+
+ /* MCSPI clocks */
+ sr32(CM_L4PER_MCSPI1_CLKCTRL, 0, 32, 0x2);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_MCSPI1_CLKCTRL, LDELAY);
+ sr32(CM_L4PER_MCSPI2_CLKCTRL, 0, 32, 0x2);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_MCSPI2_CLKCTRL, LDELAY);
+ sr32(CM_L4PER_MCSPI3_CLKCTRL, 0, 32, 0x2);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_MCSPI3_CLKCTRL, LDELAY);
+ sr32(CM_L4PER_MCSPI4_CLKCTRL, 0, 32, 0x2);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_MCSPI4_CLKCTRL, LDELAY);
+
+ /* MMC clocks */
+ sr32(CM_L3INIT_HSMMC1_CLKCTRL, 0, 2, 0x2);
+ sr32(CM_L3INIT_HSMMC1_CLKCTRL, 24, 1, 0x1);
+ sr32(CM_L3INIT_HSMMC2_CLKCTRL, 0, 2, 0x2);
+ sr32(CM_L3INIT_HSMMC2_CLKCTRL, 24, 1, 0x1);
+ sr32(CM_L4PER_MMCSD3_CLKCTRL, 0, 32, 0x2);
+ wait_on_value((1 << 18)|(1 << 17)|(1 << 16), 0, CM_L4PER_MMCSD3_CLKCTRL, LDELAY);
+ sr32(CM_L4PER_MMCSD4_CLKCTRL, 0, 32, 0x2);
+ wait_on_value((1 << 18)|(1 << 17)|(1 << 16), 0, CM_L4PER_MMCSD4_CLKCTRL, LDELAY);
+ sr32(CM_L4PER_MMCSD5_CLKCTRL, 0, 32, 0x2);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_MMCSD5_CLKCTRL, LDELAY);
+
+ /* UART clocks */
+ sr32(CM_L4PER_UART1_CLKCTRL, 0, 32, 0x2);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_UART1_CLKCTRL, LDELAY);
+ sr32(CM_L4PER_UART2_CLKCTRL, 0, 32, 0x2);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_UART2_CLKCTRL, LDELAY);
+ sr32(CM_L4PER_UART3_CLKCTRL, 0, 32, 0x2);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_UART3_CLKCTRL, LDELAY);
+ sr32(CM_L4PER_UART4_CLKCTRL, 0, 32, 0x2);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_UART4_CLKCTRL, LDELAY);
+
+ /* WKUP clocks */
+ sr32(CM_WKUP_GPIO1_CLKCTRL, 0, 32, 0x1);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_WKUP_GPIO1_CLKCTRL, LDELAY);
+ sr32(CM_WKUP_TIMER1_CLKCTRL, 0, 32, 0x01000002);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_WKUP_TIMER1_CLKCTRL, LDELAY);
+
+ sr32(CM_WKUP_KEYBOARD_CLKCTRL, 0, 32, 0x2);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_WKUP_KEYBOARD_CLKCTRL, LDELAY);
+
+ sr32(CM_SDMA_CLKSTCTRL, 0, 32, 0x0);
+ sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x3);
+ sr32(CM_MEMIF_EMIF_1_CLKCTRL, 0, 32, 0x1);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_MEMIF_EMIF_1_CLKCTRL, LDELAY);
+ sr32(CM_MEMIF_EMIF_2_CLKCTRL, 0, 32, 0x1);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_MEMIF_EMIF_2_CLKCTRL, LDELAY);
+ sr32(CM_D2D_CLKSTCTRL, 0, 32, 0x3);
+ sr32(CM_L3_2_GPMC_CLKCTRL, 0, 32, 0x1);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_L3_2_GPMC_CLKCTRL, LDELAY);
+ sr32(CM_L3INSTR_L3_3_CLKCTRL, 0, 32, 0x1);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_L3INSTR_L3_3_CLKCTRL, LDELAY);
+ sr32(CM_L3INSTR_L3_INSTR_CLKCTRL, 0, 32, 0x1);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_L3INSTR_L3_INSTR_CLKCTRL, LDELAY);
+ sr32(CM_L3INSTR_OCP_WP1_CLKCTRL, 0, 32, 0x1);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_L3INSTR_OCP_WP1_CLKCTRL, LDELAY);
+
+ /* WDT clocks */
+ sr32(CM_WKUP_WDT2_CLKCTRL, 0, 32, 0x2);
+ wait_on_value((1 << 17)|(1 << 16), 0, CM_WKUP_WDT2_CLKCTRL, LDELAY);
+
+ /* Enable Camera clocks */
+ sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x3);
+ sr32(CM_CAM_ISS_CLKCTRL, 0, 32, 0x102);
+ sr32(CM_CAM_FDIF_CLKCTRL, 0, 32, 0x2);
+ sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x0);
+
+ /* Enable DSS clocks */
+ /* PM_DSS_PWRSTCTRL ON State and LogicState = 1 (Retention) */
+ __raw_writel(7, 0x4A307100); /* DSS_PRM */
+
+ sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x2);
+ sr32(CM_DSS_DSS_CLKCTRL, 0, 32, 0xf02);
+ sr32(CM_DSS_DEISS_CLKCTRL, 0, 32, 0x2);
+
+ /* Check for DSS Clocks */
+ while ((__raw_readl(0x4A009100) & 0xF00) != 0xE00)
+ ;
+ /* Set HW_AUTO transition mode */
+ sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x3);
+
+ /* Enable SGX clocks */
+ sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x2);
+ sr32(CM_SGX_SGX_CLKCTRL, 0, 32, 0x2);
+ /* Check for SGX FCLK and ICLK */
+ while (__raw_readl(0x4A009200) != 0x302)
+ ;
+ /* Enable hsi/unipro/usb clocks */
+ sr32(CM_L3INIT_HSI_CLKCTRL, 0, 32, 0x1);
+ sr32(CM_L3INIT_UNIPRO1_CLKCTRL, 0, 32, 0x2);
+ sr32(CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, 0x2);
+ sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1);
+ sr32(CM_L3INIT_HSUSBTLL_CLKCTRL, 0, 32, 0x1);
+ sr32(CM_L3INIT_FSUSB_CLKCTRL, 0, 32, 0x2);
+ /* enable the 32K, 48M optional clocks and enable the module */
+ sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301);
+}
+
diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c
new file mode 100644
index 0000000..45e6c86
--- /dev/null
+++ b/arch/arm/mach-omap/omap4_generic.c
@@ -0,0 +1,406 @@
+#include <common.h>
+#include <init.h>
+#include <mach/silicon.h>
+#include <asm/io.h>
+#include <mach/omap4-silicon.h>
+#include <mach/omap4-clock.h>
+#include <mach/syslib.h>
+
+void __noreturn reset_cpu(unsigned long addr)
+{
+ writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL);
+
+ while (1);
+}
+
+#define WATCHDOG_WSPR 0x48
+#define WATCHDOG_WWPS 0x34
+
+static void wait_for_command_complete(void)
+{
+ int pending = 1;
+
+ do {
+ pending = readl(OMAP44XX_WDT2_BASE + WATCHDOG_WWPS);
+ } while (pending);
+}
+
+/* EMIF */
+#define EMIF_MOD_ID_REV 0x0000
+#define EMIF_STATUS 0x0004
+#define EMIF_SDRAM_CONFIG 0x0008
+#define EMIF_LPDDR2_NVM_CONFIG 0x000C
+#define EMIF_SDRAM_REF_CTRL 0x0010
+#define EMIF_SDRAM_REF_CTRL_SHDW 0x0014
+#define EMIF_SDRAM_TIM_1 0x0018
+#define EMIF_SDRAM_TIM_1_SHDW 0x001C
+#define EMIF_SDRAM_TIM_2 0x0020
+#define EMIF_SDRAM_TIM_2_SHDW 0x0024
+#define EMIF_SDRAM_TIM_3 0x0028
+#define EMIF_SDRAM_TIM_3_SHDW 0x002C
+#define EMIF_LPDDR2_NVM_TIM 0x0030
+#define EMIF_LPDDR2_NVM_TIM_SHDW 0x0034
+#define EMIF_PWR_MGMT_CTRL 0x0038
+#define EMIF_PWR_MGMT_CTRL_SHDW 0x003C
+#define EMIF_LPDDR2_MODE_REG_DATA 0x0040
+#define EMIF_LPDDR2_MODE_REG_CFG 0x0050
+#define EMIF_L3_CONFIG 0x0054
+#define EMIF_L3_CFG_VAL_1 0x0058
+#define EMIF_L3_CFG_VAL_2 0x005C
+#define IODFT_TLGC 0x0060
+#define EMIF_PERF_CNT_1 0x0080
+#define EMIF_PERF_CNT_2 0x0084
+#define EMIF_PERF_CNT_CFG 0x0088
+#define EMIF_PERF_CNT_SEL 0x008C
+#define EMIF_PERF_CNT_TIM 0x0090
+#define EMIF_READ_IDLE_CTRL 0x0098
+#define EMIF_READ_IDLE_CTRL_SHDW 0x009c
+#define EMIF_ZQ_CONFIG 0x00C8
+#define EMIF_DDR_PHY_CTRL_1 0x00E4
+#define EMIF_DDR_PHY_CTRL_1_SHDW 0x00E8
+#define EMIF_DDR_PHY_CTRL_2 0x00EC
+
+#define DMM_LISA_MAP_0 0x0040
+#define DMM_LISA_MAP_1 0x0044
+#define DMM_LISA_MAP_2 0x0048
+#define DMM_LISA_MAP_3 0x004C
+
+#define MR0_ADDR 0
+#define MR1_ADDR 1
+#define MR2_ADDR 2
+#define MR4_ADDR 4
+#define MR10_ADDR 10
+#define MR16_ADDR 16
+#define REF_EN 0x40000000
+/* defines for MR1 */
+#define MR1_BL4 2
+#define MR1_BL8 3
+#define MR1_BL16 4
+
+#define MR1_BT_SEQ 0
+#define BT_INT 1
+
+#define MR1_WC 0
+#define MR1_NWC 1
+
+#define MR1_NWR3 1
+#define MR1_NWR4 2
+#define MR1_NWR5 3
+#define MR1_NWR6 4
+#define MR1_NWR7 5
+#define MR1_NWR8 6
+
+#define MR1_VALUE (MR1_NWR3 << 5) | (MR1_WC << 4) | (MR1_BT_SEQ << 3) \
+ | (MR1_BL8 << 0)
+
+/* defines for MR2 */
+#define MR2_RL3_WL1 1
+#define MR2_RL4_WL2 2
+#define MR2_RL5_WL2 3
+#define MR2_RL6_WL3 4
+
+/* defines for MR10 */
+#define MR10_ZQINIT 0xFF
+#define MR10_ZQRESET 0xC3
+#define MR10_ZQCL 0xAB
+#define MR10_ZQCS 0x56
+
+
+/* TODO: FREQ update method is not working so shadow registers programming
+ * is just for same of completeness. This would be safer if auto
+ * trasnitions are working
+ */
+#define FREQ_UPDATE_EMIF
+/* EMIF Needs to be configured@19.2 MHz and shadow registers
+ * should be programmed for new OPP.
+ */
+/* Elpida 2x2Gbit */
+#define SDRAM_CONFIG_INIT 0x80800EB1
+#define DDR_PHY_CTRL_1_INIT 0x849FFFF5
+#define READ_IDLE_CTRL 0x000501FF
+#define PWR_MGMT_CTRL 0x4000000f
+#define PWR_MGMT_CTRL_OPP100 0x4000000f
+#define ZQ_CONFIG 0x500b3215
+
+#define CS1_MR(mr) ((mr) | 0x80000000)
+
+static inline void delay(unsigned long loops)
+{
+ __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+ "bne 1b" : "=r" (loops) : "0"(loops));
+}
+
+int omap4_emif_config(unsigned int base, const struct ddr_regs *ddr_regs)
+{
+ /*
+ * set SDRAM CONFIG register
+ * EMIF_SDRAM_CONFIG[31:29] REG_SDRAM_TYPE = 4 for LPDDR2-S4
+ * EMIF_SDRAM_CONFIG[28:27] REG_IBANK_POS = 0
+ * EMIF_SDRAM_CONFIG[13:10] REG_CL = 3
+ * EMIF_SDRAM_CONFIG[6:4] REG_IBANK = 3 - 8 banks
+ * EMIF_SDRAM_CONFIG[3] REG_EBANK = 0 - CS0
+ * EMIF_SDRAM_CONFIG[2:0] REG_PAGESIZE = 2 - 512- 9 column
+ * JDEC specs - S4-2Gb --8 banks -- R0-R13, C0-c8
+ */
+ writel(readl(base + EMIF_LPDDR2_NVM_CONFIG) & 0xbfffffff,
+ base + EMIF_LPDDR2_NVM_CONFIG);
+ writel(ddr_regs->config_init, base + EMIF_SDRAM_CONFIG);
+
+ /* PHY control values */
+ writel(DDR_PHY_CTRL_1_INIT, base + EMIF_DDR_PHY_CTRL_1);
+ writel(ddr_regs->phy_ctrl_1, base + EMIF_DDR_PHY_CTRL_1_SHDW);
+
+ /*
+ * EMIF_READ_IDLE_CTRL
+ */
+ writel(READ_IDLE_CTRL, base + EMIF_READ_IDLE_CTRL);
+ writel(READ_IDLE_CTRL, base + EMIF_READ_IDLE_CTRL);
+
+ /*
+ * EMIF_SDRAM_TIM_1
+ */
+ writel(ddr_regs->tim1, base + EMIF_SDRAM_TIM_1);
+ writel(ddr_regs->tim1, base + EMIF_SDRAM_TIM_1_SHDW);
+
+ /*
+ * EMIF_SDRAM_TIM_2
+ */
+ writel(ddr_regs->tim2, base + EMIF_SDRAM_TIM_2);
+ writel(ddr_regs->tim2, base + EMIF_SDRAM_TIM_2_SHDW);
+
+ /*
+ * EMIF_SDRAM_TIM_3
+ */
+ writel(ddr_regs->tim3, base + EMIF_SDRAM_TIM_3);
+ writel(ddr_regs->tim3, base + EMIF_SDRAM_TIM_3_SHDW);
+
+ writel(ddr_regs->zq_config, base + EMIF_ZQ_CONFIG);
+
+ /*
+ * poll MR0 register (DAI bit)
+ * REG_CS[31] = 0 -- Mode register command to CS0
+ * REG_REFRESH_EN[30] = 1 -- Refresh enable after MRW
+ * REG_ADDRESS[7:0] = 00 -- Refresh enable after MRW
+ */
+
+ writel(MR0_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG);
+
+ while (readl(base + EMIF_LPDDR2_MODE_REG_DATA) & 1)
+ ;
+
+ writel(CS1_MR(MR0_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG);
+
+ while (readl(base + EMIF_LPDDR2_MODE_REG_DATA) & 1)
+ ;
+
+
+ /* set MR10 register */
+ writel(MR10_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG);
+ writel(MR10_ZQINIT, base + EMIF_LPDDR2_MODE_REG_DATA);
+ writel(CS1_MR(MR10_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG);
+ writel(MR10_ZQINIT, base + EMIF_LPDDR2_MODE_REG_DATA);
+
+ /* wait for tZQINIT=1us */
+ delay(10);
+
+ /* set MR1 register */
+ writel(MR1_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG);
+ writel(ddr_regs->mr1, base + EMIF_LPDDR2_MODE_REG_DATA);
+ writel(CS1_MR(MR1_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG);
+ writel(ddr_regs->mr1, base + EMIF_LPDDR2_MODE_REG_DATA);
+
+ /* set MR2 register RL=6 for OPP100 */
+ writel(MR2_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG);
+ writel(ddr_regs->mr2, base + EMIF_LPDDR2_MODE_REG_DATA);
+ writel(CS1_MR(MR2_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG);
+ writel(ddr_regs->mr2, base + EMIF_LPDDR2_MODE_REG_DATA);
+
+ /* Set SDRAM CONFIG register again here with final RL-WL value */
+ writel(ddr_regs->config_final, base + EMIF_SDRAM_CONFIG);
+ writel(ddr_regs->phy_ctrl_1, base + EMIF_DDR_PHY_CTRL_1);
+
+ /*
+ * EMIF_SDRAM_REF_CTRL
+ * refresh rate = DDR_CLK / reg_refresh_rate
+ * 3.9 uS = (400MHz) / reg_refresh_rate
+ */
+ writel(ddr_regs->ref_ctrl, base + EMIF_SDRAM_REF_CTRL);
+ writel(ddr_regs->ref_ctrl, base + EMIF_SDRAM_REF_CTRL_SHDW);
+
+ /* set MR16 register */
+ writel(MR16_ADDR | REF_EN, base + EMIF_LPDDR2_MODE_REG_CFG);
+ writel(0, base + EMIF_LPDDR2_MODE_REG_DATA);
+ writel(CS1_MR(MR16_ADDR | REF_EN),
+ base + EMIF_LPDDR2_MODE_REG_CFG);
+ writel(0, base + EMIF_LPDDR2_MODE_REG_DATA);
+
+ /* LPDDR2 init complete */
+
+ return 0;
+}
+
+static void reset_phy(unsigned int base)
+{
+ *(volatile int*)(base + IODFT_TLGC) |= (1 << 10);
+}
+
+void omap4_ddr_init(const struct ddr_regs *ddr_regs,
+ const struct dpll_param *core)
+{
+ unsigned int rev;
+ rev = omap4_revision();
+
+ if (rev == OMAP4430_ES2_0) {
+ writel(0x9e9e9e9e, 0x4A100638);
+ writel(0x9e9e9e9e, 0x4A10063c);
+ writel(0x9e9e9e9e, 0x4A100640);
+ writel(0x9e9e9e9e, 0x4A100648);
+ writel(0x9e9e9e9e, 0x4A10064c);
+ writel(0x9e9e9e9e, 0x4A100650);
+ /* LPDDR2IO set to NMOS PTV */
+ writel(0x00ffc000, 0x4A100704);
+ }
+
+ /*
+ * DMM Configuration
+ */
+
+ /* Both EMIFs 128 byte interleaved */
+ writel(0x80640300, OMAP44XX_DMM_BASE + DMM_LISA_MAP_0);
+
+ *(volatile int*)(OMAP44XX_DMM_BASE + DMM_LISA_MAP_2) = 0x00000000;
+ *(volatile int*)(OMAP44XX_DMM_BASE + DMM_LISA_MAP_3) = 0xFF020100;
+
+ /* DDR needs to be initialised @ 19.2 MHz
+ * So put core DPLL in bypass mode
+ * Configure the Core DPLL but don't lock it
+ */
+ omap4_configure_core_dpll_no_lock(core);
+
+ /* No IDLE: BUG in SDC */
+ sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2);
+ while(((*(volatile int*)CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700);
+
+ *(volatile int*)(OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL) = 0x0;
+ *(volatile int*)(OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL) = 0x0;
+
+ omap4_emif_config(OMAP44XX_EMIF1_BASE, ddr_regs);
+ omap4_emif_config(OMAP44XX_EMIF2_BASE, ddr_regs);
+
+ /* Lock Core using shadow CM_SHADOW_FREQ_CONFIG1 */
+ omap4_lock_core_dpll_shadow(core);
+
+ /* Set DLL_OVERRIDE = 0 */
+ *(volatile int*)CM_DLL_CTRL = 0x0;
+
+ delay(200);
+
+ /* Check for DDR PHY ready for EMIF1 & EMIF2 */
+ while((((*(volatile int*)(OMAP44XX_EMIF1_BASE + EMIF_STATUS))&(0x04)) != 0x04) \
+ || (((*(volatile int*)(OMAP44XX_EMIF2_BASE + EMIF_STATUS))&(0x04)) != 0x04));
+
+ /* Reprogram the DDR PYHY Control register */
+ /* PHY control values */
+
+ sr32(CM_MEMIF_EMIF_1_CLKCTRL, 0, 32, 0x1);
+ sr32(CM_MEMIF_EMIF_2_CLKCTRL, 0, 32, 0x1);
+
+ /* Put the Core Subsystem PD to ON State */
+
+ /* No IDLE: BUG in SDC */
+ //sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2);
+ //while(((*(volatile int*)CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700);
+ *(volatile int*)(OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL) = 0x80000000;
+ *(volatile int*)(OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL) = 0x80000000;
+
+ /*
+ * DMM : DMM_LISA_MAP_0(Section_0)
+ * [31:24] SYS_ADDR 0x80
+ * [22:20] SYS_SIZE 0x7 - 2Gb
+ * [19:18] SDRC_INTLDMM 0x1 - 128 byte
+ * [17:16] SDRC_ADDRSPC 0x0
+ * [9:8] SDRC_MAP 0x3
+ * [7:0] SDRC_ADDR 0X0
+ */
+ reset_phy(OMAP44XX_EMIF1_BASE);
+ reset_phy(OMAP44XX_EMIF2_BASE);
+
+ *((volatile int *)0x80000000) = 0;
+ *((volatile int *)0x80000080) = 0;
+}
+
+void omap4_power_i2c_send(u32 r)
+{
+ u32 val;
+
+ writel(r, OMAP44XX_PRM_VC_VAL_BYPASS);
+
+ val = readl(OMAP44XX_PRM_VC_VAL_BYPASS);
+ val |= 0x1000000;
+ writel(val, OMAP44XX_PRM_VC_VAL_BYPASS);
+
+ while (readl(OMAP44XX_PRM_VC_VAL_BYPASS) & 0x1000000)
+ ;
+
+ val = readl(OMAP44XX_PRM_IRQSTATUS_MPU_A9);
+ writel(val, OMAP44XX_PRM_IRQSTATUS_MPU_A9);
+}
+
+static unsigned int cortex_a9_rev(void)
+{
+
+ unsigned int i;
+
+ asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (i));
+
+ return i;
+}
+
+unsigned int omap4_revision(void)
+{
+ unsigned int chip_rev = 0;
+ unsigned int rev = cortex_a9_rev();
+
+ switch(rev) {
+ case 0x410FC091:
+ return OMAP4430_ES1_0;
+ case 0x411FC092:
+ chip_rev = (readl(OMAP44XX_CTRL_BASE + 0x204) >> 28) & 0xF;
+ if (chip_rev == 3)
+ return OMAP4430_ES2_1;
+ else if (chip_rev >= 4)
+ return OMAP4430_ES2_2;
+ else
+ return OMAP4430_ES2_0;
+ }
+ return OMAP4430_SILICON_ID_INVALID;
+}
+
+/*
+ * shutdown watchdog
+ */
+static int watchdog_init(void)
+{
+ void __iomem *wd2_base = (void *)OMAP44XX_WDT2_BASE;
+
+ writel(WD_UNLOCK1, wd2_base + WATCHDOG_WSPR);
+ wait_for_command_complete();
+ writel(WD_UNLOCK2, wd2_base + WATCHDOG_WSPR);
+
+ return 0;
+}
+late_initcall(watchdog_init);
+
+static int omap_vector_init(void)
+{
+ __asm__ __volatile__ (
+ "mov r0, #0;"
+ "mcr p15, #0, r0, c12, c0, #0;"
+ :
+ :
+ : "r0"
+ );
+
+ return 0;
+}
+core_initcall(omap_vector_init);
--
1.7.2.3
_______________________________________________
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^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 05/12] ARM omap: add xload helper functions
2011-04-11 14:39 OMAP4 support Sascha Hauer
` (3 preceding siblings ...)
2011-04-11 14:39 ` [PATCH 04/12] ARM omap: Add omap4 support Sascha Hauer
@ 2011-04-11 14:39 ` Sascha Hauer
2011-04-11 14:39 ` [PATCH 06/12] ARM omap4: panda board support Sascha Hauer
` (6 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Sascha Hauer @ 2011-04-11 14:39 UTC (permalink / raw)
To: barebox
Add some common xload helper functions to determine the boot source
on omap3/4 and to load images from mmc and nand.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-omap/Makefile | 2 +-
arch/arm/mach-omap/include/mach/xload.h | 16 +++++++++
arch/arm/mach-omap/omap3_generic.c | 14 ++++++++
arch/arm/mach-omap/omap4_generic.c | 14 ++++++++
arch/arm/mach-omap/xload.c | 54 +++++++++++++++++++++++++++++++
5 files changed, 99 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-omap/include/mach/xload.h
create mode 100644 arch/arm/mach-omap/xload.c
diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile
index 9c31456..a4b9a55 100644
--- a/arch/arm/mach-omap/Makefile
+++ b/arch/arm/mach-omap/Makefile
@@ -25,4 +25,4 @@ obj-$(CONFIG_ARCH_OMAP3) += omap3_core.o omap3_generic.o
obj-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o
obj-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock_core.o omap3_clock.o
obj-$(CONFIG_OMAP_GPMC) += gpmc.o devices-gpmc-nand.o
-obj-y += omap-uart.o gpio.o
+obj-y += omap-uart.o gpio.o xload.o
diff --git a/arch/arm/mach-omap/include/mach/xload.h b/arch/arm/mach-omap/include/mach/xload.h
new file mode 100644
index 0000000..844b57f
--- /dev/null
+++ b/arch/arm/mach-omap/include/mach/xload.h
@@ -0,0 +1,16 @@
+#ifndef _MACH_XLOAD_H
+#define _MACH_XLOAD_H
+
+void *omap_xload_boot_nand(int offset, int size);
+void *omap_xload_boot_mmc(void);
+
+enum omap_boot_src {
+ OMAP_BOOTSRC_UNKNOWN,
+ OMAP_BOOTSRC_MMC1,
+ OMAP_BOOTSRC_NAND,
+};
+
+enum omap_boot_src omap3_bootsrc(void);
+enum omap_boot_src omap4_bootsrc(void);
+
+#endif /* _MACH_XLOAD_H */
diff --git a/arch/arm/mach-omap/omap3_generic.c b/arch/arm/mach-omap/omap3_generic.c
index c1940d2..661a971 100644
--- a/arch/arm/mach-omap/omap3_generic.c
+++ b/arch/arm/mach-omap/omap3_generic.c
@@ -46,6 +46,7 @@
#include <mach/wdt.h>
#include <mach/sys_info.h>
#include <mach/syslib.h>
+#include <mach/xload.h>
/**
* @brief Reset the CPU
@@ -483,3 +484,16 @@ void a_init(void)
#endif
}
+
+#define OMAP3_TRACING_VECTOR1 0x4020ffb4
+
+enum omap_boot_src omap3_bootsrc(void)
+{
+ u32 bootsrc = readl(OMAP3_TRACING_VECTOR1);
+
+ if (bootsrc & (1 << 2))
+ return OMAP_BOOTSRC_NAND;
+ if (bootsrc & (1 << 6))
+ return OMAP_BOOTSRC_MMC1;
+ return OMAP_BOOTSRC_UNKNOWN;
+}
diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c
index 45e6c86..e4838e9 100644
--- a/arch/arm/mach-omap/omap4_generic.c
+++ b/arch/arm/mach-omap/omap4_generic.c
@@ -5,6 +5,7 @@
#include <mach/omap4-silicon.h>
#include <mach/omap4-clock.h>
#include <mach/syslib.h>
+#include <mach/xload.h>
void __noreturn reset_cpu(unsigned long addr)
{
@@ -404,3 +405,16 @@ static int omap_vector_init(void)
return 0;
}
core_initcall(omap_vector_init);
+
+#define OMAP4_TRACING_VECTOR3 0x4030d048
+
+enum omap_boot_src omap4_bootsrc(void)
+{
+ u32 bootsrc = readl(OMAP4_TRACING_VECTOR3);
+
+ if (bootsrc & (1 << 3))
+ return OMAP_BOOTSRC_NAND;
+ if (bootsrc & (1 << 5))
+ return OMAP_BOOTSRC_MMC1;
+ return OMAP_BOOTSRC_UNKNOWN;
+}
diff --git a/arch/arm/mach-omap/xload.c b/arch/arm/mach-omap/xload.c
new file mode 100644
index 0000000..216b9b5
--- /dev/null
+++ b/arch/arm/mach-omap/xload.c
@@ -0,0 +1,54 @@
+#include <common.h>
+#include <partition.h>
+#include <nand.h>
+#include <driver.h>
+#include <linux/mtd/mtd.h>
+#include <fs.h>
+#include <fcntl.h>
+#include <mach/xload.h>
+#include <sizes.h>
+
+void *omap_xload_boot_nand(int offset, int size)
+{
+ int ret;
+ void *to = xmalloc(size);
+ struct cdev *cdev;
+
+ devfs_add_partition("nand0", offset, size, PARTITION_FIXED, "x");
+ dev_add_bb_dev("x", "bbx");
+
+ cdev = cdev_open("bbx", O_RDONLY);
+ if (!cdev) {
+ printf("failed to open nand\n");
+ return NULL;
+ }
+
+ ret = cdev_read(cdev, to, size, 0, 0);
+ if (ret != size) {
+ printf("failed to read from nand\n");
+ return NULL;
+ }
+
+ return to;
+}
+
+void *omap_xload_boot_mmc(void)
+{
+ int ret;
+ void *buf;
+ int len;
+
+ ret = mount("disk0.0", "fat", "/");
+ if (ret) {
+ printf("mounting sd card failed with %d\n", ret);
+ return NULL;
+ }
+
+ buf = read_file("/barebox.bin", &len);
+ if (!buf) {
+ printf("could not read barebox.bin from sd card\n");
+ return NULL;
+ }
+
+ return buf;
+}
--
1.7.2.3
_______________________________________________
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^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 06/12] ARM omap4: panda board support
2011-04-11 14:39 OMAP4 support Sascha Hauer
` (4 preceding siblings ...)
2011-04-11 14:39 ` [PATCH 05/12] ARM omap: add xload helper functions Sascha Hauer
@ 2011-04-11 14:39 ` Sascha Hauer
2011-04-12 8:18 ` Marc Kleine-Budde
2011-04-11 14:39 ` [PATCH 07/12] add panda defconfigs Sascha Hauer
` (5 subsequent siblings)
11 siblings, 1 reply; 15+ messages in thread
From: Sascha Hauer @ 2011-04-11 14:39 UTC (permalink / raw)
To: barebox
This patch adds support for the TI omap4 panda board.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/Makefile | 1 +
arch/arm/boards/panda/Makefile | 1 +
arch/arm/boards/panda/board.c | 230 ++++++++++++++++++++++++++++++++++
arch/arm/boards/panda/config.h | 1 +
arch/arm/boards/panda/env/config | 45 +++++++
arch/arm/boards/panda/lowlevel.c | 121 ++++++++++++++++++
arch/arm/boards/panda/mux.c | 257 ++++++++++++++++++++++++++++++++++++++
arch/arm/mach-omap/Kconfig | 8 ++
8 files changed, 664 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/boards/panda/Makefile
create mode 100644 arch/arm/boards/panda/board.c
create mode 100644 arch/arm/boards/panda/config.h
create mode 100644 arch/arm/boards/panda/env/config
create mode 100644 arch/arm/boards/panda/lowlevel.c
create mode 100644 arch/arm/boards/panda/mux.c
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index fa1677c..1aaefce 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -86,6 +86,7 @@ board-$(CONFIG_MACH_NXDB500) := netx
board-$(CONFIG_MACH_OMAP343xSDP) := omap
board-$(CONFIG_MACH_BEAGLE) := omap
board-$(CONFIG_MACH_OMAP3EVM) := omap
+board-$(CONFIG_MACH_PANDA) := panda
board-$(CONFIG_MACH_PCA100) := phycard-i.MX27
board-$(CONFIG_MACH_PCM037) := pcm037
board-$(CONFIG_MACH_PCM038) := pcm038
diff --git a/arch/arm/boards/panda/Makefile b/arch/arm/boards/panda/Makefile
new file mode 100644
index 0000000..c55e26e
--- /dev/null
+++ b/arch/arm/boards/panda/Makefile
@@ -0,0 +1 @@
+obj-y += board.o lowlevel.o mux.o
diff --git a/arch/arm/boards/panda/board.c b/arch/arm/boards/panda/board.c
new file mode 100644
index 0000000..ff05f9e
--- /dev/null
+++ b/arch/arm/boards/panda/board.c
@@ -0,0 +1,230 @@
+#include <common.h>
+#include <console.h>
+#include <init.h>
+#include <fs.h>
+#include <driver.h>
+#include <asm/io.h>
+#include <ns16550.h>
+#include <asm/armlinux.h>
+#include <linux/stat.h>
+#include <generated/mach-types.h>
+#include <mach/silicon.h>
+#include <mach/sdrc.h>
+#include <mach/sys_info.h>
+#include <mach/syslib.h>
+#include <mach/control.h>
+#include <usb/ehci.h>
+#include <linux/err.h>
+#include <sizes.h>
+#include <asm/mmu.h>
+#include <mach/gpio.h>
+#include <environment.h>
+#include <mach/xload.h>
+
+static int board_revision;
+
+#define GPIO_HUB_POWER 1
+#define GPIO_HUB_NRESET_39 39
+#define GPIO_HUB_NRESET_62 62
+#define GPIO_BOARD_ID0 182
+#define GPIO_BOARD_ID1 101
+#define GPIO_BOARD_ID2 171
+
+static struct NS16550_plat serial_plat = {
+ .clock = 48000000, /* 48MHz (APLL96/2) */
+ .f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR,
+ .reg_read = omap_uart_read,
+ .reg_write = omap_uart_write,
+};
+
+static struct device_d panda_serial_device = {
+ .id = -1,
+ .name = "serial_ns16550",
+ .map_base = OMAP44XX_UART3_BASE,
+ .size = 1024,
+ .platform_data = (void *)&serial_plat,
+};
+
+static int panda_console_init(void)
+{
+ /* Register the serial port */
+ return register_device(&panda_serial_device);
+}
+console_initcall(panda_console_init);
+
+static struct memory_platform_data sram_pdata = {
+ .name = "ram0",
+ .flags = DEVFS_RDWR,
+};
+
+static struct device_d sdram_dev = {
+ .id = -1,
+ .name = "mem",
+ .map_base = 0x80000000,
+ .size = SZ_1G,
+ .platform_data = &sram_pdata,
+};
+
+#ifdef CONFIG_MMU
+static int panda_mmu_init(void)
+{
+ mmu_init();
+
+ arm_create_section(0x80000000, 0x80000000, 256, PMD_SECT_DEF_CACHED);
+ arm_create_section(0x90000000, 0x80000000, 256, PMD_SECT_DEF_UNCACHED);
+
+ mmu_enable();
+
+ return 0;
+}
+device_initcall(panda_mmu_init);
+#endif
+
+static struct ehci_platform_data ehci_pdata = {
+ .flags = 0,
+ .hccr_offset = 0x0,
+ .hcor_offset = 0x10,
+};
+
+static struct device_d usbh_dev = {
+ .id = -1,
+ .name = "ehci",
+ .map_base = 0x4a064c00,
+ .size = 4 * 1024,
+ .platform_data = &ehci_pdata,
+};
+
+static void panda_ehci_init(void)
+{
+ u32 val;
+ int hub_nreset;
+
+ if (board_revision)
+ hub_nreset = GPIO_HUB_NRESET_62;
+ else
+ hub_nreset = GPIO_HUB_NRESET_39;
+
+ /* disable the power to the usb hub prior to init */
+ gpio_direction_output(GPIO_HUB_POWER, 0);
+ gpio_set_value(GPIO_HUB_POWER, 0);
+
+ /* reset phy+hub */
+ gpio_direction_output(hub_nreset, 0);
+ gpio_set_value(hub_nreset, 0);
+ gpio_set_value(hub_nreset, 1);
+ val = readl(0x4a009358);
+ val |= (1 << 24);
+ writel(val, 0x4a009358);
+ writel(0x7, 0x4a008180);
+ mdelay(10);
+
+ writel(0x00000014, 0x4a064010);
+ writel(0x8000001c, 0x4a064040);
+
+ /* enable power to hub */
+ gpio_set_value(GPIO_HUB_POWER, 1);
+
+ register_device(&usbh_dev);
+}
+
+static void __init panda_boardrev_init(void)
+{
+ board_revision = gpio_get_value(GPIO_BOARD_ID0);
+ board_revision |= (gpio_get_value(GPIO_BOARD_ID1)<<1);
+ board_revision |= (gpio_get_value(GPIO_BOARD_ID2)<<2);
+
+ pr_info("PandaBoard Revision: %03d\n", board_revision);
+}
+
+static struct device_d hsmmc_dev = {
+ .id = -1,
+ .name = "omap-hsmmc",
+ .map_base = 0x4809C100,
+ .size = SZ_4K,
+};
+
+static int panda_devices_init(void)
+{
+ panda_boardrev_init();
+
+ if (gpio_get_value(182)) {
+ /* enable software ioreq */
+ sr32(OMAP44XX_SCRM_AUXCLK3, 8, 1, 0x1);
+ /* set for sys_clk (38.4MHz) */
+ sr32(OMAP44XX_SCRM_AUXCLK3, 1, 2, 0x0);
+ /* set divisor to 2 */
+ sr32(OMAP44XX_SCRM_AUXCLK3, 16, 4, 0x1);
+ /* set the clock source to active */
+ sr32(OMAP44XX_SCRM_ALTCLKSRC, 0, 1, 0x1);
+ /* enable clocks */
+ sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3);
+ } else {
+ /* enable software ioreq */
+ sr32(OMAP44XX_SCRM_AUXCLK1, 8, 1, 0x1);
+ /* set for PER_DPLL */
+ sr32(OMAP44XX_SCRM_AUXCLK1, 1, 2, 0x2);
+ /* set divisor to 16 */
+ sr32(OMAP44XX_SCRM_AUXCLK1, 16, 4, 0xf);
+ /* set the clock source to active */
+ sr32(OMAP44XX_SCRM_ALTCLKSRC, 0, 1, 0x1);
+ /* enable clocks */
+ sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3);
+ }
+
+ register_device(&sdram_dev);
+ register_device(&hsmmc_dev);
+ panda_ehci_init();
+
+ armlinux_add_dram(&sdram_dev);
+ armlinux_set_bootparams((void *)0x80000100);
+ armlinux_set_architecture(MACH_TYPE_OMAP4_PANDA);
+
+ return 0;
+}
+device_initcall(panda_devices_init);
+
+#ifdef CONFIG_DEFAULT_ENVIRONMENT
+static int panda_env_init(void)
+{
+ struct stat s;
+ char *diskdev = "/dev/disk0.0";
+ int ret;
+
+ ret = stat(diskdev, &s);
+ if (ret) {
+ printf("no %s. using default env\n", diskdev);
+ return 0;
+ }
+
+ mkdir ("/boot", 0666);
+ ret = mount(diskdev, "fat", "/boot");
+ if (ret) {
+ printf("failed to mount %s\n", diskdev);
+ return 0;
+ }
+
+ default_environment_path = "/boot/bareboxenv";
+
+ return 0;
+}
+late_initcall(panda_env_init);
+#endif
+
+
+#ifdef CONFIG_SHELL_NONE
+int run_shell(void)
+{
+ int (*func)(void);
+
+ func = omap_xload_boot_mmc();
+ if (!func) {
+ printf("booting failed\n");
+ while (1);
+ }
+
+ shutdown_barebox();
+ func();
+
+ while (1);
+}
+#endif
diff --git a/arch/arm/boards/panda/config.h b/arch/arm/boards/panda/config.h
new file mode 100644
index 0000000..da84fa5
--- /dev/null
+++ b/arch/arm/boards/panda/config.h
@@ -0,0 +1 @@
+/* nothing */
diff --git a/arch/arm/boards/panda/env/config b/arch/arm/boards/panda/env/config
new file mode 100644
index 0000000..5c65d21
--- /dev/null
+++ b/arch/arm/boards/panda/env/config
@@ -0,0 +1,45 @@
+#!/bin/sh
+
+machine=panda
+user=
+
+# use 'dhcp' to do dhcp in barebox and in kernel
+# use 'none' if you want to skip kernel ip autoconfiguration
+ip=dhcp
+
+# or set your networking parameters here
+#eth0.ipaddr=a.b.c.d
+#eth0.netmask=a.b.c.d
+#eth0.gateway=a.b.c.d
+#eth0.serverip=a.b.c.d
+
+# can be either 'nfs', 'tftp', 'nor' or 'nand'
+kernel_loc=tftp
+# can be either 'net', 'nor', 'nand' or 'initrd'
+rootfs_loc=net
+
+# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
+kernelimage_type=zimage
+kernelimage=zImage-$machine
+#kernelimage_type=uimage
+#kernelimage=uImage-$machine
+#kernelimage_type=raw
+#kernelimage=Image-$machine
+#kernelimage_type=raw_lzo
+#kernelimage=Image-$machine.lzo
+
+if [ -n $user ]; then
+ kernelimage="$user"-"$kernelimage"
+ nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
+ rootfsimage="$user"-"$rootfsimage"
+else
+ nfsroot="$eth0.serverip:/path/to/nfs/root"
+fi
+
+autoboot_timeout=3
+
+bootargs="console=ttyO2,115200"
+
+# set a fancy prompt (if support is compiled in)
+PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "
+
diff --git a/arch/arm/boards/panda/lowlevel.c b/arch/arm/boards/panda/lowlevel.c
new file mode 100644
index 0000000..cc0c374
--- /dev/null
+++ b/arch/arm/boards/panda/lowlevel.c
@@ -0,0 +1,121 @@
+/*
+ * (C) Copyright 2004-2009
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <mach/omap4-mux.h>
+#include <mach/omap4-silicon.h>
+#include <mach/omap4-clock.h>
+#include <mach/syslib.h>
+#include <asm/barebox-arm.h>
+
+void set_muxconf_regs(void);
+
+static const struct ddr_regs ddr_regs_400_mhz_2cs = {
+ /* tRRD changed from 10ns to 12.5ns because of the tFAW requirement*/
+ .tim1 = 0x10eb0662,
+ .tim2 = 0x20370dd2,
+ .tim3 = 0x00b1c33f,
+ .phy_ctrl_1 = 0x849FF408,
+ .ref_ctrl = 0x00000618,
+ .config_init = 0x80000eb9,
+ .config_final = 0x80001ab9,
+ .zq_config = 0xD00b3215,
+ .mr1 = 0x83,
+ .mr2 = 0x4
+};
+
+#define I2C_SLAVE 0x12
+
+static int noinline scale_vcores(void)
+{
+ unsigned int rev = omap4_revision();
+
+ /* For VC bypass only VCOREx_CGF_FORCE is necessary and
+ * VCOREx_CFG_VOLTAGE changes can be discarded
+ */
+ writel(0, OMAP44XX_PRM_VC_CFG_I2C_MODE);
+ writel(0x6026, OMAP44XX_PRM_VC_CFG_I2C_CLK);
+
+ /* set VCORE1 force VSEL */
+ omap4_power_i2c_send((0x3A55 << 8) | I2C_SLAVE);
+
+ /* FIXME: set VCORE2 force VSEL, Check the reset value */
+ omap4_power_i2c_send((0x295B << 8) | I2C_SLAVE);
+
+ /* set VCORE3 force VSEL */
+ switch (rev) {
+ case OMAP4430_ES2_0:
+ omap4_power_i2c_send((0x2961 << 8) | I2C_SLAVE);
+ break;
+ case OMAP4430_ES2_1:
+ omap4_power_i2c_send((0x2A61 << 8) | I2C_SLAVE);
+ break;
+ }
+
+ return 0;
+}
+
+static void noinline panda_init_lowlevel(void)
+{
+ struct dpll_param core = OMAP4_CORE_DPLL_PARAM_38M4_DDR400;
+ struct dpll_param mpu = OMAP4_MPU_DPLL_PARAM_38M4_MPU600;
+ struct dpll_param iva = OMAP4_IVA_DPLL_PARAM_38M4;
+ struct dpll_param per = OMAP4_PER_DPLL_PARAM_38M4;
+ struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_38M4;
+ struct dpll_param usb = OMAP4_USB_DPLL_PARAM_38M4;
+
+ writel(CM_SYS_CLKSEL_38M4, CM_SYS_CLKSEL);
+
+ /* Configure all DPLL's at 100% OPP */
+ omap4_configure_mpu_dpll(&mpu);
+ omap4_configure_iva_dpll(&iva);
+ omap4_configure_per_dpll(&per);
+ omap4_configure_abe_dpll(&abe);
+ omap4_configure_usb_dpll(&usb);
+
+ /* Enable all clocks */
+ omap4_enable_all_clocks();
+
+ set_muxconf_regs();
+
+ omap4_ddr_init(&ddr_regs_400_mhz_2cs, &core);
+
+ /* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
+ scale_vcores();
+
+ board_init_lowlevel_return();
+}
+
+void board_init_lowlevel(void)
+{
+ u32 r;
+
+ if (get_pc() > 0x80000000)
+ return;
+
+ r = 0x4030d000;
+ __asm__ __volatile__("mov sp, %0" : : "r"(r));
+
+ panda_init_lowlevel();
+}
+
diff --git a/arch/arm/boards/panda/mux.c b/arch/arm/boards/panda/mux.c
new file mode 100644
index 0000000..a031040
--- /dev/null
+++ b/arch/arm/boards/panda/mux.c
@@ -0,0 +1,257 @@
+#include <common.h>
+#include <init.h>
+#include <asm/io.h>
+#include <mach/omap4-silicon.h>
+#include <mach/omap4-mux.h>
+
+static const struct pad_conf_entry core_padconf_array[] = {
+ { GPMC_AD0, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* sdmmc2_dat0 */ },
+ { GPMC_AD1, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* sdmmc2_dat1 */ },
+ { GPMC_AD2, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* sdmmc2_dat2 */ },
+ { GPMC_AD3, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* sdmmc2_dat3 */ },
+ { GPMC_AD4, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* sdmmc2_dat4 */ },
+ { GPMC_AD5, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* sdmmc2_dat5 */ },
+ { GPMC_AD6, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* sdmmc2_dat6 */ },
+ { GPMC_AD7, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* sdmmc2_dat7 */ },
+ { GPMC_AD8, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3 /* gpio_32 */ },
+ { GPMC_AD9, PTU | IEN | M3 /* gpio_33 */ },
+ { GPMC_AD10, PTU | IEN | M3 /* gpio_34 */ },
+ { GPMC_AD11, PTU | IEN | M3 /* gpio_35 */ },
+ { GPMC_AD12, PTU | IEN | M3 /* gpio_36 */ },
+ { GPMC_AD13, PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3 /* gpio_37 */ },
+ { GPMC_AD14, PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3 /* gpio_38 */ },
+ { GPMC_AD15, PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3 /* gpio_39 */ },
+ { GPMC_A16, M3 /* gpio_40 */ },
+ { GPMC_A17, PTD | M3 /* gpio_41 */ },
+ { GPMC_A18, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_row6 */ },
+ { GPMC_A19, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_row7 */ },
+ { GPMC_A20, IEN | M3 /* gpio_44 */ },
+ { GPMC_A21, M3 /* gpio_45 */ },
+ { GPMC_A22, M3 /* gpio_46 */ },
+ { GPMC_A23, OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_col7 */ },
+ { GPMC_A24, PTD | M3 /* gpio_48 */ },
+ { GPMC_A25, PTD | M3 /* gpio_49 */ },
+ { GPMC_NCS0, M3 /* gpio_50 */ },
+ { GPMC_NCS1, IEN | M3 /* gpio_51 */ },
+ { GPMC_NCS2, IEN | M3 /* gpio_52 */ },
+ { GPMC_NCS3, IEN | M3 /* gpio_53 */ },
+ { GPMC_NWP, M3 /* gpio_54 */ },
+ { GPMC_CLK, PTD | M3 /* gpio_55 */ },
+ { GPMC_NADV_ALE, M3 /* gpio_56 */ },
+ { GPMC_NOE, PTU | IEN | OFF_EN | OFF_OUT_PTD | M1 /* sdmmc2_clk */ },
+ { GPMC_NWE, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* sdmmc2_cmd */ },
+ { GPMC_NBE0_CLE, M3 /* gpio_59 */ },
+ { GPMC_NBE1, PTD | M3 /* gpio_60 */ },
+ { GPMC_WAIT0, PTU | IEN | M3 /* gpio_61 */ },
+ { GPMC_WAIT1, PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3 /* gpio_62 */ },
+ { C2C_DATA11, PTD | M3 /* gpio_100 */ },
+ { C2C_DATA12, PTD | IEN | M3 /* gpio_101 */ },
+ { C2C_DATA13, PTD | M3 /* gpio_102 */ },
+ { C2C_DATA14, M1 /* dsi2_te0 */ },
+ { C2C_DATA15, PTD | M3 /* gpio_104 */ },
+ { HDMI_HPD, M0 /* hdmi_hpd */ },
+ { HDMI_CEC, M0 /* hdmi_cec */ },
+ { HDMI_DDC_SCL, PTU | M0 /* hdmi_ddc_scl */ },
+ { HDMI_DDC_SDA, PTU | IEN | M0 /* hdmi_ddc_sda */ },
+ { CSI21_DX0, IEN | M0 /* csi21_dx0 */ },
+ { CSI21_DY0, IEN | M0 /* csi21_dy0 */ },
+ { CSI21_DX1, IEN | M0 /* csi21_dx1 */ },
+ { CSI21_DY1, IEN | M0 /* csi21_dy1 */ },
+ { CSI21_DX2, IEN | M0 /* csi21_dx2 */ },
+ { CSI21_DY2, IEN | M0 /* csi21_dy2 */ },
+ { CSI21_DX3, PTD | M7 /* csi21_dx3 */ },
+ { CSI21_DY3, PTD | M7 /* csi21_dy3 */ },
+ { CSI21_DX4, PTD | OFF_EN | OFF_PD | OFF_IN | M7 /* csi21_dx4 */ },
+ { CSI21_DY4, PTD | OFF_EN | OFF_PD | OFF_IN | M7 /* csi21_dy4 */ },
+ { CSI22_DX0, IEN | M0 /* csi22_dx0 */ },
+ { CSI22_DY0, IEN | M0 /* csi22_dy0 */ },
+ { CSI22_DX1, IEN | M0 /* csi22_dx1 */ },
+ { CSI22_DY1, IEN | M0 /* csi22_dy1 */ },
+ { CAM_SHUTTER, OFF_EN | OFF_PD | OFF_OUT_PTD | M0 /* cam_shutter */ },
+ { CAM_STROBE, OFF_EN | OFF_PD | OFF_OUT_PTD | M0 /* cam_strobe */ },
+ { CAM_GLOBALRESET, PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3 /* gpio_83 */ },
+ { USBB1_ULPITLL_CLK, PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4 /* usbb1_ulpiphy_clk */ },
+ { USBB1_ULPITLL_STP, OFF_EN | OFF_OUT_PTD | M4 /* usbb1_ulpiphy_stp */ },
+ { USBB1_ULPITLL_DIR, IEN | OFF_EN | OFF_PD | OFF_IN | M4 /* usbb1_ulpiphy_dir */ },
+ { USBB1_ULPITLL_NXT, IEN | OFF_EN | OFF_PD | OFF_IN | M4 /* usbb1_ulpiphy_nxt */ },
+ { USBB1_ULPITLL_DAT0, IEN | OFF_EN | OFF_PD | OFF_IN | M4 /* usbb1_ulpiphy_dat0 */ },
+ { USBB1_ULPITLL_DAT1, IEN | OFF_EN | OFF_PD | OFF_IN | M4 /* usbb1_ulpiphy_dat1 */ },
+ { USBB1_ULPITLL_DAT2, IEN | OFF_EN | OFF_PD | OFF_IN | M4 /* usbb1_ulpiphy_dat2 */ },
+ { USBB1_ULPITLL_DAT3, IEN | OFF_EN | OFF_PD | OFF_IN | M4 /* usbb1_ulpiphy_dat3 */ },
+ { USBB1_ULPITLL_DAT4, IEN | OFF_EN | OFF_PD | OFF_IN | M4 /* usbb1_ulpiphy_dat4 */ },
+ { USBB1_ULPITLL_DAT5, IEN | OFF_EN | OFF_PD | OFF_IN | M4 /* usbb1_ulpiphy_dat5 */ },
+ { USBB1_ULPITLL_DAT6, IEN | OFF_EN | OFF_PD | OFF_IN | M4 /* usbb1_ulpiphy_dat6 */ },
+ { USBB1_ULPITLL_DAT7, IEN | OFF_EN | OFF_PD | OFF_IN | M4 /* usbb1_ulpiphy_dat7 */ },
+ { USBB1_HSIC_DATA, IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* usbb1_hsic_data */ },
+ { USBB1_HSIC_STROBE, IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* usbb1_hsic_strobe */ },
+ { USBC1_ICUSB_DP, IEN | M0 /* usbc1_icusb_dp */ },
+ { USBC1_ICUSB_DM, IEN | M0 /* usbc1_icusb_dm */ },
+ { SDMMC1_CLK, PTU | OFF_EN | OFF_OUT_PTD | M0 /* sdmmc1_clk */ },
+ { SDMMC1_CMD, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc1_cmd */ },
+ { SDMMC1_DAT0, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc1_dat0 */ },
+ { SDMMC1_DAT1, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc1_dat1 */ },
+ { SDMMC1_DAT2, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc1_dat2 */ },
+ { SDMMC1_DAT3, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc1_dat3 */ },
+ { SDMMC1_DAT4, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc1_dat4 */ },
+ { SDMMC1_DAT5, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc1_dat5 */ },
+ { SDMMC1_DAT6, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc1_dat6 */ },
+ { SDMMC1_DAT7, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc1_dat7 */ },
+ { ABE_MCBSP2_CLKX, IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* abe_mcbsp2_clkx */ },
+ { ABE_MCBSP2_DR, IEN | OFF_EN | OFF_OUT_PTD | M0 /* abe_mcbsp2_dr */ },
+ { ABE_MCBSP2_DX, OFF_EN | OFF_OUT_PTD | M0 /* abe_mcbsp2_dx */ },
+ { ABE_MCBSP2_FSX, IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* abe_mcbsp2_fsx */ },
+ { ABE_MCBSP1_CLKX, IEN | M1 /* abe_slimbus1_clock */ },
+ { ABE_MCBSP1_DR, IEN | M1 /* abe_slimbus1_data */ },
+ { ABE_MCBSP1_DX, OFF_EN | OFF_OUT_PTD | M0 /* abe_mcbsp1_dx */ },
+ { ABE_MCBSP1_FSX, IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* abe_mcbsp1_fsx */ },
+ { ABE_PDM_UL_DATA, PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* abe_pdm_ul_data */ },
+ { ABE_PDM_DL_DATA, PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* abe_pdm_dl_data */ },
+ { ABE_PDM_FRAME, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* abe_pdm_frame */ },
+ { ABE_PDM_LB_CLK, PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* abe_pdm_lb_clk */ },
+ { ABE_CLKS, PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* abe_clks */ },
+ { ABE_DMIC_CLK1, M0 /* abe_dmic_clk1 */ },
+ { ABE_DMIC_DIN1, IEN | M0 /* abe_dmic_din1 */ },
+ { ABE_DMIC_DIN2, IEN | M0 /* abe_dmic_din2 */ },
+ { ABE_DMIC_DIN3, IEN | M0 /* abe_dmic_din3 */ },
+ { UART2_CTS, PTU | IEN | M0 /* uart2_cts */ },
+ { UART2_RTS, M0 /* uart2_rts */ },
+ { UART2_RX, PTU | IEN | M0 /* uart2_rx */ },
+ { UART2_TX, M0 /* uart2_tx */ },
+ { HDQ_SIO, M3 /* gpio_127 */ },
+ { I2C1_SCL, PTU | IEN | M0 /* i2c1_scl */ },
+ { I2C1_SDA, PTU | IEN | M0 /* i2c1_sda */ },
+ { I2C2_SCL, PTU | IEN | M0 /* i2c2_scl */ },
+ { I2C2_SDA, PTU | IEN | M0 /* i2c2_sda */ },
+ { I2C3_SCL, PTU | IEN | M0 /* i2c3_scl */ },
+ { I2C3_SDA, PTU | IEN | M0 /* i2c3_sda */ },
+ { I2C4_SCL, PTU | IEN | M0 /* i2c4_scl */ },
+ { I2C4_SDA, PTU | IEN | M0 /* i2c4_sda */ },
+ { MCSPI1_CLK, IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* mcspi1_clk */ },
+ { MCSPI1_SOMI, IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* mcspi1_somi */ },
+ { MCSPI1_SIMO, IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* mcspi1_simo */ },
+ { MCSPI1_CS0, PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* mcspi1_cs0 */ },
+ { MCSPI1_CS1, PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3 /* mcspi1_cs1 */ },
+ { MCSPI1_CS2, PTU | OFF_EN | OFF_OUT_PTU | M3 /* gpio_139 */ },
+ { MCSPI1_CS3, PTU | IEN | M3 /* gpio_140 */ },
+ { UART3_CTS_RCTX, PTU | IEN | M0 /* uart3_tx */ },
+ { UART3_RTS_SD, M0 /* uart3_rts_sd */ },
+ { UART3_RX_IRRX, IEN | M0 /* uart3_rx */ },
+ { UART3_TX_IRTX, M0 /* uart3_tx */ },
+ { SDMMC5_CLK, PTU | IEN | OFF_EN | OFF_OUT_PTD | M0 /* sdmmc5_clk */ },
+ { SDMMC5_CMD, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc5_cmd */ },
+ { SDMMC5_DAT0, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc5_dat0 */ },
+ { SDMMC5_DAT1, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc5_dat1 */ },
+ { SDMMC5_DAT2, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc5_dat2 */ },
+ { SDMMC5_DAT3, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc5_dat3 */ },
+ { MCSPI4_CLK, IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* mcspi4_clk */ },
+ { MCSPI4_SIMO, IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* mcspi4_simo */ },
+ { MCSPI4_SOMI, IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* mcspi4_somi */ },
+ { MCSPI4_CS0, PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* mcspi4_cs0 */ },
+ { UART4_RX, IEN | M0 /* uart4_rx */ },
+ { UART4_TX, M0 /* uart4_tx */ },
+ { USBB2_ULPITLL_CLK, IEN | M3 /* gpio_157 */ },
+ { USBB2_ULPITLL_STP, IEN | M5 /* dispc2_data23 */ },
+ { USBB2_ULPITLL_DIR, IEN | M5 /* dispc2_data22 */ },
+ { USBB2_ULPITLL_NXT, IEN | M5 /* dispc2_data21 */ },
+ { USBB2_ULPITLL_DAT0, IEN | M5 /* dispc2_data20 */ },
+ { USBB2_ULPITLL_DAT1, IEN | M5 /* dispc2_data19 */ },
+ { USBB2_ULPITLL_DAT2, IEN | M5 /* dispc2_data18 */ },
+ { USBB2_ULPITLL_DAT3, IEN | M5 /* dispc2_data15 */ },
+ { USBB2_ULPITLL_DAT4, IEN | M5 /* dispc2_data14 */ },
+ { USBB2_ULPITLL_DAT5, IEN | M5 /* dispc2_data13 */ },
+ { USBB2_ULPITLL_DAT6, IEN | M5 /* dispc2_data12 */ },
+ { USBB2_ULPITLL_DAT7, IEN | M5 /* dispc2_data11 */ },
+ { USBB2_HSIC_DATA, PTD | OFF_EN | OFF_OUT_PTU | M3 /* gpio_169 */ },
+ { USBB2_HSIC_STROBE, PTD | OFF_EN | OFF_OUT_PTU | M3 /* gpio_170 */ },
+ { UNIPRO_TX0, PTD | IEN | M3 /* gpio_171 */ },
+ { UNIPRO_TY0, OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_col1 */ },
+ { UNIPRO_TX1, OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_col2 */ },
+ { UNIPRO_TY1, OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_col3 */ },
+ { UNIPRO_TX2, PTU | IEN | M3 /* gpio_0 */ },
+ { UNIPRO_TY2, PTU | IEN | M3 /* gpio_1 */ },
+ { UNIPRO_RX0, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_row0 */ },
+ { UNIPRO_RY0, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_row1 */ },
+ { UNIPRO_RX1, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_row2 */ },
+ { UNIPRO_RY1, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_row3 */ },
+ { UNIPRO_RX2, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_row4 */ },
+ { UNIPRO_RY2, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_row5 */ },
+ { USBA0_OTG_CE, PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0 /* usba0_otg_ce */ },
+ { USBA0_OTG_DP, IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* usba0_otg_dp */ },
+ { USBA0_OTG_DM, IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* usba0_otg_dm */ },
+ { FREF_CLK1_OUT, M0 /* fref_clk1_out */ },
+ { FREF_CLK2_OUT, PTD | IEN | M3 /* gpio_182 */ },
+ { SYS_NIRQ1, PTU | IEN | M0 /* sys_nirq1 */ },
+ { SYS_NIRQ2, PTU | IEN | M0 /* sys_nirq2 */ },
+ { SYS_BOOT0, PTU | IEN | M3 /* gpio_184 */ },
+ { SYS_BOOT1, M3 /* gpio_185 */ },
+ { SYS_BOOT2, PTD | IEN | M3 /* gpio_186 */ },
+ { SYS_BOOT3, M3 /* gpio_187 */ },
+ { SYS_BOOT4, M3 /* gpio_188 */ },
+ { SYS_BOOT5, PTD | IEN | M3 /* gpio_189 */ },
+ { DPM_EMU0, IEN | M0 /* dpm_emu0 */ },
+ { DPM_EMU1, IEN | M0 /* dpm_emu1 */ },
+ { DPM_EMU2, IEN | M0 /* dpm_emu2 */ },
+ { DPM_EMU3, IEN | M5 /* dispc2_data10 */ },
+ { DPM_EMU4, IEN | M5 /* dispc2_data9 */ },
+ { DPM_EMU5, IEN | M5 /* dispc2_data16 */ },
+ { DPM_EMU6, IEN | M5 /* dispc2_data17 */ },
+ { DPM_EMU7, IEN | M5 /* dispc2_hsync */ },
+ { DPM_EMU8, IEN | M5 /* dispc2_pclk */ },
+ { DPM_EMU9, IEN | M5 /* dispc2_vsync */ },
+ { DPM_EMU10, IEN | M5 /* dispc2_de */ },
+ { DPM_EMU11, IEN | M5 /* dispc2_data8 */ },
+ { DPM_EMU12, IEN | M5 /* dispc2_data7 */ },
+ { DPM_EMU13, IEN | M5 /* dispc2_data6 */ },
+ { DPM_EMU14, IEN | M5 /* dispc2_data5 */ },
+ { DPM_EMU15, IEN | M5 /* dispc2_data4 */ },
+ { DPM_EMU16, M3 /* gpio_27 */ },
+ { DPM_EMU17, IEN | M5 /* dispc2_data2 */ },
+ { DPM_EMU18, IEN | M5 /* dispc2_data1 */ },
+ { DPM_EMU19, IEN | M5 /* dispc2_data0 */ },
+};
+
+static const struct pad_conf_entry wkup_padconf_array[] = {
+ { PAD0_SIM_IO, IEN | M0 /* sim_io */ },
+ { PAD1_SIM_CLK, M0 /* sim_clk */ },
+ { PAD0_SIM_RESET, M0 /* sim_reset */ },
+ { PAD1_SIM_CD, PTU | IEN | M0 /* sim_cd */ },
+ { PAD0_SIM_PWRCTRL, M0 /* sim_pwrctrl */ },
+ { PAD1_SR_SCL, PTU | IEN | M0 /* sr_scl */ },
+ { PAD0_SR_SDA, PTU | IEN | M0 /* sr_sda */ },
+ { PAD1_FREF_XTAL_IN, M0 /* # */ },
+ { PAD0_FREF_SLICER_IN, M0 /* fref_slicer_in */ },
+ { PAD1_FREF_CLK_IOREQ, M0 /* fref_clk_ioreq */ },
+ { PAD0_FREF_CLK0_OUT, M2 /* sys_drm_msecure */ },
+ { PAD1_FREF_CLK3_REQ, PTU | IEN | M0 /* # */ },
+ { PAD0_FREF_CLK3_OUT, M0 /* fref_clk3_out */ },
+ { PAD1_FREF_CLK4_REQ, PTU | IEN | M0 /* # */ },
+ { PAD0_FREF_CLK4_OUT, M0 /* # */ },
+ { PAD1_SYS_32K, IEN | M0 /* sys_32k */ },
+ { PAD0_SYS_NRESPWRON, M0 /* sys_nrespwron */ },
+ { PAD1_SYS_NRESWARM, M0 /* sys_nreswarm */ },
+ { PAD0_SYS_PWR_REQ, PTU | M0 /* sys_pwr_req */ },
+ { PAD1_SYS_PWRON_RESET, M3 /* gpio_wk29 */ },
+ { PAD0_SYS_BOOT6, IEN | M3 /* gpio_wk9 */ },
+ { PAD1_SYS_BOOT7, IEN | M3 /* gpio_wk10 */ },
+ { PAD1_FREF_CLK3_REQ, M3 /* gpio_wk30 */ },
+ { PAD1_FREF_CLK4_REQ, M3 /* gpio_wk7 */ },
+ { PAD0_FREF_CLK4_OUT, M3 /* gpio_wk8 */ },
+};
+
+static void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
+{
+ int i;
+ struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
+
+ for (i = 0; i < size; i++, pad++)
+ writew(pad->val, base + pad->offset);
+}
+
+void set_muxconf_regs(void)
+{
+ do_set_mux(OMAP44XX_CONTROL_PADCONF_CORE, core_padconf_array,
+ ARRAY_SIZE(core_padconf_array));
+
+ do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP, wkup_padconf_array,
+ ARRAY_SIZE(wkup_padconf_array));
+}
diff --git a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig
index df83b17..13a3df8 100644
--- a/arch/arm/mach-omap/Kconfig
+++ b/arch/arm/mach-omap/Kconfig
@@ -136,6 +136,14 @@ config MACH_OMAP3EVM
help
Say Y here if you are using OMAP3EVM
+config MACH_PANDA
+ bool "Texas Instrument's Panda Board"
+ select HAVE_MMU
+ select HAVE_NOSHELL
+ select MACH_HAS_LOWLEVEL_INIT
+ help
+ Say Y here if you are using OMAP4 Panda board
+
endchoice
if MACH_OMAP3EVM
--
1.7.2.3
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^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH 06/12] ARM omap4: panda board support
2011-04-11 14:39 ` [PATCH 06/12] ARM omap4: panda board support Sascha Hauer
@ 2011-04-12 8:18 ` Marc Kleine-Budde
0 siblings, 0 replies; 15+ messages in thread
From: Marc Kleine-Budde @ 2011-04-12 8:18 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
[-- Attachment #1.1: Type: text/plain, Size: 2801 bytes --]
On 04/11/2011 04:39 PM, Sascha Hauer wrote:
> This patch adds support for the TI omap4 panda board.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> arch/arm/Makefile | 1 +
> arch/arm/boards/panda/Makefile | 1 +
> arch/arm/boards/panda/board.c | 230 ++++++++++++++++++++++++++++++++++
> arch/arm/boards/panda/config.h | 1 +
> arch/arm/boards/panda/env/config | 45 +++++++
> arch/arm/boards/panda/lowlevel.c | 121 ++++++++++++++++++
> arch/arm/boards/panda/mux.c | 257 ++++++++++++++++++++++++++++++++++++++
> arch/arm/mach-omap/Kconfig | 8 ++
> 8 files changed, 664 insertions(+), 0 deletions(-)
> create mode 100644 arch/arm/boards/panda/Makefile
> create mode 100644 arch/arm/boards/panda/board.c
> create mode 100644 arch/arm/boards/panda/config.h
> create mode 100644 arch/arm/boards/panda/env/config
> create mode 100644 arch/arm/boards/panda/lowlevel.c
> create mode 100644 arch/arm/boards/panda/mux.c
>
[...]
> diff --git a/arch/arm/boards/panda/env/config b/arch/arm/boards/panda/env/config
> new file mode 100644
> index 0000000..5c65d21
> --- /dev/null
> +++ b/arch/arm/boards/panda/env/config
> @@ -0,0 +1,45 @@
> +#!/bin/sh
> +
> +machine=panda
> +user=
> +
> +# use 'dhcp' to do dhcp in barebox and in kernel
> +# use 'none' if you want to skip kernel ip autoconfiguration
> +ip=dhcp
> +
> +# or set your networking parameters here
> +#eth0.ipaddr=a.b.c.d
> +#eth0.netmask=a.b.c.d
> +#eth0.gateway=a.b.c.d
> +#eth0.serverip=a.b.c.d
> +
> +# can be either 'nfs', 'tftp', 'nor' or 'nand'
> +kernel_loc=tftp
> +# can be either 'net', 'nor', 'nand' or 'initrd'
> +rootfs_loc=net
> +
> +# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
> +kernelimage_type=zimage
> +kernelimage=zImage-$machine
> +#kernelimage_type=uimage
> +#kernelimage=uImage-$machine
> +#kernelimage_type=raw
> +#kernelimage=Image-$machine
> +#kernelimage_type=raw_lzo
> +#kernelimage=Image-$machine.lzo
^^^^^^^^^^^^
${machine}.lzo
> +
> +if [ -n $user ]; then
> + kernelimage="$user"-"$kernelimage"
> + nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
> + rootfsimage="$user"-"$rootfsimage"
> +else
> + nfsroot="$eth0.serverip:/path/to/nfs/root"
> +fi
> +
> +autoboot_timeout=3
> +
> +bootargs="console=ttyO2,115200"
> +
> +# set a fancy prompt (if support is compiled in)
> +PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "
> +
Marc
--
Pengutronix e.K. | Marc Kleine-Budde |
Industrial Linux Solutions | Phone: +49-231-2826-924 |
Vertretung West/Dortmund | Fax: +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de |
[-- Attachment #1.2: OpenPGP digital signature --]
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^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 07/12] add panda defconfigs
2011-04-11 14:39 OMAP4 support Sascha Hauer
` (5 preceding siblings ...)
2011-04-11 14:39 ` [PATCH 06/12] ARM omap4: panda board support Sascha Hauer
@ 2011-04-11 14:39 ` Sascha Hauer
2011-04-11 14:39 ` [PATCH 08/12] ARM omap4: Add pcm049 board support Sascha Hauer
` (4 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Sascha Hauer @ 2011-04-11 14:39 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/configs/panda_defconfig | 60 ++++++++++++++++++++++++++++++++
arch/arm/configs/panda_xload_defconfig | 26 ++++++++++++++
2 files changed, 86 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/configs/panda_defconfig
create mode 100644 arch/arm/configs/panda_xload_defconfig
diff --git a/arch/arm/configs/panda_defconfig b/arch/arm/configs/panda_defconfig
new file mode 100644
index 0000000..38cc958
--- /dev/null
+++ b/arch/arm/configs/panda_defconfig
@@ -0,0 +1,60 @@
+CONFIG_ARCH_OMAP=y
+CONFIG_ARCH_OMAP4=y
+CONFIG_AEABI=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_ARM_UNWIND=y
+CONFIG_MMU=y
+CONFIG_TEXT_BASE=0x8f000000
+CONFIG_MALLOC_SIZE=0x2000000
+CONFIG_KALLSYMS=y
+CONFIG_PROMPT="barebox> "
+CONFIG_LONGHELP=y
+CONFIG_GLOB=y
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_HUSH_GETOPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+# CONFIG_TIMESTAMP is not set
+CONFIG_PARTITION=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
+CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/pcm049/env"
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_LOADENV=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_FLASH=y
+# CONFIG_CMD_BOOTM is not set
+CONFIG_CMD_RESET=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_UNLZO=y
+CONFIG_NET=y
+CONFIG_NET_DHCP=y
+CONFIG_NET_NFS=y
+CONFIG_NET_PING=y
+CONFIG_NET_TFTP=y
+CONFIG_NET_TFTP_PUSH=y
+CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
+CONFIG_NET_USB=y
+CONFIG_NET_USB_SMSC95XX=y
+# CONFIG_SPI is not set
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_OMAP_GPMC=y
+CONFIG_UBI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI=y
+CONFIG_MCI=y
+CONFIG_MCI_STARTUP=y
+CONFIG_MCI_OMAP_HSMMC=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_WRITE=y
+CONFIG_FS_FAT_LFN=y
diff --git a/arch/arm/configs/panda_xload_defconfig b/arch/arm/configs/panda_xload_defconfig
new file mode 100644
index 0000000..24452a6
--- /dev/null
+++ b/arch/arm/configs/panda_xload_defconfig
@@ -0,0 +1,26 @@
+CONFIG_ARCH_OMAP=y
+CONFIG_ARCH_OMAP4=y
+# CONFIG_OMAP_GPMC is not set
+CONFIG_OMAP_BUILD_IFT=y
+CONFIG_AEABI=y
+# CONFIG_CMD_ARM_CPUINFO is not set
+CONFIG_TEXT_BASE=0x40300000
+CONFIG_MEMORY_LAYOUT_FIXED=y
+CONFIG_STACK_BASE=0x8f000000
+CONFIG_MALLOC_BASE=0x84000000
+CONFIG_MALLOC_SIZE=0x2000000
+CONFIG_PROMPT="barebox> "
+CONFIG_SHELL_NONE=y
+# CONFIG_ERRNO_MESSAGES is not set
+# CONFIG_TIMESTAMP is not set
+# CONFIG_CONSOLE_FULL is not set
+CONFIG_PARTITION=y
+# CONFIG_DEFAULT_ENVIRONMENT is not set
+# CONFIG_COMMAND_SUPPORT is not set
+CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
+# CONFIG_SPI is not set
+CONFIG_MCI=y
+CONFIG_MCI_STARTUP=y
+CONFIG_MCI_OMAP_HSMMC=y
+CONFIG_FS_FAT=y
--
1.7.2.3
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^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 08/12] ARM omap4: Add pcm049 board support
2011-04-11 14:39 OMAP4 support Sascha Hauer
` (6 preceding siblings ...)
2011-04-11 14:39 ` [PATCH 07/12] add panda defconfigs Sascha Hauer
@ 2011-04-11 14:39 ` Sascha Hauer
2011-04-12 8:16 ` Marc Kleine-Budde
2011-04-11 14:39 ` [PATCH 09/12] ARM: add pcm049 defconfigs Sascha Hauer
` (3 subsequent siblings)
11 siblings, 1 reply; 15+ messages in thread
From: Sascha Hauer @ 2011-04-11 14:39 UTC (permalink / raw)
To: barebox
This patch adds support for Phytecs pcm049 board
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/Makefile | 1 +
arch/arm/boards/pcm049/Makefile | 1 +
arch/arm/boards/pcm049/board.c | 200 +++++++++++++++++++
arch/arm/boards/pcm049/config.h | 1 +
arch/arm/boards/pcm049/env/bin/nand_bootstrap | 31 +++
arch/arm/boards/pcm049/env/config | 53 +++++
arch/arm/boards/pcm049/lowlevel.c | 127 ++++++++++++
arch/arm/boards/pcm049/mux.c | 254 +++++++++++++++++++++++++
arch/arm/mach-omap/Kconfig | 11 +
9 files changed, 679 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/boards/pcm049/Makefile
create mode 100644 arch/arm/boards/pcm049/board.c
create mode 100644 arch/arm/boards/pcm049/config.h
create mode 100644 arch/arm/boards/pcm049/env/bin/nand_bootstrap
create mode 100644 arch/arm/boards/pcm049/env/config
create mode 100644 arch/arm/boards/pcm049/lowlevel.c
create mode 100644 arch/arm/boards/pcm049/mux.c
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 1aaefce..21d6157 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -87,6 +87,7 @@ board-$(CONFIG_MACH_OMAP343xSDP) := omap
board-$(CONFIG_MACH_BEAGLE) := omap
board-$(CONFIG_MACH_OMAP3EVM) := omap
board-$(CONFIG_MACH_PANDA) := panda
+board-$(CONFIG_MACH_PCM049) := pcm049
board-$(CONFIG_MACH_PCA100) := phycard-i.MX27
board-$(CONFIG_MACH_PCM037) := pcm037
board-$(CONFIG_MACH_PCM038) := pcm038
diff --git a/arch/arm/boards/pcm049/Makefile b/arch/arm/boards/pcm049/Makefile
new file mode 100644
index 0000000..1bb7212
--- /dev/null
+++ b/arch/arm/boards/pcm049/Makefile
@@ -0,0 +1 @@
+obj-y += board.o mux.o lowlevel.o
diff --git a/arch/arm/boards/pcm049/board.c b/arch/arm/boards/pcm049/board.c
new file mode 100644
index 0000000..b10ceaf
--- /dev/null
+++ b/arch/arm/boards/pcm049/board.c
@@ -0,0 +1,200 @@
+/*
+ * Copyright (C) 2011 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <console.h>
+#include <init.h>
+#include <driver.h>
+#include <asm/io.h>
+#include <ns16550.h>
+#include <asm/armlinux.h>
+#include <generated/mach-types.h>
+#include <mach/silicon.h>
+#include <mach/sdrc.h>
+#include <mach/sys_info.h>
+#include <mach/syslib.h>
+#include <mach/control.h>
+#include <linux/err.h>
+#include <sizes.h>
+#include <partition.h>
+#include <nand.h>
+#include <asm/mmu.h>
+#include <mach/gpio.h>
+#include <mach/gpmc.h>
+#include <mach/gpmc_nand.h>
+#include <mach/xload.h>
+
+static struct NS16550_plat serial_plat = {
+ .clock = 48000000, /* 48MHz (APLL96/2) */
+ .f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR,
+ .reg_read = omap_uart_read,
+ .reg_write = omap_uart_write,
+};
+
+static struct device_d pcm049_serial_device = {
+ .id = -1,
+ .name = "serial_ns16550",
+ .map_base = OMAP44XX_UART3_BASE,
+ .size = 1024,
+ .platform_data = (void *)&serial_plat,
+};
+
+static u32 bootsrc;
+
+static int pcm049_console_init(void)
+{
+ bootsrc = readl(0x4030d048);
+ /* Register the serial port */
+ return register_device(&pcm049_serial_device);
+}
+console_initcall(pcm049_console_init);
+
+static struct memory_platform_data sram_pdata = {
+ .name = "sram0",
+ .flags = DEVFS_RDWR,
+};
+
+static struct device_d sram_dev = {
+ .id = -1,
+ .name = "mem",
+ .map_base = 0x40300000,
+ .size = 48 * 1024,
+ .platform_data = &sram_pdata,
+};
+
+static struct memory_platform_data sdram_pdata = {
+ .name = "ram0",
+ .flags = DEVFS_RDWR,
+};
+
+static struct device_d sdram_dev = {
+ .id = -1,
+ .name = "mem",
+ .map_base = 0x80000000,
+ .size = SZ_512M,
+ .platform_data = &sdram_pdata,
+};
+
+#ifdef CONFIG_MMU
+static int pcm049_mmu_init(void)
+{
+ mmu_init();
+
+ arm_create_section(0x80000000, 0x80000000, 256, PMD_SECT_DEF_CACHED);
+ /* warning: This shadows the second half of our ram */
+ arm_create_section(0x90000000, 0x80000000, 256, PMD_SECT_DEF_UNCACHED);
+
+ mmu_enable();
+
+ return 0;
+}
+device_initcall(pcm049_mmu_init);
+#endif
+
+static struct device_d hsmmc_dev = {
+ .id = -1,
+ .name = "omap-hsmmc",
+ .map_base = 0x4809C100,
+ .size = SZ_4K,
+};
+
+static struct device_d smc911x_dev = {
+ .id = -1,
+ .name = "smc911x",
+ .map_base = 0x2C000000,
+ .size = 0x4000,
+};
+
+static struct gpmc_config net_cfg = {
+ .cfg = {
+ 0x00001000, /* CONF1 */
+ 0x001e1e01, /* CONF2 */
+ 0x00080300, /* CONF3 */
+ 0x1c091c09, /* CONF4 */
+ 0x04181f1f, /* CONF5 */
+ 0x00000FCF, /* CONF6 */
+ },
+ .base = 0x2C000000,
+ .size = GPMC_SIZE_16M,
+};
+
+static void pcm049_network_init(void)
+{
+ gpmc_cs_config(5, &net_cfg);
+
+ register_device(&smc911x_dev);
+}
+
+static int pcm049_devices_init(void)
+{
+ register_device(&sdram_dev);
+ register_device(&sram_dev);
+ register_device(&hsmmc_dev);
+
+ pcm049_network_init();
+
+ gpmc_generic_nand_devices_init(0, 8, OMAP_ECC_BCH8_CODE_HW);
+
+#ifdef CONFIG_PARTITION
+ devfs_add_partition("nand0", 0x00000, SZ_128K, PARTITION_FIXED, "xload_raw");
+ dev_add_bb_dev("xload_raw", "xload");
+ devfs_add_partition("nand0", SZ_128K, SZ_256K, PARTITION_FIXED, "self_raw");
+ dev_add_bb_dev("self_raw", "self0");
+ devfs_add_partition("nand0", SZ_128K + SZ_256K, SZ_128K, PARTITION_FIXED, "env_raw");
+ dev_add_bb_dev("env_raw", "env0");
+#endif
+
+ armlinux_add_dram(&sdram_dev);
+ armlinux_set_bootparams((void *)0x80000100);
+ armlinux_set_architecture(MACH_TYPE_PCM049);
+
+ return 0;
+}
+device_initcall(pcm049_devices_init);
+
+#ifdef CONFIG_SHELL_NONE
+int run_shell(void)
+{
+ int (*func)(void) = NULL;
+
+ switch (omap4_bootsrc()) {
+ case OMAP_BOOTSRC_MMC1:
+ printf("booting from MMC1\n");
+ func = omap_xload_boot_mmc();
+ break;
+ case OMAP_BOOTSRC_UNKNOWN:
+ printf("unknown boot source. Fall back to nand\n");
+ case OMAP_BOOTSRC_NAND:
+ printf("booting from NAND\n");
+ func = omap_xload_boot_nand(SZ_128K, SZ_256K);
+ break;
+ }
+
+ if (!func) {
+ printf("booting failed\n");
+ while (1);
+ }
+
+ shutdown_barebox();
+ func();
+
+ while (1);
+}
+#endif
diff --git a/arch/arm/boards/pcm049/config.h b/arch/arm/boards/pcm049/config.h
new file mode 100644
index 0000000..da84fa5
--- /dev/null
+++ b/arch/arm/boards/pcm049/config.h
@@ -0,0 +1 @@
+/* nothing */
diff --git a/arch/arm/boards/pcm049/env/bin/nand_bootstrap b/arch/arm/boards/pcm049/env/bin/nand_bootstrap
new file mode 100644
index 0000000..acd00dc
--- /dev/null
+++ b/arch/arm/boards/pcm049/env/bin/nand_bootstrap
@@ -0,0 +1,31 @@
+
+echo "copying barebox to nand..."
+
+mci0.probe=1
+mkdir mnt
+
+mount /dev/disk0.0 fat /mnt
+if [ $? != 0 ]; then
+ echo "failed to mount mmc card"
+ exit 1
+fi
+
+if [ ! -f /mnt/mlo-nand.bin ]; then
+ echo "mlo-nand.bin not found on mmc card"
+ exit 1
+fi
+
+if [ ! -f /mnt/barebox.bin ]; then
+ echo "barebox.bin not found on mmc card"
+fi
+
+gpmc_nand0.eccmode=bch8_hw_romcode
+erase /dev/nand0.xload.bb
+cp /mnt/mlo-nand.bin /dev/nand0.xload.bb
+
+gpmc_nand0.eccmode=bch8_hw
+erase /dev/nand0.barebox.bb
+cp /mnt/barebox.bin /dev/nand0.barebox.bb
+
+echo "success"
+
diff --git a/arch/arm/boards/pcm049/env/config b/arch/arm/boards/pcm049/env/config
new file mode 100644
index 0000000..e9258e1
--- /dev/null
+++ b/arch/arm/boards/pcm049/env/config
@@ -0,0 +1,53 @@
+#!/bin/sh
+
+machine=pcm049
+eth0.serverip=
+user=
+
+# use 'dhcp' to do dhcp in barebox and in kernel
+# use 'none' if you want to skip kernel ip autoconfiguration
+ip=dhcp
+
+# or set your networking parameters here
+#eth0.ipaddr=a.b.c.d
+#eth0.netmask=a.b.c.d
+#eth0.gateway=a.b.c.d
+#eth0.serverip=a.b.c.d
+
+# can be either 'nfs', 'tftp', 'nor' or 'nand'
+kernel_loc=tftp
+# can be either 'net', 'nor', 'nand' or 'initrd'
+rootfs_loc=net
+
+# can be either 'jffs2' or 'ubifs'
+rootfs_type=ubifs
+rootfsimage=root-$machine.$rootfs_type
+
+# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
+kernelimage_type=zimage
+kernelimage=zImage-$machine
+#kernelimage_type=uimage
+#kernelimage=uImage-$machine
+#kernelimage_type=raw
+#kernelimage=Image-$machine
+#kernelimage_type=raw_lzo
+#kernelimage=Image-$machine.lzo
+
+if [ -n $user ]; then
+ kernelimage="$user"-"$kernelimage"
+ nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
+ rootfsimage="$user"-"$rootfsimage"
+else
+ nfsroot="$eth0.serverip:/path/to/nfs/root"
+fi
+
+autoboot_timeout=3
+
+bootargs="console=ttyO2,115200"
+
+nand_parts="128k(xload)ro,256k(barebox),128k(bareboxenv),2M(kernel),-(root)"
+rootfs_mtdblock_nand=4
+
+# set a fancy prompt (if support is compiled in)
+PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "
+
diff --git a/arch/arm/boards/pcm049/lowlevel.c b/arch/arm/boards/pcm049/lowlevel.c
new file mode 100644
index 0000000..e036ba7
--- /dev/null
+++ b/arch/arm/boards/pcm049/lowlevel.c
@@ -0,0 +1,127 @@
+/*
+ * (C) Copyright 2004-2009
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <mach/omap4-mux.h>
+#include <mach/omap4-silicon.h>
+#include <mach/omap4-clock.h>
+#include <mach/syslib.h>
+#include <asm/barebox-arm.h>
+
+void set_muxconf_regs(void);
+
+/* Erstmal 200Mhz... */
+static const struct ddr_regs ddr_regs_mt42L64M64_3_200_mhz = {
+ .tim1 = 0x0aa8d4e3,
+ .tim2 = 0x202e0b92,
+ .tim3 = 0x009da2b3,
+ .phy_ctrl_1 = 0x849FF404, /* mostly from elpida */
+ .ref_ctrl = 0x0000030c, /* from elpida 200MHz! */
+ .config_init = 0x80000eb1,
+ .config_final = 0x80000eb1,
+ .zq_config = 0x500b3215, /* mostly from elpida */
+ .mr1 = 0x23, /* from elpida 200MHz! */
+ .mr2 = 0x1 /* from elpida 200MHz! */
+};
+
+#define I2C_SLAVE 0x12
+
+static int noinline scale_vcores(void)
+{
+ unsigned int rev = omap4_revision();
+
+ /* For VC bypass only VCOREx_CGF_FORCE is necessary and
+ * VCOREx_CFG_VOLTAGE changes can be discarded
+ */
+ writel(0, OMAP44XX_PRM_VC_CFG_I2C_MODE);
+ writel(0x6026, OMAP44XX_PRM_VC_CFG_I2C_CLK);
+
+ /* set VCORE1 force VSEL */
+ omap4_power_i2c_send((0x3A55 << 8) | I2C_SLAVE);
+
+ /* FIXME: set VCORE2 force VSEL, Check the reset value */
+ omap4_power_i2c_send((0x295B << 8) | I2C_SLAVE);
+
+ /* set VCORE3 force VSEL */
+ switch (rev) {
+ case OMAP4430_ES2_0:
+ omap4_power_i2c_send((0x2961 << 8) | I2C_SLAVE);
+ break;
+ case OMAP4430_ES2_1:
+ omap4_power_i2c_send((0x2A61 << 8) | I2C_SLAVE);
+ break;
+ }
+
+ return 0;
+}
+
+static void noinline pcm049_init_lowlevel(void)
+{
+ struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR200;
+ struct dpll_param mpu = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000;
+ struct dpll_param iva = OMAP4_IVA_DPLL_PARAM_19M2;
+ struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2;
+ struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_19M2;
+ struct dpll_param usb = OMAP4_USB_DPLL_PARAM_19M2;
+
+ set_muxconf_regs();
+
+ omap4_ddr_init(&ddr_regs_mt42L64M64_3_200_mhz, &core);
+
+ /* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
+ scale_vcores();
+
+ writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL);
+
+ /* Configure all DPLL's at 100% OPP */
+ omap4_configure_mpu_dpll(&mpu);
+ omap4_configure_iva_dpll(&iva);
+ omap4_configure_per_dpll(&per);
+ omap4_configure_abe_dpll(&abe);
+ omap4_configure_usb_dpll(&usb);
+
+ /* Enable all clocks */
+ omap4_enable_all_clocks();
+
+ sr32(0x4A30a31C, 8, 1, 0x1); /* enable software ioreq */
+ sr32(0x4A30a31C, 1, 2, 0x0); /* set for sys_clk (19.2MHz) */
+ sr32(0x4A30a31C, 16, 4, 0x0); /* set divisor to 1 */
+ sr32(0x4A30a110, 0, 1, 0x1); /* set the clock source to active */
+ sr32(0x4A30a110, 2, 2, 0x3); /* enable clocks */
+
+ board_init_lowlevel_return();
+}
+
+void board_init_lowlevel(void)
+{
+ u32 r;
+
+ if (get_pc() > 0x80000000)
+ return;
+
+ r = 0x4030d000;
+ __asm__ __volatile__("mov sp, %0" : : "r"(r));
+
+ pcm049_init_lowlevel();
+}
+
diff --git a/arch/arm/boards/pcm049/mux.c b/arch/arm/boards/pcm049/mux.c
new file mode 100644
index 0000000..d93d458
--- /dev/null
+++ b/arch/arm/boards/pcm049/mux.c
@@ -0,0 +1,254 @@
+#include <common.h>
+#include <init.h>
+#include <asm/io.h>
+#include <mach/omap4-silicon.h>
+#include <mach/omap4-mux.h>
+
+static const struct pad_conf_entry core_padconf_array[] = {
+ {GPMC_AD0, (IEN | PTD | DIS | M0)}, /* gpmc_ad0 */
+ {GPMC_AD1, (IEN | PTD | DIS | M0)}, /* gpmc_ad1 */
+ {GPMC_AD2, (IEN | PTD | DIS | M0)}, /* gpmc_ad2 */
+ {GPMC_AD3, (IEN | PTD | DIS | M0)}, /* gpmc_ad3 */
+ {GPMC_AD4, (IEN | PTD | DIS | M0)}, /* gpmc_ad4 */
+ {GPMC_AD5, (IEN | PTD | DIS | M0)}, /* gpmc_ad5 */
+ {GPMC_AD6, (IEN | PTD | DIS | M0)}, /* gpmc_ad6 */
+ {GPMC_AD7, (IEN | PTD | DIS | M0)}, /* gpmc_ad7 */
+ {GPMC_AD8, (IEN | PTD | DIS | M0)}, /* gpmc_ad8 */
+ {GPMC_AD9, (IEN | PTD | DIS | M0)}, /* gpmc_ad9 */
+ {GPMC_AD10, (IEN | PTD | DIS | M0)}, /* gpmc_ad10 */
+ {GPMC_AD11, (IEN | PTD | DIS | M0)}, /* gpmc_ad11 */
+ {GPMC_AD12, (IEN | PTD | DIS | M0)}, /* gpmc_ad12 */
+ {GPMC_AD13, (IEN | PTD | DIS | M0)}, /* gpmc_ad13 */
+ {GPMC_AD14, (IEN | PTD | DIS | M0)}, /* gpmc_ad14 */
+ {GPMC_AD15, (IEN | PTD | DIS | M0)}, /* gpmc_ad15 */
+ {GPMC_A16, (IEN | PTD | DIS | M0)}, /* gpmc_a16 */
+ {GPMC_A17, (IEN | PTD | DIS | M0)}, /* gpmc_a17 */
+ {GPMC_A18, (IEN | PTD | DIS | M0)}, /* gpmc_a18 */
+ {GPMC_A19, (IEN | PTD | DIS | M0)}, /* gpmc_a19 */
+ {GPMC_A20, (IEN | PTD | DIS | M0)}, /* gpmc_a20 */
+ {GPMC_A21, (IEN | PTD | DIS | M0)}, /* gpmc_a21 */
+ {GPMC_A22, (IEN | PTD | DIS | M0)}, /* gpmc_a22 */
+ {GPMC_A23, (IEN | PTD | DIS | M0)}, /* gpmc_a23 */
+ {GPMC_A24, (IEN | PTD | DIS | M0)}, /* gpmc_a24 */
+ {GPMC_A25, (IEN | PTD | DIS | M0)}, /* gpmc_a25 */
+ {GPMC_NCS0, (IDIS | PTU | EN | M0)}, /* gpmc_nsc0 */
+ {GPMC_NCS1, (IDIS | PTU | EN | M0)}, /* gpmc_nsc1 */
+ {GPMC_NCS2, (SAFE_MODE)}, /* nc */
+ {GPMC_NCS3, (SAFE_MODE)}, /* nc */
+ {GPMC_NWP, (IEN | PTD | DIS | M0)}, /* gpmc_nwp */
+ {GPMC_CLK, (SAFE_MODE)}, /* nc */
+ {GPMC_NADV_ALE, (IDIS | PTD | DIS | M0)}, /* gpmc_ndav_ale */
+ {GPMC_NOE, (IDIS | PTD | DIS | M0)}, /* gpmc_noe */
+ {GPMC_NWE, (IDIS | PTD | DIS | M0)}, /* gpmc_nwe */
+ {GPMC_NBE0_CLE, (IDIS | PTD | DIS | M0)}, /* gpmc_nbe0_cle */
+ {GPMC_NBE1, (SAFE_MODE)}, /* nc */
+ {GPMC_WAIT0, (IEN | PTU | EN | M0)}, /* gpmc_wait0 */
+ {GPMC_WAIT1, (SAFE_MODE)}, /* nc */
+ {C2C_DATA11, (SAFE_MODE)}, /* nc */
+ {C2C_DATA12, (SAFE_MODE)}, /* nc */
+ {C2C_DATA13, (IDIS | PTU | EN | M0)}, /* gpmc_nsc5 */
+ {C2C_DATA14, (SAFE_MODE)}, /* nc */
+ {C2C_DATA15, (SAFE_MODE)}, /* nc */
+ {HDMI_HPD, (M0)}, /* hdmi_hpd */
+ {HDMI_CEC, (DIS | IEN | M3)}, /* gpio_64 */
+ {HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */
+ {HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */
+ {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */
+ {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */
+ {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */
+ {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */
+ {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */
+ {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */
+ {CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */
+ {CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */
+ {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */
+ {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */
+ {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */
+ {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */
+ {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */
+ {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */
+ {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */
+ {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */
+ {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */
+ {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
+ {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */
+ {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */
+ {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */
+ {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */
+ {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */
+ {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */
+ {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */
+ {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */
+ {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */
+ {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */
+ {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */
+ {USBB1_HSIC_DATA, (DIS | IEN | M3)}, /* gpio_96 */
+ {USBB1_HSIC_STROBE, (DIS | IEN | M3)}, /* gpio_97 */
+ {USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */
+ {USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */
+ {SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */
+ {SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
+ {SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
+ {SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
+ {SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
+ {SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
+ {SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
+ {SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
+ {SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
+ {SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
+ {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */
+ {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */
+ {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */
+ {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */
+ {ABE_MCBSP1_CLKX, (DIS | IEN | M3)}, /* gpio_114 */
+ {ABE_MCBSP1_DR, (DIS | IEN | M3)}, /* gpio_115 */
+ {ABE_MCBSP1_DX, (DIS | IEN | M3)}, /* gpio_116 */
+ {ABE_MCBSP1_FSX, (DIS | IEN | M2)}, /* abe_mcasp_amutein */
+ {ABE_PDM_UL_DATA, (IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* abe_mcbsp3_dr */
+ {ABE_PDM_DL_DATA, (OFF_EN | OFF_OUT_PTD | M1)}, /* abe_mcbsp3_dx */
+ {ABE_PDM_FRAME, (IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* abe_mcbsp3_clkx */
+ {ABE_PDM_LB_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* abe_mcbsp3_fsx */
+ {ABE_CLKS, (DIS | IEN | M3)}, /* gpio_118 */
+ {ABE_DMIC_CLK1, (SAFE_MODE)}, /* nc */
+ {ABE_DMIC_DIN1, (SAFE_MODE)}, /* nc */
+ {ABE_DMIC_DIN2, (SAFE_MODE)}, /* nc */
+ {ABE_DMIC_DIN3, (SAFE_MODE)}, /* nc */
+ {UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */
+ {UART2_RTS, (M0)}, /* uart2_rts */
+ {UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */
+ {UART2_TX, (M0)}, /* uart2_tx */
+ {HDQ_SIO, (M0)}, /* hdq_sio */
+ {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */
+ {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */
+ {I2C2_SCL, (PTU | IEN | M1)}, /* uart1_rx */
+ {I2C2_SDA, (M1)}, /* uart1_tx */
+ {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */
+ {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */
+ {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */
+ {I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */
+ {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */
+ {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */
+ {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */
+ {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */
+ {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs1 */
+ {MCSPI1_CS2, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs2 */
+ {MCSPI1_CS3, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs3 */
+ {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */
+ {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */
+ {UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */
+ {UART3_TX_IRTX, (M0)}, /* uart3_tx */
+ {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */
+ {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */
+ {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */
+ {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */
+ {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */
+ {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */
+ {MCSPI4_CLK, (SAFE_MODE)}, /* nc */
+ {MCSPI4_SIMO, (PTU | IEN | M3)}, /* gpio_152 */
+ {MCSPI4_SOMI, (PTU | IEN | M3)}, /* gpio_153 */
+ {MCSPI4_CS0, (SAFE_MODE)}, /* nc */
+ {UART4_RX, (IEN | M0)}, /* uart4_rx */
+ {UART4_TX, (M0)}, /* uart4_tx */
+ {USBB2_ULPITLL_CLK, (IEN | M3)}, /* gpio_157 */
+ {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */
+ {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */
+ {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */
+ {USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */
+ {USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */
+ {USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */
+ {USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */
+ {USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */
+ {USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */
+ {USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */
+ {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */
+ {USBB2_HSIC_DATA, (SAFE_MODE)}, /* nc */
+ {USBB2_HSIC_STROBE, (SAFE_MODE)}, /* nc */
+ {UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col0 */
+ {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */
+ {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */
+ {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */
+ {UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col4 */
+ {UNIPRO_TY2, (SAFE_MODE)}, /* nc */
+ {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */
+ {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */
+ {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */
+ {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */
+ {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */
+ {UNIPRO_RY2, (DIS | IEN | M3)}, /* gpio_3 */
+ {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */
+ {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */
+ {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */
+ {FREF_CLK1_OUT, (SAFE_MODE)}, /* nc */
+ {FREF_CLK2_OUT, (SAFE_MODE)}, /* nc */
+ {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */
+ {SYS_NIRQ2, (DIS | IEN | M3)}, /* gpio_183 */
+ {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */
+ {SYS_BOOT1, (M3)}, /* gpio_185 */
+ {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */
+ {SYS_BOOT3, (M3)}, /* gpio_187 */
+ {SYS_BOOT4, (M3)}, /* gpio_188 */
+ {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */
+ {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */
+ {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */
+ {DPM_EMU2, (SAFE_MODE)}, /* nc */
+ {DPM_EMU3, (SAFE_MODE)}, /* nc */
+ {DPM_EMU4, (SAFE_MODE)}, /* nc */
+ {DPM_EMU5, (SAFE_MODE)}, /* nc */
+ {DPM_EMU6, (SAFE_MODE)}, /* nc */
+ {DPM_EMU7, (SAFE_MODE)}, /* nc */
+ {DPM_EMU8, (SAFE_MODE)}, /* nc */
+ {DPM_EMU9, (SAFE_MODE)}, /* nc */
+ {DPM_EMU10, (SAFE_MODE)}, /* nc */
+ {DPM_EMU11, (SAFE_MODE)}, /* nc */
+ {DPM_EMU12, (SAFE_MODE)}, /* nc */
+ {DPM_EMU13, (SAFE_MODE)}, /* nc */
+ {DPM_EMU14, (SAFE_MODE)}, /* nc */
+ {DPM_EMU15, (DIS | M3)}, /* gpio_26 */
+ {DPM_EMU16, (M1)}, /* dmtimer8_pwm_evt */
+ {DPM_EMU17, (M1)}, /* dmtimer9_pwm_evt */
+ {DPM_EMU18, (IEN | M3)}, /* gpio_190 */
+ {DPM_EMU19, (IEN | M3)}, /* gpio_191 */
+};
+
+static const struct pad_conf_entry wkup_padconf_array[] = {
+ {PAD0_SIM_IO, (IEN | M3)}, /* gpio_wk0 */
+ {PAD1_SIM_CLK, (IEN | M3)}, /* gpio_wk1 */
+ {PAD0_SIM_RESET, (IEN | M3)}, /* gpio_wk2 */
+ {PAD1_SIM_CD, (SAFE_MODE)}, /* should be gpio_wk3 but muxed with gpio_3*/
+ {PAD0_SIM_PWRCTRL, (IEN | M3)}, /* gpio_wk4 */
+ {PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
+ {PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
+ {PAD1_FREF_XTAL_IN, (M0)}, /* # */
+ {PAD0_FREF_SLICER_IN, (SAFE_MODE)}, /* nc */
+ {PAD1_FREF_CLK_IOREQ, (SAFE_MODE)}, /* nc */
+ {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */
+ {PAD1_FREF_CLK3_REQ, (SAFE_MODE)}, /* nc */
+ {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */
+ {PAD1_FREF_CLK4_REQ, (M0)}, /* fref_clk4_req */
+ {PAD0_FREF_CLK4_OUT, (M0)}, /* fref_clk4_out */
+ {PAD1_SYS_32K, (IEN | M0)}, /* sys_32k */
+ {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */
+ {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */
+ {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */
+ {PAD1_SYS_PWRON_RESET, (M0)}, /* sys_pwron_reset_out */
+ {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */
+ {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */
+};
+
+static void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
+{
+ int i;
+ struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
+
+ for (i = 0; i < size; i++, pad++)
+ writew(pad->val, base + pad->offset);
+}
+
+void set_muxconf_regs(void)
+{
+ do_set_mux(OMAP44XX_CONTROL_PADCONF_CORE, core_padconf_array,
+ ARRAY_SIZE(core_padconf_array));
+
+ do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP, wkup_padconf_array,
+ ARRAY_SIZE(wkup_padconf_array));
+}
diff --git a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig
index 13a3df8..13966cf 100644
--- a/arch/arm/mach-omap/Kconfig
+++ b/arch/arm/mach-omap/Kconfig
@@ -105,6 +105,7 @@ config BOARDINFO
default "Texas Instrument's Beagle" if MACH_BEAGLE
default "Texas Instrument's OMAP3EVM" if MACH_OMAP3EVM
default "Texas Instrument's Panda" if MACH_PANDA
+ default "Phytec phyCORE pcm049" if MACH_PCM049
choice
prompt "Select OMAP board"
@@ -144,6 +145,16 @@ config MACH_PANDA
help
Say Y here if you are using OMAP4 Panda board
+config MACH_PCM049
+ bool "Phytec phyCORE pcm049"
+ select HAVE_MMU
+ select HAVE_NOSHELL
+ depends on ARCH_OMAP4
+ select MACH_HAS_LOWLEVEL_INIT
+ help
+ Say Y here if you are using Phytecs phyCORE pcm049 board
+ based on OMAP4
+
endchoice
if MACH_OMAP3EVM
--
1.7.2.3
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^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH 08/12] ARM omap4: Add pcm049 board support
2011-04-11 14:39 ` [PATCH 08/12] ARM omap4: Add pcm049 board support Sascha Hauer
@ 2011-04-12 8:16 ` Marc Kleine-Budde
0 siblings, 0 replies; 15+ messages in thread
From: Marc Kleine-Budde @ 2011-04-12 8:16 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
[-- Attachment #1.1: Type: text/plain, Size: 3209 bytes --]
On 04/11/2011 04:39 PM, Sascha Hauer wrote:
> This patch adds support for Phytecs pcm049 board
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> arch/arm/Makefile | 1 +
> arch/arm/boards/pcm049/Makefile | 1 +
> arch/arm/boards/pcm049/board.c | 200 +++++++++++++++++++
> arch/arm/boards/pcm049/config.h | 1 +
> arch/arm/boards/pcm049/env/bin/nand_bootstrap | 31 +++
> arch/arm/boards/pcm049/env/config | 53 +++++
> arch/arm/boards/pcm049/lowlevel.c | 127 ++++++++++++
> arch/arm/boards/pcm049/mux.c | 254 +++++++++++++++++++++++++
> arch/arm/mach-omap/Kconfig | 11 +
> 9 files changed, 679 insertions(+), 0 deletions(-)
> create mode 100644 arch/arm/boards/pcm049/Makefile
> create mode 100644 arch/arm/boards/pcm049/board.c
> create mode 100644 arch/arm/boards/pcm049/config.h
> create mode 100644 arch/arm/boards/pcm049/env/bin/nand_bootstrap
> create mode 100644 arch/arm/boards/pcm049/env/config
> create mode 100644 arch/arm/boards/pcm049/lowlevel.c
> create mode 100644 arch/arm/boards/pcm049/mux.c
>
[...]
> new file mode 100644
> index 0000000..e9258e1
> --- /dev/null
> +++ b/arch/arm/boards/pcm049/env/config
> @@ -0,0 +1,53 @@
> +#!/bin/sh
> +
> +machine=pcm049
> +eth0.serverip=
> +user=
> +
> +# use 'dhcp' to do dhcp in barebox and in kernel
> +# use 'none' if you want to skip kernel ip autoconfiguration
> +ip=dhcp
> +
> +# or set your networking parameters here
> +#eth0.ipaddr=a.b.c.d
> +#eth0.netmask=a.b.c.d
> +#eth0.gateway=a.b.c.d
> +#eth0.serverip=a.b.c.d
> +
> +# can be either 'nfs', 'tftp', 'nor' or 'nand'
> +kernel_loc=tftp
> +# can be either 'net', 'nor', 'nand' or 'initrd'
> +rootfs_loc=net
> +
> +# can be either 'jffs2' or 'ubifs'
> +rootfs_type=ubifs
> +rootfsimage=root-$machine.$rootfs_type
^^^^^^^^^^^^^^^^^^^^^
you need to quote here:
${machine}.$rootfs_type
> +
> +# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
> +kernelimage_type=zimage
> +kernelimage=zImage-$machine
> +#kernelimage_type=uimage
> +#kernelimage=uImage-$machine
> +#kernelimage_type=raw
> +#kernelimage=Image-$machine
> +#kernelimage_type=raw_lzo
> +#kernelimage=Image-$machine.lzo
dito
> +
> +if [ -n $user ]; then
> + kernelimage="$user"-"$kernelimage"
> + nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
> + rootfsimage="$user"-"$rootfsimage"
> +else
> + nfsroot="$eth0.serverip:/path/to/nfs/root"
> +fi
> +
> +autoboot_timeout=3
> +
> +bootargs="console=ttyO2,115200"
> +
> +nand_parts="128k(xload)ro,256k(barebox),128k(bareboxenv),2M(kernel),-(root)"
> +rootfs_mtdblock_nand=4
> +
> +# set a fancy prompt (if support is compiled in)
> +PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "
> +
Marc
--
Pengutronix e.K. | Marc Kleine-Budde |
Industrial Linux Solutions | Phone: +49-231-2826-924 |
Vertretung West/Dortmund | Fax: +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de |
[-- Attachment #1.2: OpenPGP digital signature --]
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[-- Attachment #2: Type: text/plain, Size: 149 bytes --]
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^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 09/12] ARM: add pcm049 defconfigs
2011-04-11 14:39 OMAP4 support Sascha Hauer
` (7 preceding siblings ...)
2011-04-11 14:39 ` [PATCH 08/12] ARM omap4: Add pcm049 board support Sascha Hauer
@ 2011-04-11 14:39 ` Sascha Hauer
2011-04-11 14:39 ` [PATCH 10/12] ARM omap beagle: Add noshell support for booting from MMC Sascha Hauer
` (2 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Sascha Hauer @ 2011-04-11 14:39 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/configs/pcm049_defconfig | 57 +++++++++++++++++++++++++++++++
arch/arm/configs/pcm049_xload_defconfig | 40 +++++++++++++++++++++
2 files changed, 97 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/configs/pcm049_defconfig
create mode 100644 arch/arm/configs/pcm049_xload_defconfig
diff --git a/arch/arm/configs/pcm049_defconfig b/arch/arm/configs/pcm049_defconfig
new file mode 100644
index 0000000..ed20f1b
--- /dev/null
+++ b/arch/arm/configs/pcm049_defconfig
@@ -0,0 +1,57 @@
+CONFIG_ARCH_OMAP=y
+CONFIG_ARCH_OMAP4=y
+CONFIG_MACH_PCM049=y
+CONFIG_AEABI=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_ARM_UNWIND=y
+CONFIG_MMU=y
+CONFIG_TEXT_BASE=0x8f000000
+CONFIG_MALLOC_SIZE=0x2000000
+CONFIG_KALLSYMS=y
+CONFIG_PROMPT="barebox> "
+CONFIG_LONGHELP=y
+CONFIG_GLOB=y
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_HUSH_GETOPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+# CONFIG_TIMESTAMP is not set
+CONFIG_PARTITION=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
+CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/pcm049/env"
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_LOADENV=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_FLASH=y
+# CONFIG_CMD_BOOTM is not set
+CONFIG_CMD_RESET=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_UNLZO=y
+CONFIG_NET=y
+CONFIG_NET_DHCP=y
+CONFIG_NET_NFS=y
+CONFIG_NET_PING=y
+CONFIG_NET_TFTP=y
+CONFIG_NET_TFTP_PUSH=y
+CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
+CONFIG_DRIVER_NET_SMC911X=y
+# CONFIG_SPI is not set
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_OMAP_GPMC=y
+CONFIG_UBI=y
+CONFIG_MCI=y
+CONFIG_MCI_OMAP_HSMMC=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_WRITE=y
+CONFIG_FS_FAT_LFN=y
diff --git a/arch/arm/configs/pcm049_xload_defconfig b/arch/arm/configs/pcm049_xload_defconfig
new file mode 100644
index 0000000..7303c9a
--- /dev/null
+++ b/arch/arm/configs/pcm049_xload_defconfig
@@ -0,0 +1,40 @@
+CONFIG_ARCH_OMAP=y
+CONFIG_ARCH_OMAP4=y
+CONFIG_OMAP_BUILD_IFT=y
+CONFIG_MACH_PCM049=y
+CONFIG_AEABI=y
+# CONFIG_CMD_ARM_CPUINFO is not set
+# CONFIG_ARM_EXCEPTIONS is not set
+CONFIG_MMU=y
+CONFIG_TEXT_BASE=0x40300000
+CONFIG_MEMORY_LAYOUT_FIXED=y
+CONFIG_STACK_BASE=0x8f000000
+CONFIG_MALLOC_BASE=0x84000000
+CONFIG_MALLOC_SIZE=0x2000000
+CONFIG_MALLOC_DUMMY=y
+CONFIG_PROMPT="barebox> "
+CONFIG_SHELL_NONE=y
+# CONFIG_ERRNO_MESSAGES is not set
+# CONFIG_TIMESTAMP is not set
+# CONFIG_CONSOLE_FULL is not set
+# CONFIG_DEFAULT_ENVIRONMENT is not set
+CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
+# CONFIG_SPI is not set
+CONFIG_MTD=y
+CONFIG_NAND=y
+# CONFIG_NAND_WRITE is not set
+# CONFIG_NAND_ECC_SOFT is not set
+# CONFIG_NAND_ECC_HW_SYNDROME is not set
+# CONFIG_NAND_ECC_HW_NONE is not set
+# CONFIG_NAND_INFO is not set
+# CONFIG_NAND_BBT is not set
+# CONFIG_NAND_READ_OOB is not set
+CONFIG_NAND_OMAP_GPMC=y
+CONFIG_MCI=y
+CONFIG_MCI_STARTUP=y
+# CONFIG_MCI_WRITE is not set
+CONFIG_MCI_OMAP_HSMMC=y
+# CONFIG_FS_RAMFS is not set
+# CONFIG_FS_DEVFS is not set
+CONFIG_FS_FAT=y
--
1.7.2.3
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^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 10/12] ARM omap beagle: Add noshell support for booting from MMC
2011-04-11 14:39 OMAP4 support Sascha Hauer
` (8 preceding siblings ...)
2011-04-11 14:39 ` [PATCH 09/12] ARM: add pcm049 defconfigs Sascha Hauer
@ 2011-04-11 14:39 ` Sascha Hauer
2011-04-11 14:39 ` [PATCH 11/12] ARM omap beagle: update defconfig Sascha Hauer
2011-04-11 14:39 ` [PATCH 12/12] ARM beagle board: add xload defconfig Sascha Hauer
11 siblings, 0 replies; 15+ messages in thread
From: Sascha Hauer @ 2011-04-11 14:39 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/omap/board-beagle.c | 42 +++++++++++++++++++++++++++++++++++
arch/arm/mach-omap/Kconfig | 1 +
2 files changed, 43 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boards/omap/board-beagle.c b/arch/arm/boards/omap/board-beagle.c
index 17a349c..ced3df7 100644
--- a/arch/arm/boards/omap/board-beagle.c
+++ b/arch/arm/boards/omap/board-beagle.c
@@ -56,6 +56,7 @@
#include <console.h>
#include <init.h>
#include <driver.h>
+#include <sizes.h>
#include <asm/io.h>
#include <ns16550.h>
#include <asm/armlinux.h>
@@ -72,6 +73,7 @@
#include <i2c/i2c.h>
#include <linux/err.h>
#include <usb/ehci.h>
+#include <mach/xload.h>
#include "board.h"
/******************** Board Boot Time *******************/
@@ -313,6 +315,13 @@ static struct i2c_board_info i2c_devices[] = {
},
};
+static struct device_d hsmmc_dev = {
+ .id = -1,
+ .name = "omap-hsmmc",
+ .map_base = 0x4809C000,
+ .size = SZ_4K,
+};
+
static int beagle_devices_init(void)
{
int ret;
@@ -334,6 +343,8 @@ static int beagle_devices_init(void)
#endif
gpmc_generic_nand_devices_init(0, 16, OMAP_ECC_HAMMING_CODE_HW_ROMCODE);
+ register_device(&hsmmc_dev);
+
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_OMAP3_BEAGLE);
@@ -341,3 +352,34 @@ failed:
return ret;
}
device_initcall(beagle_devices_init);
+
+#ifdef CONFIG_SHELL_NONE
+
+int run_shell(void)
+{
+ int (*func)(void) = NULL;
+
+ switch (omap3_bootsrc()) {
+ case OMAP_BOOTSRC_MMC1:
+ printf("booting from MMC1\n");
+ func = omap_xload_boot_mmc();
+ break;
+ case OMAP_BOOTSRC_UNKNOWN:
+ printf("unknown boot source. Fall back to nand\n");
+ case OMAP_BOOTSRC_NAND:
+ printf("booting from NAND\n");
+ func = omap_xload_boot_nand(SZ_128K, SZ_256K);
+ break;
+ }
+
+ if (!func) {
+ printf("booting failed\n");
+ while (1);
+ }
+
+ shutdown_barebox();
+ func();
+
+ while (1);
+}
+#endif
diff --git a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig
index 13966cf..f256310 100644
--- a/arch/arm/mach-omap/Kconfig
+++ b/arch/arm/mach-omap/Kconfig
@@ -123,6 +123,7 @@ config MACH_BEAGLE
bool "Texas Instrument's Beagle Board"
select MACH_HAS_LOWLEVEL_INIT
select OMAP_CLOCK_ALL
+ select HAVE_NOSHELL
select HAS_OMAP_NAND
depends on ARCH_OMAP3
help
--
1.7.2.3
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^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 11/12] ARM omap beagle: update defconfig
2011-04-11 14:39 OMAP4 support Sascha Hauer
` (9 preceding siblings ...)
2011-04-11 14:39 ` [PATCH 10/12] ARM omap beagle: Add noshell support for booting from MMC Sascha Hauer
@ 2011-04-11 14:39 ` Sascha Hauer
2011-04-11 14:39 ` [PATCH 12/12] ARM beagle board: add xload defconfig Sascha Hauer
11 siblings, 0 replies; 15+ messages in thread
From: Sascha Hauer @ 2011-04-11 14:39 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/configs/omap3530_beagle_defconfig | 15 +++++++++++++--
1 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/arm/configs/omap3530_beagle_defconfig b/arch/arm/configs/omap3530_beagle_defconfig
index d4b8737..8a12154 100644
--- a/arch/arm/configs/omap3530_beagle_defconfig
+++ b/arch/arm/configs/omap3530_beagle_defconfig
@@ -2,16 +2,19 @@ CONFIG_ARCH_OMAP=y
# CONFIG_OMAP3_COPY_CLOCK_SRAM is not set
CONFIG_MACH_BEAGLE=y
CONFIG_AEABI=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_ARM_UNWIND=y
CONFIG_TEXT_BASE=0x81000000
CONFIG_PROMPT="barebox> "
CONFIG_LONGHELP=y
CONFIG_GLOB=y
CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_HUSH_GETOPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
# CONFIG_TIMESTAMP is not set
CONFIG_PARTITION=y
-# CONFIG_DEFAULT_ENVIRONMENT is not set
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_SAVEENV=y
@@ -27,6 +30,7 @@ CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_UNLZO=y
CONFIG_CMD_I2C=y
CONFIG_NET=y
@@ -34,14 +38,15 @@ CONFIG_NET_DHCP=y
CONFIG_NET_NFS=y
CONFIG_NET_PING=y
CONFIG_NET_TFTP=y
+CONFIG_NET_TFTP_PUSH=y
CONFIG_DRIVER_SERIAL_NS16550=y
CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
CONFIG_NET_USB=y
CONFIG_NET_USB_ASIX=y
+CONFIG_NET_USB_SMSC95XX=y
# CONFIG_SPI is not set
CONFIG_I2C=y
CONFIG_I2C_OMAP=y
-CONFIG_I2C_TWL4030=y
CONFIG_MTD=y
CONFIG_NAND=y
CONFIG_NAND_OMAP_GPMC=y
@@ -49,3 +54,9 @@ CONFIG_USB=y
CONFIG_USB_EHCI=y
CONFIG_USB_EHCI_OMAP=y
CONFIG_USB_TWL4030=y
+CONFIG_MCI=y
+CONFIG_MCI_OMAP_HSMMC=y
+CONFIG_I2C_TWL4030=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_WRITE=y
+CONFIG_FS_FAT_LFN=y
--
1.7.2.3
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^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 12/12] ARM beagle board: add xload defconfig
2011-04-11 14:39 OMAP4 support Sascha Hauer
` (10 preceding siblings ...)
2011-04-11 14:39 ` [PATCH 11/12] ARM omap beagle: update defconfig Sascha Hauer
@ 2011-04-11 14:39 ` Sascha Hauer
11 siblings, 0 replies; 15+ messages in thread
From: Sascha Hauer @ 2011-04-11 14:39 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/configs/omap3530_beagle_xload_defconfig | 38 ++++++++++++++++++++++
1 files changed, 38 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/configs/omap3530_beagle_xload_defconfig
diff --git a/arch/arm/configs/omap3530_beagle_xload_defconfig b/arch/arm/configs/omap3530_beagle_xload_defconfig
new file mode 100644
index 0000000..58a2309
--- /dev/null
+++ b/arch/arm/configs/omap3530_beagle_xload_defconfig
@@ -0,0 +1,38 @@
+CONFIG_ARCH_OMAP=y
+# CONFIG_OMAP3_COPY_CLOCK_SRAM is not set
+CONFIG_OMAP_BUILD_IFT=y
+CONFIG_MACH_BEAGLE=y
+CONFIG_AEABI=y
+# CONFIG_CMD_ARM_CPUINFO is not set
+# CONFIG_ARM_EXCEPTIONS is not set
+CONFIG_TEXT_BASE=0x40200000
+CONFIG_MEMORY_LAYOUT_FIXED=y
+CONFIG_STACK_BASE=0x87BF7F10
+CONFIG_MALLOC_BASE=0x87BFFF10
+CONFIG_MALLOC_DUMMY=y
+CONFIG_PROMPT="X-load Beagle>"
+CONFIG_SHELL_NONE=y
+# CONFIG_ERRNO_MESSAGES is not set
+# CONFIG_TIMESTAMP is not set
+# CONFIG_CONSOLE_FULL is not set
+# CONFIG_DEFAULT_ENVIRONMENT is not set
+CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
+# CONFIG_SPI is not set
+CONFIG_MTD=y
+CONFIG_NAND=y
+# CONFIG_NAND_WRITE is not set
+# CONFIG_NAND_ECC_SOFT is not set
+# CONFIG_NAND_ECC_HW_SYNDROME is not set
+# CONFIG_NAND_ECC_HW_NONE is not set
+# CONFIG_NAND_INFO is not set
+# CONFIG_NAND_BBT is not set
+# CONFIG_NAND_READ_OOB is not set
+CONFIG_NAND_OMAP_GPMC=y
+CONFIG_MCI=y
+CONFIG_MCI_STARTUP=y
+# CONFIG_MCI_WRITE is not set
+CONFIG_MCI_OMAP_HSMMC=y
+# CONFIG_FS_RAMFS is not set
+# CONFIG_FS_DEVFS is not set
+CONFIG_FS_FAT=y
--
1.7.2.3
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^ permalink raw reply [flat|nested] 15+ messages in thread