From 1d425e7d90bbd7ed7bdeb0daa44a19dd8a9840c1 Mon Sep 17 00:00:00 2001 From: Christian Kapeller Date: Sun, 18 Mar 2012 11:12:43 +0100 Subject: [PATCH 1/2] Update mx51 pad definitions Signed-off-by: Christian Kapeller --- arch/arm/mach-imx/include/mach/iomux-mx51.h | 44 +++++++++++++++++++++++--- 1 files changed, 39 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-imx/include/mach/iomux-mx51.h b/arch/arm/mach-imx/include/mach/iomux-mx51.h index 908d1b2..42e26ca 100644 --- a/arch/arm/mach-imx/include/mach/iomux-mx51.h +++ b/arch/arm/mach-imx/include/mach/iomux-mx51.h @@ -86,29 +86,37 @@ #define MX51_PAD_EIM_EB2__EIM_EB2 IOMUX_PAD(0x468, 0xD4, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_EB2__FEC_MDIO IOMUX_PAD(0x468, 0x0d4, 3, 0x954, 0, MX51_FEC_PAD_CTRL) +#define MX51_PAD_EIM_EB2__GPIO2_22 IOMUX_PAD(0x468, 0x0d4, 1, 0x954, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_EB3__EIM_EB3 IOMUX_PAD(0x46C, 0xD8, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_EB3__FEC_RDATA1 IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, MX51_FEC_PAD_CTRL) +#define MX51_PAD_EIM_EB3__GPIO2_23 IOMUX_PAD(0x46c, 0x0d8, 1, 0x95c, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_OE__EIM_OE IOMUX_PAD(0x470, 0xDC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_OE__GPIO2_24 IOMUX_PAD(0x470, 0xDC, 1, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_CS0__EIM_CS0 IOMUX_PAD(0x474, 0xE0, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_CS1__EIM_CS1 IOMUX_PAD(0x478, 0xE4, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_CS2__EIM_CS2 IOMUX_PAD(0x47C, 0xE8, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_CS2__FEC_RDATA2 IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, MX51_FEC_PAD_CTRL) +#define MX51_PAD_EIM_CS2__GPIO2_27 IOMUX_PAD(0x47c, 0x0e8, 1, 0x960, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_CS3__EIM_CS3 IOMUX_PAD(0x480, 0xEC, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_CS3__FEC_RDATA3 IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, MX51_FEC_PAD_CTRL) +#define MX51_PAD_EIM_CS3__GPIO2_28 IOMUX_PAD(0x480, 0x0ec, 1, 0x964, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_CS4__EIM_CS4 IOMUX_PAD(0x484, 0xF0, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_CS4__FEC_RX_ER IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_FEC_PAD_CTRL) +#define MX51_PAD_EIM_CS4__GPIO2_29 IOMUX_PAD(0x484, 0x0f0, 1, 0x970, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_CS5__EIM_CS5 IOMUX_PAD(0x488, 0xF4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS5__GPIO2_30 IOMUX_PAD(0x488, 0xF4, 1, 0x950, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_CS5__FEC_CRS IOMUX_PAD(0x52C, 0xF4, 3, 0x950, 0, MX51_FEC_PAD_CTRL) #define MX51_PAD_EIM_DTACK__EIM_DTACK IOMUX_PAD(0x48C, 0xF8, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_DTACK__GPIO2_31 IOMUX_PAD(0x48c, 0xf8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_LBA__EIM_LBA IOMUX_PAD(0x494, 0xFC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_LBA__EIM_LBA IOMUX_PAD(0x494, 0xFC, 0, 0x978, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_LBA__GPIO3_1 IOMUX_PAD(0x494, 0xFC, 1, 0x0978, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_CRE__EIM_CRE IOMUX_PAD(0x4A0, 0x100, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_WE_B__NANDF_WE_B IOMUX_PAD(0x4E4, 0x108, 0, 0x0, 0, NO_PAD_CTRL) @@ -121,9 +129,11 @@ #define MX51_PAD_NANDF_RB2__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_FEC_PAD_CTRL) +#define MX51_PAD_NANDF_RB2__GPIO3_10 IOMUX_PAD(0x500, 0x124, 3, 0x94c, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB3__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB3__FEC_RX_CLK IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_FEC_PAD_CTRL) +#define MX51_PAD_NANDF_RB3__GPIO3_11 IOMUX_PAD(0x504, 0x128, 3, 0x968, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB4__NANDF_RB4 IOMUX_PAD(0x514, 0x12C, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB5__NANDF_RB5 IOMUX_PAD(0x5D8, 0x130, 0, 0x0, 0, NO_PAD_CTRL) @@ -135,24 +145,33 @@ #define MX51_PAD_NANDF_CS0__NANDF_CS0 IOMUX_PAD(0x518, 0x130, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS1__NANDF_CS1 IOMUX_PAD(0x51C, 0x134, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS2__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 0, 0x0, 0, NO_PAD_CTRL) +//FIXME: +#define MX51_PAD_NANDF_CS2__FEC_TX_ER IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, MX51_FEC_PAD_CTRL) +#define MX51_PAD_NANDF_CS2__GPIO3_18 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS3__NANDF_CS3 IOMUX_PAD(0x524, 0x13C, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13C, 2, 0x0, 0,MX51_FEC_PAD_CTRL) +#define MX51_PAD_NANDF_CS3__GPIO3_19 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS4__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS4__FEC_TDATA1 IOMUX_PAD(0x528, 0x140, 2, 0x0, 0, MX51_FEC_PAD_CTRL) +#define MX51_PAD_NANDF_CS4__GPIO3_20 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS5__NANDF_CS5 IOMUX_PAD(0x52C, 0x144, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS5__FEC_TDATA2 IOMUX_PAD(0x52C, 0x144, 2, 0x0, 0, MX51_FEC_PAD_CTRL) +#define MX51_PAD_NANDF_CS5__GPIO3_21 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS6__NANDF_CS6 IOMUX_PAD(0x530, 0x148, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS6__FEC_TDATA3 IOMUX_PAD(0x530, 0x148, 2, 0x0, 0, MX51_FEC_PAD_CTRL) +#define MX51_PAD_NANDF_CS6__GPIO3_22 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS7__NANDF_CS7 IOMUX_PAD(0x534, 0x14C, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS7__FEC_TX_EN IOMUX_PAD(0x534, 0x14C, 1, 0x0, 0, MX51_FEC_PAD_CTRL) +#define MX51_PAD_NANDF_CS7__GPIO3_23 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_FEC_PAD_CTRL) +#define MX51_PAD_NANDF_RDY_INT__GPIO3_24 IOMUX_PAD(0x538, 0x150, 3, 0x974, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_D15__NANDF_D15 IOMUX_PAD(0x53C, 0x154, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_D14__NANDF_D14 IOMUX_PAD(0x540, 0x158, 0, 0x0, 0, NO_PAD_CTRL) @@ -161,13 +180,17 @@ #define MX51_PAD_NANDF_D11__NANDF_D11 IOMUX_PAD(0x54C, 0x164, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_D11__FEC_RX_DV IOMUX_PAD(0x54C, 0x164, 2, 0x96c, 0, MX51_FEC_PAD_CTRL) +#define MX51_PAD_NANDF_D11__GPIO3_29 IOMUX_PAD(0x54C, 0x164, 3, 0x96c, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_D10__NANDF_D10 IOMUX_PAD(0x550, 0x168, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D9__NANDF_D9 IOMUX_PAD(0x554, 0x16C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D9__NANDF_D9 IOMUX_PAD(0x554, 0x16C, 0, 0x958, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D9__FEC_RDATA0 IOMUX_PAD(0x554, 0x16C, 2, 0x958, 0, MX51_FEC_PAD_CTRL) +#define MX51_PAD_NANDF_D9__GPIO3_31 IOMUX_PAD(0x554, 0x16C, 3, 0x958, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_D8__NANDF_D8 IOMUX_PAD(0x558, 0x170, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_D8__FEC_TDATA0 IOMUX_PAD(0x558, 0x170, 2, 0x0, 0, MX51_FEC_PAD_CTRL) +#define MX51_PAD_NANDF_D8__GPIO4_0 IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_D7__NANDF_D7 IOMUX_PAD(0x55C, 0x174, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_D6__NANDF_D6 IOMUX_PAD(0x560, 0x178, 0, 0x0, 0, NO_PAD_CTRL) @@ -179,6 +202,7 @@ #define MX51_PAD_NANDF_D0__NANDF_D0 IOMUX_PAD(0x578, 0x190, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSI1_D8__CSI1_D8 IOMUX_PAD(0x57C, 0x194, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSI1_D9__CSI1_D9 IOMUX_PAD(0x580, 0x198, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D9__GPIO3_13 IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL) @@ -196,6 +220,7 @@ #define MX51_PAD_CSI1_PKE0__CSI1_PKE0 IOMUX_PAD(0x860, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSI2_D12__CSI2_D12 IOMUX_PAD(0x5BC, 0x1CC, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSI2_D13__CSI2_D13 IOMUX_PAD(0x5C0, 0x1D0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D13__GPIO4_10 IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSI2_D14__CSI2_D14 IOMUX_PAD(0x5C4, 0x1D4, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSI2_D15__CSI2_D15 IOMUX_PAD(0x5C8, 0x1D8, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSI2_D16__CSI2_D16 IOMUX_PAD(0x5CC, 0x1DC, 0, 0x0, 0, NO_PAD_CTRL) @@ -209,13 +234,18 @@ #define MX51_PAD_I2C1_CLK__I2C1_CLK IOMUX_PAD(0x5E8, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_I2C1_DAT__I2C1_DAT IOMUX_PAD(0x5EC, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_AUD3_BB_TXD__AUD3_BB_TXD IOMUX_PAD(0x5F0, 0x200, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_TXD__GPIO4_18 IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_AUD3_BB_RXD__AUD3_BB_RXD IOMUX_PAD(0x5F4, 0x204, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_RXD__GPIO4_19 IOMUX_PAD(0x5f4, 0x204, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_AUD3_BB_CK__AUD3_BB_CK IOMUX_PAD(0x5F8, 0x208, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_CK__GPIO4_20 IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_AUD3_BB_FS__AUD3_BB_FS IOMUX_PAD(0x5FC, 0x20C, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSPI1_MOSI__CSPI1_MOSI IOMUX_PAD(0x600, 0x210, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSPI1_MISO__CSPI1_MISO IOMUX_PAD(0x604, 0x214, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSPI1_SS0__CSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_SS0__GPIO4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSPI1_SS1__CSPI1_SS1 IOMUX_PAD(0x60C, 0x21C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_SS1__GPIO4_25 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSPI1_RDY__CSPI1_RDY IOMUX_PAD(0x610, 0x220, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSPI1_SCLK__CSPI1_SCLK IOMUX_PAD(0x614, 0x224, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x0, 0, NO_PAD_CTRL) @@ -252,13 +282,17 @@ #define MX51_PAD_DI1_PIN11__DI1_PIN11 IOMUX_PAD(0x6A8, 0x2A8, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DI1_PIN12__DI1_PIN12 IOMUX_PAD(0x6AC, 0x2AC, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DI1_PIN13__DI1_PIN13 IOMUX_PAD(0x6B0, 0x2B0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_D0_CS__DI1_D0_CS IOMUX_PAD(0x6B4, 0x2B4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_D0_CS__DI1_D0_CS IOMUX_PAD(0x6B4, 0x2B4, 0, 0x980, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_D0_CS__GPIO3_3 IOMUX_PAD(0x6B4, 0x2B4, 4, 0x980, 1, NO_PAD_CTRL) #define MX51_PAD_DI1_D1_CS__DI1_D1_CS IOMUX_PAD(0x6B8, 0x2B8, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DI1_D1_CS__GPIO3_4 IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0984, 1, NO_PAD_CTRL) #define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN IOMUX_PAD(0x6BC, 0x2BC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO IOMUX_PAD(0x6C0, 0x2C0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO IOMUX_PAD(0x6C0, 0x2C0, 0, 0x098C, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6 IOMUX_PAD(0x6c0, 0x2C0, 4, 0x098C, 1, NO_PAD_CTRL) + #define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK IOMUX_PAD(0x6C4, 0x2C4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6C8, 0x2C8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6C8, 0x2C8, 0, 0x994, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_RS__GPIO3_8 IOMUX_PAD(0x6C8, 0x2C8, 4, 0x994, 1, NO_PAD_CTRL) #define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL) -- 1.7.9.1