* [PATCH] omap4-fb: add driver
@ 2013-04-04 6:42 Christoph Fritz
2013-04-05 8:59 ` Sascha Hauer
0 siblings, 1 reply; 24+ messages in thread
From: Christoph Fritz @ 2013-04-04 6:42 UTC (permalink / raw)
To: Sascha Hauer, barebox
This patch adds omap4 display controller support.
Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
---
arch/arm/mach-omap/Makefile | 1 +
arch/arm/mach-omap/include/mach/omap4-fb.h | 52 +++
arch/arm/mach-omap/omap4_fb.c | 29 ++
drivers/video/Kconfig | 8 +
drivers/video/Makefile | 1 +
drivers/video/omap4.c | 525 ++++++++++++++++++++++++++++
drivers/video/omap4.h | 408 +++++++++++++++++++++
7 files changed, 1024 insertions(+)
create mode 100644 arch/arm/mach-omap/include/mach/omap4-fb.h
create mode 100644 arch/arm/mach-omap/omap4_fb.c
create mode 100644 drivers/video/omap4.c
create mode 100644 drivers/video/omap4.h
diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile
index 94e42c6..e70ddbd 100644
--- a/arch/arm/mach-omap/Makefile
+++ b/arch/arm/mach-omap/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
pbl-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
obj-$(CONFIG_OMAP_GPMC) += gpmc.o devices-gpmc-nand.o
obj-$(CONFIG_SHELL_NONE) += xload.o
+obj-$(CONFIG_DRIVER_VIDEO_OMAP4) += omap4_fb.o
obj-$(CONFIG_I2C_TWL6030) += omap4_twl6030_mmc.o
obj-$(CONFIG_OMAP4_USBBOOT) += omap4_rom_usb.o
obj-y += gpio.o
diff --git a/arch/arm/mach-omap/include/mach/omap4-fb.h b/arch/arm/mach-omap/include/mach/omap4-fb.h
new file mode 100644
index 0000000..bb4c8e9
--- /dev/null
+++ b/arch/arm/mach-omap/include/mach/omap4-fb.h
@@ -0,0 +1,52 @@
+#ifndef H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H
+#define H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H
+
+#include <fb.h>
+
+/* device resource index */
+enum {
+ OMAP4_FB_RESOURCE_DSS,
+ OMAP4_FB_RESOURCE_DISPC,
+};
+
+#define OMAP_DSS_LCD_TFT (1u << 0)
+#define OMAP_DSS_LCD_IVS (1u << 1)
+#define OMAP_DSS_LCD_IHS (1u << 2)
+#define OMAP_DSS_LCD_IPC (1u << 3)
+#define OMAP_DSS_LCD_IEO (1u << 4)
+#define OMAP_DSS_LCD_RF (1u << 5)
+#define OMAP_DSS_LCD_ONOFF (1u << 6)
+
+#define OMAP_DSS_LCD_DATALINES(_l) ((_l) << 10)
+#define OMAP_DSS_LCD_DATALINES_msk OMAP_DSS_LCD_DATALINES(3u)
+#define OMAP_DSS_LCD_DATALINES_12 OMAP_DSS_LCD_DATALINES(0u)
+#define OMAP_DSS_LCD_DATALINES_16 OMAP_DSS_LCD_DATALINES(1u)
+#define OMAP_DSS_LCD_DATALINES_18 OMAP_DSS_LCD_DATALINES(2u)
+#define OMAP_DSS_LCD_DATALINES_24 OMAP_DSS_LCD_DATALINES(3u)
+
+struct omap4fb_display {
+ struct fb_videomode mode;
+
+ unsigned long config;
+
+ unsigned int power_on_delay;
+ unsigned int power_off_delay;
+};
+
+struct omap4fb_platform_data {
+ struct omap4fb_display const *displays;
+ size_t num_displays;
+
+ unsigned int dss_clk_hz;
+
+ unsigned int bpp;
+
+ struct resource const *screen;
+
+ void (*enable)(int p);
+};
+
+struct device_d;
+struct device_d *omap4_add_display(void *pdata);
+
+#endif /* H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H */
diff --git a/arch/arm/mach-omap/omap4_fb.c b/arch/arm/mach-omap/omap4_fb.c
new file mode 100644
index 0000000..70fbab6
--- /dev/null
+++ b/arch/arm/mach-omap/omap4_fb.c
@@ -0,0 +1,29 @@
+#include <driver.h>
+#include <common.h>
+#include <linux/ioport.h>
+#include <mach/omap4-fb.h>
+
+static struct resource omap4_fb_resources[] = {
+ [OMAP4_FB_RESOURCE_DSS] = {
+ .start = 0x48040000,
+ .end = 0x48040000 + 512 - 1,
+ .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+ .name = "DSS",
+ },
+
+ [OMAP4_FB_RESOURCE_DISPC] = {
+ .start = 0x48041000,
+ .end = 0x48041000 + 3072 - 1,
+ .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+ .name = "DISPC",
+ },
+};
+
+struct device_d *omap4_add_display(void *pdata)
+{
+ return add_generic_device_res("omap4_fb", -1,
+ omap4_fb_resources,
+ ARRAY_SIZE(omap4_fb_resources),
+ pdata);
+}
+EXPORT_SYMBOL(omap4_add_display);
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 6d6b08f..15eaa2f 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -45,6 +45,14 @@ config DRIVER_VIDEO_S3C24XX
help
Add support for the S3C244x LCD controller.
+config DRIVER_VIDEO_OMAP4
+ bool "OMAP4 framebuffer driver"
+ depends on ARCH_OMAP4
+ help
+ Add support for the OMAP4 Display Controller.
+ DSI is unsupported, only DISPC parallel mode on LCD2
+ is supported.
+
if DRIVER_VIDEO_S3C24XX
config DRIVER_VIDEO_S3C_VERBOSE
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 7429141..83feebb 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_DRIVER_VIDEO_IMX_IPU) += imx-ipu-fb.o
obj-$(CONFIG_DRIVER_VIDEO_S3C24XX) += s3c24xx.o
obj-$(CONFIG_DRIVER_VIDEO_PXA) += pxa.o
obj-$(CONFIG_DRIVER_VIDEO_SDL) += sdl.o
+obj-$(CONFIG_DRIVER_VIDEO_OMAP4) += omap4.o
diff --git a/drivers/video/omap4.c b/drivers/video/omap4.c
new file mode 100644
index 0000000..780b668
--- /dev/null
+++ b/drivers/video/omap4.c
@@ -0,0 +1,525 @@
+/*
+ * TI Omap4 Frame Buffer device driver
+ *
+ * Copyright (C) 2013 Christoph Fritz <chf.fritz@googlemail.com>
+ * Based on work by Enrico Scholz
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <driver.h>
+#include <fb.h>
+#include <errno.h>
+#include <xfuncs.h>
+#include <init.h>
+#include <stdio.h>
+#include <io.h>
+#include <common.h>
+#include <malloc.h>
+#include <common.h>
+#include <clock.h>
+
+#include <mach/omap4-silicon.h>
+#include <mach/omap4-fb.h>
+
+#include "omap4.h"
+
+struct omap4fb_device {
+ struct fb_info info;
+ struct device_d *dev;
+
+ struct omap4fb_display const *cur_display;
+
+ struct omap4fb_display const *displays;
+ size_t num_displays;
+
+ struct {
+ struct omap4_regs_dss __iomem *dss;
+ struct omap4_regs_dispc __iomem *dispc;
+ } regs;
+
+ struct {
+ void __iomem *addr;
+ size_t size;
+ } prealloc_screen;
+
+ struct {
+ uint32_t dispc_control;
+ uint32_t dispc_pol_freq;
+ } shadow;
+
+ struct {
+ unsigned int dss_clk_hz;
+ unsigned int lckd;
+ unsigned int pckd;
+ } divisor;
+
+ void (*enable_fn)(int);
+
+ struct fb_videomode video_modes[];
+};
+
+static inline void fb_write(uint32_t v, void __iomem *addr)
+{
+ __raw_writel(v, addr);
+}
+
+static inline uint32_t fb_read(void const __iomem *addr)
+{
+ return __raw_readl(addr);
+}
+
+static void omap4fb_enable(struct fb_info *info)
+{
+ struct omap4fb_device *fbi =
+ container_of(info, struct omap4fb_device, info);
+ struct omap4_regs_dispc __iomem *dispc = fbi->regs.dispc;
+
+ dev_info(fbi->dev, "%s\n", __func__);
+
+ if (!fbi->cur_display) {
+ dev_err(fbi->dev, "no valid mode set\n");
+ return;
+ }
+
+ if (fbi->enable_fn)
+ fbi->enable_fn(1);
+
+ udelay(fbi->cur_display->power_on_delay * 1000u);
+
+ fb_write(fb_read(&dispc->control2) |
+ DSS_DISPC_CONTROL_LCDENABLE |
+ 1*DSS_DISPC_CONTROL_LCDENABLESIGNAL,
+ &dispc->control2);
+
+ fb_write(fb_read(&dispc->vid1.attributes) |
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE,
+ &dispc->vid1.attributes);
+
+ fb_write(fb_read(&dispc->control2) |
+ DSS_DISPC_CONTROL_GOLCD,
+ &dispc->control2);
+}
+
+static void omap4fb_disable(struct fb_info *info)
+{
+ struct omap4fb_device *fbi =
+ container_of(info, struct omap4fb_device, info);
+ struct omap4_regs_dispc __iomem *dispc = fbi->regs.dispc;
+
+ dev_info(fbi->dev, "%s\n", __func__);
+
+ if (!fbi->cur_display) {
+ dev_err(fbi->dev, "no valid mode set\n");
+ return;
+ }
+
+ fb_write(fb_read(&dispc->control2) &
+ ~(DSS_DISPC_CONTROL_LCDENABLE |
+ DSS_DISPC_CONTROL_LCDENABLESIGNAL),
+ &dispc->control2);
+
+ fb_write(fb_read(&dispc->vid1.attributes) &
+ ~(DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE),
+ &dispc->vid1.attributes);
+
+ if (fbi->prealloc_screen.addr == NULL)
+ /* free frame buffer; but only when screen is not
+ * preallocated */
+ free(info->screen_base);
+
+ info->screen_base = NULL;
+
+ udelay(fbi->cur_display->power_off_delay * 1000u);
+
+ if (fbi->enable_fn)
+ fbi->enable_fn(0);
+}
+
+static void omap4fb_calc_divisor(struct omap4fb_device *fbi,
+ struct fb_videomode const *mode)
+{
+ unsigned int l, k, t, b;
+
+ b = UINT_MAX;
+ for (l = 1; l < 256; l++) {
+ for (k = 1; k < 256; k++) {
+ t = abs(mode->pixclock * 100 -
+ (fbi->divisor.dss_clk_hz / l / k));
+ if (t <= b) {
+ b = t;
+ fbi->divisor.lckd = l;
+ fbi->divisor.pckd = k;
+ }
+ }
+ }
+}
+
+static unsigned int omap4fb_calc_format(struct fb_info const *info)
+{
+ switch (info->bits_per_pixel) {
+ case 24: return 9;
+ case 32: return 0x8; /* xRGB24-8888 (32-bit container) */
+ default:
+ printf("%s: unsupported bpp %d\n", __func__,
+ info->bits_per_pixel);
+ return 0;
+ }
+}
+
+struct omap4fb_colors {
+ struct fb_bitfield red;
+ struct fb_bitfield green;
+ struct fb_bitfield blue;
+ struct fb_bitfield transp;
+};
+
+static struct omap4fb_colors const omap4FB_COLORS[] = {
+ [0] = {
+ .red = { .length = 0, .offset = 0 },
+ },
+ [1] = {
+ .blue = { .length = 8, .offset = 0 },
+ .green = { .length = 8, .offset = 8 },
+ .red = { .length = 8, .offset = 16 },
+ },
+ [2] = {
+ .blue = { .length = 8, .offset = 0 },
+ .green = { .length = 8, .offset = 8 },
+ .red = { .length = 8, .offset = 16 },
+ .transp = { .length = 8, .offset = 24 },
+ },
+};
+
+static void omap4fb_fill_bootenv(struct omap4fb_device *fbi,
+ size_t screen_size)
+{
+ char buf[sizeof("bootsplash=0x12345678+12345678910")];
+ int rc;
+
+ snprintf(buf, sizeof buf, "bootsplash=0x%08lx+%zu",
+ (unsigned long)fbi->info.screen_base,
+ screen_size);
+
+ rc = dev_set_param(fbi->dev, "bootargs", buf);
+ if (rc < 0) {
+ dev_err(fbi->dev, "failed to set bootargs '%s': %d\n",
+ buf, rc);
+ }
+}
+
+static void omap4fb_fill_shadow(struct omap4fb_device *fbi,
+ struct omap4fb_display const *display)
+{
+ fbi->shadow.dispc_control = 0;
+ fbi->shadow.dispc_pol_freq = 0;
+
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_STNTFT;
+
+ switch (display->config & OMAP_DSS_LCD_DATALINES_msk) {
+ case OMAP_DSS_LCD_DATALINES_12:
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_12;
+ break;
+ case OMAP_DSS_LCD_DATALINES_16:
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_16;
+ break;
+ case OMAP_DSS_LCD_DATALINES_18:
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_18;
+ break;
+ case OMAP_DSS_LCD_DATALINES_24:
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_24;
+ break;
+ }
+
+ if (display->config & OMAP_DSS_LCD_IPC)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IPC;
+
+ if (display->config & OMAP_DSS_LCD_IVS)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IVS;
+
+ if (display->config & OMAP_DSS_LCD_IHS)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IHS;
+
+ if (display->config & OMAP_DSS_LCD_IEO)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IEO;
+
+ if (display->config & OMAP_DSS_LCD_RF)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_RF;
+
+ if (display->config & OMAP_DSS_LCD_ONOFF)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_ONOFF;
+}
+
+static int omap4fb_activate_var(struct fb_info *info)
+{
+ struct omap4fb_device *fbi =
+ container_of(info, struct omap4fb_device, info);
+ struct omap4_regs_dispc __iomem *dispc = fbi->regs.dispc;
+ struct fb_videomode const *mode = info->mode;
+ size_t size = mode->xres * mode->yres * (info->bits_per_pixel / 8);
+ int rc;
+ unsigned int fmt = omap4fb_calc_format(info);
+ struct omap4fb_colors const *cols;
+ size_t i;
+ struct omap4fb_display const *new_display = NULL;
+
+ for (i = 0; i < fbi->num_displays && new_display == NULL; ++i) {
+ if (strcmp(mode->name, fbi->displays[i].mode.name) == 0)
+ new_display = &fbi->displays[i];
+ }
+
+ if (WARN_ON(!new_display)) {
+ dev_err(fbi->dev, "no matching display found for this mode '%s'\n",
+ mode->name);
+ rc = -ENXIO;
+ goto out;
+ }
+
+ if (fbi->prealloc_screen.addr == NULL) {
+ /* case 1: no preallocated screen */
+ free(info->screen_base);
+ info->screen_base = memalign(0x100, size);
+ } else if (fbi->prealloc_screen.size < size) {
+ /* case 2: preallocated screen, but too small */
+ dev_err(fbi->dev,
+ "allocated framebuffer too small (%zu < %zu)\n",
+ fbi->prealloc_screen.size, size);
+ rc = -ENOMEM;
+ goto out;
+ } else {
+ /* case 3: preallocated screen */
+ info->screen_base = fbi->prealloc_screen.addr;
+ }
+
+ omap4fb_fill_shadow(fbi, new_display);
+
+ omap4fb_calc_divisor(fbi, mode);
+
+ switch (info->bits_per_pixel) {
+ case 24:
+ cols = &omap4FB_COLORS[1];
+ break;
+ case 32:
+ cols = &omap4FB_COLORS[2];
+ break;
+ default:
+ cols = &omap4FB_COLORS[0];
+ }
+
+ info->red = cols->red;
+ info->green = cols->green;
+ info->blue = cols->blue;
+ info->transp = cols->transp;
+
+ fb_write(fbi->shadow.dispc_control,
+ &dispc->control2);
+
+ fb_write(fbi->shadow.dispc_pol_freq,
+ &dispc->pol_freq2);
+
+ fb_write(DSS_DISPC_TIMING_H_HSW(mode->hsync_len - 1) |
+ DSS_DISPC_TIMING_H_HFP(mode->right_margin - 1) |
+ DSS_DISPC_TIMING_H_HBP(mode->left_margin - 1),
+ &dispc->timing_h2);
+
+ fb_write(DSS_DISPC_TIMING_V_VSW(mode->vsync_len - 1) |
+ DSS_DISPC_TIMING_V_VFP(mode->lower_margin) |
+ DSS_DISPC_TIMING_V_VBP(mode->upper_margin),
+ &dispc->timing_v2);
+
+ fb_write(DSS_DISPC_DIVISOR_ENABLE | DSS_DISPC_DIVISOR_LCD(1),
+ &dispc->divisor);
+
+ fb_write(DSS_DISPC_DIVISOR2_LCD(fbi->divisor.lckd) |
+ DSS_DISPC_DIVISOR2_PCD(fbi->divisor.pckd),
+ &dispc->divisor2);
+
+ fb_write(DSS_DISPC_SIZE_LCD_PPL(mode->xres - 1) |
+ DSS_DISPC_SIZE_LCD_LPP(mode->yres - 1),
+ &dispc->size_lcd2);
+
+ fb_write(0x0000FF00, &dispc->default_color2);
+
+ /* we use VID1 */
+ fb_write((uintptr_t)info->screen_base, &dispc->vid1.ba[0]);
+ fb_write((uintptr_t)info->screen_base, &dispc->vid1.ba[1]);
+
+ fb_write(DSS_DISPC_VIDn_POSITION_VIDPOSX(0) |
+ DSS_DISPC_VIDn_POSITION_VIDPOSY(0),
+ &dispc->vid1.position);
+ fb_write(DSS_DISPC_VIDn_SIZE_VIDSIZEX(mode->xres - 1) |
+ DSS_DISPC_VIDn_SIZE_VIDSIZEY(mode->yres - 1),
+ &dispc->vid1.size);
+ fb_write(DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEX(mode->xres - 1) |
+ DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEY(mode->yres - 1),
+ &dispc->vid1.picture_size);
+ fb_write(1, &dispc->vid1.row_inc);
+ fb_write(1, &dispc->vid1.pixel_inc);
+
+ fb_write(0xfff, &dispc->vid_preload[0]);
+
+ fb_write(DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(fmt) |
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_8x128 |
+ DSS_DISPC_VIDn_ATTRIBUTES_ZORDERENABLE |
+ DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_SECONDARY_LCD,
+ &dispc->vid1.attributes);
+
+ while (fb_read(&dispc->control2) & DSS_DISPC_CONTROL_GOLCD)
+ ; /* noop */
+
+ fb_write(fb_read(&dispc->control2) |
+ DSS_DISPC_CONTROL_GOLCD,
+ &dispc->control2);
+
+ fbi->cur_display = new_display;
+ info->xres = mode->xres;
+ info->yres = mode->yres;
+ omap4fb_fill_bootenv(fbi, size);
+
+ rc = 0;
+
+out:
+ return rc;
+}
+
+static void omap4fb_reset(struct omap4fb_device const *fbi)
+{
+ struct omap4_regs_dispc __iomem *dispc = fbi->regs.dispc;
+ struct omap4_regs_dss __iomem *dss = fbi->regs.dss;
+
+ uint32_t v = fb_read(&dispc->control2);
+
+ /* step 1: stop the LCD controller */
+ if (v & DSS_DISPC_CONTROL_LCDENABLE) {
+ fb_write(v & ~DSS_DISPC_CONTROL_LCDENABLE,
+ &dispc->control2);
+
+ fb_write(DSS_DISPC_IRQSTATUS_FRAMEDONE2, &dispc->irqstatus);
+
+ while ((fb_read(&dispc->irqstatus) &
+ DSS_DISPC_IRQSTATUS_FRAMEDONE) == 0)
+ ; /* noop */
+ }
+
+ /* step 2: wait for reset done status */
+ while (!(fb_read(&dss->sysstatus) & DSS_DSS_SYSSTATUS_RESETDONE))
+ ; /* noop */
+
+ /* DSS_CTL: set to reset value */
+ fb_write(0, &dss->ctrl);
+}
+
+static struct fb_ops omap4fb_ops = {
+ .fb_enable = omap4fb_enable,
+ .fb_disable = omap4fb_disable,
+ .fb_activate_var = omap4fb_activate_var,
+};
+
+static int omap4fb_probe(struct device_d *dev)
+{
+ struct omap4fb_platform_data const *pdata = dev->platform_data;
+ struct omap4fb_device *fbi;
+ struct fb_info *info;
+ struct omap4_regs_dispc __iomem *dispc;
+ struct omap4_regs_dss __iomem *dss;
+ int rc;
+ size_t i;
+
+ if (!pdata)
+ return -ENODEV;
+
+ fbi = xzalloc(sizeof *fbi +
+ pdata->num_displays * sizeof fbi->video_modes[0]);
+ info = &fbi->info;
+
+ fbi->dev = dev;
+
+ /* CM_DSS_CLKSTCTRL (TRM: 935) trigger SW_WKUP */
+ __raw_writel(0x2, 0x4a009100); /* TODO: move this to clockmanagement */
+
+ fbi->regs.dss = dev_request_mem_region(dev, OMAP4_FB_RESOURCE_DSS);
+ fbi->regs.dispc = dev_request_mem_region(dev, OMAP4_FB_RESOURCE_DISPC);
+
+ if (!fbi->regs.dss || !fbi->regs.dispc) {
+ dev_err(dev, "Insufficient register description\n");
+ rc = -EINVAL;
+ goto out;
+ }
+
+ dispc = fbi->regs.dispc;
+ dss = fbi->regs.dss;
+ dev_info(dev, "HW-Revision 0x%04x 0x%04x\n",
+ fb_read(&dispc->revision),
+ fb_read(&dss->revision));
+
+
+ if (!pdata->dss_clk_hz | !pdata->displays | !pdata->num_displays |
+ !pdata->bpp) {
+ dev_err(dev, "Insufficient omap4fb_platform_data\n");
+ rc = -EINVAL;
+ goto out;
+ }
+
+ fbi->enable_fn = pdata->enable;
+ fbi->displays = pdata->displays;
+ fbi->num_displays = pdata->num_displays;
+ fbi->divisor.dss_clk_hz = pdata->dss_clk_hz;
+
+ for (i = 0; i < pdata->num_displays; ++i)
+ fbi->video_modes[i] = pdata->displays[i].mode;
+
+ info->mode_list = fbi->video_modes;
+ info->num_modes = pdata->num_displays;
+
+ info->priv = fbi;
+ info->fbops = &omap4fb_ops;
+ info->bits_per_pixel = pdata->bpp;
+
+ if (pdata->screen) {
+ fbi->prealloc_screen.addr =
+ (void __iomem *)pdata->screen->start;
+ fbi->prealloc_screen.size = resource_size(pdata->screen);
+ }
+
+ omap4fb_reset(fbi);
+
+ dev_add_param(fbi->dev, "bootargs", NULL, NULL, 0);
+
+ rc = register_framebuffer(info);
+ if (rc < 0) {
+ dev_err(dev, "failed to register framebuffer: %d\n", rc);
+ goto out;
+ }
+
+ rc = 0;
+ dev_info(dev, "registered omap4 framebuffer\n");
+
+out:
+ if (rc < 0)
+ free(fbi);
+
+ return rc;
+}
+
+static struct driver_d omap4fb_driver = {
+ .name = "omap4_fb",
+ .probe = omap4fb_probe,
+};
+
+static int omap4fb_init(void)
+{
+ return platform_driver_register(&omap4fb_driver);
+}
+
+device_initcall(omap4fb_init);
diff --git a/drivers/video/omap4.h b/drivers/video/omap4.h
new file mode 100644
index 0000000..b3364a5
--- /dev/null
+++ b/drivers/video/omap4.h
@@ -0,0 +1,408 @@
+/*
+ * TI Omap4 Frame Buffer device driver
+ *
+ * Copyright (C) 2013 Christoph Fritz <chf.fritz@googlemail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef H_BAREBOX_DRIVER_VIDEO_OMAP4_REGS_H
+#define H_BAREBOX_DRIVER_VIDEO_OMAP4_REGS_H
+
+#include <types.h>
+#include <common.h>
+
+#define OMAP4_RESERVED(_f, _t) \
+ uint32_t const reserved_ ## _f ## _ ## _t[((_t) - (_f)) / 4]
+
+
+/* TRM: 10.1.3.2 DSS Registers */
+struct omap4_regs_dss {
+ uint32_t revision;
+ OMAP4_RESERVED(0x4, 0x14);
+ uint32_t const sysstatus;
+ OMAP4_RESERVED(0x18, 0x40);
+ uint32_t ctrl;
+ OMAP4_RESERVED(0x44, 0x5C);
+ uint32_t const status;
+};
+
+
+struct omap4_regs_dispc_vid {
+ uint32_t ba[2];
+ uint32_t position;
+ uint32_t size;
+ uint32_t attributes;
+ uint32_t buf_threshold;
+ uint32_t const buf_size_status;
+ uint32_t row_inc;
+ uint32_t pixel_inc;
+ uint32_t fir;
+ uint32_t picture_size;
+ uint32_t accu[2];
+ struct {
+ uint32_t h;
+ uint32_t hv;
+ } fir_coef[8];
+ uint32_t conv_coef0;
+ uint32_t conv_coef1;
+ uint32_t conv_coef2;
+ uint32_t conv_coef3;
+ uint32_t conv_coef4;
+};
+
+/* TRM: 10.2.7.3 Display Controller Registers */
+struct omap4_regs_dispc {
+ uint32_t const revision;
+ OMAP4_RESERVED(0x04, 0x10);
+ uint32_t sysconfig;
+ uint32_t const sysstatus;
+ uint32_t irqstatus;
+ uint32_t irqenable;
+ OMAP4_RESERVED(0x20, 0x40);
+ uint32_t control1;
+ uint32_t config1;
+ OMAP4_RESERVED(0x48, 0x4C);
+
+ uint32_t default_color[2];
+ uint32_t trans_color[2];
+
+ uint32_t const line_status;
+ uint32_t line_number;
+ uint32_t timing_h1;
+ uint32_t timing_v1;
+ uint32_t pol_freq1;
+ uint32_t divisor1;
+ uint32_t global_alpha;
+ uint32_t size_tv;
+ uint32_t size_lcd1;
+
+ struct {
+ uint32_t ba[2];
+ uint32_t position;
+ uint32_t size;
+ OMAP4_RESERVED(0x90, 0xA0);
+ uint32_t attributes;
+ uint32_t buf_threshold;
+ uint32_t const buf_size_status;
+ uint32_t row_inc;
+ uint32_t pixel_inc;
+ OMAP4_RESERVED(0xB4, 0xB8);
+ uint32_t table_ba;
+ } gfx;
+
+ struct omap4_regs_dispc_vid vid1;
+ OMAP4_RESERVED(0x144, 0x14C);
+ struct omap4_regs_dispc_vid vid2;
+
+ uint32_t data1_cycle[3];
+
+ uint32_t vid1_fir_coef_v[8];
+ uint32_t vid2_fir_coef_v[8];
+ uint32_t cpr1_coef_r;
+ uint32_t cpr1_coef_g;
+ uint32_t cpr1_coef_b;
+ uint32_t gfx_preload;
+ uint32_t vid_preload[2];
+ uint32_t control2;
+ OMAP4_RESERVED(0x23C, 0x300);
+
+ struct {
+ uint32_t accu[2];
+ uint32_t ba[2];
+ struct {
+ uint32_t h;
+ uint32_t hv;
+ } fir_coef[8];
+ uint32_t fir_coef_v[8];
+ uint32_t attributes;
+ uint32_t conv_coef0;
+ uint32_t conv_coef1;
+ uint32_t conv_coef2;
+ uint32_t conv_coef3;
+ uint32_t conv_coef4;
+ uint32_t const buf_size_status;
+ uint32_t buf_threshold;
+ uint32_t fir;
+ uint32_t picture_size;
+ uint32_t pixel_inc;
+ uint32_t position;
+ uint32_t preload;
+ uint32_t row_inc;
+ uint32_t size;
+ } vid3;
+
+ uint32_t default_color2;
+ uint32_t trans_color2;
+ uint32_t cpr2_coef_b;
+ uint32_t cpr2_coef_g;
+ uint32_t cpr2_coef_r;
+ uint32_t data2_cycle[3];
+ uint32_t size_lcd2;
+ OMAP4_RESERVED(0x3D0, 0x400);
+ uint32_t timing_h2;
+ uint32_t timing_v2;
+ uint32_t pol_freq2;
+ uint32_t divisor2;
+ OMAP4_RESERVED(0x410, 0x500);
+
+ struct {
+ uint32_t accu[2];
+ uint32_t ba[2];
+ struct {
+ uint32_t h;
+ uint32_t hv;
+ } fir_coef[8];
+ uint32_t fir_coef_v[8];
+ uint32_t attributes;
+ uint32_t conv_coef0;
+ uint32_t conv_coef1;
+ uint32_t conv_coef2;
+ uint32_t conv_coef3;
+ uint32_t conv_coef4;
+ uint32_t const buf_size_status;
+ uint32_t buf_threshold;
+ uint32_t fir;
+ uint32_t picture_size;
+ uint32_t pixel_inc;
+ OMAP4_RESERVED(0x59C, 0x5A4);
+ uint32_t row_inc;
+ uint32_t size;
+ } wb;
+
+ OMAP4_RESERVED(0x5AC, 0x600);
+ uint32_t vid1_ba_uv[2];
+ uint32_t vid2_ba_uv[2];
+ uint32_t vid3_ba_uv[2];
+ uint32_t wb_ba_uv[2];
+ uint32_t config2;
+ uint32_t vid1_attributes2;
+ uint32_t vid2_attributes2;
+ uint32_t vid3_attributes2;
+ uint32_t gamma_table0;
+ uint32_t gamma_table1;
+ uint32_t gamma_table2;
+ uint32_t vid1_fir2;
+ uint32_t vid1_accu2[2];
+ struct {
+ uint32_t h2;
+ uint32_t hv2;
+ } vid1_fir_coef[8];
+ uint32_t vid1_fir_coef_v2[8];
+ uint32_t vid2_fir2;
+ uint32_t vid2_accu2[2];
+ struct {
+ uint32_t h2;
+ uint32_t hv2;
+ } vid2_fir_coef[8];
+ uint32_t vid2_fir_coef_v2[8];
+ OMAP4_RESERVED(0x714, 0x724);
+ uint32_t vid3_fir2;
+ uint32_t vid3_accu2[2];
+ struct {
+ uint32_t h2;
+ uint32_t hv2;
+ } vid3_fir_coef[8];
+ uint32_t vid3_fir_coef_v2[8];
+ uint32_t wb_fir2;
+ uint32_t wb_accu2[2];
+ OMAP4_RESERVED(0x79C, 0x7A0);
+ struct {
+ uint32_t h2;
+ uint32_t hv2;
+ } wb_fir_coef[8];
+ uint32_t wb_fir_coef_v2[8];
+ uint32_t global_buffer;
+ uint32_t divisor;
+ OMAP4_RESERVED(0x808, 0x810);
+ uint32_t wb_attributes2;
+};
+
+#define DSS_DISPC_VIDn_POSITION_VIDPOSX(_x) ((_x) << 0)
+#define DSS_DISPC_VIDn_POSITION_VIDPOSY(_y) ((_y) << 16)
+
+#define DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEX(_x) ((_x) << 0)
+#define DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEY(_y) ((_y) << 16)
+
+#define DSS_DISPC_VIDn_SIZE_VIDSIZEX(_x) ((_x) << 0)
+#define DSS_DISPC_VIDn_SIZE_VIDSIZEY(_y) ((_y) << 16)
+
+#define DSS_DISPC_SIZE_LCD_PPL(_x) ((_x) << 0)
+#define DSS_DISPC_SIZE_LCD_LPP(_y) ((_y) << 16)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE (1u << 0)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(_fmt) ((_fmt) << 1)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB12 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(4u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB16 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(5u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB16 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(6u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB16o \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(7u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_xRGB24u \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(8u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB24p \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(9u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_YUV2 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(10u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_UYVY \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(11u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB32 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(12u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGBA32 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(13u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_xRGB32 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(14u)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE(_f) ((_f) << 5)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE_NONE \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE(0u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE_H \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE(1u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE_V \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE(2u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE_HV \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE(3u)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDCOLORCONVENABLE (1u << 9)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDREPLICATIONENABLE (1u << 10)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFULLRANGE (1u << 11)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION(_r) ((_r) << 12)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION_0 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION(0u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION_90 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION(1u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION_180 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION(2u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION_270 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION(3u)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(_b) ((_b) << 14)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_2x128 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(0u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_4x128 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(1u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_8x128 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(2u)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDCHANNELOUT (1u << 16)
+#define DSS_DISPC_VIDn_ATTRIBUTES_SELFREFRESHAUTO (1u << 17)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFIFOPRELOAD (1u << 19)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDVERTICALTAPS (1u << 21)
+#define DSS_DISPC_VIDn_ATTRIBUTES_DOUBLESTRIDE (1u << 22)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDARBITRATION (1u << 23)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDSELFREFRESH (1u << 24)
+#define DSS_DISPC_VIDn_ATTRIBUTES_ZORDERENABLE (1u << 25)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(_b) ((_b) << 30)
+#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_PRIMARY_LCD \
+ DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(0u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_SECONDARY_LCD \
+ DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(1u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_WRITEBACK_MEM \
+ DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(3u)
+
+#define DSS_DISPC_CONFIG_PIXELGATED (1u << 0)
+#define DSS_DISPC_CONFIG_PIXELDATAGATED (1u << 4)
+#define DSS_DISPC_CONFIG_PIXELCLOCKGATED (1u << 5)
+#define DSS_DISPC_CONFIG_HSYNCGATED (1u << 6)
+#define DSS_DISPC_CONFIG_VSYNCGATED (1u << 7)
+#define DSS_DISPC_CONFIG_ACBIASGATED (1u << 8)
+#define DSS_DISPC_CONFIG_FUNCGATED (1u << 9)
+#define DSS_DISPC_CONFIG_TCKLCDENABLE (1u << 10)
+#define DSS_DISPC_CONFIG_TCKLCDSELECTION (1u << 11)
+#define DSS_DISPC_CONFIG_CPR (1u << 15)
+#define DSS_DISPC_CONFIG_FIFOHANDCHECK (1u << 16)
+#define DSS_DISPC_CONFIG_OUTPUTMODE (1u << 22)
+#define DSS_DISPC_CONFIG_FIDFIRST (1u << 23)
+#define DSS_DISPC_CONFIG_COLORCONV (1u << 24)
+#define DSS_DISPC_CONFIG_FULLRANGE (1u << 25)
+
+#define DSS_DISPC_CONTROL_LCDENABLE (1u << 0)
+#define DSS_DISPC_CONTROL_TVENABLE (1u << 1)
+#define DSS_DISPC_CONTROL_MONOCOLOR (1u << 2)
+#define DSS_DISPC_CONTROL_STNTFT (1u << 3)
+#define DSS_DISPC_CONTROL_M8B (1u << 4)
+#define DSS_DISPC_CONTROL_GOLCD (1u << 5)
+#define DSS_DISPC_CONTROL_GOTV (1u << 6)
+#define DSS_DISPC_CONTROL_STDITHERENABLE (1u << 7)
+
+#define DSS_DISPC_CONTROL_TFTDATALINES(_l) ((_l) << 8)
+#define DSS_DISPC_CONTROL_TFTDATALINES_12 \
+ DSS_DISPC_CONTROL_TFTDATALINES(0u)
+#define DSS_DISPC_CONTROL_TFTDATALINES_16 \
+ DSS_DISPC_CONTROL_TFTDATALINES(1u)
+#define DSS_DISPC_CONTROL_TFTDATALINES_18 \
+ DSS_DISPC_CONTROL_TFTDATALINES(2u)
+#define DSS_DISPC_CONTROL_TFTDATALINES_24 \
+ DSS_DISPC_CONTROL_TFTDATALINES(3u)
+
+#define DSS_DISPC_CONTROL_STALLMODE (1u << 11)
+#define DSS_DISPC_CONTROL_OVERLAYOPTIMIZATION (1u << 12)
+#define DSS_DISPC_CONTROL_GPIN0 (1u << 13) /* ro */
+#define DSS_DISPC_CONTROL_GPIN1 (1u << 14) /* ro */
+#define DSS_DISPC_CONTROL_GPOUT0 (1u << 15)
+#define DSS_DISPC_CONTROL_GPOUT1 (1u << 16)
+#define DSS_DISPC_CONTROL_HT(_ht) ((_ht) << 17)
+#define DSS_DISPC_CONTROL_TDMENABLE (1u << 20)
+#define DSS_DISPC_CONTROL_TDMPARALLELMODE(_pm) ((_pm) << 21)
+#define DSS_DISPC_CONTROL_TDMCYCLEFORMAT(_cf) ((_cf) << 23)
+#define DSS_DISPC_CONTROL_TDMUNUSEDBITS(_ub) ((_ub) << 25)
+#define DSS_DISPC_CONTROL_PCKFREEENABLE (1u << 27)
+#define DSS_DISPC_CONTROL_LCDENABLESIGNAL (1u << 28)
+#define DSS_DISPC_CONTROL_LCDENABLEPOL (1u << 29)
+#define DSS_DISPC_CONTROL_SPATIALTEMPD(_df) ((_df) << 30)
+
+#define DSS_DISPC_POL_FREQ_IVS (1u << 12)
+#define DSS_DISPC_POL_FREQ_IHS (1u << 13)
+#define DSS_DISPC_POL_FREQ_IPC (1u << 14)
+#define DSS_DISPC_POL_FREQ_IEO (1u << 15)
+#define DSS_DISPC_POL_FREQ_RF (1u << 16)
+#define DSS_DISPC_POL_FREQ_ONOFF (1u << 17)
+
+#define DSS_DISPC_TIMING_H_HSW(_hsw) ((_hsw) << 0)
+#define DSS_DISPC_TIMING_H_HFP(_hfp) ((_hfp) << 8)
+#define DSS_DISPC_TIMING_H_HBP(_hbp) ((_hbp) << 20)
+
+#define DSS_DISPC_TIMING_V_VSW(_vsw) ((_vsw) << 0)
+#define DSS_DISPC_TIMING_V_VFP(_vfp) ((_vfp) << 8)
+#define DSS_DISPC_TIMING_V_VBP(_vbp) ((_vbp) << 20)
+
+#define DSS_DISPC_DIVISOR_ENABLE (1u << 0)
+#define DSS_DISPC_DIVISOR_LCD(_lcd) ((_lcd) << 16)
+
+#define DSS_DISPC_DIVISOR2_PCD(_pcd) ((_pcd) << 0)
+#define DSS_DISPC_DIVISOR2_LCD(_lcd) ((_lcd) << 16)
+
+#define DSS_DISPC_IRQSTATUS_FRAMEDONE (1u << 0)
+#define DSS_DISPC_IRQSTATUS_FRAMEDONE2 (1u << 22)
+
+#define DSS_DSS_SYSCONFIG_SOFTRESET (1u << 1)
+#define DSS_DSS_SYSSTATUS_RESETDONE (1u << 0)
+
+#define DSS_DSS_CONTROL_DISPC_CLK_SWITCH (1u << 0)
+#define DSS_DSS_CONTROL_DSI_CLK_SWITCH (1u << 1)
+
+#define CM_FCLKEN_DSS_EN_DSS1 (1u << 0)
+#define CM_FCLKEN_DSS_EN_DSS2 (1u << 1)
+#define CM_FCLKEN_DSS_EN_TV (1u << 2)
+
+#define CM_ICLKEN_DSS_EN_DSS (1u << 0)
+
+
+#undef OMAP4_RESERVED
+
+#endif /* H_BAREBOX_DRIVER_VIDEO_OMAP4_REGS_H */
--
1.7.10.4
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH] omap4-fb: add driver
2013-04-04 6:42 [PATCH] omap4-fb: add driver Christoph Fritz
@ 2013-04-05 8:59 ` Sascha Hauer
2013-04-07 22:15 ` [PATCH v2] " Christoph Fritz
0 siblings, 1 reply; 24+ messages in thread
From: Sascha Hauer @ 2013-04-05 8:59 UTC (permalink / raw)
To: Christoph Fritz; +Cc: barebox
Hi Christoph,
mostly ok, some comments inline.
On Thu, Apr 04, 2013 at 08:42:42AM +0200, Christoph Fritz wrote:
> diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
> index 6d6b08f..15eaa2f 100644
> --- a/drivers/video/Kconfig
> +++ b/drivers/video/Kconfig
> @@ -45,6 +45,14 @@ config DRIVER_VIDEO_S3C24XX
> help
> Add support for the S3C244x LCD controller.
>
> +config DRIVER_VIDEO_OMAP4
> + bool "OMAP4 framebuffer driver"
\t please
> + depends on ARCH_OMAP4
> + help
> + Add support for the OMAP4 Display Controller.
> + DSI is unsupported, only DISPC parallel mode on LCD2
> + is supported.
> +
> if DRIVER_VIDEO_S3C24XX
> +
> +struct omap4fb_colors {
> + struct fb_bitfield red;
> + struct fb_bitfield green;
> + struct fb_bitfield blue;
> + struct fb_bitfield transp;
> +};
> +
> +static struct omap4fb_colors const omap4FB_COLORS[] = {
lower case variable names please.
> + [0] = {
> + .red = { .length = 0, .offset = 0 },
> + },
> + [1] = {
> + .blue = { .length = 8, .offset = 0 },
> + .green = { .length = 8, .offset = 8 },
> + .red = { .length = 8, .offset = 16 },
> + },
> + [2] = {
> + .blue = { .length = 8, .offset = 0 },
> + .green = { .length = 8, .offset = 8 },
> + .red = { .length = 8, .offset = 16 },
> + .transp = { .length = 8, .offset = 24 },
> + },
> +};
> +
> +static void omap4fb_fill_bootenv(struct omap4fb_device *fbi,
> + size_t screen_size)
> +{
> + char buf[sizeof("bootsplash=0x12345678+12345678910")];
> + int rc;
> +
> + snprintf(buf, sizeof buf, "bootsplash=0x%08lx+%zu",
> + (unsigned long)fbi->info.screen_base,
> + screen_size);
> +
> + rc = dev_set_param(fbi->dev, "bootargs", buf);
> + if (rc < 0) {
> + dev_err(fbi->dev, "failed to set bootargs '%s': %d\n",
> + buf, rc);
> + }
> +}
Where is this used in the kernel? You should probably rather use the
simple fb driver Steven Warren suggested.
> +
> + rc = register_framebuffer(info);
> + if (rc < 0) {
> + dev_err(dev, "failed to register framebuffer: %d\n", rc);
> + goto out;
> + }
> +
> + rc = 0;
> + dev_info(dev, "registered omap4 framebuffer\n");
The context is already in dev_info, so you can just do a
dev_info(dev, "registered\n");
> +/* TRM: 10.2.7.3 Display Controller Registers */
> +struct omap4_regs_dispc {
> + uint32_t const revision;
> + OMAP4_RESERVED(0x04, 0x10);
> + uint32_t sysconfig;
> + uint32_t const sysstatus;
> + uint32_t irqstatus;
> + uint32_t irqenable;
> + OMAP4_RESERVED(0x20, 0x40);
> + uint32_t control1;
> + uint32_t config1;
> + OMAP4_RESERVED(0x48, 0x4C);
> +
> + uint32_t default_color[2];
> + uint32_t trans_color[2];
> +
> + uint32_t const line_status;
> + uint32_t line_number;
> + uint32_t timing_h1;
> + uint32_t timing_v1;
> + uint32_t pol_freq1;
> + uint32_t divisor1;
> + uint32_t global_alpha;
> + uint32_t size_tv;
> + uint32_t size_lcd1;
> +
> + struct {
> + uint32_t ba[2];
> + uint32_t position;
> + uint32_t size;
> + OMAP4_RESERVED(0x90, 0xA0);
> + uint32_t attributes;
> + uint32_t buf_threshold;
> + uint32_t const buf_size_status;
> + uint32_t row_inc;
> + uint32_t pixel_inc;
> + OMAP4_RESERVED(0xB4, 0xB8);
> + uint32_t table_ba;
> + } gfx;
> +
> + struct omap4_regs_dispc_vid vid1;
> + OMAP4_RESERVED(0x144, 0x14C);
> + struct omap4_regs_dispc_vid vid2;
> +
> + uint32_t data1_cycle[3];
> +
> + uint32_t vid1_fir_coef_v[8];
> + uint32_t vid2_fir_coef_v[8];
> + uint32_t cpr1_coef_r;
> + uint32_t cpr1_coef_g;
> + uint32_t cpr1_coef_b;
> + uint32_t gfx_preload;
> + uint32_t vid_preload[2];
> + uint32_t control2;
> + OMAP4_RESERVED(0x23C, 0x300);
> +
> + struct {
> + uint32_t accu[2];
> + uint32_t ba[2];
> + struct {
> + uint32_t h;
> + uint32_t hv;
> + } fir_coef[8];
> + uint32_t fir_coef_v[8];
> + uint32_t attributes;
> + uint32_t conv_coef0;
> + uint32_t conv_coef1;
> + uint32_t conv_coef2;
> + uint32_t conv_coef3;
> + uint32_t conv_coef4;
> + uint32_t const buf_size_status;
> + uint32_t buf_threshold;
> + uint32_t fir;
> + uint32_t picture_size;
> + uint32_t pixel_inc;
> + uint32_t position;
> + uint32_t preload;
> + uint32_t row_inc;
> + uint32_t size;
> + } vid3;
> +
> + uint32_t default_color2;
> + uint32_t trans_color2;
> + uint32_t cpr2_coef_b;
> + uint32_t cpr2_coef_g;
> + uint32_t cpr2_coef_r;
> + uint32_t data2_cycle[3];
> + uint32_t size_lcd2;
> + OMAP4_RESERVED(0x3D0, 0x400);
> + uint32_t timing_h2;
> + uint32_t timing_v2;
> + uint32_t pol_freq2;
> + uint32_t divisor2;
> + OMAP4_RESERVED(0x410, 0x500);
> +
> + struct {
> + uint32_t accu[2];
> + uint32_t ba[2];
> + struct {
> + uint32_t h;
> + uint32_t hv;
> + } fir_coef[8];
> + uint32_t fir_coef_v[8];
> + uint32_t attributes;
> + uint32_t conv_coef0;
> + uint32_t conv_coef1;
> + uint32_t conv_coef2;
> + uint32_t conv_coef3;
> + uint32_t conv_coef4;
> + uint32_t const buf_size_status;
> + uint32_t buf_threshold;
> + uint32_t fir;
> + uint32_t picture_size;
> + uint32_t pixel_inc;
> + OMAP4_RESERVED(0x59C, 0x5A4);
> + uint32_t row_inc;
> + uint32_t size;
> + } wb;
> +
> + OMAP4_RESERVED(0x5AC, 0x600);
> + uint32_t vid1_ba_uv[2];
> + uint32_t vid2_ba_uv[2];
> + uint32_t vid3_ba_uv[2];
> + uint32_t wb_ba_uv[2];
> + uint32_t config2;
> + uint32_t vid1_attributes2;
> + uint32_t vid2_attributes2;
> + uint32_t vid3_attributes2;
> + uint32_t gamma_table0;
> + uint32_t gamma_table1;
> + uint32_t gamma_table2;
> + uint32_t vid1_fir2;
> + uint32_t vid1_accu2[2];
> + struct {
> + uint32_t h2;
> + uint32_t hv2;
> + } vid1_fir_coef[8];
> + uint32_t vid1_fir_coef_v2[8];
> + uint32_t vid2_fir2;
> + uint32_t vid2_accu2[2];
> + struct {
> + uint32_t h2;
> + uint32_t hv2;
> + } vid2_fir_coef[8];
> + uint32_t vid2_fir_coef_v2[8];
> + OMAP4_RESERVED(0x714, 0x724);
> + uint32_t vid3_fir2;
> + uint32_t vid3_accu2[2];
> + struct {
> + uint32_t h2;
> + uint32_t hv2;
> + } vid3_fir_coef[8];
> + uint32_t vid3_fir_coef_v2[8];
> + uint32_t wb_fir2;
> + uint32_t wb_accu2[2];
> + OMAP4_RESERVED(0x79C, 0x7A0);
> + struct {
> + uint32_t h2;
> + uint32_t hv2;
> + } wb_fir_coef[8];
> + uint32_t wb_fir_coef_v2[8];
> + uint32_t global_buffer;
> + uint32_t divisor;
> + OMAP4_RESERVED(0x808, 0x810);
> + uint32_t wb_attributes2;
> +};
This looks awful. I wonder who ever had the idea that placing structs
over registers is a good idea.
Sascha
--
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Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
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^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v2] omap4-fb: add driver
2013-04-05 8:59 ` Sascha Hauer
@ 2013-04-07 22:15 ` Christoph Fritz
2013-04-08 7:17 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 1 reply; 24+ messages in thread
From: Christoph Fritz @ 2013-04-07 22:15 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
This patch adds omap4 display controller support.
Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
---
arch/arm/mach-omap/Makefile | 1 +
arch/arm/mach-omap/include/mach/omap4-fb.h | 52 +++
arch/arm/mach-omap/omap4_fb.c | 29 ++
drivers/video/Kconfig | 8 +
drivers/video/Makefile | 1 +
drivers/video/omap4.c | 507 ++++++++++++++++++++++++++++
drivers/video/omap4.h | 408 ++++++++++++++++++++++
7 files changed, 1006 insertions(+)
create mode 100644 arch/arm/mach-omap/include/mach/omap4-fb.h
create mode 100644 arch/arm/mach-omap/omap4_fb.c
create mode 100644 drivers/video/omap4.c
create mode 100644 drivers/video/omap4.h
diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile
index 94e42c6..e70ddbd 100644
--- a/arch/arm/mach-omap/Makefile
+++ b/arch/arm/mach-omap/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
pbl-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
obj-$(CONFIG_OMAP_GPMC) += gpmc.o devices-gpmc-nand.o
obj-$(CONFIG_SHELL_NONE) += xload.o
+obj-$(CONFIG_DRIVER_VIDEO_OMAP4) += omap4_fb.o
obj-$(CONFIG_I2C_TWL6030) += omap4_twl6030_mmc.o
obj-$(CONFIG_OMAP4_USBBOOT) += omap4_rom_usb.o
obj-y += gpio.o
diff --git a/arch/arm/mach-omap/include/mach/omap4-fb.h b/arch/arm/mach-omap/include/mach/omap4-fb.h
new file mode 100644
index 0000000..bb4c8e9
--- /dev/null
+++ b/arch/arm/mach-omap/include/mach/omap4-fb.h
@@ -0,0 +1,52 @@
+#ifndef H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H
+#define H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H
+
+#include <fb.h>
+
+/* device resource index */
+enum {
+ OMAP4_FB_RESOURCE_DSS,
+ OMAP4_FB_RESOURCE_DISPC,
+};
+
+#define OMAP_DSS_LCD_TFT (1u << 0)
+#define OMAP_DSS_LCD_IVS (1u << 1)
+#define OMAP_DSS_LCD_IHS (1u << 2)
+#define OMAP_DSS_LCD_IPC (1u << 3)
+#define OMAP_DSS_LCD_IEO (1u << 4)
+#define OMAP_DSS_LCD_RF (1u << 5)
+#define OMAP_DSS_LCD_ONOFF (1u << 6)
+
+#define OMAP_DSS_LCD_DATALINES(_l) ((_l) << 10)
+#define OMAP_DSS_LCD_DATALINES_msk OMAP_DSS_LCD_DATALINES(3u)
+#define OMAP_DSS_LCD_DATALINES_12 OMAP_DSS_LCD_DATALINES(0u)
+#define OMAP_DSS_LCD_DATALINES_16 OMAP_DSS_LCD_DATALINES(1u)
+#define OMAP_DSS_LCD_DATALINES_18 OMAP_DSS_LCD_DATALINES(2u)
+#define OMAP_DSS_LCD_DATALINES_24 OMAP_DSS_LCD_DATALINES(3u)
+
+struct omap4fb_display {
+ struct fb_videomode mode;
+
+ unsigned long config;
+
+ unsigned int power_on_delay;
+ unsigned int power_off_delay;
+};
+
+struct omap4fb_platform_data {
+ struct omap4fb_display const *displays;
+ size_t num_displays;
+
+ unsigned int dss_clk_hz;
+
+ unsigned int bpp;
+
+ struct resource const *screen;
+
+ void (*enable)(int p);
+};
+
+struct device_d;
+struct device_d *omap4_add_display(void *pdata);
+
+#endif /* H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H */
diff --git a/arch/arm/mach-omap/omap4_fb.c b/arch/arm/mach-omap/omap4_fb.c
new file mode 100644
index 0000000..70fbab6
--- /dev/null
+++ b/arch/arm/mach-omap/omap4_fb.c
@@ -0,0 +1,29 @@
+#include <driver.h>
+#include <common.h>
+#include <linux/ioport.h>
+#include <mach/omap4-fb.h>
+
+static struct resource omap4_fb_resources[] = {
+ [OMAP4_FB_RESOURCE_DSS] = {
+ .start = 0x48040000,
+ .end = 0x48040000 + 512 - 1,
+ .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+ .name = "DSS",
+ },
+
+ [OMAP4_FB_RESOURCE_DISPC] = {
+ .start = 0x48041000,
+ .end = 0x48041000 + 3072 - 1,
+ .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+ .name = "DISPC",
+ },
+};
+
+struct device_d *omap4_add_display(void *pdata)
+{
+ return add_generic_device_res("omap4_fb", -1,
+ omap4_fb_resources,
+ ARRAY_SIZE(omap4_fb_resources),
+ pdata);
+}
+EXPORT_SYMBOL(omap4_add_display);
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 6d6b08f..9dfa0cd 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -45,6 +45,14 @@ config DRIVER_VIDEO_S3C24XX
help
Add support for the S3C244x LCD controller.
+config DRIVER_VIDEO_OMAP4
+ bool "OMAP4 framebuffer driver"
+ depends on ARCH_OMAP4
+ help
+ Add support for the OMAP4 Display Controller.
+ DSI is unsupported, only DISPC parallel mode on LCD2
+ is supported.
+
if DRIVER_VIDEO_S3C24XX
config DRIVER_VIDEO_S3C_VERBOSE
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 7429141..83feebb 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_DRIVER_VIDEO_IMX_IPU) += imx-ipu-fb.o
obj-$(CONFIG_DRIVER_VIDEO_S3C24XX) += s3c24xx.o
obj-$(CONFIG_DRIVER_VIDEO_PXA) += pxa.o
obj-$(CONFIG_DRIVER_VIDEO_SDL) += sdl.o
+obj-$(CONFIG_DRIVER_VIDEO_OMAP4) += omap4.o
diff --git a/drivers/video/omap4.c b/drivers/video/omap4.c
new file mode 100644
index 0000000..23c64d0
--- /dev/null
+++ b/drivers/video/omap4.c
@@ -0,0 +1,507 @@
+/*
+ * TI Omap4 Frame Buffer device driver
+ *
+ * Copyright (C) 2013 Christoph Fritz <chf.fritz@googlemail.com>
+ * Based on work by Enrico Scholz, sponsored by Phytec
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <driver.h>
+#include <fb.h>
+#include <errno.h>
+#include <xfuncs.h>
+#include <init.h>
+#include <stdio.h>
+#include <io.h>
+#include <common.h>
+#include <malloc.h>
+#include <common.h>
+#include <clock.h>
+
+#include <mach/omap4-silicon.h>
+#include <mach/omap4-fb.h>
+
+#include "omap4.h"
+
+struct omap4fb_device {
+ struct fb_info info;
+ struct device_d *dev;
+
+ struct omap4fb_display const *cur_display;
+
+ struct omap4fb_display const *displays;
+ size_t num_displays;
+
+ struct {
+ struct omap4_regs_dss __iomem *dss;
+ struct omap4_regs_dispc __iomem *dispc;
+ } regs;
+
+ struct {
+ void __iomem *addr;
+ size_t size;
+ } prealloc_screen;
+
+ struct {
+ uint32_t dispc_control;
+ uint32_t dispc_pol_freq;
+ } shadow;
+
+ struct {
+ unsigned int dss_clk_hz;
+ unsigned int lckd;
+ unsigned int pckd;
+ } divisor;
+
+ void (*enable_fn)(int);
+
+ struct fb_videomode video_modes[];
+};
+
+static inline void fb_write(uint32_t v, void __iomem *addr)
+{
+ __raw_writel(v, addr);
+}
+
+static inline uint32_t fb_read(void const __iomem *addr)
+{
+ return __raw_readl(addr);
+}
+
+static void omap4fb_enable(struct fb_info *info)
+{
+ struct omap4fb_device *fbi =
+ container_of(info, struct omap4fb_device, info);
+ struct omap4_regs_dispc __iomem *dispc = fbi->regs.dispc;
+
+ dev_info(fbi->dev, "%s\n", __func__);
+
+ if (!fbi->cur_display) {
+ dev_err(fbi->dev, "no valid mode set\n");
+ return;
+ }
+
+ if (fbi->enable_fn)
+ fbi->enable_fn(1);
+
+ udelay(fbi->cur_display->power_on_delay * 1000u);
+
+ fb_write(fb_read(&dispc->control2) |
+ DSS_DISPC_CONTROL_LCDENABLE |
+ 1*DSS_DISPC_CONTROL_LCDENABLESIGNAL,
+ &dispc->control2);
+
+ fb_write(fb_read(&dispc->vid1.attributes) |
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE,
+ &dispc->vid1.attributes);
+
+ fb_write(fb_read(&dispc->control2) |
+ DSS_DISPC_CONTROL_GOLCD,
+ &dispc->control2);
+}
+
+static void omap4fb_disable(struct fb_info *info)
+{
+ struct omap4fb_device *fbi =
+ container_of(info, struct omap4fb_device, info);
+ struct omap4_regs_dispc __iomem *dispc = fbi->regs.dispc;
+
+ dev_info(fbi->dev, "%s\n", __func__);
+
+ if (!fbi->cur_display) {
+ dev_err(fbi->dev, "no valid mode set\n");
+ return;
+ }
+
+ fb_write(fb_read(&dispc->control2) &
+ ~(DSS_DISPC_CONTROL_LCDENABLE |
+ DSS_DISPC_CONTROL_LCDENABLESIGNAL),
+ &dispc->control2);
+
+ fb_write(fb_read(&dispc->vid1.attributes) &
+ ~(DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE),
+ &dispc->vid1.attributes);
+
+ if (fbi->prealloc_screen.addr == NULL)
+ /* free frame buffer; but only when screen is not
+ * preallocated */
+ free(info->screen_base);
+
+ info->screen_base = NULL;
+
+ udelay(fbi->cur_display->power_off_delay * 1000u);
+
+ if (fbi->enable_fn)
+ fbi->enable_fn(0);
+}
+
+static void omap4fb_calc_divisor(struct omap4fb_device *fbi,
+ struct fb_videomode const *mode)
+{
+ unsigned int l, k, t, b;
+
+ b = UINT_MAX;
+ for (l = 1; l < 256; l++) {
+ for (k = 1; k < 256; k++) {
+ t = abs(mode->pixclock * 100 -
+ (fbi->divisor.dss_clk_hz / l / k));
+ if (t <= b) {
+ b = t;
+ fbi->divisor.lckd = l;
+ fbi->divisor.pckd = k;
+ }
+ }
+ }
+}
+
+static unsigned int omap4fb_calc_format(struct fb_info const *info)
+{
+ switch (info->bits_per_pixel) {
+ case 24: return 9;
+ case 32: return 0x8; /* xRGB24-8888 (32-bit container) */
+ default:
+ printf("%s: unsupported bpp %d\n", __func__,
+ info->bits_per_pixel);
+ return 0;
+ }
+}
+
+struct omap4fb_colors {
+ struct fb_bitfield red;
+ struct fb_bitfield green;
+ struct fb_bitfield blue;
+ struct fb_bitfield transp;
+};
+
+static struct omap4fb_colors const omap4fb_col[] = {
+ [0] = {
+ .red = { .length = 0, .offset = 0 },
+ },
+ [1] = {
+ .blue = { .length = 8, .offset = 0 },
+ .green = { .length = 8, .offset = 8 },
+ .red = { .length = 8, .offset = 16 },
+ },
+ [2] = {
+ .blue = { .length = 8, .offset = 0 },
+ .green = { .length = 8, .offset = 8 },
+ .red = { .length = 8, .offset = 16 },
+ .transp = { .length = 8, .offset = 24 },
+ },
+};
+
+static void omap4fb_fill_shadow(struct omap4fb_device *fbi,
+ struct omap4fb_display const *display)
+{
+ fbi->shadow.dispc_control = 0;
+ fbi->shadow.dispc_pol_freq = 0;
+
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_STNTFT;
+
+ switch (display->config & OMAP_DSS_LCD_DATALINES_msk) {
+ case OMAP_DSS_LCD_DATALINES_12:
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_12;
+ break;
+ case OMAP_DSS_LCD_DATALINES_16:
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_16;
+ break;
+ case OMAP_DSS_LCD_DATALINES_18:
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_18;
+ break;
+ case OMAP_DSS_LCD_DATALINES_24:
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_24;
+ break;
+ }
+
+ if (display->config & OMAP_DSS_LCD_IPC)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IPC;
+
+ if (display->config & OMAP_DSS_LCD_IVS)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IVS;
+
+ if (display->config & OMAP_DSS_LCD_IHS)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IHS;
+
+ if (display->config & OMAP_DSS_LCD_IEO)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IEO;
+
+ if (display->config & OMAP_DSS_LCD_RF)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_RF;
+
+ if (display->config & OMAP_DSS_LCD_ONOFF)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_ONOFF;
+}
+
+static int omap4fb_activate_var(struct fb_info *info)
+{
+ struct omap4fb_device *fbi =
+ container_of(info, struct omap4fb_device, info);
+ struct omap4_regs_dispc __iomem *dispc = fbi->regs.dispc;
+ struct fb_videomode const *mode = info->mode;
+ size_t size = mode->xres * mode->yres * (info->bits_per_pixel / 8);
+ int rc;
+ unsigned int fmt = omap4fb_calc_format(info);
+ struct omap4fb_colors const *cols;
+ size_t i;
+ struct omap4fb_display const *new_display = NULL;
+
+ for (i = 0; i < fbi->num_displays && new_display == NULL; ++i) {
+ if (strcmp(mode->name, fbi->displays[i].mode.name) == 0)
+ new_display = &fbi->displays[i];
+ }
+
+ if (WARN_ON(!new_display)) {
+ dev_err(fbi->dev, "no matching display found for this mode '%s'\n",
+ mode->name);
+ rc = -ENXIO;
+ goto out;
+ }
+
+ if (fbi->prealloc_screen.addr == NULL) {
+ /* case 1: no preallocated screen */
+ free(info->screen_base);
+ info->screen_base = memalign(0x100, size);
+ } else if (fbi->prealloc_screen.size < size) {
+ /* case 2: preallocated screen, but too small */
+ dev_err(fbi->dev,
+ "allocated framebuffer too small (%zu < %zu)\n",
+ fbi->prealloc_screen.size, size);
+ rc = -ENOMEM;
+ goto out;
+ } else {
+ /* case 3: preallocated screen */
+ info->screen_base = fbi->prealloc_screen.addr;
+ }
+
+ omap4fb_fill_shadow(fbi, new_display);
+
+ omap4fb_calc_divisor(fbi, mode);
+
+ switch (info->bits_per_pixel) {
+ case 24:
+ cols = &omap4fb_col[1];
+ break;
+ case 32:
+ cols = &omap4fb_col[2];
+ break;
+ default:
+ cols = &omap4fb_col[0];
+ }
+
+ info->red = cols->red;
+ info->green = cols->green;
+ info->blue = cols->blue;
+ info->transp = cols->transp;
+
+ fb_write(fbi->shadow.dispc_control,
+ &dispc->control2);
+
+ fb_write(fbi->shadow.dispc_pol_freq,
+ &dispc->pol_freq2);
+
+ fb_write(DSS_DISPC_TIMING_H_HSW(mode->hsync_len - 1) |
+ DSS_DISPC_TIMING_H_HFP(mode->right_margin - 1) |
+ DSS_DISPC_TIMING_H_HBP(mode->left_margin - 1),
+ &dispc->timing_h2);
+
+ fb_write(DSS_DISPC_TIMING_V_VSW(mode->vsync_len - 1) |
+ DSS_DISPC_TIMING_V_VFP(mode->lower_margin) |
+ DSS_DISPC_TIMING_V_VBP(mode->upper_margin),
+ &dispc->timing_v2);
+
+ fb_write(DSS_DISPC_DIVISOR_ENABLE | DSS_DISPC_DIVISOR_LCD(1),
+ &dispc->divisor);
+
+ fb_write(DSS_DISPC_DIVISOR2_LCD(fbi->divisor.lckd) |
+ DSS_DISPC_DIVISOR2_PCD(fbi->divisor.pckd),
+ &dispc->divisor2);
+
+ fb_write(DSS_DISPC_SIZE_LCD_PPL(mode->xres - 1) |
+ DSS_DISPC_SIZE_LCD_LPP(mode->yres - 1),
+ &dispc->size_lcd2);
+
+ fb_write(0x0000FF00, &dispc->default_color2);
+
+ /* we use VID1 */
+ fb_write((uintptr_t)info->screen_base, &dispc->vid1.ba[0]);
+ fb_write((uintptr_t)info->screen_base, &dispc->vid1.ba[1]);
+
+ fb_write(DSS_DISPC_VIDn_POSITION_VIDPOSX(0) |
+ DSS_DISPC_VIDn_POSITION_VIDPOSY(0),
+ &dispc->vid1.position);
+ fb_write(DSS_DISPC_VIDn_SIZE_VIDSIZEX(mode->xres - 1) |
+ DSS_DISPC_VIDn_SIZE_VIDSIZEY(mode->yres - 1),
+ &dispc->vid1.size);
+ fb_write(DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEX(mode->xres - 1) |
+ DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEY(mode->yres - 1),
+ &dispc->vid1.picture_size);
+ fb_write(1, &dispc->vid1.row_inc);
+ fb_write(1, &dispc->vid1.pixel_inc);
+
+ fb_write(0xfff, &dispc->vid_preload[0]);
+
+ fb_write(DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(fmt) |
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_8x128 |
+ DSS_DISPC_VIDn_ATTRIBUTES_ZORDERENABLE |
+ DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_SECONDARY_LCD,
+ &dispc->vid1.attributes);
+
+ while (fb_read(&dispc->control2) & DSS_DISPC_CONTROL_GOLCD)
+ ; /* noop */
+
+ fb_write(fb_read(&dispc->control2) |
+ DSS_DISPC_CONTROL_GOLCD,
+ &dispc->control2);
+
+ fbi->cur_display = new_display;
+ info->xres = mode->xres;
+ info->yres = mode->yres;
+
+ rc = 0;
+
+out:
+ return rc;
+}
+
+static void omap4fb_reset(struct omap4fb_device const *fbi)
+{
+ struct omap4_regs_dispc __iomem *dispc = fbi->regs.dispc;
+ struct omap4_regs_dss __iomem *dss = fbi->regs.dss;
+
+ uint32_t v = fb_read(&dispc->control2);
+
+ /* step 1: stop the LCD controller */
+ if (v & DSS_DISPC_CONTROL_LCDENABLE) {
+ fb_write(v & ~DSS_DISPC_CONTROL_LCDENABLE,
+ &dispc->control2);
+
+ fb_write(DSS_DISPC_IRQSTATUS_FRAMEDONE2, &dispc->irqstatus);
+
+ while ((fb_read(&dispc->irqstatus) &
+ DSS_DISPC_IRQSTATUS_FRAMEDONE) == 0)
+ ; /* noop */
+ }
+
+ /* step 2: wait for reset done status */
+ while (!(fb_read(&dss->sysstatus) & DSS_DSS_SYSSTATUS_RESETDONE))
+ ; /* noop */
+
+ /* DSS_CTL: set to reset value */
+ fb_write(0, &dss->ctrl);
+}
+
+static struct fb_ops omap4fb_ops = {
+ .fb_enable = omap4fb_enable,
+ .fb_disable = omap4fb_disable,
+ .fb_activate_var = omap4fb_activate_var,
+};
+
+static int omap4fb_probe(struct device_d *dev)
+{
+ struct omap4fb_platform_data const *pdata = dev->platform_data;
+ struct omap4fb_device *fbi;
+ struct fb_info *info;
+ struct omap4_regs_dispc __iomem *dispc;
+ struct omap4_regs_dss __iomem *dss;
+ int rc;
+ size_t i;
+
+ if (!pdata)
+ return -ENODEV;
+
+ fbi = xzalloc(sizeof *fbi +
+ pdata->num_displays * sizeof fbi->video_modes[0]);
+ info = &fbi->info;
+
+ fbi->dev = dev;
+
+ /* CM_DSS_CLKSTCTRL (TRM: 935) trigger SW_WKUP */
+ __raw_writel(0x2, 0x4a009100); /* TODO: move this to clockmanagement */
+
+ fbi->regs.dss = dev_request_mem_region(dev, OMAP4_FB_RESOURCE_DSS);
+ fbi->regs.dispc = dev_request_mem_region(dev, OMAP4_FB_RESOURCE_DISPC);
+
+ if (!fbi->regs.dss || !fbi->regs.dispc) {
+ dev_err(dev, "Insufficient register description\n");
+ rc = -EINVAL;
+ goto out;
+ }
+
+ dispc = fbi->regs.dispc;
+ dss = fbi->regs.dss;
+ dev_info(dev, "HW-Revision 0x%04x 0x%04x\n",
+ fb_read(&dispc->revision),
+ fb_read(&dss->revision));
+
+
+ if (!pdata->dss_clk_hz | !pdata->displays | !pdata->num_displays |
+ !pdata->bpp) {
+ dev_err(dev, "Insufficient omap4fb_platform_data\n");
+ rc = -EINVAL;
+ goto out;
+ }
+
+ fbi->enable_fn = pdata->enable;
+ fbi->displays = pdata->displays;
+ fbi->num_displays = pdata->num_displays;
+ fbi->divisor.dss_clk_hz = pdata->dss_clk_hz;
+
+ for (i = 0; i < pdata->num_displays; ++i)
+ fbi->video_modes[i] = pdata->displays[i].mode;
+
+ info->mode_list = fbi->video_modes;
+ info->num_modes = pdata->num_displays;
+
+ info->priv = fbi;
+ info->fbops = &omap4fb_ops;
+ info->bits_per_pixel = pdata->bpp;
+
+ if (pdata->screen) {
+ fbi->prealloc_screen.addr =
+ (void __iomem *)pdata->screen->start;
+ fbi->prealloc_screen.size = resource_size(pdata->screen);
+ }
+
+ omap4fb_reset(fbi);
+
+ dev_add_param(fbi->dev, "bootargs", NULL, NULL, 0);
+
+ rc = register_framebuffer(info);
+ if (rc < 0) {
+ dev_err(dev, "failed to register framebuffer: %d\n", rc);
+ goto out;
+ }
+
+ rc = 0;
+ dev_info(dev, "registered\n");
+
+out:
+ if (rc < 0)
+ free(fbi);
+
+ return rc;
+}
+
+static struct driver_d omap4fb_driver = {
+ .name = "omap4_fb",
+ .probe = omap4fb_probe,
+};
+
+static int omap4fb_init(void)
+{
+ return platform_driver_register(&omap4fb_driver);
+}
+
+device_initcall(omap4fb_init);
diff --git a/drivers/video/omap4.h b/drivers/video/omap4.h
new file mode 100644
index 0000000..b3364a5
--- /dev/null
+++ b/drivers/video/omap4.h
@@ -0,0 +1,408 @@
+/*
+ * TI Omap4 Frame Buffer device driver
+ *
+ * Copyright (C) 2013 Christoph Fritz <chf.fritz@googlemail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef H_BAREBOX_DRIVER_VIDEO_OMAP4_REGS_H
+#define H_BAREBOX_DRIVER_VIDEO_OMAP4_REGS_H
+
+#include <types.h>
+#include <common.h>
+
+#define OMAP4_RESERVED(_f, _t) \
+ uint32_t const reserved_ ## _f ## _ ## _t[((_t) - (_f)) / 4]
+
+
+/* TRM: 10.1.3.2 DSS Registers */
+struct omap4_regs_dss {
+ uint32_t revision;
+ OMAP4_RESERVED(0x4, 0x14);
+ uint32_t const sysstatus;
+ OMAP4_RESERVED(0x18, 0x40);
+ uint32_t ctrl;
+ OMAP4_RESERVED(0x44, 0x5C);
+ uint32_t const status;
+};
+
+
+struct omap4_regs_dispc_vid {
+ uint32_t ba[2];
+ uint32_t position;
+ uint32_t size;
+ uint32_t attributes;
+ uint32_t buf_threshold;
+ uint32_t const buf_size_status;
+ uint32_t row_inc;
+ uint32_t pixel_inc;
+ uint32_t fir;
+ uint32_t picture_size;
+ uint32_t accu[2];
+ struct {
+ uint32_t h;
+ uint32_t hv;
+ } fir_coef[8];
+ uint32_t conv_coef0;
+ uint32_t conv_coef1;
+ uint32_t conv_coef2;
+ uint32_t conv_coef3;
+ uint32_t conv_coef4;
+};
+
+/* TRM: 10.2.7.3 Display Controller Registers */
+struct omap4_regs_dispc {
+ uint32_t const revision;
+ OMAP4_RESERVED(0x04, 0x10);
+ uint32_t sysconfig;
+ uint32_t const sysstatus;
+ uint32_t irqstatus;
+ uint32_t irqenable;
+ OMAP4_RESERVED(0x20, 0x40);
+ uint32_t control1;
+ uint32_t config1;
+ OMAP4_RESERVED(0x48, 0x4C);
+
+ uint32_t default_color[2];
+ uint32_t trans_color[2];
+
+ uint32_t const line_status;
+ uint32_t line_number;
+ uint32_t timing_h1;
+ uint32_t timing_v1;
+ uint32_t pol_freq1;
+ uint32_t divisor1;
+ uint32_t global_alpha;
+ uint32_t size_tv;
+ uint32_t size_lcd1;
+
+ struct {
+ uint32_t ba[2];
+ uint32_t position;
+ uint32_t size;
+ OMAP4_RESERVED(0x90, 0xA0);
+ uint32_t attributes;
+ uint32_t buf_threshold;
+ uint32_t const buf_size_status;
+ uint32_t row_inc;
+ uint32_t pixel_inc;
+ OMAP4_RESERVED(0xB4, 0xB8);
+ uint32_t table_ba;
+ } gfx;
+
+ struct omap4_regs_dispc_vid vid1;
+ OMAP4_RESERVED(0x144, 0x14C);
+ struct omap4_regs_dispc_vid vid2;
+
+ uint32_t data1_cycle[3];
+
+ uint32_t vid1_fir_coef_v[8];
+ uint32_t vid2_fir_coef_v[8];
+ uint32_t cpr1_coef_r;
+ uint32_t cpr1_coef_g;
+ uint32_t cpr1_coef_b;
+ uint32_t gfx_preload;
+ uint32_t vid_preload[2];
+ uint32_t control2;
+ OMAP4_RESERVED(0x23C, 0x300);
+
+ struct {
+ uint32_t accu[2];
+ uint32_t ba[2];
+ struct {
+ uint32_t h;
+ uint32_t hv;
+ } fir_coef[8];
+ uint32_t fir_coef_v[8];
+ uint32_t attributes;
+ uint32_t conv_coef0;
+ uint32_t conv_coef1;
+ uint32_t conv_coef2;
+ uint32_t conv_coef3;
+ uint32_t conv_coef4;
+ uint32_t const buf_size_status;
+ uint32_t buf_threshold;
+ uint32_t fir;
+ uint32_t picture_size;
+ uint32_t pixel_inc;
+ uint32_t position;
+ uint32_t preload;
+ uint32_t row_inc;
+ uint32_t size;
+ } vid3;
+
+ uint32_t default_color2;
+ uint32_t trans_color2;
+ uint32_t cpr2_coef_b;
+ uint32_t cpr2_coef_g;
+ uint32_t cpr2_coef_r;
+ uint32_t data2_cycle[3];
+ uint32_t size_lcd2;
+ OMAP4_RESERVED(0x3D0, 0x400);
+ uint32_t timing_h2;
+ uint32_t timing_v2;
+ uint32_t pol_freq2;
+ uint32_t divisor2;
+ OMAP4_RESERVED(0x410, 0x500);
+
+ struct {
+ uint32_t accu[2];
+ uint32_t ba[2];
+ struct {
+ uint32_t h;
+ uint32_t hv;
+ } fir_coef[8];
+ uint32_t fir_coef_v[8];
+ uint32_t attributes;
+ uint32_t conv_coef0;
+ uint32_t conv_coef1;
+ uint32_t conv_coef2;
+ uint32_t conv_coef3;
+ uint32_t conv_coef4;
+ uint32_t const buf_size_status;
+ uint32_t buf_threshold;
+ uint32_t fir;
+ uint32_t picture_size;
+ uint32_t pixel_inc;
+ OMAP4_RESERVED(0x59C, 0x5A4);
+ uint32_t row_inc;
+ uint32_t size;
+ } wb;
+
+ OMAP4_RESERVED(0x5AC, 0x600);
+ uint32_t vid1_ba_uv[2];
+ uint32_t vid2_ba_uv[2];
+ uint32_t vid3_ba_uv[2];
+ uint32_t wb_ba_uv[2];
+ uint32_t config2;
+ uint32_t vid1_attributes2;
+ uint32_t vid2_attributes2;
+ uint32_t vid3_attributes2;
+ uint32_t gamma_table0;
+ uint32_t gamma_table1;
+ uint32_t gamma_table2;
+ uint32_t vid1_fir2;
+ uint32_t vid1_accu2[2];
+ struct {
+ uint32_t h2;
+ uint32_t hv2;
+ } vid1_fir_coef[8];
+ uint32_t vid1_fir_coef_v2[8];
+ uint32_t vid2_fir2;
+ uint32_t vid2_accu2[2];
+ struct {
+ uint32_t h2;
+ uint32_t hv2;
+ } vid2_fir_coef[8];
+ uint32_t vid2_fir_coef_v2[8];
+ OMAP4_RESERVED(0x714, 0x724);
+ uint32_t vid3_fir2;
+ uint32_t vid3_accu2[2];
+ struct {
+ uint32_t h2;
+ uint32_t hv2;
+ } vid3_fir_coef[8];
+ uint32_t vid3_fir_coef_v2[8];
+ uint32_t wb_fir2;
+ uint32_t wb_accu2[2];
+ OMAP4_RESERVED(0x79C, 0x7A0);
+ struct {
+ uint32_t h2;
+ uint32_t hv2;
+ } wb_fir_coef[8];
+ uint32_t wb_fir_coef_v2[8];
+ uint32_t global_buffer;
+ uint32_t divisor;
+ OMAP4_RESERVED(0x808, 0x810);
+ uint32_t wb_attributes2;
+};
+
+#define DSS_DISPC_VIDn_POSITION_VIDPOSX(_x) ((_x) << 0)
+#define DSS_DISPC_VIDn_POSITION_VIDPOSY(_y) ((_y) << 16)
+
+#define DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEX(_x) ((_x) << 0)
+#define DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEY(_y) ((_y) << 16)
+
+#define DSS_DISPC_VIDn_SIZE_VIDSIZEX(_x) ((_x) << 0)
+#define DSS_DISPC_VIDn_SIZE_VIDSIZEY(_y) ((_y) << 16)
+
+#define DSS_DISPC_SIZE_LCD_PPL(_x) ((_x) << 0)
+#define DSS_DISPC_SIZE_LCD_LPP(_y) ((_y) << 16)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE (1u << 0)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(_fmt) ((_fmt) << 1)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB12 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(4u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB16 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(5u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB16 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(6u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB16o \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(7u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_xRGB24u \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(8u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB24p \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(9u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_YUV2 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(10u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_UYVY \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(11u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB32 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(12u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGBA32 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(13u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_xRGB32 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(14u)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE(_f) ((_f) << 5)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE_NONE \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE(0u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE_H \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE(1u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE_V \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE(2u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE_HV \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE(3u)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDCOLORCONVENABLE (1u << 9)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDREPLICATIONENABLE (1u << 10)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFULLRANGE (1u << 11)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION(_r) ((_r) << 12)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION_0 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION(0u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION_90 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION(1u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION_180 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION(2u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION_270 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION(3u)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(_b) ((_b) << 14)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_2x128 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(0u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_4x128 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(1u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_8x128 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(2u)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDCHANNELOUT (1u << 16)
+#define DSS_DISPC_VIDn_ATTRIBUTES_SELFREFRESHAUTO (1u << 17)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFIFOPRELOAD (1u << 19)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDVERTICALTAPS (1u << 21)
+#define DSS_DISPC_VIDn_ATTRIBUTES_DOUBLESTRIDE (1u << 22)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDARBITRATION (1u << 23)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDSELFREFRESH (1u << 24)
+#define DSS_DISPC_VIDn_ATTRIBUTES_ZORDERENABLE (1u << 25)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(_b) ((_b) << 30)
+#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_PRIMARY_LCD \
+ DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(0u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_SECONDARY_LCD \
+ DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(1u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_WRITEBACK_MEM \
+ DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(3u)
+
+#define DSS_DISPC_CONFIG_PIXELGATED (1u << 0)
+#define DSS_DISPC_CONFIG_PIXELDATAGATED (1u << 4)
+#define DSS_DISPC_CONFIG_PIXELCLOCKGATED (1u << 5)
+#define DSS_DISPC_CONFIG_HSYNCGATED (1u << 6)
+#define DSS_DISPC_CONFIG_VSYNCGATED (1u << 7)
+#define DSS_DISPC_CONFIG_ACBIASGATED (1u << 8)
+#define DSS_DISPC_CONFIG_FUNCGATED (1u << 9)
+#define DSS_DISPC_CONFIG_TCKLCDENABLE (1u << 10)
+#define DSS_DISPC_CONFIG_TCKLCDSELECTION (1u << 11)
+#define DSS_DISPC_CONFIG_CPR (1u << 15)
+#define DSS_DISPC_CONFIG_FIFOHANDCHECK (1u << 16)
+#define DSS_DISPC_CONFIG_OUTPUTMODE (1u << 22)
+#define DSS_DISPC_CONFIG_FIDFIRST (1u << 23)
+#define DSS_DISPC_CONFIG_COLORCONV (1u << 24)
+#define DSS_DISPC_CONFIG_FULLRANGE (1u << 25)
+
+#define DSS_DISPC_CONTROL_LCDENABLE (1u << 0)
+#define DSS_DISPC_CONTROL_TVENABLE (1u << 1)
+#define DSS_DISPC_CONTROL_MONOCOLOR (1u << 2)
+#define DSS_DISPC_CONTROL_STNTFT (1u << 3)
+#define DSS_DISPC_CONTROL_M8B (1u << 4)
+#define DSS_DISPC_CONTROL_GOLCD (1u << 5)
+#define DSS_DISPC_CONTROL_GOTV (1u << 6)
+#define DSS_DISPC_CONTROL_STDITHERENABLE (1u << 7)
+
+#define DSS_DISPC_CONTROL_TFTDATALINES(_l) ((_l) << 8)
+#define DSS_DISPC_CONTROL_TFTDATALINES_12 \
+ DSS_DISPC_CONTROL_TFTDATALINES(0u)
+#define DSS_DISPC_CONTROL_TFTDATALINES_16 \
+ DSS_DISPC_CONTROL_TFTDATALINES(1u)
+#define DSS_DISPC_CONTROL_TFTDATALINES_18 \
+ DSS_DISPC_CONTROL_TFTDATALINES(2u)
+#define DSS_DISPC_CONTROL_TFTDATALINES_24 \
+ DSS_DISPC_CONTROL_TFTDATALINES(3u)
+
+#define DSS_DISPC_CONTROL_STALLMODE (1u << 11)
+#define DSS_DISPC_CONTROL_OVERLAYOPTIMIZATION (1u << 12)
+#define DSS_DISPC_CONTROL_GPIN0 (1u << 13) /* ro */
+#define DSS_DISPC_CONTROL_GPIN1 (1u << 14) /* ro */
+#define DSS_DISPC_CONTROL_GPOUT0 (1u << 15)
+#define DSS_DISPC_CONTROL_GPOUT1 (1u << 16)
+#define DSS_DISPC_CONTROL_HT(_ht) ((_ht) << 17)
+#define DSS_DISPC_CONTROL_TDMENABLE (1u << 20)
+#define DSS_DISPC_CONTROL_TDMPARALLELMODE(_pm) ((_pm) << 21)
+#define DSS_DISPC_CONTROL_TDMCYCLEFORMAT(_cf) ((_cf) << 23)
+#define DSS_DISPC_CONTROL_TDMUNUSEDBITS(_ub) ((_ub) << 25)
+#define DSS_DISPC_CONTROL_PCKFREEENABLE (1u << 27)
+#define DSS_DISPC_CONTROL_LCDENABLESIGNAL (1u << 28)
+#define DSS_DISPC_CONTROL_LCDENABLEPOL (1u << 29)
+#define DSS_DISPC_CONTROL_SPATIALTEMPD(_df) ((_df) << 30)
+
+#define DSS_DISPC_POL_FREQ_IVS (1u << 12)
+#define DSS_DISPC_POL_FREQ_IHS (1u << 13)
+#define DSS_DISPC_POL_FREQ_IPC (1u << 14)
+#define DSS_DISPC_POL_FREQ_IEO (1u << 15)
+#define DSS_DISPC_POL_FREQ_RF (1u << 16)
+#define DSS_DISPC_POL_FREQ_ONOFF (1u << 17)
+
+#define DSS_DISPC_TIMING_H_HSW(_hsw) ((_hsw) << 0)
+#define DSS_DISPC_TIMING_H_HFP(_hfp) ((_hfp) << 8)
+#define DSS_DISPC_TIMING_H_HBP(_hbp) ((_hbp) << 20)
+
+#define DSS_DISPC_TIMING_V_VSW(_vsw) ((_vsw) << 0)
+#define DSS_DISPC_TIMING_V_VFP(_vfp) ((_vfp) << 8)
+#define DSS_DISPC_TIMING_V_VBP(_vbp) ((_vbp) << 20)
+
+#define DSS_DISPC_DIVISOR_ENABLE (1u << 0)
+#define DSS_DISPC_DIVISOR_LCD(_lcd) ((_lcd) << 16)
+
+#define DSS_DISPC_DIVISOR2_PCD(_pcd) ((_pcd) << 0)
+#define DSS_DISPC_DIVISOR2_LCD(_lcd) ((_lcd) << 16)
+
+#define DSS_DISPC_IRQSTATUS_FRAMEDONE (1u << 0)
+#define DSS_DISPC_IRQSTATUS_FRAMEDONE2 (1u << 22)
+
+#define DSS_DSS_SYSCONFIG_SOFTRESET (1u << 1)
+#define DSS_DSS_SYSSTATUS_RESETDONE (1u << 0)
+
+#define DSS_DSS_CONTROL_DISPC_CLK_SWITCH (1u << 0)
+#define DSS_DSS_CONTROL_DSI_CLK_SWITCH (1u << 1)
+
+#define CM_FCLKEN_DSS_EN_DSS1 (1u << 0)
+#define CM_FCLKEN_DSS_EN_DSS2 (1u << 1)
+#define CM_FCLKEN_DSS_EN_TV (1u << 2)
+
+#define CM_ICLKEN_DSS_EN_DSS (1u << 0)
+
+
+#undef OMAP4_RESERVED
+
+#endif /* H_BAREBOX_DRIVER_VIDEO_OMAP4_REGS_H */
--
1.7.10.4
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2] omap4-fb: add driver
2013-04-07 22:15 ` [PATCH v2] " Christoph Fritz
@ 2013-04-08 7:17 ` Jean-Christophe PLAGNIOL-VILLARD
2013-04-09 7:16 ` Sascha Hauer
0 siblings, 1 reply; 24+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2013-04-08 7:17 UTC (permalink / raw)
To: Christoph Fritz; +Cc: barebox
On 00:15 Mon 08 Apr , Christoph Fritz wrote:
> This patch adds omap4 display controller support.
>
> Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
> ---
> arch/arm/mach-omap/Makefile | 1 +
> arch/arm/mach-omap/include/mach/omap4-fb.h | 52 +++
> arch/arm/mach-omap/omap4_fb.c | 29 ++
> drivers/video/Kconfig | 8 +
> drivers/video/Makefile | 1 +
> drivers/video/omap4.c | 507 ++++++++++++++++++++++++++++
> drivers/video/omap4.h | 408 ++++++++++++++++++++++
> 7 files changed, 1006 insertions(+)
> create mode 100644 arch/arm/mach-omap/include/mach/omap4-fb.h
> create mode 100644 arch/arm/mach-omap/omap4_fb.c
> create mode 100644 drivers/video/omap4.c
> create mode 100644 drivers/video/omap4.h
>
> diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile
> index 94e42c6..e70ddbd 100644
> --- a/arch/arm/mach-omap/Makefile
> +++ b/arch/arm/mach-omap/Makefile
> @@ -28,6 +28,7 @@ obj-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
> pbl-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
> obj-$(CONFIG_OMAP_GPMC) += gpmc.o devices-gpmc-nand.o
> obj-$(CONFIG_SHELL_NONE) += xload.o
> +obj-$(CONFIG_DRIVER_VIDEO_OMAP4) += omap4_fb.o
> obj-$(CONFIG_I2C_TWL6030) += omap4_twl6030_mmc.o
> obj-$(CONFIG_OMAP4_USBBOOT) += omap4_rom_usb.o
> obj-y += gpio.o
> diff --git a/arch/arm/mach-omap/include/mach/omap4-fb.h b/arch/arm/mach-omap/include/mach/omap4-fb.h
> new file mode 100644
> index 0000000..bb4c8e9
> --- /dev/null
> +++ b/arch/arm/mach-omap/include/mach/omap4-fb.h
> @@ -0,0 +1,52 @@
> +#ifndef H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H
> +#define H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H
> +
> +#include <fb.h>
> +
> +/* device resource index */
> +enum {
> + OMAP4_FB_RESOURCE_DSS,
> + OMAP4_FB_RESOURCE_DISPC,
> +};
> +
> +#define OMAP_DSS_LCD_TFT (1u << 0)
> +#define OMAP_DSS_LCD_IVS (1u << 1)
> +#define OMAP_DSS_LCD_IHS (1u << 2)
> +#define OMAP_DSS_LCD_IPC (1u << 3)
> +#define OMAP_DSS_LCD_IEO (1u << 4)
> +#define OMAP_DSS_LCD_RF (1u << 5)
> +#define OMAP_DSS_LCD_ONOFF (1u << 6)
> +
> +#define OMAP_DSS_LCD_DATALINES(_l) ((_l) << 10)
> +#define OMAP_DSS_LCD_DATALINES_msk OMAP_DSS_LCD_DATALINES(3u)
> +#define OMAP_DSS_LCD_DATALINES_12 OMAP_DSS_LCD_DATALINES(0u)
> +#define OMAP_DSS_LCD_DATALINES_16 OMAP_DSS_LCD_DATALINES(1u)
> +#define OMAP_DSS_LCD_DATALINES_18 OMAP_DSS_LCD_DATALINES(2u)
> +#define OMAP_DSS_LCD_DATALINES_24 OMAP_DSS_LCD_DATALINES(3u)
> +
> +struct omap4fb_display {
> + struct fb_videomode mode;
> +
> + unsigned long config;
> +
> + unsigned int power_on_delay;
> + unsigned int power_off_delay;
> +};
> +
> +struct omap4fb_platform_data {
> + struct omap4fb_display const *displays;
> + size_t num_displays;
> +
> + unsigned int dss_clk_hz;
> +
> + unsigned int bpp;
> +
> + struct resource const *screen;
> +
> + void (*enable)(int p);
> +};
> +
> +struct device_d;
> +struct device_d *omap4_add_display(void *pdata);
> +
> +#endif /* H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H */
> diff --git a/arch/arm/mach-omap/omap4_fb.c b/arch/arm/mach-omap/omap4_fb.c
> new file mode 100644
> index 0000000..70fbab6
> --- /dev/null
> +++ b/arch/arm/mach-omap/omap4_fb.c
> @@ -0,0 +1,29 @@
> +#include <driver.h>
> +#include <common.h>
> +#include <linux/ioport.h>
> +#include <mach/omap4-fb.h>
> +
> +static struct resource omap4_fb_resources[] = {
> + [OMAP4_FB_RESOURCE_DSS] = {
> + .start = 0x48040000,
> + .end = 0x48040000 + 512 - 1,
> + .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
> + .name = "DSS",
> + },
> +
> + [OMAP4_FB_RESOURCE_DISPC] = {
> + .start = 0x48041000,
> + .end = 0x48041000 + 3072 - 1,
> + .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
> + .name = "DISPC",
> + },
> +};
> +
> +struct device_d *omap4_add_display(void *pdata)
> +{
> + return add_generic_device_res("omap4_fb", -1,
> + omap4_fb_resources,
> + ARRAY_SIZE(omap4_fb_resources),
> + pdata);
> +}
> +EXPORT_SYMBOL(omap4_add_display);
> diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
> index 6d6b08f..9dfa0cd 100644
> --- a/drivers/video/Kconfig
> +++ b/drivers/video/Kconfig
> @@ -45,6 +45,14 @@ config DRIVER_VIDEO_S3C24XX
> help
> Add support for the S3C244x LCD controller.
>
> +config DRIVER_VIDEO_OMAP4
> + bool "OMAP4 framebuffer driver"
> + depends on ARCH_OMAP4
> + help
> + Add support for the OMAP4 Display Controller.
> + DSI is unsupported, only DISPC parallel mode on LCD2
> + is supported.
> +
> if DRIVER_VIDEO_S3C24XX
>
> config DRIVER_VIDEO_S3C_VERBOSE
> diff --git a/drivers/video/Makefile b/drivers/video/Makefile
> index 7429141..83feebb 100644
> --- a/drivers/video/Makefile
> +++ b/drivers/video/Makefile
> @@ -8,3 +8,4 @@ obj-$(CONFIG_DRIVER_VIDEO_IMX_IPU) += imx-ipu-fb.o
> obj-$(CONFIG_DRIVER_VIDEO_S3C24XX) += s3c24xx.o
> obj-$(CONFIG_DRIVER_VIDEO_PXA) += pxa.o
> obj-$(CONFIG_DRIVER_VIDEO_SDL) += sdl.o
> +obj-$(CONFIG_DRIVER_VIDEO_OMAP4) += omap4.o
> diff --git a/drivers/video/omap4.c b/drivers/video/omap4.c
> new file mode 100644
> index 0000000..23c64d0
> --- /dev/null
> +++ b/drivers/video/omap4.c
> @@ -0,0 +1,507 @@
> +/*
> + * TI Omap4 Frame Buffer device driver
> + *
> + * Copyright (C) 2013 Christoph Fritz <chf.fritz@googlemail.com>
> + * Based on work by Enrico Scholz, sponsored by Phytec
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <driver.h>
> +#include <fb.h>
> +#include <errno.h>
> +#include <xfuncs.h>
> +#include <init.h>
> +#include <stdio.h>
> +#include <io.h>
> +#include <common.h>
> +#include <malloc.h>
> +#include <common.h>
> +#include <clock.h>
> +
> +#include <mach/omap4-silicon.h>
> +#include <mach/omap4-fb.h>
> +
> +#include "omap4.h"
> +
> +struct omap4fb_device {
> + struct fb_info info;
> + struct device_d *dev;
> +
> + struct omap4fb_display const *cur_display;
> +
> + struct omap4fb_display const *displays;
> + size_t num_displays;
> +
> + struct {
> + struct omap4_regs_dss __iomem *dss;
> + struct omap4_regs_dispc __iomem *dispc;
> + } regs;
please drop those non-sense regs struct
> +
> + struct {
> + void __iomem *addr;
> + size_t size;
> + } prealloc_screen;
> +
> + struct {
> + uint32_t dispc_control;
> + uint32_t dispc_pol_freq;
> + } shadow;
> +
> + struct {
> + unsigned int dss_clk_hz;
> + unsigned int lckd;
> + unsigned int pckd;
> + } divisor;
> +
> + void (*enable_fn)(int);
> +
> + struct fb_videomode video_modes[];
> +};
> +
> +static inline void fb_write(uint32_t v, void __iomem *addr)
> +{
> + __raw_writel(v, addr);
> +}
> +
> +static inline uint32_t fb_read(void const __iomem *addr)
> +{
> + return __raw_readl(addr);
> +}
what is the dif?
> +
> +static void omap4fb_enable(struct fb_info *info)
> +{
> + struct omap4fb_device *fbi =
> + container_of(info, struct omap4fb_device, info);
> + struct omap4_regs_dispc __iomem *dispc = fbi->regs.dispc;
> +
> + dev_info(fbi->dev, "%s\n", __func__);
> +
> + if (!fbi->cur_display) {
> + dev_err(fbi->dev, "no valid mode set\n");
> + return;
> + }
> +
> + if (fbi->enable_fn)
> + fbi->enable_fn(1);
> +
> + udelay(fbi->cur_display->power_on_delay * 1000u);
mdelay
> +
> + fb_write(fb_read(&dispc->control2) |
> + DSS_DISPC_CONTROL_LCDENABLE |
> + 1*DSS_DISPC_CONTROL_LCDENABLESIGNAL,
> + &dispc->control2);
> +
> + fb_write(fb_read(&dispc->vid1.attributes) |
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE,
> + &dispc->vid1.attributes);
> +
> + fb_write(fb_read(&dispc->control2) |
> + DSS_DISPC_CONTROL_GOLCD,
> + &dispc->control2);
> +}
> +
> +static void omap4fb_disable(struct fb_info *info)
> +{
> + struct omap4fb_device *fbi =
> + container_of(info, struct omap4fb_device, info);
> + struct omap4_regs_dispc __iomem *dispc = fbi->regs.dispc;
> +
> + dev_info(fbi->dev, "%s\n", __func__);
> +
> + if (!fbi->cur_display) {
> + dev_err(fbi->dev, "no valid mode set\n");
> + return;
> + }
> +
> + fb_write(fb_read(&dispc->control2) &
> + ~(DSS_DISPC_CONTROL_LCDENABLE |
> + DSS_DISPC_CONTROL_LCDENABLESIGNAL),
> + &dispc->control2);
> +
> + fb_write(fb_read(&dispc->vid1.attributes) &
> + ~(DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE),
> + &dispc->vid1.attributes);
> +
> + if (fbi->prealloc_screen.addr == NULL)
> + /* free frame buffer; but only when screen is not
> + * preallocated */
> + free(info->screen_base);
> +
> + info->screen_base = NULL;
> +
> + udelay(fbi->cur_display->power_off_delay * 1000u);
> +
> + if (fbi->enable_fn)
> + fbi->enable_fn(0);
> +}
> +
> +static void omap4fb_calc_divisor(struct omap4fb_device *fbi,
> + struct fb_videomode const *mode)
> +{
> + unsigned int l, k, t, b;
> +
> + b = UINT_MAX;
> + for (l = 1; l < 256; l++) {
> + for (k = 1; k < 256; k++) {
> + t = abs(mode->pixclock * 100 -
> + (fbi->divisor.dss_clk_hz / l / k));
> + if (t <= b) {
> + b = t;
> + fbi->divisor.lckd = l;
> + fbi->divisor.pckd = k;
> + }
> + }
> + }
> +}
> +
> +static unsigned int omap4fb_calc_format(struct fb_info const *info)
> +{
> + switch (info->bits_per_pixel) {
> + case 24: return 9;
> + case 32: return 0x8; /* xRGB24-8888 (32-bit container) */
> + default:
> + printf("%s: unsupported bpp %d\n", __func__,
> + info->bits_per_pixel);
> + return 0;
> + }
> +}
> +
> +struct omap4fb_colors {
> + struct fb_bitfield red;
> + struct fb_bitfield green;
> + struct fb_bitfield blue;
> + struct fb_bitfield transp;
> +};
> +
> +static struct omap4fb_colors const omap4fb_col[] = {
> + [0] = {
> + .red = { .length = 0, .offset = 0 },
> + },
> + [1] = {
> + .blue = { .length = 8, .offset = 0 },
> + .green = { .length = 8, .offset = 8 },
> + .red = { .length = 8, .offset = 16 },
> + },
> + [2] = {
> + .blue = { .length = 8, .offset = 0 },
> + .green = { .length = 8, .offset = 8 },
> + .red = { .length = 8, .offset = 16 },
> + .transp = { .length = 8, .offset = 24 },
> + },
> +};
> +
> +static void omap4fb_fill_shadow(struct omap4fb_device *fbi,
> + struct omap4fb_display const *display)
> +{
> + fbi->shadow.dispc_control = 0;
> + fbi->shadow.dispc_pol_freq = 0;
> +
> + fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_STNTFT;
> +
> + switch (display->config & OMAP_DSS_LCD_DATALINES_msk) {
> + case OMAP_DSS_LCD_DATALINES_12:
> + fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_12;
> + break;
> + case OMAP_DSS_LCD_DATALINES_16:
> + fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_16;
> + break;
> + case OMAP_DSS_LCD_DATALINES_18:
> + fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_18;
> + break;
> + case OMAP_DSS_LCD_DATALINES_24:
> + fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_24;
> + break;
> + }
> +
> + if (display->config & OMAP_DSS_LCD_IPC)
> + fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IPC;
> +
> + if (display->config & OMAP_DSS_LCD_IVS)
> + fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IVS;
> +
> + if (display->config & OMAP_DSS_LCD_IHS)
> + fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IHS;
> +
> + if (display->config & OMAP_DSS_LCD_IEO)
> + fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IEO;
> +
> + if (display->config & OMAP_DSS_LCD_RF)
> + fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_RF;
> +
> + if (display->config & OMAP_DSS_LCD_ONOFF)
> + fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_ONOFF;
> +}
> +
> +static int omap4fb_activate_var(struct fb_info *info)
> +{
> + struct omap4fb_device *fbi =
> + container_of(info, struct omap4fb_device, info);
> + struct omap4_regs_dispc __iomem *dispc = fbi->regs.dispc;
> + struct fb_videomode const *mode = info->mode;
> + size_t size = mode->xres * mode->yres * (info->bits_per_pixel / 8);
> + int rc;
> + unsigned int fmt = omap4fb_calc_format(info);
> + struct omap4fb_colors const *cols;
> + size_t i;
> + struct omap4fb_display const *new_display = NULL;
> +
> + for (i = 0; i < fbi->num_displays && new_display == NULL; ++i) {
> + if (strcmp(mode->name, fbi->displays[i].mode.name) == 0)
> + new_display = &fbi->displays[i];
> + }
> +
> + if (WARN_ON(!new_display)) {
> + dev_err(fbi->dev, "no matching display found for this mode '%s'\n",
> + mode->name);
> + rc = -ENXIO;
> + goto out;
> + }
> +
> + if (fbi->prealloc_screen.addr == NULL) {
> + /* case 1: no preallocated screen */
> + free(info->screen_base);
> + info->screen_base = memalign(0x100, size);
> + } else if (fbi->prealloc_screen.size < size) {
> + /* case 2: preallocated screen, but too small */
> + dev_err(fbi->dev,
> + "allocated framebuffer too small (%zu < %zu)\n",
> + fbi->prealloc_screen.size, size);
> + rc = -ENOMEM;
> + goto out;
> + } else {
> + /* case 3: preallocated screen */
> + info->screen_base = fbi->prealloc_screen.addr;
> + }
> +
> + omap4fb_fill_shadow(fbi, new_display);
> +
> + omap4fb_calc_divisor(fbi, mode);
> +
> + switch (info->bits_per_pixel) {
> + case 24:
> + cols = &omap4fb_col[1];
> + break;
> + case 32:
> + cols = &omap4fb_col[2];
> + break;
> + default:
> + cols = &omap4fb_col[0];
> + }
> +
> + info->red = cols->red;
> + info->green = cols->green;
> + info->blue = cols->blue;
> + info->transp = cols->transp;
> +
> + fb_write(fbi->shadow.dispc_control,
> + &dispc->control2);
> +
> + fb_write(fbi->shadow.dispc_pol_freq,
> + &dispc->pol_freq2);
> +
> + fb_write(DSS_DISPC_TIMING_H_HSW(mode->hsync_len - 1) |
> + DSS_DISPC_TIMING_H_HFP(mode->right_margin - 1) |
> + DSS_DISPC_TIMING_H_HBP(mode->left_margin - 1),
> + &dispc->timing_h2);
> +
> + fb_write(DSS_DISPC_TIMING_V_VSW(mode->vsync_len - 1) |
> + DSS_DISPC_TIMING_V_VFP(mode->lower_margin) |
> + DSS_DISPC_TIMING_V_VBP(mode->upper_margin),
> + &dispc->timing_v2);
> +
> + fb_write(DSS_DISPC_DIVISOR_ENABLE | DSS_DISPC_DIVISOR_LCD(1),
> + &dispc->divisor);
> +
> + fb_write(DSS_DISPC_DIVISOR2_LCD(fbi->divisor.lckd) |
> + DSS_DISPC_DIVISOR2_PCD(fbi->divisor.pckd),
> + &dispc->divisor2);
> +
> + fb_write(DSS_DISPC_SIZE_LCD_PPL(mode->xres - 1) |
> + DSS_DISPC_SIZE_LCD_LPP(mode->yres - 1),
> + &dispc->size_lcd2);
> +
> + fb_write(0x0000FF00, &dispc->default_color2);
> +
> + /* we use VID1 */
> + fb_write((uintptr_t)info->screen_base, &dispc->vid1.ba[0]);
> + fb_write((uintptr_t)info->screen_base, &dispc->vid1.ba[1]);
> +
> + fb_write(DSS_DISPC_VIDn_POSITION_VIDPOSX(0) |
> + DSS_DISPC_VIDn_POSITION_VIDPOSY(0),
> + &dispc->vid1.position);
> + fb_write(DSS_DISPC_VIDn_SIZE_VIDSIZEX(mode->xres - 1) |
> + DSS_DISPC_VIDn_SIZE_VIDSIZEY(mode->yres - 1),
> + &dispc->vid1.size);
> + fb_write(DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEX(mode->xres - 1) |
> + DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEY(mode->yres - 1),
> + &dispc->vid1.picture_size);
> + fb_write(1, &dispc->vid1.row_inc);
> + fb_write(1, &dispc->vid1.pixel_inc);
> +
> + fb_write(0xfff, &dispc->vid_preload[0]);
> +
> + fb_write(DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(fmt) |
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_8x128 |
> + DSS_DISPC_VIDn_ATTRIBUTES_ZORDERENABLE |
> + DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_SECONDARY_LCD,
> + &dispc->vid1.attributes);
> +
> + while (fb_read(&dispc->control2) & DSS_DISPC_CONTROL_GOLCD)
> + ; /* noop */
> +
> + fb_write(fb_read(&dispc->control2) |
> + DSS_DISPC_CONTROL_GOLCD,
> + &dispc->control2);
> +
> + fbi->cur_display = new_display;
> + info->xres = mode->xres;
> + info->yres = mode->yres;
> +
> + rc = 0;
> +
> +out:
> + return rc;
> +}
> +
> +static void omap4fb_reset(struct omap4fb_device const *fbi)
> +{
> + struct omap4_regs_dispc __iomem *dispc = fbi->regs.dispc;
> + struct omap4_regs_dss __iomem *dss = fbi->regs.dss;
> +
> + uint32_t v = fb_read(&dispc->control2);
> +
> + /* step 1: stop the LCD controller */
> + if (v & DSS_DISPC_CONTROL_LCDENABLE) {
> + fb_write(v & ~DSS_DISPC_CONTROL_LCDENABLE,
> + &dispc->control2);
> +
> + fb_write(DSS_DISPC_IRQSTATUS_FRAMEDONE2, &dispc->irqstatus);
> +
> + while ((fb_read(&dispc->irqstatus) &
> + DSS_DISPC_IRQSTATUS_FRAMEDONE) == 0)
> + ; /* noop */
> + }
> +
> + /* step 2: wait for reset done status */
> + while (!(fb_read(&dss->sysstatus) & DSS_DSS_SYSSTATUS_RESETDONE))
> + ; /* noop */
> +
> + /* DSS_CTL: set to reset value */
> + fb_write(0, &dss->ctrl);
> +}
> +
> +static struct fb_ops omap4fb_ops = {
> + .fb_enable = omap4fb_enable,
> + .fb_disable = omap4fb_disable,
> + .fb_activate_var = omap4fb_activate_var,
> +};
> +
> +static int omap4fb_probe(struct device_d *dev)
> +{
> + struct omap4fb_platform_data const *pdata = dev->platform_data;
> + struct omap4fb_device *fbi;
> + struct fb_info *info;
> + struct omap4_regs_dispc __iomem *dispc;
> + struct omap4_regs_dss __iomem *dss;
> + int rc;
> + size_t i;
> +
> + if (!pdata)
> + return -ENODEV;
> +
> + fbi = xzalloc(sizeof *fbi +
> + pdata->num_displays * sizeof fbi->video_modes[0]);
> + info = &fbi->info;
> +
> + fbi->dev = dev;
> +
> + /* CM_DSS_CLKSTCTRL (TRM: 935) trigger SW_WKUP */
> + __raw_writel(0x2, 0x4a009100); /* TODO: move this to clockmanagement */
> +
> + fbi->regs.dss = dev_request_mem_region(dev, OMAP4_FB_RESOURCE_DSS);
> + fbi->regs.dispc = dev_request_mem_region(dev, OMAP4_FB_RESOURCE_DISPC);
use named dev_request
> +
> + if (!fbi->regs.dss || !fbi->regs.dispc) {
> + dev_err(dev, "Insufficient register description\n");
> + rc = -EINVAL;
> + goto out;
> + }
> +
> + dispc = fbi->regs.dispc;
> + dss = fbi->regs.dss;
> + dev_info(dev, "HW-Revision 0x%04x 0x%04x\n",
> + fb_read(&dispc->revision),
> + fb_read(&dss->revision));
> +
> +
> + if (!pdata->dss_clk_hz | !pdata->displays | !pdata->num_displays |
> + !pdata->bpp) {
> + dev_err(dev, "Insufficient omap4fb_platform_data\n");
> + rc = -EINVAL;
> + goto out;
> + }
> +
> + fbi->enable_fn = pdata->enable;
> + fbi->displays = pdata->displays;
> + fbi->num_displays = pdata->num_displays;
> + fbi->divisor.dss_clk_hz = pdata->dss_clk_hz;
why via pdata?
> +
> + for (i = 0; i < pdata->num_displays; ++i)
> + fbi->video_modes[i] = pdata->displays[i].mode;
> +
> + info->mode_list = fbi->video_modes;
> + info->num_modes = pdata->num_displays;
> +
> + info->priv = fbi;
> + info->fbops = &omap4fb_ops;
> + info->bits_per_pixel = pdata->bpp;
> +
> + if (pdata->screen) {
> + fbi->prealloc_screen.addr =
> + (void __iomem *)pdata->screen->start;
> + fbi->prealloc_screen.size = resource_size(pdata->screen);
> + }
> +
> + omap4fb_reset(fbi);
> +
> + dev_add_param(fbi->dev, "bootargs", NULL, NULL, 0);
??
> +
> + rc = register_framebuffer(info);
> + if (rc < 0) {
> + dev_err(dev, "failed to register framebuffer: %d\n", rc);
> + goto out;
> + }
> +
> + rc = 0;
> + dev_info(dev, "registered\n");
> +
> +out:
> + if (rc < 0)
> + free(fbi);
> +
> + return rc;
> +}
> +
> +static struct driver_d omap4fb_driver = {
> + .name = "omap4_fb",
> + .probe = omap4fb_probe,
> +};
> +
> +static int omap4fb_init(void)
> +{
> + return platform_driver_register(&omap4fb_driver);
> +}
> +
> +device_initcall(omap4fb_init);
> diff --git a/drivers/video/omap4.h b/drivers/video/omap4.h
> new file mode 100644
> index 0000000..b3364a5
> --- /dev/null
> +++ b/drivers/video/omap4.h
> @@ -0,0 +1,408 @@
> +/*
> + * TI Omap4 Frame Buffer device driver
> + *
> + * Copyright (C) 2013 Christoph Fritz <chf.fritz@googlemail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef H_BAREBOX_DRIVER_VIDEO_OMAP4_REGS_H
> +#define H_BAREBOX_DRIVER_VIDEO_OMAP4_REGS_H
> +
> +#include <types.h>
> +#include <common.h>
> +
> +#define OMAP4_RESERVED(_f, _t) \
> + uint32_t const reserved_ ## _f ## _ ## _t[((_t) - (_f)) / 4]
> +
> +
> +/* TRM: 10.1.3.2 DSS Registers */
> +struct omap4_regs_dss {
> + uint32_t revision;
> + OMAP4_RESERVED(0x4, 0x14);
> + uint32_t const sysstatus;
> + OMAP4_RESERVED(0x18, 0x40);
> + uint32_t ctrl;
> + OMAP4_RESERVED(0x44, 0x5C);
> + uint32_t const status;
> +};
> +
> +
> +struct omap4_regs_dispc_vid {
> + uint32_t ba[2];
> + uint32_t position;
> + uint32_t size;
> + uint32_t attributes;
> + uint32_t buf_threshold;
> + uint32_t const buf_size_status;
> + uint32_t row_inc;
> + uint32_t pixel_inc;
> + uint32_t fir;
> + uint32_t picture_size;
> + uint32_t accu[2];
> + struct {
> + uint32_t h;
> + uint32_t hv;
> + } fir_coef[8];
> + uint32_t conv_coef0;
> + uint32_t conv_coef1;
> + uint32_t conv_coef2;
> + uint32_t conv_coef3;
> + uint32_t conv_coef4;
> +};
> +
> +/* TRM: 10.2.7.3 Display Controller Registers */
> +struct omap4_regs_dispc {
> + uint32_t const revision;
> + OMAP4_RESERVED(0x04, 0x10);
> + uint32_t sysconfig;
> + uint32_t const sysstatus;
> + uint32_t irqstatus;
> + uint32_t irqenable;
> + OMAP4_RESERVED(0x20, 0x40);
> + uint32_t control1;
> + uint32_t config1;
> + OMAP4_RESERVED(0x48, 0x4C);
> +
> + uint32_t default_color[2];
> + uint32_t trans_color[2];
> +
> + uint32_t const line_status;
> + uint32_t line_number;
> + uint32_t timing_h1;
> + uint32_t timing_v1;
> + uint32_t pol_freq1;
> + uint32_t divisor1;
> + uint32_t global_alpha;
> + uint32_t size_tv;
> + uint32_t size_lcd1;
> +
> + struct {
> + uint32_t ba[2];
> + uint32_t position;
> + uint32_t size;
> + OMAP4_RESERVED(0x90, 0xA0);
> + uint32_t attributes;
> + uint32_t buf_threshold;
> + uint32_t const buf_size_status;
> + uint32_t row_inc;
> + uint32_t pixel_inc;
> + OMAP4_RESERVED(0xB4, 0xB8);
> + uint32_t table_ba;
> + } gfx;
> +
> + struct omap4_regs_dispc_vid vid1;
> + OMAP4_RESERVED(0x144, 0x14C);
> + struct omap4_regs_dispc_vid vid2;
> +
> + uint32_t data1_cycle[3];
> +
> + uint32_t vid1_fir_coef_v[8];
> + uint32_t vid2_fir_coef_v[8];
> + uint32_t cpr1_coef_r;
> + uint32_t cpr1_coef_g;
> + uint32_t cpr1_coef_b;
> + uint32_t gfx_preload;
> + uint32_t vid_preload[2];
> + uint32_t control2;
> + OMAP4_RESERVED(0x23C, 0x300);
> +
> + struct {
> + uint32_t accu[2];
> + uint32_t ba[2];
> + struct {
> + uint32_t h;
> + uint32_t hv;
> + } fir_coef[8];
> + uint32_t fir_coef_v[8];
> + uint32_t attributes;
> + uint32_t conv_coef0;
> + uint32_t conv_coef1;
> + uint32_t conv_coef2;
> + uint32_t conv_coef3;
> + uint32_t conv_coef4;
> + uint32_t const buf_size_status;
> + uint32_t buf_threshold;
> + uint32_t fir;
> + uint32_t picture_size;
> + uint32_t pixel_inc;
> + uint32_t position;
> + uint32_t preload;
> + uint32_t row_inc;
> + uint32_t size;
> + } vid3;
> +
> + uint32_t default_color2;
> + uint32_t trans_color2;
> + uint32_t cpr2_coef_b;
> + uint32_t cpr2_coef_g;
> + uint32_t cpr2_coef_r;
> + uint32_t data2_cycle[3];
> + uint32_t size_lcd2;
> + OMAP4_RESERVED(0x3D0, 0x400);
> + uint32_t timing_h2;
> + uint32_t timing_v2;
> + uint32_t pol_freq2;
> + uint32_t divisor2;
> + OMAP4_RESERVED(0x410, 0x500);
> +
> + struct {
> + uint32_t accu[2];
> + uint32_t ba[2];
> + struct {
> + uint32_t h;
> + uint32_t hv;
> + } fir_coef[8];
> + uint32_t fir_coef_v[8];
> + uint32_t attributes;
> + uint32_t conv_coef0;
> + uint32_t conv_coef1;
> + uint32_t conv_coef2;
> + uint32_t conv_coef3;
> + uint32_t conv_coef4;
> + uint32_t const buf_size_status;
> + uint32_t buf_threshold;
> + uint32_t fir;
> + uint32_t picture_size;
> + uint32_t pixel_inc;
> + OMAP4_RESERVED(0x59C, 0x5A4);
> + uint32_t row_inc;
> + uint32_t size;
> + } wb;
> +
> + OMAP4_RESERVED(0x5AC, 0x600);
> + uint32_t vid1_ba_uv[2];
> + uint32_t vid2_ba_uv[2];
> + uint32_t vid3_ba_uv[2];
> + uint32_t wb_ba_uv[2];
> + uint32_t config2;
> + uint32_t vid1_attributes2;
> + uint32_t vid2_attributes2;
> + uint32_t vid3_attributes2;
> + uint32_t gamma_table0;
> + uint32_t gamma_table1;
> + uint32_t gamma_table2;
> + uint32_t vid1_fir2;
> + uint32_t vid1_accu2[2];
> + struct {
> + uint32_t h2;
> + uint32_t hv2;
> + } vid1_fir_coef[8];
> + uint32_t vid1_fir_coef_v2[8];
> + uint32_t vid2_fir2;
> + uint32_t vid2_accu2[2];
> + struct {
> + uint32_t h2;
> + uint32_t hv2;
> + } vid2_fir_coef[8];
> + uint32_t vid2_fir_coef_v2[8];
> + OMAP4_RESERVED(0x714, 0x724);
> + uint32_t vid3_fir2;
> + uint32_t vid3_accu2[2];
> + struct {
> + uint32_t h2;
> + uint32_t hv2;
> + } vid3_fir_coef[8];
> + uint32_t vid3_fir_coef_v2[8];
> + uint32_t wb_fir2;
> + uint32_t wb_accu2[2];
> + OMAP4_RESERVED(0x79C, 0x7A0);
> + struct {
> + uint32_t h2;
> + uint32_t hv2;
> + } wb_fir_coef[8];
> + uint32_t wb_fir_coef_v2[8];
> + uint32_t global_buffer;
> + uint32_t divisor;
> + OMAP4_RESERVED(0x808, 0x810);
> + uint32_t wb_attributes2;
> +};
> +
> +#define DSS_DISPC_VIDn_POSITION_VIDPOSX(_x) ((_x) << 0)
> +#define DSS_DISPC_VIDn_POSITION_VIDPOSY(_y) ((_y) << 16)
> +
> +#define DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEX(_x) ((_x) << 0)
> +#define DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEY(_y) ((_y) << 16)
> +
> +#define DSS_DISPC_VIDn_SIZE_VIDSIZEX(_x) ((_x) << 0)
> +#define DSS_DISPC_VIDn_SIZE_VIDSIZEY(_y) ((_y) << 16)
> +
> +#define DSS_DISPC_SIZE_LCD_PPL(_x) ((_x) << 0)
> +#define DSS_DISPC_SIZE_LCD_LPP(_y) ((_y) << 16)
> +
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE (1u << 0)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(_fmt) ((_fmt) << 1)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB12 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(4u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB16 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(5u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB16 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(6u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB16o \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(7u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_xRGB24u \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(8u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB24p \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(9u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_YUV2 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(10u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_UYVY \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(11u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB32 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(12u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGBA32 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(13u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_xRGB32 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(14u)
> +
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE(_f) ((_f) << 5)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE_NONE \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE(0u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE_H \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE(1u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE_V \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE(2u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE_HV \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE(3u)
> +
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDCOLORCONVENABLE (1u << 9)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDREPLICATIONENABLE (1u << 10)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFULLRANGE (1u << 11)
> +
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION(_r) ((_r) << 12)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION_0 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION(0u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION_90 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION(1u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION_180 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION(2u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION_270 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION(3u)
> +
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(_b) ((_b) << 14)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_2x128 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(0u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_4x128 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(1u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_8x128 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(2u)
> +
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDCHANNELOUT (1u << 16)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_SELFREFRESHAUTO (1u << 17)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFIFOPRELOAD (1u << 19)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDVERTICALTAPS (1u << 21)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_DOUBLESTRIDE (1u << 22)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDARBITRATION (1u << 23)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDSELFREFRESH (1u << 24)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_ZORDERENABLE (1u << 25)
> +
> +#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(_b) ((_b) << 30)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_PRIMARY_LCD \
> + DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(0u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_SECONDARY_LCD \
> + DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(1u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_WRITEBACK_MEM \
> + DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(3u)
> +
> +#define DSS_DISPC_CONFIG_PIXELGATED (1u << 0)
> +#define DSS_DISPC_CONFIG_PIXELDATAGATED (1u << 4)
> +#define DSS_DISPC_CONFIG_PIXELCLOCKGATED (1u << 5)
> +#define DSS_DISPC_CONFIG_HSYNCGATED (1u << 6)
> +#define DSS_DISPC_CONFIG_VSYNCGATED (1u << 7)
> +#define DSS_DISPC_CONFIG_ACBIASGATED (1u << 8)
> +#define DSS_DISPC_CONFIG_FUNCGATED (1u << 9)
> +#define DSS_DISPC_CONFIG_TCKLCDENABLE (1u << 10)
> +#define DSS_DISPC_CONFIG_TCKLCDSELECTION (1u << 11)
> +#define DSS_DISPC_CONFIG_CPR (1u << 15)
> +#define DSS_DISPC_CONFIG_FIFOHANDCHECK (1u << 16)
> +#define DSS_DISPC_CONFIG_OUTPUTMODE (1u << 22)
> +#define DSS_DISPC_CONFIG_FIDFIRST (1u << 23)
> +#define DSS_DISPC_CONFIG_COLORCONV (1u << 24)
> +#define DSS_DISPC_CONFIG_FULLRANGE (1u << 25)
> +
> +#define DSS_DISPC_CONTROL_LCDENABLE (1u << 0)
> +#define DSS_DISPC_CONTROL_TVENABLE (1u << 1)
> +#define DSS_DISPC_CONTROL_MONOCOLOR (1u << 2)
> +#define DSS_DISPC_CONTROL_STNTFT (1u << 3)
> +#define DSS_DISPC_CONTROL_M8B (1u << 4)
> +#define DSS_DISPC_CONTROL_GOLCD (1u << 5)
> +#define DSS_DISPC_CONTROL_GOTV (1u << 6)
> +#define DSS_DISPC_CONTROL_STDITHERENABLE (1u << 7)
> +
> +#define DSS_DISPC_CONTROL_TFTDATALINES(_l) ((_l) << 8)
> +#define DSS_DISPC_CONTROL_TFTDATALINES_12 \
> + DSS_DISPC_CONTROL_TFTDATALINES(0u)
> +#define DSS_DISPC_CONTROL_TFTDATALINES_16 \
> + DSS_DISPC_CONTROL_TFTDATALINES(1u)
> +#define DSS_DISPC_CONTROL_TFTDATALINES_18 \
> + DSS_DISPC_CONTROL_TFTDATALINES(2u)
> +#define DSS_DISPC_CONTROL_TFTDATALINES_24 \
> + DSS_DISPC_CONTROL_TFTDATALINES(3u)
> +
> +#define DSS_DISPC_CONTROL_STALLMODE (1u << 11)
> +#define DSS_DISPC_CONTROL_OVERLAYOPTIMIZATION (1u << 12)
> +#define DSS_DISPC_CONTROL_GPIN0 (1u << 13) /* ro */
> +#define DSS_DISPC_CONTROL_GPIN1 (1u << 14) /* ro */
> +#define DSS_DISPC_CONTROL_GPOUT0 (1u << 15)
> +#define DSS_DISPC_CONTROL_GPOUT1 (1u << 16)
> +#define DSS_DISPC_CONTROL_HT(_ht) ((_ht) << 17)
> +#define DSS_DISPC_CONTROL_TDMENABLE (1u << 20)
> +#define DSS_DISPC_CONTROL_TDMPARALLELMODE(_pm) ((_pm) << 21)
> +#define DSS_DISPC_CONTROL_TDMCYCLEFORMAT(_cf) ((_cf) << 23)
> +#define DSS_DISPC_CONTROL_TDMUNUSEDBITS(_ub) ((_ub) << 25)
> +#define DSS_DISPC_CONTROL_PCKFREEENABLE (1u << 27)
> +#define DSS_DISPC_CONTROL_LCDENABLESIGNAL (1u << 28)
> +#define DSS_DISPC_CONTROL_LCDENABLEPOL (1u << 29)
> +#define DSS_DISPC_CONTROL_SPATIALTEMPD(_df) ((_df) << 30)
> +
> +#define DSS_DISPC_POL_FREQ_IVS (1u << 12)
> +#define DSS_DISPC_POL_FREQ_IHS (1u << 13)
> +#define DSS_DISPC_POL_FREQ_IPC (1u << 14)
> +#define DSS_DISPC_POL_FREQ_IEO (1u << 15)
> +#define DSS_DISPC_POL_FREQ_RF (1u << 16)
> +#define DSS_DISPC_POL_FREQ_ONOFF (1u << 17)
> +
> +#define DSS_DISPC_TIMING_H_HSW(_hsw) ((_hsw) << 0)
> +#define DSS_DISPC_TIMING_H_HFP(_hfp) ((_hfp) << 8)
> +#define DSS_DISPC_TIMING_H_HBP(_hbp) ((_hbp) << 20)
> +
> +#define DSS_DISPC_TIMING_V_VSW(_vsw) ((_vsw) << 0)
> +#define DSS_DISPC_TIMING_V_VFP(_vfp) ((_vfp) << 8)
> +#define DSS_DISPC_TIMING_V_VBP(_vbp) ((_vbp) << 20)
> +
> +#define DSS_DISPC_DIVISOR_ENABLE (1u << 0)
> +#define DSS_DISPC_DIVISOR_LCD(_lcd) ((_lcd) << 16)
> +
> +#define DSS_DISPC_DIVISOR2_PCD(_pcd) ((_pcd) << 0)
> +#define DSS_DISPC_DIVISOR2_LCD(_lcd) ((_lcd) << 16)
> +
> +#define DSS_DISPC_IRQSTATUS_FRAMEDONE (1u << 0)
> +#define DSS_DISPC_IRQSTATUS_FRAMEDONE2 (1u << 22)
> +
> +#define DSS_DSS_SYSCONFIG_SOFTRESET (1u << 1)
> +#define DSS_DSS_SYSSTATUS_RESETDONE (1u << 0)
> +
> +#define DSS_DSS_CONTROL_DISPC_CLK_SWITCH (1u << 0)
> +#define DSS_DSS_CONTROL_DSI_CLK_SWITCH (1u << 1)
> +
> +#define CM_FCLKEN_DSS_EN_DSS1 (1u << 0)
> +#define CM_FCLKEN_DSS_EN_DSS2 (1u << 1)
> +#define CM_FCLKEN_DSS_EN_TV (1u << 2)
> +
> +#define CM_ICLKEN_DSS_EN_DSS (1u << 0)
> +
> +
> +#undef OMAP4_RESERVED
> +
> +#endif /* H_BAREBOX_DRIVER_VIDEO_OMAP4_REGS_H */
> --
> 1.7.10.4
>
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2] omap4-fb: add driver
2013-04-08 7:17 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2013-04-09 7:16 ` Sascha Hauer
2013-04-09 13:29 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 1 reply; 24+ messages in thread
From: Sascha Hauer @ 2013-04-09 7:16 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox
On Mon, Apr 08, 2013 at 09:17:15AM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 00:15 Mon 08 Apr , Christoph Fritz wrote:
> > This patch adds omap4 display controller support.
> >
> > +
> > +static inline void fb_write(uint32_t v, void __iomem *addr)
> > +{
> > + __raw_writel(v, addr);
> > +}
> > +
> > +static inline uint32_t fb_read(void const __iomem *addr)
> > +{
> > + return __raw_readl(addr);
> > +}
> what is the dif?
Maybe Christoph understands what you mean here. I don't
> > +
> > + fbi->regs.dss = dev_request_mem_region(dev, OMAP4_FB_RESOURCE_DSS);
> > + fbi->regs.dispc = dev_request_mem_region(dev, OMAP4_FB_RESOURCE_DISPC);
> use named dev_request
We don't have such a function.
Could you please trim the context to sensible limits when reviewing
patches? It's hard to find your comments when you keep the complete
patch.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2] omap4-fb: add driver
2013-04-09 7:16 ` Sascha Hauer
@ 2013-04-09 13:29 ` Jean-Christophe PLAGNIOL-VILLARD
2013-04-11 19:01 ` Christoph Fritz
0 siblings, 1 reply; 24+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2013-04-09 13:29 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
On 09:16 Tue 09 Apr , Sascha Hauer wrote:
> On Mon, Apr 08, 2013 at 09:17:15AM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 00:15 Mon 08 Apr , Christoph Fritz wrote:
> > > This patch adds omap4 display controller support.
> > >
> > > +
> > > +static inline void fb_write(uint32_t v, void __iomem *addr)
> > > +{
> > > + __raw_writel(v, addr);
> > > +}
> > > +
> > > +static inline uint32_t fb_read(void const __iomem *addr)
> > > +{
> > > + return __raw_readl(addr);
> > > +}
> > what is the dif?
>
> Maybe Christoph understands what you mean here. I don't
those 2 inline as useless
>
> > > +
> > > + fbi->regs.dss = dev_request_mem_region(dev, OMAP4_FB_RESOURCE_DSS);
> > > + fbi->regs.dispc = dev_request_mem_region(dev, OMAP4_FB_RESOURCE_DISPC);
> > use named dev_request
>
> We don't have such a function.
yes we do
dev_request_mem_region_by_name
>
> Could you please trim the context to sensible limits when reviewing
> patches? It's hard to find your comments when you keep the complete
> patch.
>
> Sascha
>
> --
> Pengutronix e.K. | |
> Industrial Linux Solutions | http://www.pengutronix.de/ |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2] omap4-fb: add driver
2013-04-09 13:29 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2013-04-11 19:01 ` Christoph Fritz
2013-06-02 21:07 ` Christoph Fritz
0 siblings, 1 reply; 24+ messages in thread
From: Christoph Fritz @ 2013-04-11 19:01 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox
Hi Jean-Christophe
On Tue, 2013-04-09 at 15:29 +0200, Jean-Christophe PLAGNIOL-VILLARD
wrote:
> On 09:16 Tue 09 Apr , Sascha Hauer wrote:
> > On Mon, Apr 08, 2013 at 09:17:15AM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > > On 00:15 Mon 08 Apr , Christoph Fritz wrote:
> > > > This patch adds omap4 display controller support.
> > > >
> > > > +
> > > > +static inline void fb_write(uint32_t v, void __iomem *addr)
> > > > +{
> > > > + __raw_writel(v, addr);
> > > > +}
> > > > +
> > > > +static inline uint32_t fb_read(void const __iomem *addr)
> > > > +{
> > > > + return __raw_readl(addr);
> > > > +}
> > > what is the dif?
> >
> > Maybe Christoph understands what you mean here. I don't
> those 2 inline as useless
You want me to purge the "inline" because gcc is smart enough to use
inlining on its own?
Or are you noting that using a function here is overkill for only one
call inside?
I use functions here because it makes debugging more easy and if you
have a weird hardware config, here you can easily adapt the read and
write functions.
> > > > +
> > > > + fbi->regs.dss = dev_request_mem_region(dev, OMAP4_FB_RESOURCE_DSS);
> > > > + fbi->regs.dispc = dev_request_mem_region(dev, OMAP4_FB_RESOURCE_DISPC);
> > > use named dev_request
> >
> > We don't have such a function.
> yes we do
>
> dev_request_mem_region_by_name
Ok
Thanks
-- Christoph
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2] omap4-fb: add driver
2013-04-11 19:01 ` Christoph Fritz
@ 2013-06-02 21:07 ` Christoph Fritz
2013-06-12 20:45 ` [PATCH v3] " Christoph Fritz
0 siblings, 1 reply; 24+ messages in thread
From: Christoph Fritz @ 2013-06-02 21:07 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox
*ping*
On Thu, 2013-04-11 at 21:01 +0200, Christoph Fritz wrote:
> Hi Jean-Christophe
>
> On Tue, 2013-04-09 at 15:29 +0200, Jean-Christophe PLAGNIOL-VILLARD
> wrote:
> > On 09:16 Tue 09 Apr , Sascha Hauer wrote:
> > > On Mon, Apr 08, 2013 at 09:17:15AM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > > > On 00:15 Mon 08 Apr , Christoph Fritz wrote:
> > > > > This patch adds omap4 display controller support.
> > > > >
> > > > > +
> > > > > +static inline void fb_write(uint32_t v, void __iomem *addr)
> > > > > +{
> > > > > + __raw_writel(v, addr);
> > > > > +}
> > > > > +
> > > > > +static inline uint32_t fb_read(void const __iomem *addr)
> > > > > +{
> > > > > + return __raw_readl(addr);
> > > > > +}
> > > > what is the dif?
> > >
> > > Maybe Christoph understands what you mean here. I don't
> > those 2 inline as useless
>
> You want me to purge the "inline" because gcc is smart enough to use
> inlining on its own?
>
> Or are you noting that using a function here is overkill for only one
> call inside?
>
> I use functions here because it makes debugging more easy and if you
> have a weird hardware config, here you can easily adapt the read and
> write functions.
>
> > > > > +
> > > > > + fbi->regs.dss = dev_request_mem_region(dev, OMAP4_FB_RESOURCE_DSS);
> > > > > + fbi->regs.dispc = dev_request_mem_region(dev, OMAP4_FB_RESOURCE_DISPC);
> > > > use named dev_request
> > >
> > > We don't have such a function.
> > yes we do
> >
> > dev_request_mem_region_by_name
>
> Ok
>
> Thanks
> -- Christoph
>
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3] omap4-fb: add driver
2013-06-02 21:07 ` Christoph Fritz
@ 2013-06-12 20:45 ` Christoph Fritz
2013-06-13 10:10 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 1 reply; 24+ messages in thread
From: Christoph Fritz @ 2013-06-12 20:45 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
This patch adds omap4 display controller support.
Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
---
changes since v2:
- use dev_request_mem_region_by_name()
---
arch/arm/mach-omap/Makefile | 1 +
arch/arm/mach-omap/include/mach/omap4-fb.h | 46 +++
arch/arm/mach-omap/omap4_fb.c | 27 ++
drivers/video/Kconfig | 8 +
drivers/video/Makefile | 1 +
drivers/video/omap4.c | 507 ++++++++++++++++++++++++++++
drivers/video/omap4.h | 408 ++++++++++++++++++++++
7 files changed, 998 insertions(+)
create mode 100644 arch/arm/mach-omap/include/mach/omap4-fb.h
create mode 100644 arch/arm/mach-omap/omap4_fb.c
create mode 100644 drivers/video/omap4.c
create mode 100644 drivers/video/omap4.h
diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile
index 94e42c6..e70ddbd 100644
--- a/arch/arm/mach-omap/Makefile
+++ b/arch/arm/mach-omap/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
pbl-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
obj-$(CONFIG_OMAP_GPMC) += gpmc.o devices-gpmc-nand.o
obj-$(CONFIG_SHELL_NONE) += xload.o
+obj-$(CONFIG_DRIVER_VIDEO_OMAP4) += omap4_fb.o
obj-$(CONFIG_I2C_TWL6030) += omap4_twl6030_mmc.o
obj-$(CONFIG_OMAP4_USBBOOT) += omap4_rom_usb.o
obj-y += gpio.o
diff --git a/arch/arm/mach-omap/include/mach/omap4-fb.h b/arch/arm/mach-omap/include/mach/omap4-fb.h
new file mode 100644
index 0000000..5c0a54b
--- /dev/null
+++ b/arch/arm/mach-omap/include/mach/omap4-fb.h
@@ -0,0 +1,46 @@
+#ifndef H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H
+#define H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H
+
+#include <fb.h>
+
+#define OMAP_DSS_LCD_TFT (1u << 0)
+#define OMAP_DSS_LCD_IVS (1u << 1)
+#define OMAP_DSS_LCD_IHS (1u << 2)
+#define OMAP_DSS_LCD_IPC (1u << 3)
+#define OMAP_DSS_LCD_IEO (1u << 4)
+#define OMAP_DSS_LCD_RF (1u << 5)
+#define OMAP_DSS_LCD_ONOFF (1u << 6)
+
+#define OMAP_DSS_LCD_DATALINES(_l) ((_l) << 10)
+#define OMAP_DSS_LCD_DATALINES_msk OMAP_DSS_LCD_DATALINES(3u)
+#define OMAP_DSS_LCD_DATALINES_12 OMAP_DSS_LCD_DATALINES(0u)
+#define OMAP_DSS_LCD_DATALINES_16 OMAP_DSS_LCD_DATALINES(1u)
+#define OMAP_DSS_LCD_DATALINES_18 OMAP_DSS_LCD_DATALINES(2u)
+#define OMAP_DSS_LCD_DATALINES_24 OMAP_DSS_LCD_DATALINES(3u)
+
+struct omap4fb_display {
+ struct fb_videomode mode;
+
+ unsigned long config;
+
+ unsigned int power_on_delay;
+ unsigned int power_off_delay;
+};
+
+struct omap4fb_platform_data {
+ struct omap4fb_display const *displays;
+ size_t num_displays;
+
+ unsigned int dss_clk_hz;
+
+ unsigned int bpp;
+
+ struct resource const *screen;
+
+ void (*enable)(int p);
+};
+
+struct device_d;
+struct device_d *omap4_add_display(void *pdata);
+
+#endif /* H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H */
diff --git a/arch/arm/mach-omap/omap4_fb.c b/arch/arm/mach-omap/omap4_fb.c
new file mode 100644
index 0000000..09a6af3
--- /dev/null
+++ b/arch/arm/mach-omap/omap4_fb.c
@@ -0,0 +1,27 @@
+#include <driver.h>
+#include <common.h>
+#include <linux/ioport.h>
+#include <mach/omap4-fb.h>
+
+static struct resource omap4_fb_resources[] = {
+ {
+ .name = "omap4_dss",
+ .start = 0x48040000,
+ .end = 0x48040000 + 512 - 1,
+ .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+ }, {
+ .name = "omap4_dispc",
+ .start = 0x48041000,
+ .end = 0x48041000 + 3072 - 1,
+ .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+ },
+};
+
+struct device_d *omap4_add_display(void *pdata)
+{
+ return add_generic_device_res("omap4_fb", -1,
+ omap4_fb_resources,
+ ARRAY_SIZE(omap4_fb_resources),
+ pdata);
+}
+EXPORT_SYMBOL(omap4_add_display);
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 6d6b08f..9dfa0cd 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -45,6 +45,14 @@ config DRIVER_VIDEO_S3C24XX
help
Add support for the S3C244x LCD controller.
+config DRIVER_VIDEO_OMAP4
+ bool "OMAP4 framebuffer driver"
+ depends on ARCH_OMAP4
+ help
+ Add support for the OMAP4 Display Controller.
+ DSI is unsupported, only DISPC parallel mode on LCD2
+ is supported.
+
if DRIVER_VIDEO_S3C24XX
config DRIVER_VIDEO_S3C_VERBOSE
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 7429141..83feebb 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_DRIVER_VIDEO_IMX_IPU) += imx-ipu-fb.o
obj-$(CONFIG_DRIVER_VIDEO_S3C24XX) += s3c24xx.o
obj-$(CONFIG_DRIVER_VIDEO_PXA) += pxa.o
obj-$(CONFIG_DRIVER_VIDEO_SDL) += sdl.o
+obj-$(CONFIG_DRIVER_VIDEO_OMAP4) += omap4.o
diff --git a/drivers/video/omap4.c b/drivers/video/omap4.c
new file mode 100644
index 0000000..887a5c0
--- /dev/null
+++ b/drivers/video/omap4.c
@@ -0,0 +1,507 @@
+/*
+ * TI Omap4 Frame Buffer device driver
+ *
+ * Copyright (C) 2013 Christoph Fritz <chf.fritz@googlemail.com>
+ * Based on work by Enrico Scholz, sponsored by Phytec
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <driver.h>
+#include <fb.h>
+#include <errno.h>
+#include <xfuncs.h>
+#include <init.h>
+#include <stdio.h>
+#include <io.h>
+#include <common.h>
+#include <malloc.h>
+#include <common.h>
+#include <clock.h>
+
+#include <mach/omap4-silicon.h>
+#include <mach/omap4-fb.h>
+
+#include "omap4.h"
+
+struct omap4fb_device {
+ struct fb_info info;
+ struct device_d *dev;
+
+ struct omap4fb_display const *cur_display;
+
+ struct omap4fb_display const *displays;
+ size_t num_displays;
+
+ struct {
+ struct omap4_regs_dss __iomem *dss;
+ struct omap4_regs_dispc __iomem *dispc;
+ } regs;
+
+ struct {
+ void __iomem *addr;
+ size_t size;
+ } prealloc_screen;
+
+ struct {
+ uint32_t dispc_control;
+ uint32_t dispc_pol_freq;
+ } shadow;
+
+ struct {
+ unsigned int dss_clk_hz;
+ unsigned int lckd;
+ unsigned int pckd;
+ } divisor;
+
+ void (*enable_fn)(int);
+
+ struct fb_videomode video_modes[];
+};
+
+static inline void fb_write(uint32_t v, void __iomem *addr)
+{
+ __raw_writel(v, addr);
+}
+
+static inline uint32_t fb_read(void const __iomem *addr)
+{
+ return __raw_readl(addr);
+}
+
+static void omap4fb_enable(struct fb_info *info)
+{
+ struct omap4fb_device *fbi =
+ container_of(info, struct omap4fb_device, info);
+ struct omap4_regs_dispc __iomem *dispc = fbi->regs.dispc;
+
+ dev_info(fbi->dev, "%s\n", __func__);
+
+ if (!fbi->cur_display) {
+ dev_err(fbi->dev, "no valid mode set\n");
+ return;
+ }
+
+ if (fbi->enable_fn)
+ fbi->enable_fn(1);
+
+ udelay(fbi->cur_display->power_on_delay * 1000u);
+
+ fb_write(fb_read(&dispc->control2) |
+ DSS_DISPC_CONTROL_LCDENABLE |
+ 1*DSS_DISPC_CONTROL_LCDENABLESIGNAL,
+ &dispc->control2);
+
+ fb_write(fb_read(&dispc->vid1.attributes) |
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE,
+ &dispc->vid1.attributes);
+
+ fb_write(fb_read(&dispc->control2) |
+ DSS_DISPC_CONTROL_GOLCD,
+ &dispc->control2);
+}
+
+static void omap4fb_disable(struct fb_info *info)
+{
+ struct omap4fb_device *fbi =
+ container_of(info, struct omap4fb_device, info);
+ struct omap4_regs_dispc __iomem *dispc = fbi->regs.dispc;
+
+ dev_info(fbi->dev, "%s\n", __func__);
+
+ if (!fbi->cur_display) {
+ dev_err(fbi->dev, "no valid mode set\n");
+ return;
+ }
+
+ fb_write(fb_read(&dispc->control2) &
+ ~(DSS_DISPC_CONTROL_LCDENABLE |
+ DSS_DISPC_CONTROL_LCDENABLESIGNAL),
+ &dispc->control2);
+
+ fb_write(fb_read(&dispc->vid1.attributes) &
+ ~(DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE),
+ &dispc->vid1.attributes);
+
+ if (fbi->prealloc_screen.addr == NULL)
+ /* free frame buffer; but only when screen is not
+ * preallocated */
+ free(info->screen_base);
+
+ info->screen_base = NULL;
+
+ udelay(fbi->cur_display->power_off_delay * 1000u);
+
+ if (fbi->enable_fn)
+ fbi->enable_fn(0);
+}
+
+static void omap4fb_calc_divisor(struct omap4fb_device *fbi,
+ struct fb_videomode const *mode)
+{
+ unsigned int l, k, t, b;
+
+ b = UINT_MAX;
+ for (l = 1; l < 256; l++) {
+ for (k = 1; k < 256; k++) {
+ t = abs(mode->pixclock * 100 -
+ (fbi->divisor.dss_clk_hz / l / k));
+ if (t <= b) {
+ b = t;
+ fbi->divisor.lckd = l;
+ fbi->divisor.pckd = k;
+ }
+ }
+ }
+}
+
+static unsigned int omap4fb_calc_format(struct fb_info const *info)
+{
+ switch (info->bits_per_pixel) {
+ case 24: return 9;
+ case 32: return 0x8; /* xRGB24-8888 (32-bit container) */
+ default:
+ printf("%s: unsupported bpp %d\n", __func__,
+ info->bits_per_pixel);
+ return 0;
+ }
+}
+
+struct omap4fb_colors {
+ struct fb_bitfield red;
+ struct fb_bitfield green;
+ struct fb_bitfield blue;
+ struct fb_bitfield transp;
+};
+
+static struct omap4fb_colors const omap4fb_col[] = {
+ [0] = {
+ .red = { .length = 0, .offset = 0 },
+ },
+ [1] = {
+ .blue = { .length = 8, .offset = 0 },
+ .green = { .length = 8, .offset = 8 },
+ .red = { .length = 8, .offset = 16 },
+ },
+ [2] = {
+ .blue = { .length = 8, .offset = 0 },
+ .green = { .length = 8, .offset = 8 },
+ .red = { .length = 8, .offset = 16 },
+ .transp = { .length = 8, .offset = 24 },
+ },
+};
+
+static void omap4fb_fill_shadow(struct omap4fb_device *fbi,
+ struct omap4fb_display const *display)
+{
+ fbi->shadow.dispc_control = 0;
+ fbi->shadow.dispc_pol_freq = 0;
+
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_STNTFT;
+
+ switch (display->config & OMAP_DSS_LCD_DATALINES_msk) {
+ case OMAP_DSS_LCD_DATALINES_12:
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_12;
+ break;
+ case OMAP_DSS_LCD_DATALINES_16:
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_16;
+ break;
+ case OMAP_DSS_LCD_DATALINES_18:
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_18;
+ break;
+ case OMAP_DSS_LCD_DATALINES_24:
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_24;
+ break;
+ }
+
+ if (display->config & OMAP_DSS_LCD_IPC)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IPC;
+
+ if (display->config & OMAP_DSS_LCD_IVS)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IVS;
+
+ if (display->config & OMAP_DSS_LCD_IHS)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IHS;
+
+ if (display->config & OMAP_DSS_LCD_IEO)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IEO;
+
+ if (display->config & OMAP_DSS_LCD_RF)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_RF;
+
+ if (display->config & OMAP_DSS_LCD_ONOFF)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_ONOFF;
+}
+
+static int omap4fb_activate_var(struct fb_info *info)
+{
+ struct omap4fb_device *fbi =
+ container_of(info, struct omap4fb_device, info);
+ struct omap4_regs_dispc __iomem *dispc = fbi->regs.dispc;
+ struct fb_videomode const *mode = info->mode;
+ size_t size = mode->xres * mode->yres * (info->bits_per_pixel / 8);
+ int rc;
+ unsigned int fmt = omap4fb_calc_format(info);
+ struct omap4fb_colors const *cols;
+ size_t i;
+ struct omap4fb_display const *new_display = NULL;
+
+ for (i = 0; i < fbi->num_displays && new_display == NULL; ++i) {
+ if (strcmp(mode->name, fbi->displays[i].mode.name) == 0)
+ new_display = &fbi->displays[i];
+ }
+
+ if (WARN_ON(!new_display)) {
+ dev_err(fbi->dev, "no matching display found for this mode '%s'\n",
+ mode->name);
+ rc = -ENXIO;
+ goto out;
+ }
+
+ if (fbi->prealloc_screen.addr == NULL) {
+ /* case 1: no preallocated screen */
+ free(info->screen_base);
+ info->screen_base = memalign(0x100, size);
+ } else if (fbi->prealloc_screen.size < size) {
+ /* case 2: preallocated screen, but too small */
+ dev_err(fbi->dev,
+ "allocated framebuffer too small (%zu < %zu)\n",
+ fbi->prealloc_screen.size, size);
+ rc = -ENOMEM;
+ goto out;
+ } else {
+ /* case 3: preallocated screen */
+ info->screen_base = fbi->prealloc_screen.addr;
+ }
+
+ omap4fb_fill_shadow(fbi, new_display);
+
+ omap4fb_calc_divisor(fbi, mode);
+
+ switch (info->bits_per_pixel) {
+ case 24:
+ cols = &omap4fb_col[1];
+ break;
+ case 32:
+ cols = &omap4fb_col[2];
+ break;
+ default:
+ cols = &omap4fb_col[0];
+ }
+
+ info->red = cols->red;
+ info->green = cols->green;
+ info->blue = cols->blue;
+ info->transp = cols->transp;
+
+ fb_write(fbi->shadow.dispc_control,
+ &dispc->control2);
+
+ fb_write(fbi->shadow.dispc_pol_freq,
+ &dispc->pol_freq2);
+
+ fb_write(DSS_DISPC_TIMING_H_HSW(mode->hsync_len - 1) |
+ DSS_DISPC_TIMING_H_HFP(mode->right_margin - 1) |
+ DSS_DISPC_TIMING_H_HBP(mode->left_margin - 1),
+ &dispc->timing_h2);
+
+ fb_write(DSS_DISPC_TIMING_V_VSW(mode->vsync_len - 1) |
+ DSS_DISPC_TIMING_V_VFP(mode->lower_margin) |
+ DSS_DISPC_TIMING_V_VBP(mode->upper_margin),
+ &dispc->timing_v2);
+
+ fb_write(DSS_DISPC_DIVISOR_ENABLE | DSS_DISPC_DIVISOR_LCD(1),
+ &dispc->divisor);
+
+ fb_write(DSS_DISPC_DIVISOR2_LCD(fbi->divisor.lckd) |
+ DSS_DISPC_DIVISOR2_PCD(fbi->divisor.pckd),
+ &dispc->divisor2);
+
+ fb_write(DSS_DISPC_SIZE_LCD_PPL(mode->xres - 1) |
+ DSS_DISPC_SIZE_LCD_LPP(mode->yres - 1),
+ &dispc->size_lcd2);
+
+ fb_write(0x0000FF00, &dispc->default_color2);
+
+ /* we use VID1 */
+ fb_write((uintptr_t)info->screen_base, &dispc->vid1.ba[0]);
+ fb_write((uintptr_t)info->screen_base, &dispc->vid1.ba[1]);
+
+ fb_write(DSS_DISPC_VIDn_POSITION_VIDPOSX(0) |
+ DSS_DISPC_VIDn_POSITION_VIDPOSY(0),
+ &dispc->vid1.position);
+ fb_write(DSS_DISPC_VIDn_SIZE_VIDSIZEX(mode->xres - 1) |
+ DSS_DISPC_VIDn_SIZE_VIDSIZEY(mode->yres - 1),
+ &dispc->vid1.size);
+ fb_write(DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEX(mode->xres - 1) |
+ DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEY(mode->yres - 1),
+ &dispc->vid1.picture_size);
+ fb_write(1, &dispc->vid1.row_inc);
+ fb_write(1, &dispc->vid1.pixel_inc);
+
+ fb_write(0xfff, &dispc->vid_preload[0]);
+
+ fb_write(DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(fmt) |
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_8x128 |
+ DSS_DISPC_VIDn_ATTRIBUTES_ZORDERENABLE |
+ DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_SECONDARY_LCD,
+ &dispc->vid1.attributes);
+
+ while (fb_read(&dispc->control2) & DSS_DISPC_CONTROL_GOLCD)
+ ; /* noop */
+
+ fb_write(fb_read(&dispc->control2) |
+ DSS_DISPC_CONTROL_GOLCD,
+ &dispc->control2);
+
+ fbi->cur_display = new_display;
+ info->xres = mode->xres;
+ info->yres = mode->yres;
+
+ rc = 0;
+
+out:
+ return rc;
+}
+
+static void omap4fb_reset(struct omap4fb_device const *fbi)
+{
+ struct omap4_regs_dispc __iomem *dispc = fbi->regs.dispc;
+ struct omap4_regs_dss __iomem *dss = fbi->regs.dss;
+
+ uint32_t v = fb_read(&dispc->control2);
+
+ /* step 1: stop the LCD controller */
+ if (v & DSS_DISPC_CONTROL_LCDENABLE) {
+ fb_write(v & ~DSS_DISPC_CONTROL_LCDENABLE,
+ &dispc->control2);
+
+ fb_write(DSS_DISPC_IRQSTATUS_FRAMEDONE2, &dispc->irqstatus);
+
+ while ((fb_read(&dispc->irqstatus) &
+ DSS_DISPC_IRQSTATUS_FRAMEDONE) == 0)
+ ; /* noop */
+ }
+
+ /* step 2: wait for reset done status */
+ while (!(fb_read(&dss->sysstatus) & DSS_DSS_SYSSTATUS_RESETDONE))
+ ; /* noop */
+
+ /* DSS_CTL: set to reset value */
+ fb_write(0, &dss->ctrl);
+}
+
+static struct fb_ops omap4fb_ops = {
+ .fb_enable = omap4fb_enable,
+ .fb_disable = omap4fb_disable,
+ .fb_activate_var = omap4fb_activate_var,
+};
+
+static int omap4fb_probe(struct device_d *dev)
+{
+ struct omap4fb_platform_data const *pdata = dev->platform_data;
+ struct omap4fb_device *fbi;
+ struct fb_info *info;
+ struct omap4_regs_dispc __iomem *dispc;
+ struct omap4_regs_dss __iomem *dss;
+ int rc;
+ size_t i;
+
+ if (!pdata)
+ return -ENODEV;
+
+ fbi = xzalloc(sizeof *fbi +
+ pdata->num_displays * sizeof fbi->video_modes[0]);
+ info = &fbi->info;
+
+ fbi->dev = dev;
+
+ /* CM_DSS_CLKSTCTRL (TRM: 935) trigger SW_WKUP */
+ __raw_writel(0x2, 0x4a009100); /* TODO: move this to clockmanagement */
+
+ fbi->regs.dss = dev_request_mem_region_by_name(dev, "omap4_dss");
+ fbi->regs.dispc = dev_request_mem_region_by_name(dev, "omap4_dispc");
+
+ if (!fbi->regs.dss || !fbi->regs.dispc) {
+ dev_err(dev, "Insufficient register description\n");
+ rc = -EINVAL;
+ goto out;
+ }
+
+ dispc = fbi->regs.dispc;
+ dss = fbi->regs.dss;
+ dev_info(dev, "HW-Revision 0x%04x 0x%04x\n",
+ fb_read(&dispc->revision),
+ fb_read(&dss->revision));
+
+
+ if (!pdata->dss_clk_hz | !pdata->displays | !pdata->num_displays |
+ !pdata->bpp) {
+ dev_err(dev, "Insufficient omap4fb_platform_data\n");
+ rc = -EINVAL;
+ goto out;
+ }
+
+ fbi->enable_fn = pdata->enable;
+ fbi->displays = pdata->displays;
+ fbi->num_displays = pdata->num_displays;
+ fbi->divisor.dss_clk_hz = pdata->dss_clk_hz;
+
+ for (i = 0; i < pdata->num_displays; ++i)
+ fbi->video_modes[i] = pdata->displays[i].mode;
+
+ info->mode_list = fbi->video_modes;
+ info->num_modes = pdata->num_displays;
+
+ info->priv = fbi;
+ info->fbops = &omap4fb_ops;
+ info->bits_per_pixel = pdata->bpp;
+
+ if (pdata->screen) {
+ fbi->prealloc_screen.addr =
+ (void __iomem *)pdata->screen->start;
+ fbi->prealloc_screen.size = resource_size(pdata->screen);
+ }
+
+ omap4fb_reset(fbi);
+
+ dev_add_param(fbi->dev, "bootargs", NULL, NULL, 0);
+
+ rc = register_framebuffer(info);
+ if (rc < 0) {
+ dev_err(dev, "failed to register framebuffer: %d\n", rc);
+ goto out;
+ }
+
+ rc = 0;
+ dev_info(dev, "registered\n");
+
+out:
+ if (rc < 0)
+ free(fbi);
+
+ return rc;
+}
+
+static struct driver_d omap4fb_driver = {
+ .name = "omap4_fb",
+ .probe = omap4fb_probe,
+};
+
+static int omap4fb_init(void)
+{
+ return platform_driver_register(&omap4fb_driver);
+}
+
+device_initcall(omap4fb_init);
diff --git a/drivers/video/omap4.h b/drivers/video/omap4.h
new file mode 100644
index 0000000..b3364a5
--- /dev/null
+++ b/drivers/video/omap4.h
@@ -0,0 +1,408 @@
+/*
+ * TI Omap4 Frame Buffer device driver
+ *
+ * Copyright (C) 2013 Christoph Fritz <chf.fritz@googlemail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef H_BAREBOX_DRIVER_VIDEO_OMAP4_REGS_H
+#define H_BAREBOX_DRIVER_VIDEO_OMAP4_REGS_H
+
+#include <types.h>
+#include <common.h>
+
+#define OMAP4_RESERVED(_f, _t) \
+ uint32_t const reserved_ ## _f ## _ ## _t[((_t) - (_f)) / 4]
+
+
+/* TRM: 10.1.3.2 DSS Registers */
+struct omap4_regs_dss {
+ uint32_t revision;
+ OMAP4_RESERVED(0x4, 0x14);
+ uint32_t const sysstatus;
+ OMAP4_RESERVED(0x18, 0x40);
+ uint32_t ctrl;
+ OMAP4_RESERVED(0x44, 0x5C);
+ uint32_t const status;
+};
+
+
+struct omap4_regs_dispc_vid {
+ uint32_t ba[2];
+ uint32_t position;
+ uint32_t size;
+ uint32_t attributes;
+ uint32_t buf_threshold;
+ uint32_t const buf_size_status;
+ uint32_t row_inc;
+ uint32_t pixel_inc;
+ uint32_t fir;
+ uint32_t picture_size;
+ uint32_t accu[2];
+ struct {
+ uint32_t h;
+ uint32_t hv;
+ } fir_coef[8];
+ uint32_t conv_coef0;
+ uint32_t conv_coef1;
+ uint32_t conv_coef2;
+ uint32_t conv_coef3;
+ uint32_t conv_coef4;
+};
+
+/* TRM: 10.2.7.3 Display Controller Registers */
+struct omap4_regs_dispc {
+ uint32_t const revision;
+ OMAP4_RESERVED(0x04, 0x10);
+ uint32_t sysconfig;
+ uint32_t const sysstatus;
+ uint32_t irqstatus;
+ uint32_t irqenable;
+ OMAP4_RESERVED(0x20, 0x40);
+ uint32_t control1;
+ uint32_t config1;
+ OMAP4_RESERVED(0x48, 0x4C);
+
+ uint32_t default_color[2];
+ uint32_t trans_color[2];
+
+ uint32_t const line_status;
+ uint32_t line_number;
+ uint32_t timing_h1;
+ uint32_t timing_v1;
+ uint32_t pol_freq1;
+ uint32_t divisor1;
+ uint32_t global_alpha;
+ uint32_t size_tv;
+ uint32_t size_lcd1;
+
+ struct {
+ uint32_t ba[2];
+ uint32_t position;
+ uint32_t size;
+ OMAP4_RESERVED(0x90, 0xA0);
+ uint32_t attributes;
+ uint32_t buf_threshold;
+ uint32_t const buf_size_status;
+ uint32_t row_inc;
+ uint32_t pixel_inc;
+ OMAP4_RESERVED(0xB4, 0xB8);
+ uint32_t table_ba;
+ } gfx;
+
+ struct omap4_regs_dispc_vid vid1;
+ OMAP4_RESERVED(0x144, 0x14C);
+ struct omap4_regs_dispc_vid vid2;
+
+ uint32_t data1_cycle[3];
+
+ uint32_t vid1_fir_coef_v[8];
+ uint32_t vid2_fir_coef_v[8];
+ uint32_t cpr1_coef_r;
+ uint32_t cpr1_coef_g;
+ uint32_t cpr1_coef_b;
+ uint32_t gfx_preload;
+ uint32_t vid_preload[2];
+ uint32_t control2;
+ OMAP4_RESERVED(0x23C, 0x300);
+
+ struct {
+ uint32_t accu[2];
+ uint32_t ba[2];
+ struct {
+ uint32_t h;
+ uint32_t hv;
+ } fir_coef[8];
+ uint32_t fir_coef_v[8];
+ uint32_t attributes;
+ uint32_t conv_coef0;
+ uint32_t conv_coef1;
+ uint32_t conv_coef2;
+ uint32_t conv_coef3;
+ uint32_t conv_coef4;
+ uint32_t const buf_size_status;
+ uint32_t buf_threshold;
+ uint32_t fir;
+ uint32_t picture_size;
+ uint32_t pixel_inc;
+ uint32_t position;
+ uint32_t preload;
+ uint32_t row_inc;
+ uint32_t size;
+ } vid3;
+
+ uint32_t default_color2;
+ uint32_t trans_color2;
+ uint32_t cpr2_coef_b;
+ uint32_t cpr2_coef_g;
+ uint32_t cpr2_coef_r;
+ uint32_t data2_cycle[3];
+ uint32_t size_lcd2;
+ OMAP4_RESERVED(0x3D0, 0x400);
+ uint32_t timing_h2;
+ uint32_t timing_v2;
+ uint32_t pol_freq2;
+ uint32_t divisor2;
+ OMAP4_RESERVED(0x410, 0x500);
+
+ struct {
+ uint32_t accu[2];
+ uint32_t ba[2];
+ struct {
+ uint32_t h;
+ uint32_t hv;
+ } fir_coef[8];
+ uint32_t fir_coef_v[8];
+ uint32_t attributes;
+ uint32_t conv_coef0;
+ uint32_t conv_coef1;
+ uint32_t conv_coef2;
+ uint32_t conv_coef3;
+ uint32_t conv_coef4;
+ uint32_t const buf_size_status;
+ uint32_t buf_threshold;
+ uint32_t fir;
+ uint32_t picture_size;
+ uint32_t pixel_inc;
+ OMAP4_RESERVED(0x59C, 0x5A4);
+ uint32_t row_inc;
+ uint32_t size;
+ } wb;
+
+ OMAP4_RESERVED(0x5AC, 0x600);
+ uint32_t vid1_ba_uv[2];
+ uint32_t vid2_ba_uv[2];
+ uint32_t vid3_ba_uv[2];
+ uint32_t wb_ba_uv[2];
+ uint32_t config2;
+ uint32_t vid1_attributes2;
+ uint32_t vid2_attributes2;
+ uint32_t vid3_attributes2;
+ uint32_t gamma_table0;
+ uint32_t gamma_table1;
+ uint32_t gamma_table2;
+ uint32_t vid1_fir2;
+ uint32_t vid1_accu2[2];
+ struct {
+ uint32_t h2;
+ uint32_t hv2;
+ } vid1_fir_coef[8];
+ uint32_t vid1_fir_coef_v2[8];
+ uint32_t vid2_fir2;
+ uint32_t vid2_accu2[2];
+ struct {
+ uint32_t h2;
+ uint32_t hv2;
+ } vid2_fir_coef[8];
+ uint32_t vid2_fir_coef_v2[8];
+ OMAP4_RESERVED(0x714, 0x724);
+ uint32_t vid3_fir2;
+ uint32_t vid3_accu2[2];
+ struct {
+ uint32_t h2;
+ uint32_t hv2;
+ } vid3_fir_coef[8];
+ uint32_t vid3_fir_coef_v2[8];
+ uint32_t wb_fir2;
+ uint32_t wb_accu2[2];
+ OMAP4_RESERVED(0x79C, 0x7A0);
+ struct {
+ uint32_t h2;
+ uint32_t hv2;
+ } wb_fir_coef[8];
+ uint32_t wb_fir_coef_v2[8];
+ uint32_t global_buffer;
+ uint32_t divisor;
+ OMAP4_RESERVED(0x808, 0x810);
+ uint32_t wb_attributes2;
+};
+
+#define DSS_DISPC_VIDn_POSITION_VIDPOSX(_x) ((_x) << 0)
+#define DSS_DISPC_VIDn_POSITION_VIDPOSY(_y) ((_y) << 16)
+
+#define DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEX(_x) ((_x) << 0)
+#define DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEY(_y) ((_y) << 16)
+
+#define DSS_DISPC_VIDn_SIZE_VIDSIZEX(_x) ((_x) << 0)
+#define DSS_DISPC_VIDn_SIZE_VIDSIZEY(_y) ((_y) << 16)
+
+#define DSS_DISPC_SIZE_LCD_PPL(_x) ((_x) << 0)
+#define DSS_DISPC_SIZE_LCD_LPP(_y) ((_y) << 16)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE (1u << 0)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(_fmt) ((_fmt) << 1)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB12 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(4u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB16 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(5u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB16 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(6u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB16o \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(7u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_xRGB24u \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(8u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB24p \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(9u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_YUV2 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(10u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_UYVY \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(11u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB32 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(12u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGBA32 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(13u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_xRGB32 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(14u)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE(_f) ((_f) << 5)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE_NONE \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE(0u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE_H \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE(1u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE_V \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE(2u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE_HV \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE(3u)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDCOLORCONVENABLE (1u << 9)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDREPLICATIONENABLE (1u << 10)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFULLRANGE (1u << 11)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION(_r) ((_r) << 12)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION_0 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION(0u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION_90 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION(1u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION_180 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION(2u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION_270 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION(3u)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(_b) ((_b) << 14)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_2x128 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(0u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_4x128 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(1u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_8x128 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(2u)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDCHANNELOUT (1u << 16)
+#define DSS_DISPC_VIDn_ATTRIBUTES_SELFREFRESHAUTO (1u << 17)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFIFOPRELOAD (1u << 19)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDVERTICALTAPS (1u << 21)
+#define DSS_DISPC_VIDn_ATTRIBUTES_DOUBLESTRIDE (1u << 22)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDARBITRATION (1u << 23)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDSELFREFRESH (1u << 24)
+#define DSS_DISPC_VIDn_ATTRIBUTES_ZORDERENABLE (1u << 25)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(_b) ((_b) << 30)
+#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_PRIMARY_LCD \
+ DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(0u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_SECONDARY_LCD \
+ DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(1u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_WRITEBACK_MEM \
+ DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(3u)
+
+#define DSS_DISPC_CONFIG_PIXELGATED (1u << 0)
+#define DSS_DISPC_CONFIG_PIXELDATAGATED (1u << 4)
+#define DSS_DISPC_CONFIG_PIXELCLOCKGATED (1u << 5)
+#define DSS_DISPC_CONFIG_HSYNCGATED (1u << 6)
+#define DSS_DISPC_CONFIG_VSYNCGATED (1u << 7)
+#define DSS_DISPC_CONFIG_ACBIASGATED (1u << 8)
+#define DSS_DISPC_CONFIG_FUNCGATED (1u << 9)
+#define DSS_DISPC_CONFIG_TCKLCDENABLE (1u << 10)
+#define DSS_DISPC_CONFIG_TCKLCDSELECTION (1u << 11)
+#define DSS_DISPC_CONFIG_CPR (1u << 15)
+#define DSS_DISPC_CONFIG_FIFOHANDCHECK (1u << 16)
+#define DSS_DISPC_CONFIG_OUTPUTMODE (1u << 22)
+#define DSS_DISPC_CONFIG_FIDFIRST (1u << 23)
+#define DSS_DISPC_CONFIG_COLORCONV (1u << 24)
+#define DSS_DISPC_CONFIG_FULLRANGE (1u << 25)
+
+#define DSS_DISPC_CONTROL_LCDENABLE (1u << 0)
+#define DSS_DISPC_CONTROL_TVENABLE (1u << 1)
+#define DSS_DISPC_CONTROL_MONOCOLOR (1u << 2)
+#define DSS_DISPC_CONTROL_STNTFT (1u << 3)
+#define DSS_DISPC_CONTROL_M8B (1u << 4)
+#define DSS_DISPC_CONTROL_GOLCD (1u << 5)
+#define DSS_DISPC_CONTROL_GOTV (1u << 6)
+#define DSS_DISPC_CONTROL_STDITHERENABLE (1u << 7)
+
+#define DSS_DISPC_CONTROL_TFTDATALINES(_l) ((_l) << 8)
+#define DSS_DISPC_CONTROL_TFTDATALINES_12 \
+ DSS_DISPC_CONTROL_TFTDATALINES(0u)
+#define DSS_DISPC_CONTROL_TFTDATALINES_16 \
+ DSS_DISPC_CONTROL_TFTDATALINES(1u)
+#define DSS_DISPC_CONTROL_TFTDATALINES_18 \
+ DSS_DISPC_CONTROL_TFTDATALINES(2u)
+#define DSS_DISPC_CONTROL_TFTDATALINES_24 \
+ DSS_DISPC_CONTROL_TFTDATALINES(3u)
+
+#define DSS_DISPC_CONTROL_STALLMODE (1u << 11)
+#define DSS_DISPC_CONTROL_OVERLAYOPTIMIZATION (1u << 12)
+#define DSS_DISPC_CONTROL_GPIN0 (1u << 13) /* ro */
+#define DSS_DISPC_CONTROL_GPIN1 (1u << 14) /* ro */
+#define DSS_DISPC_CONTROL_GPOUT0 (1u << 15)
+#define DSS_DISPC_CONTROL_GPOUT1 (1u << 16)
+#define DSS_DISPC_CONTROL_HT(_ht) ((_ht) << 17)
+#define DSS_DISPC_CONTROL_TDMENABLE (1u << 20)
+#define DSS_DISPC_CONTROL_TDMPARALLELMODE(_pm) ((_pm) << 21)
+#define DSS_DISPC_CONTROL_TDMCYCLEFORMAT(_cf) ((_cf) << 23)
+#define DSS_DISPC_CONTROL_TDMUNUSEDBITS(_ub) ((_ub) << 25)
+#define DSS_DISPC_CONTROL_PCKFREEENABLE (1u << 27)
+#define DSS_DISPC_CONTROL_LCDENABLESIGNAL (1u << 28)
+#define DSS_DISPC_CONTROL_LCDENABLEPOL (1u << 29)
+#define DSS_DISPC_CONTROL_SPATIALTEMPD(_df) ((_df) << 30)
+
+#define DSS_DISPC_POL_FREQ_IVS (1u << 12)
+#define DSS_DISPC_POL_FREQ_IHS (1u << 13)
+#define DSS_DISPC_POL_FREQ_IPC (1u << 14)
+#define DSS_DISPC_POL_FREQ_IEO (1u << 15)
+#define DSS_DISPC_POL_FREQ_RF (1u << 16)
+#define DSS_DISPC_POL_FREQ_ONOFF (1u << 17)
+
+#define DSS_DISPC_TIMING_H_HSW(_hsw) ((_hsw) << 0)
+#define DSS_DISPC_TIMING_H_HFP(_hfp) ((_hfp) << 8)
+#define DSS_DISPC_TIMING_H_HBP(_hbp) ((_hbp) << 20)
+
+#define DSS_DISPC_TIMING_V_VSW(_vsw) ((_vsw) << 0)
+#define DSS_DISPC_TIMING_V_VFP(_vfp) ((_vfp) << 8)
+#define DSS_DISPC_TIMING_V_VBP(_vbp) ((_vbp) << 20)
+
+#define DSS_DISPC_DIVISOR_ENABLE (1u << 0)
+#define DSS_DISPC_DIVISOR_LCD(_lcd) ((_lcd) << 16)
+
+#define DSS_DISPC_DIVISOR2_PCD(_pcd) ((_pcd) << 0)
+#define DSS_DISPC_DIVISOR2_LCD(_lcd) ((_lcd) << 16)
+
+#define DSS_DISPC_IRQSTATUS_FRAMEDONE (1u << 0)
+#define DSS_DISPC_IRQSTATUS_FRAMEDONE2 (1u << 22)
+
+#define DSS_DSS_SYSCONFIG_SOFTRESET (1u << 1)
+#define DSS_DSS_SYSSTATUS_RESETDONE (1u << 0)
+
+#define DSS_DSS_CONTROL_DISPC_CLK_SWITCH (1u << 0)
+#define DSS_DSS_CONTROL_DSI_CLK_SWITCH (1u << 1)
+
+#define CM_FCLKEN_DSS_EN_DSS1 (1u << 0)
+#define CM_FCLKEN_DSS_EN_DSS2 (1u << 1)
+#define CM_FCLKEN_DSS_EN_TV (1u << 2)
+
+#define CM_ICLKEN_DSS_EN_DSS (1u << 0)
+
+
+#undef OMAP4_RESERVED
+
+#endif /* H_BAREBOX_DRIVER_VIDEO_OMAP4_REGS_H */
--
1.7.10.4
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3] omap4-fb: add driver
2013-06-12 20:45 ` [PATCH v3] " Christoph Fritz
@ 2013-06-13 10:10 ` Jean-Christophe PLAGNIOL-VILLARD
2013-06-13 22:40 ` [PATCH v4] " Christoph Fritz
0 siblings, 1 reply; 24+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2013-06-13 10:10 UTC (permalink / raw)
To: Christoph Fritz; +Cc: barebox
On Jun 12, 2013, at 10:45 PM, Christoph Fritz <chf.fritz@googlemail.com> wrote:
> This patch adds omap4 display controller support.
>
> Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
> ---
> changes since v2:
> - use dev_request_mem_region_by_name()
> ---
> arch/arm/mach-omap/Makefile | 1 +
> arch/arm/mach-omap/include/mach/omap4-fb.h | 46 +++
> arch/arm/mach-omap/omap4_fb.c | 27 ++
> drivers/video/Kconfig | 8 +
> drivers/video/Makefile | 1 +
> drivers/video/omap4.c | 507 ++++++++++++++++++++++++++++
> drivers/video/omap4.h | 408 ++++++++++++++++++++++
> 7 files changed, 998 insertions(+)
In linux we does not use the struct for regs and I'll *never* accept this
so please drop me this. This is a huge nightmare to maintain and hugely easy to
move registers by touching the struct
really DROP IT
Best Regards,
J.
> create mode 100644 arch/arm/mach-omap/include/mach/omap4-fb.h
> create mode 100644 arch/arm/mach-omap/omap4_fb.c
> create mode 100644 drivers/video/omap4.c
> create mode 100644 drivers/video/omap4.h
>
> diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile
> index 94e42c6..e70ddbd 100644
> --- a/arch/arm/mach-omap/Makefile
> +++ b/arch/arm/mach-omap/Makefile
> @@ -28,6 +28,7 @@ obj-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
> pbl-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
> obj-$(CONFIG_OMAP_GPMC) += gpmc.o devices-gpmc-nand.o
> obj-$(CONFIG_SHELL_NONE) += xload.o
> +obj-$(CONFIG_DRIVER_VIDEO_OMAP4) += omap4_fb.o
> obj-$(CONFIG_I2C_TWL6030) += omap4_twl6030_mmc.o
> obj-$(CONFIG_OMAP4_USBBOOT) += omap4_rom_usb.o
> obj-y += gpio.o
> diff --git a/arch/arm/mach-omap/include/mach/omap4-fb.h b/arch/arm/mach-omap/include/mach/omap4-fb.h
> new file mode 100644
> index 0000000..5c0a54b
> --- /dev/null
> +++ b/arch/arm/mach-omap/include/mach/omap4-fb.h
> @@ -0,0 +1,46 @@
> +#ifndef H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H
> +#define H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H
> +
> +#include <fb.h>
> +
> +#define OMAP_DSS_LCD_TFT (1u << 0)
> +#define OMAP_DSS_LCD_IVS (1u << 1)
> +#define OMAP_DSS_LCD_IHS (1u << 2)
> +#define OMAP_DSS_LCD_IPC (1u << 3)
> +#define OMAP_DSS_LCD_IEO (1u << 4)
> +#define OMAP_DSS_LCD_RF (1u << 5)
> +#define OMAP_DSS_LCD_ONOFF (1u << 6)
> +
> +#define OMAP_DSS_LCD_DATALINES(_l) ((_l) << 10)
> +#define OMAP_DSS_LCD_DATALINES_msk OMAP_DSS_LCD_DATALINES(3u)
> +#define OMAP_DSS_LCD_DATALINES_12 OMAP_DSS_LCD_DATALINES(0u)
> +#define OMAP_DSS_LCD_DATALINES_16 OMAP_DSS_LCD_DATALINES(1u)
> +#define OMAP_DSS_LCD_DATALINES_18 OMAP_DSS_LCD_DATALINES(2u)
> +#define OMAP_DSS_LCD_DATALINES_24 OMAP_DSS_LCD_DATALINES(3u)
> +
> +struct omap4fb_display {
> + struct fb_videomode mode;
> +
> + unsigned long config;
> +
> + unsigned int power_on_delay;
> + unsigned int power_off_delay;
> +};
> +
> +struct omap4fb_platform_data {
> + struct omap4fb_display const *displays;
> + size_t num_displays;
> +
> + unsigned int dss_clk_hz;
> +
> + unsigned int bpp;
> +
> + struct resource const *screen;
> +
> + void (*enable)(int p);
> +};
> +
> +struct device_d;
> +struct device_d *omap4_add_display(void *pdata);
> +
> +#endif /* H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H */
> diff --git a/arch/arm/mach-omap/omap4_fb.c b/arch/arm/mach-omap/omap4_fb.c
> new file mode 100644
> index 0000000..09a6af3
> --- /dev/null
> +++ b/arch/arm/mach-omap/omap4_fb.c
> @@ -0,0 +1,27 @@
> +#include <driver.h>
> +#include <common.h>
> +#include <linux/ioport.h>
> +#include <mach/omap4-fb.h>
> +
> +static struct resource omap4_fb_resources[] = {
> + {
> + .name = "omap4_dss",
> + .start = 0x48040000,
> + .end = 0x48040000 + 512 - 1,
> + .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
> + }, {
> + .name = "omap4_dispc",
> + .start = 0x48041000,
> + .end = 0x48041000 + 3072 - 1,
> + .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
> + },
> +};
> +
> +struct device_d *omap4_add_display(void *pdata)
> +{
> + return add_generic_device_res("omap4_fb", -1,
> + omap4_fb_resources,
> + ARRAY_SIZE(omap4_fb_resources),
> + pdata);
> +}
> +EXPORT_SYMBOL(omap4_add_display);
> diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
> index 6d6b08f..9dfa0cd 100644
> --- a/drivers/video/Kconfig
> +++ b/drivers/video/Kconfig
> @@ -45,6 +45,14 @@ config DRIVER_VIDEO_S3C24XX
> help
> Add support for the S3C244x LCD controller.
>
> +config DRIVER_VIDEO_OMAP4
> + bool "OMAP4 framebuffer driver"
> + depends on ARCH_OMAP4
> + help
> + Add support for the OMAP4 Display Controller.
> + DSI is unsupported, only DISPC parallel mode on LCD2
> + is supported.
> +
> if DRIVER_VIDEO_S3C24XX
>
> config DRIVER_VIDEO_S3C_VERBOSE
> diff --git a/drivers/video/Makefile b/drivers/video/Makefile
> index 7429141..83feebb 100644
> --- a/drivers/video/Makefile
> +++ b/drivers/video/Makefile
> @@ -8,3 +8,4 @@ obj-$(CONFIG_DRIVER_VIDEO_IMX_IPU) += imx-ipu-fb.o
> obj-$(CONFIG_DRIVER_VIDEO_S3C24XX) += s3c24xx.o
> obj-$(CONFIG_DRIVER_VIDEO_PXA) += pxa.o
> obj-$(CONFIG_DRIVER_VIDEO_SDL) += sdl.o
> +obj-$(CONFIG_DRIVER_VIDEO_OMAP4) += omap4.o
> diff --git a/drivers/video/omap4.c b/drivers/video/omap4.c
> new file mode 100644
> index 0000000..887a5c0
> --- /dev/null
> +++ b/drivers/video/omap4.c
> @@ -0,0 +1,507 @@
> +/*
> + * TI Omap4 Frame Buffer device driver
> + *
> + * Copyright (C) 2013 Christoph Fritz <chf.fritz@googlemail.com>
> + * Based on work by Enrico Scholz, sponsored by Phytec
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <driver.h>
> +#include <fb.h>
> +#include <errno.h>
> +#include <xfuncs.h>
> +#include <init.h>
> +#include <stdio.h>
> +#include <io.h>
> +#include <common.h>
> +#include <malloc.h>
> +#include <common.h>
> +#include <clock.h>
> +
> +#include <mach/omap4-silicon.h>
> +#include <mach/omap4-fb.h>
> +
> +#include "omap4.h"
> +
> +struct omap4fb_device {
> + struct fb_info info;
> + struct device_d *dev;
> +
> + struct omap4fb_display const *cur_display;
> +
> + struct omap4fb_display const *displays;
> + size_t num_displays;
> +
> + struct {
> + struct omap4_regs_dss __iomem *dss;
> + struct omap4_regs_dispc __iomem *dispc;
> + } regs;
> +
> + struct {
> + void __iomem *addr;
> + size_t size;
> + } prealloc_screen;
> +
> + struct {
> + uint32_t dispc_control;
> + uint32_t dispc_pol_freq;
> + } shadow;
> +
> + struct {
> + unsigned int dss_clk_hz;
> + unsigned int lckd;
> + unsigned int pckd;
> + } divisor;
> +
> + void (*enable_fn)(int);
> +
> + struct fb_videomode video_modes[];
> +};
> +
> +static inline void fb_write(uint32_t v, void __iomem *addr)
> +{
> + __raw_writel(v, addr);
> +}
> +
> +static inline uint32_t fb_read(void const __iomem *addr)
> +{
> + return __raw_readl(addr);
> +}
> +
> +static void omap4fb_enable(struct fb_info *info)
> +{
> + struct omap4fb_device *fbi =
> + container_of(info, struct omap4fb_device, info);
> + struct omap4_regs_dispc __iomem *dispc = fbi->regs.dispc;
> +
> + dev_info(fbi->dev, "%s\n", __func__);
> +
> + if (!fbi->cur_display) {
> + dev_err(fbi->dev, "no valid mode set\n");
> + return;
> + }
> +
> + if (fbi->enable_fn)
> + fbi->enable_fn(1);
> +
> + udelay(fbi->cur_display->power_on_delay * 1000u);
> +
> + fb_write(fb_read(&dispc->control2) |
> + DSS_DISPC_CONTROL_LCDENABLE |
> + 1*DSS_DISPC_CONTROL_LCDENABLESIGNAL,
> + &dispc->control2);
> +
> + fb_write(fb_read(&dispc->vid1.attributes) |
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE,
> + &dispc->vid1.attributes);
> +
> + fb_write(fb_read(&dispc->control2) |
> + DSS_DISPC_CONTROL_GOLCD,
> + &dispc->control2);
> +}
> +
> +static void omap4fb_disable(struct fb_info *info)
> +{
> + struct omap4fb_device *fbi =
> + container_of(info, struct omap4fb_device, info);
> + struct omap4_regs_dispc __iomem *dispc = fbi->regs.dispc;
> +
> + dev_info(fbi->dev, "%s\n", __func__);
> +
> + if (!fbi->cur_display) {
> + dev_err(fbi->dev, "no valid mode set\n");
> + return;
> + }
> +
> + fb_write(fb_read(&dispc->control2) &
> + ~(DSS_DISPC_CONTROL_LCDENABLE |
> + DSS_DISPC_CONTROL_LCDENABLESIGNAL),
> + &dispc->control2);
> +
> + fb_write(fb_read(&dispc->vid1.attributes) &
> + ~(DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE),
> + &dispc->vid1.attributes);
> +
> + if (fbi->prealloc_screen.addr == NULL)
> + /* free frame buffer; but only when screen is not
> + * preallocated */
> + free(info->screen_base);
> +
> + info->screen_base = NULL;
> +
> + udelay(fbi->cur_display->power_off_delay * 1000u);
> +
> + if (fbi->enable_fn)
> + fbi->enable_fn(0);
> +}
> +
> +static void omap4fb_calc_divisor(struct omap4fb_device *fbi,
> + struct fb_videomode const *mode)
> +{
> + unsigned int l, k, t, b;
> +
> + b = UINT_MAX;
> + for (l = 1; l < 256; l++) {
> + for (k = 1; k < 256; k++) {
> + t = abs(mode->pixclock * 100 -
> + (fbi->divisor.dss_clk_hz / l / k));
> + if (t <= b) {
> + b = t;
> + fbi->divisor.lckd = l;
> + fbi->divisor.pckd = k;
> + }
> + }
> + }
> +}
> +
> +static unsigned int omap4fb_calc_format(struct fb_info const *info)
> +{
> + switch (info->bits_per_pixel) {
> + case 24: return 9;
> + case 32: return 0x8; /* xRGB24-8888 (32-bit container) */
> + default:
> + printf("%s: unsupported bpp %d\n", __func__,
> + info->bits_per_pixel);
> + return 0;
> + }
> +}
> +
> +struct omap4fb_colors {
> + struct fb_bitfield red;
> + struct fb_bitfield green;
> + struct fb_bitfield blue;
> + struct fb_bitfield transp;
> +};
> +
> +static struct omap4fb_colors const omap4fb_col[] = {
> + [0] = {
> + .red = { .length = 0, .offset = 0 },
> + },
> + [1] = {
> + .blue = { .length = 8, .offset = 0 },
> + .green = { .length = 8, .offset = 8 },
> + .red = { .length = 8, .offset = 16 },
> + },
> + [2] = {
> + .blue = { .length = 8, .offset = 0 },
> + .green = { .length = 8, .offset = 8 },
> + .red = { .length = 8, .offset = 16 },
> + .transp = { .length = 8, .offset = 24 },
> + },
> +};
> +
> +static void omap4fb_fill_shadow(struct omap4fb_device *fbi,
> + struct omap4fb_display const *display)
> +{
> + fbi->shadow.dispc_control = 0;
> + fbi->shadow.dispc_pol_freq = 0;
> +
> + fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_STNTFT;
> +
> + switch (display->config & OMAP_DSS_LCD_DATALINES_msk) {
> + case OMAP_DSS_LCD_DATALINES_12:
> + fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_12;
> + break;
> + case OMAP_DSS_LCD_DATALINES_16:
> + fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_16;
> + break;
> + case OMAP_DSS_LCD_DATALINES_18:
> + fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_18;
> + break;
> + case OMAP_DSS_LCD_DATALINES_24:
> + fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_24;
> + break;
> + }
> +
> + if (display->config & OMAP_DSS_LCD_IPC)
> + fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IPC;
> +
> + if (display->config & OMAP_DSS_LCD_IVS)
> + fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IVS;
> +
> + if (display->config & OMAP_DSS_LCD_IHS)
> + fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IHS;
> +
> + if (display->config & OMAP_DSS_LCD_IEO)
> + fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IEO;
> +
> + if (display->config & OMAP_DSS_LCD_RF)
> + fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_RF;
> +
> + if (display->config & OMAP_DSS_LCD_ONOFF)
> + fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_ONOFF;
> +}
> +
> +static int omap4fb_activate_var(struct fb_info *info)
> +{
> + struct omap4fb_device *fbi =
> + container_of(info, struct omap4fb_device, info);
> + struct omap4_regs_dispc __iomem *dispc = fbi->regs.dispc;
> + struct fb_videomode const *mode = info->mode;
> + size_t size = mode->xres * mode->yres * (info->bits_per_pixel / 8);
> + int rc;
> + unsigned int fmt = omap4fb_calc_format(info);
> + struct omap4fb_colors const *cols;
> + size_t i;
> + struct omap4fb_display const *new_display = NULL;
> +
> + for (i = 0; i < fbi->num_displays && new_display == NULL; ++i) {
> + if (strcmp(mode->name, fbi->displays[i].mode.name) == 0)
> + new_display = &fbi->displays[i];
> + }
> +
> + if (WARN_ON(!new_display)) {
> + dev_err(fbi->dev, "no matching display found for this mode '%s'\n",
> + mode->name);
> + rc = -ENXIO;
> + goto out;
> + }
> +
> + if (fbi->prealloc_screen.addr == NULL) {
> + /* case 1: no preallocated screen */
> + free(info->screen_base);
> + info->screen_base = memalign(0x100, size);
> + } else if (fbi->prealloc_screen.size < size) {
> + /* case 2: preallocated screen, but too small */
> + dev_err(fbi->dev,
> + "allocated framebuffer too small (%zu < %zu)\n",
> + fbi->prealloc_screen.size, size);
> + rc = -ENOMEM;
> + goto out;
> + } else {
> + /* case 3: preallocated screen */
> + info->screen_base = fbi->prealloc_screen.addr;
> + }
> +
> + omap4fb_fill_shadow(fbi, new_display);
> +
> + omap4fb_calc_divisor(fbi, mode);
> +
> + switch (info->bits_per_pixel) {
> + case 24:
> + cols = &omap4fb_col[1];
> + break;
> + case 32:
> + cols = &omap4fb_col[2];
> + break;
> + default:
> + cols = &omap4fb_col[0];
> + }
> +
> + info->red = cols->red;
> + info->green = cols->green;
> + info->blue = cols->blue;
> + info->transp = cols->transp;
> +
> + fb_write(fbi->shadow.dispc_control,
> + &dispc->control2);
> +
> + fb_write(fbi->shadow.dispc_pol_freq,
> + &dispc->pol_freq2);
> +
> + fb_write(DSS_DISPC_TIMING_H_HSW(mode->hsync_len - 1) |
> + DSS_DISPC_TIMING_H_HFP(mode->right_margin - 1) |
> + DSS_DISPC_TIMING_H_HBP(mode->left_margin - 1),
> + &dispc->timing_h2);
> +
> + fb_write(DSS_DISPC_TIMING_V_VSW(mode->vsync_len - 1) |
> + DSS_DISPC_TIMING_V_VFP(mode->lower_margin) |
> + DSS_DISPC_TIMING_V_VBP(mode->upper_margin),
> + &dispc->timing_v2);
> +
> + fb_write(DSS_DISPC_DIVISOR_ENABLE | DSS_DISPC_DIVISOR_LCD(1),
> + &dispc->divisor);
> +
> + fb_write(DSS_DISPC_DIVISOR2_LCD(fbi->divisor.lckd) |
> + DSS_DISPC_DIVISOR2_PCD(fbi->divisor.pckd),
> + &dispc->divisor2);
> +
> + fb_write(DSS_DISPC_SIZE_LCD_PPL(mode->xres - 1) |
> + DSS_DISPC_SIZE_LCD_LPP(mode->yres - 1),
> + &dispc->size_lcd2);
> +
> + fb_write(0x0000FF00, &dispc->default_color2);
> +
> + /* we use VID1 */
> + fb_write((uintptr_t)info->screen_base, &dispc->vid1.ba[0]);
> + fb_write((uintptr_t)info->screen_base, &dispc->vid1.ba[1]);
> +
> + fb_write(DSS_DISPC_VIDn_POSITION_VIDPOSX(0) |
> + DSS_DISPC_VIDn_POSITION_VIDPOSY(0),
> + &dispc->vid1.position);
> + fb_write(DSS_DISPC_VIDn_SIZE_VIDSIZEX(mode->xres - 1) |
> + DSS_DISPC_VIDn_SIZE_VIDSIZEY(mode->yres - 1),
> + &dispc->vid1.size);
> + fb_write(DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEX(mode->xres - 1) |
> + DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEY(mode->yres - 1),
> + &dispc->vid1.picture_size);
> + fb_write(1, &dispc->vid1.row_inc);
> + fb_write(1, &dispc->vid1.pixel_inc);
> +
> + fb_write(0xfff, &dispc->vid_preload[0]);
> +
> + fb_write(DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(fmt) |
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_8x128 |
> + DSS_DISPC_VIDn_ATTRIBUTES_ZORDERENABLE |
> + DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_SECONDARY_LCD,
> + &dispc->vid1.attributes);
> +
> + while (fb_read(&dispc->control2) & DSS_DISPC_CONTROL_GOLCD)
> + ; /* noop */
> +
> + fb_write(fb_read(&dispc->control2) |
> + DSS_DISPC_CONTROL_GOLCD,
> + &dispc->control2);
> +
> + fbi->cur_display = new_display;
> + info->xres = mode->xres;
> + info->yres = mode->yres;
> +
> + rc = 0;
> +
> +out:
> + return rc;
> +}
> +
> +static void omap4fb_reset(struct omap4fb_device const *fbi)
> +{
> + struct omap4_regs_dispc __iomem *dispc = fbi->regs.dispc;
> + struct omap4_regs_dss __iomem *dss = fbi->regs.dss;
> +
> + uint32_t v = fb_read(&dispc->control2);
> +
> + /* step 1: stop the LCD controller */
> + if (v & DSS_DISPC_CONTROL_LCDENABLE) {
> + fb_write(v & ~DSS_DISPC_CONTROL_LCDENABLE,
> + &dispc->control2);
> +
> + fb_write(DSS_DISPC_IRQSTATUS_FRAMEDONE2, &dispc->irqstatus);
> +
> + while ((fb_read(&dispc->irqstatus) &
> + DSS_DISPC_IRQSTATUS_FRAMEDONE) == 0)
> + ; /* noop */
> + }
> +
> + /* step 2: wait for reset done status */
> + while (!(fb_read(&dss->sysstatus) & DSS_DSS_SYSSTATUS_RESETDONE))
> + ; /* noop */
> +
> + /* DSS_CTL: set to reset value */
> + fb_write(0, &dss->ctrl);
> +}
> +
> +static struct fb_ops omap4fb_ops = {
> + .fb_enable = omap4fb_enable,
> + .fb_disable = omap4fb_disable,
> + .fb_activate_var = omap4fb_activate_var,
> +};
> +
> +static int omap4fb_probe(struct device_d *dev)
> +{
> + struct omap4fb_platform_data const *pdata = dev->platform_data;
> + struct omap4fb_device *fbi;
> + struct fb_info *info;
> + struct omap4_regs_dispc __iomem *dispc;
> + struct omap4_regs_dss __iomem *dss;
> + int rc;
> + size_t i;
> +
> + if (!pdata)
> + return -ENODEV;
> +
> + fbi = xzalloc(sizeof *fbi +
> + pdata->num_displays * sizeof fbi->video_modes[0]);
> + info = &fbi->info;
> +
> + fbi->dev = dev;
> +
> + /* CM_DSS_CLKSTCTRL (TRM: 935) trigger SW_WKUP */
> + __raw_writel(0x2, 0x4a009100); /* TODO: move this to clockmanagement */
> +
> + fbi->regs.dss = dev_request_mem_region_by_name(dev, "omap4_dss");
> + fbi->regs.dispc = dev_request_mem_region_by_name(dev, "omap4_dispc");
> +
> + if (!fbi->regs.dss || !fbi->regs.dispc) {
> + dev_err(dev, "Insufficient register description\n");
> + rc = -EINVAL;
> + goto out;
> + }
> +
> + dispc = fbi->regs.dispc;
> + dss = fbi->regs.dss;
> + dev_info(dev, "HW-Revision 0x%04x 0x%04x\n",
> + fb_read(&dispc->revision),
> + fb_read(&dss->revision));
> +
> +
> + if (!pdata->dss_clk_hz | !pdata->displays | !pdata->num_displays |
> + !pdata->bpp) {
> + dev_err(dev, "Insufficient omap4fb_platform_data\n");
> + rc = -EINVAL;
> + goto out;
> + }
> +
> + fbi->enable_fn = pdata->enable;
> + fbi->displays = pdata->displays;
> + fbi->num_displays = pdata->num_displays;
> + fbi->divisor.dss_clk_hz = pdata->dss_clk_hz;
> +
> + for (i = 0; i < pdata->num_displays; ++i)
> + fbi->video_modes[i] = pdata->displays[i].mode;
> +
> + info->mode_list = fbi->video_modes;
> + info->num_modes = pdata->num_displays;
> +
> + info->priv = fbi;
> + info->fbops = &omap4fb_ops;
> + info->bits_per_pixel = pdata->bpp;
> +
> + if (pdata->screen) {
> + fbi->prealloc_screen.addr =
> + (void __iomem *)pdata->screen->start;
> + fbi->prealloc_screen.size = resource_size(pdata->screen);
> + }
> +
> + omap4fb_reset(fbi);
> +
> + dev_add_param(fbi->dev, "bootargs", NULL, NULL, 0);
> +
> + rc = register_framebuffer(info);
> + if (rc < 0) {
> + dev_err(dev, "failed to register framebuffer: %d\n", rc);
> + goto out;
> + }
> +
> + rc = 0;
> + dev_info(dev, "registered\n");
> +
> +out:
> + if (rc < 0)
> + free(fbi);
> +
> + return rc;
> +}
> +
> +static struct driver_d omap4fb_driver = {
> + .name = "omap4_fb",
> + .probe = omap4fb_probe,
> +};
> +
> +static int omap4fb_init(void)
> +{
> + return platform_driver_register(&omap4fb_driver);
> +}
> +
> +device_initcall(omap4fb_init);
> diff --git a/drivers/video/omap4.h b/drivers/video/omap4.h
> new file mode 100644
> index 0000000..b3364a5
> --- /dev/null
> +++ b/drivers/video/omap4.h
> @@ -0,0 +1,408 @@
> +/*
> + * TI Omap4 Frame Buffer device driver
> + *
> + * Copyright (C) 2013 Christoph Fritz <chf.fritz@googlemail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef H_BAREBOX_DRIVER_VIDEO_OMAP4_REGS_H
> +#define H_BAREBOX_DRIVER_VIDEO_OMAP4_REGS_H
> +
> +#include <types.h>
> +#include <common.h>
> +
> +#define OMAP4_RESERVED(_f, _t) \
> + uint32_t const reserved_ ## _f ## _ ## _t[((_t) - (_f)) / 4]
> +
> +
> +/* TRM: 10.1.3.2 DSS Registers */
> +struct omap4_regs_dss {
> + uint32_t revision;
> + OMAP4_RESERVED(0x4, 0x14);
> + uint32_t const sysstatus;
> + OMAP4_RESERVED(0x18, 0x40);
> + uint32_t ctrl;
> + OMAP4_RESERVED(0x44, 0x5C);
> + uint32_t const status;
> +};
> +
> +
> +struct omap4_regs_dispc_vid {
> + uint32_t ba[2];
> + uint32_t position;
> + uint32_t size;
> + uint32_t attributes;
> + uint32_t buf_threshold;
> + uint32_t const buf_size_status;
> + uint32_t row_inc;
> + uint32_t pixel_inc;
> + uint32_t fir;
> + uint32_t picture_size;
> + uint32_t accu[2];
> + struct {
> + uint32_t h;
> + uint32_t hv;
> + } fir_coef[8];
> + uint32_t conv_coef0;
> + uint32_t conv_coef1;
> + uint32_t conv_coef2;
> + uint32_t conv_coef3;
> + uint32_t conv_coef4;
> +};
> +
> +/* TRM: 10.2.7.3 Display Controller Registers */
> +struct omap4_regs_dispc {
> + uint32_t const revision;
> + OMAP4_RESERVED(0x04, 0x10);
> + uint32_t sysconfig;
> + uint32_t const sysstatus;
> + uint32_t irqstatus;
> + uint32_t irqenable;
> + OMAP4_RESERVED(0x20, 0x40);
> + uint32_t control1;
> + uint32_t config1;
> + OMAP4_RESERVED(0x48, 0x4C);
> +
> + uint32_t default_color[2];
> + uint32_t trans_color[2];
> +
> + uint32_t const line_status;
> + uint32_t line_number;
> + uint32_t timing_h1;
> + uint32_t timing_v1;
> + uint32_t pol_freq1;
> + uint32_t divisor1;
> + uint32_t global_alpha;
> + uint32_t size_tv;
> + uint32_t size_lcd1;
> +
> + struct {
> + uint32_t ba[2];
> + uint32_t position;
> + uint32_t size;
> + OMAP4_RESERVED(0x90, 0xA0);
> + uint32_t attributes;
> + uint32_t buf_threshold;
> + uint32_t const buf_size_status;
> + uint32_t row_inc;
> + uint32_t pixel_inc;
> + OMAP4_RESERVED(0xB4, 0xB8);
> + uint32_t table_ba;
> + } gfx;
> +
> + struct omap4_regs_dispc_vid vid1;
> + OMAP4_RESERVED(0x144, 0x14C);
> + struct omap4_regs_dispc_vid vid2;
> +
> + uint32_t data1_cycle[3];
> +
> + uint32_t vid1_fir_coef_v[8];
> + uint32_t vid2_fir_coef_v[8];
> + uint32_t cpr1_coef_r;
> + uint32_t cpr1_coef_g;
> + uint32_t cpr1_coef_b;
> + uint32_t gfx_preload;
> + uint32_t vid_preload[2];
> + uint32_t control2;
> + OMAP4_RESERVED(0x23C, 0x300);
> +
> + struct {
> + uint32_t accu[2];
> + uint32_t ba[2];
> + struct {
> + uint32_t h;
> + uint32_t hv;
> + } fir_coef[8];
> + uint32_t fir_coef_v[8];
> + uint32_t attributes;
> + uint32_t conv_coef0;
> + uint32_t conv_coef1;
> + uint32_t conv_coef2;
> + uint32_t conv_coef3;
> + uint32_t conv_coef4;
> + uint32_t const buf_size_status;
> + uint32_t buf_threshold;
> + uint32_t fir;
> + uint32_t picture_size;
> + uint32_t pixel_inc;
> + uint32_t position;
> + uint32_t preload;
> + uint32_t row_inc;
> + uint32_t size;
> + } vid3;
> +
> + uint32_t default_color2;
> + uint32_t trans_color2;
> + uint32_t cpr2_coef_b;
> + uint32_t cpr2_coef_g;
> + uint32_t cpr2_coef_r;
> + uint32_t data2_cycle[3];
> + uint32_t size_lcd2;
> + OMAP4_RESERVED(0x3D0, 0x400);
> + uint32_t timing_h2;
> + uint32_t timing_v2;
> + uint32_t pol_freq2;
> + uint32_t divisor2;
> + OMAP4_RESERVED(0x410, 0x500);
> +
> + struct {
> + uint32_t accu[2];
> + uint32_t ba[2];
> + struct {
> + uint32_t h;
> + uint32_t hv;
> + } fir_coef[8];
> + uint32_t fir_coef_v[8];
> + uint32_t attributes;
> + uint32_t conv_coef0;
> + uint32_t conv_coef1;
> + uint32_t conv_coef2;
> + uint32_t conv_coef3;
> + uint32_t conv_coef4;
> + uint32_t const buf_size_status;
> + uint32_t buf_threshold;
> + uint32_t fir;
> + uint32_t picture_size;
> + uint32_t pixel_inc;
> + OMAP4_RESERVED(0x59C, 0x5A4);
> + uint32_t row_inc;
> + uint32_t size;
> + } wb;
> +
> + OMAP4_RESERVED(0x5AC, 0x600);
> + uint32_t vid1_ba_uv[2];
> + uint32_t vid2_ba_uv[2];
> + uint32_t vid3_ba_uv[2];
> + uint32_t wb_ba_uv[2];
> + uint32_t config2;
> + uint32_t vid1_attributes2;
> + uint32_t vid2_attributes2;
> + uint32_t vid3_attributes2;
> + uint32_t gamma_table0;
> + uint32_t gamma_table1;
> + uint32_t gamma_table2;
> + uint32_t vid1_fir2;
> + uint32_t vid1_accu2[2];
> + struct {
> + uint32_t h2;
> + uint32_t hv2;
> + } vid1_fir_coef[8];
> + uint32_t vid1_fir_coef_v2[8];
> + uint32_t vid2_fir2;
> + uint32_t vid2_accu2[2];
> + struct {
> + uint32_t h2;
> + uint32_t hv2;
> + } vid2_fir_coef[8];
> + uint32_t vid2_fir_coef_v2[8];
> + OMAP4_RESERVED(0x714, 0x724);
> + uint32_t vid3_fir2;
> + uint32_t vid3_accu2[2];
> + struct {
> + uint32_t h2;
> + uint32_t hv2;
> + } vid3_fir_coef[8];
> + uint32_t vid3_fir_coef_v2[8];
> + uint32_t wb_fir2;
> + uint32_t wb_accu2[2];
> + OMAP4_RESERVED(0x79C, 0x7A0);
> + struct {
> + uint32_t h2;
> + uint32_t hv2;
> + } wb_fir_coef[8];
> + uint32_t wb_fir_coef_v2[8];
> + uint32_t global_buffer;
> + uint32_t divisor;
> + OMAP4_RESERVED(0x808, 0x810);
> + uint32_t wb_attributes2;
> +};
> +
> +#define DSS_DISPC_VIDn_POSITION_VIDPOSX(_x) ((_x) << 0)
> +#define DSS_DISPC_VIDn_POSITION_VIDPOSY(_y) ((_y) << 16)
> +
> +#define DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEX(_x) ((_x) << 0)
> +#define DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEY(_y) ((_y) << 16)
> +
> +#define DSS_DISPC_VIDn_SIZE_VIDSIZEX(_x) ((_x) << 0)
> +#define DSS_DISPC_VIDn_SIZE_VIDSIZEY(_y) ((_y) << 16)
> +
> +#define DSS_DISPC_SIZE_LCD_PPL(_x) ((_x) << 0)
> +#define DSS_DISPC_SIZE_LCD_LPP(_y) ((_y) << 16)
> +
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE (1u << 0)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(_fmt) ((_fmt) << 1)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB12 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(4u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB16 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(5u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB16 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(6u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB16o \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(7u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_xRGB24u \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(8u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB24p \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(9u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_YUV2 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(10u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_UYVY \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(11u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB32 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(12u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGBA32 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(13u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_xRGB32 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(14u)
> +
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE(_f) ((_f) << 5)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE_NONE \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE(0u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE_H \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE(1u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE_V \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE(2u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE_HV \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDRESIZEENABLE(3u)
> +
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDCOLORCONVENABLE (1u << 9)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDREPLICATIONENABLE (1u << 10)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFULLRANGE (1u << 11)
> +
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION(_r) ((_r) << 12)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION_0 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION(0u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION_90 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION(1u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION_180 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION(2u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION_270 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDROTATION(3u)
> +
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(_b) ((_b) << 14)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_2x128 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(0u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_4x128 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(1u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_8x128 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(2u)
> +
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDCHANNELOUT (1u << 16)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_SELFREFRESHAUTO (1u << 17)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFIFOPRELOAD (1u << 19)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDVERTICALTAPS (1u << 21)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_DOUBLESTRIDE (1u << 22)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDARBITRATION (1u << 23)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDSELFREFRESH (1u << 24)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_ZORDERENABLE (1u << 25)
> +
> +#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(_b) ((_b) << 30)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_PRIMARY_LCD \
> + DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(0u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_SECONDARY_LCD \
> + DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(1u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_WRITEBACK_MEM \
> + DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(3u)
> +
> +#define DSS_DISPC_CONFIG_PIXELGATED (1u << 0)
> +#define DSS_DISPC_CONFIG_PIXELDATAGATED (1u << 4)
> +#define DSS_DISPC_CONFIG_PIXELCLOCKGATED (1u << 5)
> +#define DSS_DISPC_CONFIG_HSYNCGATED (1u << 6)
> +#define DSS_DISPC_CONFIG_VSYNCGATED (1u << 7)
> +#define DSS_DISPC_CONFIG_ACBIASGATED (1u << 8)
> +#define DSS_DISPC_CONFIG_FUNCGATED (1u << 9)
> +#define DSS_DISPC_CONFIG_TCKLCDENABLE (1u << 10)
> +#define DSS_DISPC_CONFIG_TCKLCDSELECTION (1u << 11)
> +#define DSS_DISPC_CONFIG_CPR (1u << 15)
> +#define DSS_DISPC_CONFIG_FIFOHANDCHECK (1u << 16)
> +#define DSS_DISPC_CONFIG_OUTPUTMODE (1u << 22)
> +#define DSS_DISPC_CONFIG_FIDFIRST (1u << 23)
> +#define DSS_DISPC_CONFIG_COLORCONV (1u << 24)
> +#define DSS_DISPC_CONFIG_FULLRANGE (1u << 25)
> +
> +#define DSS_DISPC_CONTROL_LCDENABLE (1u << 0)
> +#define DSS_DISPC_CONTROL_TVENABLE (1u << 1)
> +#define DSS_DISPC_CONTROL_MONOCOLOR (1u << 2)
> +#define DSS_DISPC_CONTROL_STNTFT (1u << 3)
> +#define DSS_DISPC_CONTROL_M8B (1u << 4)
> +#define DSS_DISPC_CONTROL_GOLCD (1u << 5)
> +#define DSS_DISPC_CONTROL_GOTV (1u << 6)
> +#define DSS_DISPC_CONTROL_STDITHERENABLE (1u << 7)
> +
> +#define DSS_DISPC_CONTROL_TFTDATALINES(_l) ((_l) << 8)
> +#define DSS_DISPC_CONTROL_TFTDATALINES_12 \
> + DSS_DISPC_CONTROL_TFTDATALINES(0u)
> +#define DSS_DISPC_CONTROL_TFTDATALINES_16 \
> + DSS_DISPC_CONTROL_TFTDATALINES(1u)
> +#define DSS_DISPC_CONTROL_TFTDATALINES_18 \
> + DSS_DISPC_CONTROL_TFTDATALINES(2u)
> +#define DSS_DISPC_CONTROL_TFTDATALINES_24 \
> + DSS_DISPC_CONTROL_TFTDATALINES(3u)
> +
> +#define DSS_DISPC_CONTROL_STALLMODE (1u << 11)
> +#define DSS_DISPC_CONTROL_OVERLAYOPTIMIZATION (1u << 12)
> +#define DSS_DISPC_CONTROL_GPIN0 (1u << 13) /* ro */
> +#define DSS_DISPC_CONTROL_GPIN1 (1u << 14) /* ro */
> +#define DSS_DISPC_CONTROL_GPOUT0 (1u << 15)
> +#define DSS_DISPC_CONTROL_GPOUT1 (1u << 16)
> +#define DSS_DISPC_CONTROL_HT(_ht) ((_ht) << 17)
> +#define DSS_DISPC_CONTROL_TDMENABLE (1u << 20)
> +#define DSS_DISPC_CONTROL_TDMPARALLELMODE(_pm) ((_pm) << 21)
> +#define DSS_DISPC_CONTROL_TDMCYCLEFORMAT(_cf) ((_cf) << 23)
> +#define DSS_DISPC_CONTROL_TDMUNUSEDBITS(_ub) ((_ub) << 25)
> +#define DSS_DISPC_CONTROL_PCKFREEENABLE (1u << 27)
> +#define DSS_DISPC_CONTROL_LCDENABLESIGNAL (1u << 28)
> +#define DSS_DISPC_CONTROL_LCDENABLEPOL (1u << 29)
> +#define DSS_DISPC_CONTROL_SPATIALTEMPD(_df) ((_df) << 30)
> +
> +#define DSS_DISPC_POL_FREQ_IVS (1u << 12)
> +#define DSS_DISPC_POL_FREQ_IHS (1u << 13)
> +#define DSS_DISPC_POL_FREQ_IPC (1u << 14)
> +#define DSS_DISPC_POL_FREQ_IEO (1u << 15)
> +#define DSS_DISPC_POL_FREQ_RF (1u << 16)
> +#define DSS_DISPC_POL_FREQ_ONOFF (1u << 17)
> +
> +#define DSS_DISPC_TIMING_H_HSW(_hsw) ((_hsw) << 0)
> +#define DSS_DISPC_TIMING_H_HFP(_hfp) ((_hfp) << 8)
> +#define DSS_DISPC_TIMING_H_HBP(_hbp) ((_hbp) << 20)
> +
> +#define DSS_DISPC_TIMING_V_VSW(_vsw) ((_vsw) << 0)
> +#define DSS_DISPC_TIMING_V_VFP(_vfp) ((_vfp) << 8)
> +#define DSS_DISPC_TIMING_V_VBP(_vbp) ((_vbp) << 20)
> +
> +#define DSS_DISPC_DIVISOR_ENABLE (1u << 0)
> +#define DSS_DISPC_DIVISOR_LCD(_lcd) ((_lcd) << 16)
> +
> +#define DSS_DISPC_DIVISOR2_PCD(_pcd) ((_pcd) << 0)
> +#define DSS_DISPC_DIVISOR2_LCD(_lcd) ((_lcd) << 16)
> +
> +#define DSS_DISPC_IRQSTATUS_FRAMEDONE (1u << 0)
> +#define DSS_DISPC_IRQSTATUS_FRAMEDONE2 (1u << 22)
> +
> +#define DSS_DSS_SYSCONFIG_SOFTRESET (1u << 1)
> +#define DSS_DSS_SYSSTATUS_RESETDONE (1u << 0)
> +
> +#define DSS_DSS_CONTROL_DISPC_CLK_SWITCH (1u << 0)
> +#define DSS_DSS_CONTROL_DSI_CLK_SWITCH (1u << 1)
> +
> +#define CM_FCLKEN_DSS_EN_DSS1 (1u << 0)
> +#define CM_FCLKEN_DSS_EN_DSS2 (1u << 1)
> +#define CM_FCLKEN_DSS_EN_TV (1u << 2)
> +
> +#define CM_ICLKEN_DSS_EN_DSS (1u << 0)
> +
> +
> +#undef OMAP4_RESERVED
> +
> +#endif /* H_BAREBOX_DRIVER_VIDEO_OMAP4_REGS_H */
> --
> 1.7.10.4
>
>
>
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^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v4] omap4-fb: add driver
2013-06-13 10:10 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2013-06-13 22:40 ` Christoph Fritz
2013-06-14 6:29 ` Alexander Aring
0 siblings, 1 reply; 24+ messages in thread
From: Christoph Fritz @ 2013-06-13 22:40 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox
This patch adds omap4 display controller support.
Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
---
changes since v2:
- use dev_request_mem_region_by_name()
changes since v3:
- remove register struct
- use uncached screen_base
---
arch/arm/mach-omap/Makefile | 1 +
arch/arm/mach-omap/include/mach/omap4-fb.h | 46 +++
arch/arm/mach-omap/omap4_fb.c | 27 ++
drivers/video/Kconfig | 8 +
drivers/video/Makefile | 1 +
drivers/video/omap4.c | 505 ++++++++++++++++++++++++++++
drivers/video/omap4.h | 179 ++++++++++
7 files changed, 767 insertions(+)
create mode 100644 arch/arm/mach-omap/include/mach/omap4-fb.h
create mode 100644 arch/arm/mach-omap/omap4_fb.c
create mode 100644 drivers/video/omap4.c
create mode 100644 drivers/video/omap4.h
diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile
index 94e42c6..e70ddbd 100644
--- a/arch/arm/mach-omap/Makefile
+++ b/arch/arm/mach-omap/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
pbl-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
obj-$(CONFIG_OMAP_GPMC) += gpmc.o devices-gpmc-nand.o
obj-$(CONFIG_SHELL_NONE) += xload.o
+obj-$(CONFIG_DRIVER_VIDEO_OMAP4) += omap4_fb.o
obj-$(CONFIG_I2C_TWL6030) += omap4_twl6030_mmc.o
obj-$(CONFIG_OMAP4_USBBOOT) += omap4_rom_usb.o
obj-y += gpio.o
diff --git a/arch/arm/mach-omap/include/mach/omap4-fb.h b/arch/arm/mach-omap/include/mach/omap4-fb.h
new file mode 100644
index 0000000..5c0a54b
--- /dev/null
+++ b/arch/arm/mach-omap/include/mach/omap4-fb.h
@@ -0,0 +1,46 @@
+#ifndef H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H
+#define H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H
+
+#include <fb.h>
+
+#define OMAP_DSS_LCD_TFT (1u << 0)
+#define OMAP_DSS_LCD_IVS (1u << 1)
+#define OMAP_DSS_LCD_IHS (1u << 2)
+#define OMAP_DSS_LCD_IPC (1u << 3)
+#define OMAP_DSS_LCD_IEO (1u << 4)
+#define OMAP_DSS_LCD_RF (1u << 5)
+#define OMAP_DSS_LCD_ONOFF (1u << 6)
+
+#define OMAP_DSS_LCD_DATALINES(_l) ((_l) << 10)
+#define OMAP_DSS_LCD_DATALINES_msk OMAP_DSS_LCD_DATALINES(3u)
+#define OMAP_DSS_LCD_DATALINES_12 OMAP_DSS_LCD_DATALINES(0u)
+#define OMAP_DSS_LCD_DATALINES_16 OMAP_DSS_LCD_DATALINES(1u)
+#define OMAP_DSS_LCD_DATALINES_18 OMAP_DSS_LCD_DATALINES(2u)
+#define OMAP_DSS_LCD_DATALINES_24 OMAP_DSS_LCD_DATALINES(3u)
+
+struct omap4fb_display {
+ struct fb_videomode mode;
+
+ unsigned long config;
+
+ unsigned int power_on_delay;
+ unsigned int power_off_delay;
+};
+
+struct omap4fb_platform_data {
+ struct omap4fb_display const *displays;
+ size_t num_displays;
+
+ unsigned int dss_clk_hz;
+
+ unsigned int bpp;
+
+ struct resource const *screen;
+
+ void (*enable)(int p);
+};
+
+struct device_d;
+struct device_d *omap4_add_display(void *pdata);
+
+#endif /* H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H */
diff --git a/arch/arm/mach-omap/omap4_fb.c b/arch/arm/mach-omap/omap4_fb.c
new file mode 100644
index 0000000..09a6af3
--- /dev/null
+++ b/arch/arm/mach-omap/omap4_fb.c
@@ -0,0 +1,27 @@
+#include <driver.h>
+#include <common.h>
+#include <linux/ioport.h>
+#include <mach/omap4-fb.h>
+
+static struct resource omap4_fb_resources[] = {
+ {
+ .name = "omap4_dss",
+ .start = 0x48040000,
+ .end = 0x48040000 + 512 - 1,
+ .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+ }, {
+ .name = "omap4_dispc",
+ .start = 0x48041000,
+ .end = 0x48041000 + 3072 - 1,
+ .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+ },
+};
+
+struct device_d *omap4_add_display(void *pdata)
+{
+ return add_generic_device_res("omap4_fb", -1,
+ omap4_fb_resources,
+ ARRAY_SIZE(omap4_fb_resources),
+ pdata);
+}
+EXPORT_SYMBOL(omap4_add_display);
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 6d6b08f..9dfa0cd 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -45,6 +45,14 @@ config DRIVER_VIDEO_S3C24XX
help
Add support for the S3C244x LCD controller.
+config DRIVER_VIDEO_OMAP4
+ bool "OMAP4 framebuffer driver"
+ depends on ARCH_OMAP4
+ help
+ Add support for the OMAP4 Display Controller.
+ DSI is unsupported, only DISPC parallel mode on LCD2
+ is supported.
+
if DRIVER_VIDEO_S3C24XX
config DRIVER_VIDEO_S3C_VERBOSE
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 7429141..83feebb 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_DRIVER_VIDEO_IMX_IPU) += imx-ipu-fb.o
obj-$(CONFIG_DRIVER_VIDEO_S3C24XX) += s3c24xx.o
obj-$(CONFIG_DRIVER_VIDEO_PXA) += pxa.o
obj-$(CONFIG_DRIVER_VIDEO_SDL) += sdl.o
+obj-$(CONFIG_DRIVER_VIDEO_OMAP4) += omap4.o
diff --git a/drivers/video/omap4.c b/drivers/video/omap4.c
new file mode 100644
index 0000000..74b1478
--- /dev/null
+++ b/drivers/video/omap4.c
@@ -0,0 +1,505 @@
+/*
+ * TI Omap4 Frame Buffer device driver
+ *
+ * Copyright (C) 2013 Christoph Fritz <chf.fritz@googlemail.com>
+ * Based on work by Enrico Scholz, sponsored by Phytec
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <driver.h>
+#include <fb.h>
+#include <errno.h>
+#include <xfuncs.h>
+#include <init.h>
+#include <stdio.h>
+#include <io.h>
+#include <common.h>
+#include <malloc.h>
+#include <common.h>
+#include <clock.h>
+
+#include <mach/omap4-silicon.h>
+#include <mach/omap4-fb.h>
+
+#include <asm/mmu.h>
+
+#include "omap4.h"
+
+struct omap4fb_device {
+ struct fb_info info;
+ struct device_d *dev;
+
+ struct omap4fb_display const *cur_display;
+
+ struct omap4fb_display const *displays;
+ size_t num_displays;
+
+ void __iomem *dss;
+ void __iomem *dispc;
+
+ struct {
+ void __iomem *addr;
+ size_t size;
+ } prealloc_screen;
+
+ struct {
+ uint32_t dispc_control;
+ uint32_t dispc_pol_freq;
+ } shadow;
+
+ struct {
+ unsigned int dss_clk_hz;
+ unsigned int lckd;
+ unsigned int pckd;
+ } divisor;
+ size_t dma_size;
+ void (*enable_fn)(int);
+
+ struct fb_videomode video_modes[];
+};
+
+static void omap4fb_enable(struct fb_info *info)
+{
+ struct omap4fb_device *fbi =
+ container_of(info, struct omap4fb_device, info);
+
+ dev_info(fbi->dev, "%s\n", __func__);
+
+ if (!fbi->cur_display) {
+ dev_err(fbi->dev, "no valid mode set\n");
+ return;
+ }
+
+ if (fbi->enable_fn)
+ fbi->enable_fn(1);
+
+ udelay(fbi->cur_display->power_on_delay * 1000u);
+
+ fb_write(fb_read(fbi->dispc, O4_DISPC_CONTROL2) |
+ DSS_DISPC_CONTROL_LCDENABLE |
+ DSS_DISPC_CONTROL_LCDENABLESIGNAL,
+ fbi->dispc, O4_DISPC_CONTROL2);
+
+ fb_write(fb_read(fbi->dispc, O4_DISPC_VID1_ATTRIBUTES) |
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE,
+ fbi->dispc, O4_DISPC_VID1_ATTRIBUTES);
+
+ fb_write(fb_read(fbi->dispc, O4_DISPC_CONTROL2) |
+ DSS_DISPC_CONTROL_GOLCD,
+ fbi->dispc, O4_DISPC_CONTROL2);
+}
+
+static void omap4fb_disable(struct fb_info *info)
+{
+ struct omap4fb_device *fbi =
+ container_of(info, struct omap4fb_device, info);
+
+ dev_info(fbi->dev, "%s\n", __func__);
+
+ if (!fbi->cur_display) {
+ dev_err(fbi->dev, "no valid mode set\n");
+ return;
+ }
+
+ fb_write(fb_read(fbi->dispc, O4_DISPC_CONTROL2) &
+ ~(DSS_DISPC_CONTROL_LCDENABLE |
+ DSS_DISPC_CONTROL_LCDENABLESIGNAL),
+ fbi->dispc, O4_DISPC_CONTROL2);
+
+ fb_write(fb_read(fbi->dispc, O4_DISPC_VID1_ATTRIBUTES) &
+ ~(DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE),
+ fbi->dispc, O4_DISPC_VID1_ATTRIBUTES);
+
+ if (fbi->prealloc_screen.addr == NULL) {
+ /* free frame buffer; but only when screen is not
+ * preallocated */
+ if (info->screen_base)
+ dma_free_coherent(info->screen_base, fbi->dma_size);
+ }
+
+ info->screen_base = NULL;
+
+ udelay(fbi->cur_display->power_off_delay * 1000u);
+
+ if (fbi->enable_fn)
+ fbi->enable_fn(0);
+}
+
+static void omap4fb_calc_divisor(struct omap4fb_device *fbi,
+ struct fb_videomode const *mode)
+{
+ unsigned int l, k, t, b;
+
+ b = UINT_MAX;
+ for (l = 1; l < 256; l++) {
+ for (k = 1; k < 256; k++) {
+ t = abs(mode->pixclock * 100 -
+ (fbi->divisor.dss_clk_hz / l / k));
+ if (t <= b) {
+ b = t;
+ fbi->divisor.lckd = l;
+ fbi->divisor.pckd = k;
+ }
+ }
+ }
+}
+
+static unsigned int omap4fb_calc_format(struct fb_info const *info)
+{
+ switch (info->bits_per_pixel) {
+ case 24: return 9;
+ case 32: return 0x8; /* xRGB24-8888 (32-bit container) */
+ default:
+ printf("%s: unsupported bpp %d\n", __func__,
+ info->bits_per_pixel);
+ return 0;
+ }
+}
+
+struct omap4fb_colors {
+ struct fb_bitfield red;
+ struct fb_bitfield green;
+ struct fb_bitfield blue;
+ struct fb_bitfield transp;
+};
+
+static struct omap4fb_colors const omap4fb_col[] = {
+ [0] = {
+ .red = { .length = 0, .offset = 0 },
+ },
+ [1] = {
+ .blue = { .length = 8, .offset = 0 },
+ .green = { .length = 8, .offset = 8 },
+ .red = { .length = 8, .offset = 16 },
+ },
+ [2] = {
+ .blue = { .length = 8, .offset = 0 },
+ .green = { .length = 8, .offset = 8 },
+ .red = { .length = 8, .offset = 16 },
+ .transp = { .length = 8, .offset = 24 },
+ },
+};
+
+static void omap4fb_fill_shadow(struct omap4fb_device *fbi,
+ struct omap4fb_display const *display)
+{
+ fbi->shadow.dispc_control = 0;
+ fbi->shadow.dispc_pol_freq = 0;
+
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_STNTFT;
+
+ switch (display->config & OMAP_DSS_LCD_DATALINES_msk) {
+ case OMAP_DSS_LCD_DATALINES_12:
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_12;
+ break;
+ case OMAP_DSS_LCD_DATALINES_16:
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_16;
+ break;
+ case OMAP_DSS_LCD_DATALINES_18:
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_18;
+ break;
+ case OMAP_DSS_LCD_DATALINES_24:
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_24;
+ break;
+ }
+
+ if (display->config & OMAP_DSS_LCD_IPC)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IPC;
+
+ if (display->config & OMAP_DSS_LCD_IVS)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IVS;
+
+ if (display->config & OMAP_DSS_LCD_IHS)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IHS;
+
+ if (display->config & OMAP_DSS_LCD_IEO)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IEO;
+
+ if (display->config & OMAP_DSS_LCD_RF)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_RF;
+
+ if (display->config & OMAP_DSS_LCD_ONOFF)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_ONOFF;
+}
+
+static int omap4fb_activate_var(struct fb_info *info)
+{
+ struct omap4fb_device *fbi =
+ container_of(info, struct omap4fb_device, info);
+ struct fb_videomode const *mode = info->mode;
+ size_t size = mode->xres * mode->yres * (info->bits_per_pixel / 8);
+ int rc;
+ unsigned int fmt = omap4fb_calc_format(info);
+ struct omap4fb_colors const *cols;
+ size_t i;
+ struct omap4fb_display const *new_display = NULL;
+
+ for (i = 0; i < fbi->num_displays && new_display == NULL; ++i) {
+ if (strcmp(mode->name, fbi->displays[i].mode.name) == 0)
+ new_display = &fbi->displays[i];
+ }
+
+ if (WARN_ON(!new_display)) {
+ dev_err(fbi->dev, "no display found for this mode '%s'\n",
+ mode->name);
+ rc = -ENXIO;
+ goto out;
+ }
+
+ /*Free old screen buf*/
+ if (!fbi->prealloc_screen.addr && info->screen_base)
+ dma_free_coherent(info->screen_base, fbi->dma_size);
+
+ fbi->dma_size = PAGE_ALIGN(size);
+
+ if (fbi->prealloc_screen.addr == NULL) {
+ /* case 1: no preallocated screen */
+ info->screen_base = dma_alloc_coherent(size);
+ } else if (fbi->prealloc_screen.size < fbi->dma_size) {
+ /* case 2: preallocated screen, but too small */
+ dev_err(fbi->dev,
+ "allocated framebuffer too small (%zu < %zu)\n",
+ fbi->prealloc_screen.size, fbi->dma_size);
+ rc = -ENOMEM;
+ goto out;
+ } else {
+ /* case 3: preallocated screen */
+ info->screen_base = fbi->prealloc_screen.addr;
+ }
+
+ omap4fb_fill_shadow(fbi, new_display);
+
+ omap4fb_calc_divisor(fbi, mode);
+
+ switch (info->bits_per_pixel) {
+ case 24:
+ cols = &omap4fb_col[1];
+ break;
+ case 32:
+ cols = &omap4fb_col[2];
+ break;
+ default:
+ cols = &omap4fb_col[0];
+ }
+
+ info->red = cols->red;
+ info->green = cols->green;
+ info->blue = cols->blue;
+ info->transp = cols->transp;
+
+ fb_write(fbi->shadow.dispc_control,
+ fbi->dispc, O4_DISPC_CONTROL2);
+
+ fb_write(fbi->shadow.dispc_pol_freq,
+ fbi->dispc, O4_DISPC_POL_FREQ2);
+
+ fb_write(DSS_DISPC_TIMING_H_HSW(mode->hsync_len - 1) |
+ DSS_DISPC_TIMING_H_HFP(mode->right_margin - 1) |
+ DSS_DISPC_TIMING_H_HBP(mode->left_margin - 1),
+ fbi->dispc, O4_DISPC_TIMING_H2);
+
+ fb_write(DSS_DISPC_TIMING_V_VSW(mode->vsync_len - 1) |
+ DSS_DISPC_TIMING_V_VFP(mode->lower_margin) |
+ DSS_DISPC_TIMING_V_VBP(mode->upper_margin),
+ fbi->dispc, O4_DISPC_TIMING_V2);
+
+ fb_write(DSS_DISPC_DIVISOR_ENABLE | DSS_DISPC_DIVISOR_LCD(1),
+ fbi->dispc, O4_DISPC_DIVISOR);
+
+ fb_write(DSS_DISPC_DIVISOR2_LCD(fbi->divisor.lckd) |
+ DSS_DISPC_DIVISOR2_PCD(fbi->divisor.pckd),
+ fbi->dispc, O4_DISPC_DIVISOR2);
+
+ fb_write(DSS_DISPC_SIZE_LCD_PPL(mode->xres - 1) |
+ DSS_DISPC_SIZE_LCD_LPP(mode->yres - 1),
+ fbi->dispc, O4_DISPC_SIZE_LCD2);
+
+ fb_write(0x0000ff00, fbi->dispc, O4_DISPC_DEFAULT_COLOR2);
+
+ /* we use VID1 */
+ fb_write((uintptr_t)info->screen_base, fbi->dispc, O4_DISPC_VID1_BA0);
+ fb_write((uintptr_t)info->screen_base, fbi->dispc, O4_DISPC_VID1_BA1);
+
+ fb_write(DSS_DISPC_VIDn_POSITION_VIDPOSX(0) |
+ DSS_DISPC_VIDn_POSITION_VIDPOSY(0),
+ fbi->dispc, O4_DISPC_VID1_POSITION);
+ fb_write(DSS_DISPC_VIDn_SIZE_VIDSIZEX(mode->xres - 1) |
+ DSS_DISPC_VIDn_SIZE_VIDSIZEY(mode->yres - 1),
+ fbi->dispc, O4_DISPC_VID1_SIZE);
+ fb_write(DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEX(mode->xres - 1) |
+ DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEY(mode->yres - 1),
+ fbi->dispc, O4_DISPC_VID1_PICTURE_SIZE);
+ fb_write(1, fbi->dispc, O4_DISPC_VID1_ROW_INC);
+ fb_write(1, fbi->dispc, O4_DISPC_VID1_PIXEL_INC);
+
+ fb_write(0xfff, fbi->dispc, O4_DISPC_VID1_PRELOAD);
+
+ fb_write(DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(fmt) |
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_8x128 |
+ DSS_DISPC_VIDn_ATTRIBUTES_ZORDERENABLE |
+ DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_SECONDARY_LCD,
+ fbi->dispc, O4_DISPC_VID1_ATTRIBUTES);
+
+ while (fb_read(fbi->dispc, O4_DISPC_CONTROL2) & DSS_DISPC_CONTROL_GOLCD)
+ ; /* noop */
+
+ fb_write(fb_read(fbi->dispc, O4_DISPC_CONTROL2) |
+ DSS_DISPC_CONTROL_GOLCD,
+ fbi->dispc, O4_DISPC_CONTROL2);
+
+ fbi->cur_display = new_display;
+ info->xres = mode->xres;
+ info->yres = mode->yres;
+
+ rc = 0;
+
+out:
+ return rc;
+}
+
+static void omap4fb_reset(struct omap4fb_device const *fbi)
+{
+ uint32_t v = fb_read(fbi->dispc, O4_DISPC_CONTROL2);
+
+ /* step 1: stop the LCD controller */
+ if (v & DSS_DISPC_CONTROL_LCDENABLE) {
+ fb_write(v & ~DSS_DISPC_CONTROL_LCDENABLE,
+ fbi->dispc, O4_DISPC_CONTROL2);
+
+ fb_write(DSS_DISPC_IRQSTATUS_FRAMEDONE2, fbi->dispc,
+ O4_DISPC_IRQSTATUS);
+
+ while ((fb_read(fbi->dispc, O4_DISPC_IRQSTATUS) &
+ DSS_DISPC_IRQSTATUS_FRAMEDONE) == 0)
+ ; /* noop */
+ }
+
+ /* step 2: wait for reset done status */
+ while (!(fb_read(fbi->dss, O4_DSS_SYSSTATUS) &
+ DSS_DSS_SYSSTATUS_RESETDONE))
+ ; /* noop */
+
+ /* DSS_CTL: set to reset value */
+ fb_write(0, fbi->dss, O4_DSS_CTRL);
+}
+
+static struct fb_ops omap4fb_ops = {
+ .fb_enable = omap4fb_enable,
+ .fb_disable = omap4fb_disable,
+ .fb_activate_var = omap4fb_activate_var,
+};
+
+static int omap4fb_probe(struct device_d *dev)
+{
+ struct omap4fb_platform_data const *pdata = dev->platform_data;
+ struct omap4fb_device *fbi;
+ struct fb_info *info;
+ int rc;
+ size_t i;
+
+ if (!pdata)
+ return -ENODEV;
+
+ fbi = xzalloc(sizeof *fbi +
+ pdata->num_displays * sizeof fbi->video_modes[0]);
+ info = &fbi->info;
+
+ fbi->dev = dev;
+
+ /* CM_DSS_CLKSTCTRL (TRM: 935) trigger SW_WKUP */
+ __raw_writel(0x2, 0x4a009100); /* TODO: move this to clockmanagement */
+
+ fbi->dss = dev_request_mem_region_by_name(dev, "omap4_dss");
+ fbi->dispc = dev_request_mem_region_by_name(dev, "omap4_dispc");
+
+ if (!fbi->dss || !fbi->dispc) {
+ dev_err(dev, "Insufficient register description\n");
+ rc = -EINVAL;
+ goto out;
+ }
+
+ dev_info(dev, "HW-Revision 0x%04x 0x%04x\n",
+ fb_read(fbi->dss, O4_DISPC_REVISION),
+ fb_read(fbi->dss, O4_DSS_REVISION));
+
+
+ if (!pdata->dss_clk_hz | !pdata->displays | !pdata->num_displays |
+ !pdata->bpp) {
+ dev_err(dev, "Insufficient omap4fb_platform_data\n");
+ rc = -EINVAL;
+ goto out;
+ }
+
+ fbi->enable_fn = pdata->enable;
+ fbi->displays = pdata->displays;
+ fbi->num_displays = pdata->num_displays;
+ fbi->divisor.dss_clk_hz = pdata->dss_clk_hz;
+
+ for (i = 0; i < pdata->num_displays; ++i)
+ fbi->video_modes[i] = pdata->displays[i].mode;
+
+ info->mode_list = fbi->video_modes;
+ info->num_modes = pdata->num_displays;
+
+ info->priv = fbi;
+ info->fbops = &omap4fb_ops;
+ info->bits_per_pixel = pdata->bpp;
+
+ if (pdata->screen) {
+ if (!IS_ALIGNED(pdata->screen->start, PAGE_SIZE) ||
+ !IS_ALIGNED(resource_size(pdata->screen), PAGE_SIZE)) {
+ dev_err(dev, "screen resource not aligned\n");
+ rc = -EINVAL;
+ goto out;
+ }
+ fbi->prealloc_screen.addr =
+ (void __iomem *)pdata->screen->start;
+ fbi->prealloc_screen.size = resource_size(pdata->screen);
+ remap_range(fbi->prealloc_screen.addr,
+ fbi->prealloc_screen.size,
+ mmu_get_pte_uncached_flags());
+ }
+
+ omap4fb_reset(fbi);
+
+ dev_add_param(fbi->dev, "bootargs", NULL, NULL, 0);
+
+ rc = register_framebuffer(info);
+ if (rc < 0) {
+ dev_err(dev, "failed to register framebuffer: %d\n", rc);
+ goto out;
+ }
+
+ rc = 0;
+ dev_info(dev, "registered\n");
+
+out:
+ if (rc < 0)
+ free(fbi);
+
+ return rc;
+}
+
+static struct driver_d omap4fb_driver = {
+ .name = "omap4_fb",
+ .probe = omap4fb_probe,
+};
+
+static int omap4fb_init(void)
+{
+ return platform_driver_register(&omap4fb_driver);
+}
+
+device_initcall(omap4fb_init);
diff --git a/drivers/video/omap4.h b/drivers/video/omap4.h
new file mode 100644
index 0000000..d8b39f9
--- /dev/null
+++ b/drivers/video/omap4.h
@@ -0,0 +1,179 @@
+/*
+ * TI Omap4 Frame Buffer device driver
+ *
+ * Copyright (C) 2013 Christoph Fritz <chf.fritz@googlemail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef H_BAREBOX_DRIVER_VIDEO_OMAP4_REGS_H
+#define H_BAREBOX_DRIVER_VIDEO_OMAP4_REGS_H
+
+#include <types.h>
+#include <common.h>
+
+#define fb_read(io, reg) __raw_readl((io)+(reg))
+#define fb_write(val, io, reg) __raw_writel((val), (io)+(reg))
+
+/* TRM: 10.1.3.2 DSS Registers */
+#define O4_DSS_REVISION 0x0
+#define O4_DSS_SYSSTATUS 0x14
+#define O4_DSS_CTRL 0x40
+#define O4_DSS_STATUS 0x5c
+
+/* TRM: 10.2.7.3 Display Controller Registers */
+#define O4_DISPC_REVISION 0x0
+#define O4_DISPC_IRQSTATUS 0x18
+#define O4_DISPC_CONTROL2 0x238
+#define O4_DISPC_VID1_ATTRIBUTES 0xcc
+#define O4_DISPC_TIMING_H2 0x400
+#define O4_DISPC_TIMING_V2 0x404
+#define O4_DISPC_POL_FREQ2 0x408
+#define O4_DISPC_DIVISOR2 0x40c
+#define O4_DISPC_DEFAULT_COLOR2 0x3ac
+#define O4_DISPC_SIZE_LCD2 0x3cc
+#define O4_DISPC_DIVISOR 0x804
+#define O4_DISPC_VID1_BA0 0xbc
+#define O4_DISPC_VID1_BA1 0xc0
+#define O4_DISPC_VID1_POSITION 0xc4
+#define O4_DISPC_VID1_SIZE 0xc8
+#define O4_DISPC_VID1_PICTURE_SIZE 0xe4
+#define O4_DISPC_VID1_ROW_INC 0xd8
+#define O4_DISPC_VID1_PIXEL_INC 0xdc
+#define O4_DISPC_VID1_PRELOAD 0x230
+
+#define DSS_DISPC_VIDn_POSITION_VIDPOSX(_x) ((_x) << 0)
+#define DSS_DISPC_VIDn_POSITION_VIDPOSY(_y) ((_y) << 16)
+
+#define DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEX(_x) ((_x) << 0)
+#define DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEY(_y) ((_y) << 16)
+
+#define DSS_DISPC_VIDn_SIZE_VIDSIZEX(_x) ((_x) << 0)
+#define DSS_DISPC_VIDn_SIZE_VIDSIZEY(_y) ((_y) << 16)
+
+#define DSS_DISPC_SIZE_LCD_PPL(_x) ((_x) << 0)
+#define DSS_DISPC_SIZE_LCD_LPP(_y) ((_y) << 16)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE (1u << 0)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(_fmt) ((_fmt) << 1)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB12 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(4u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB16 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(5u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB16 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(6u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB16o \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(7u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_xRGB24u \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(8u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB24p \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(9u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_YUV2 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(10u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_UYVY \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(11u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB32 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(12u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGBA32 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(13u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_xRGB32 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(14u)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(_b) ((_b) << 14)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_2x128 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(0u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_4x128 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(1u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_8x128 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(2u)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDCHANNELOUT (1u << 16)
+#define DSS_DISPC_VIDn_ATTRIBUTES_SELFREFRESHAUTO (1u << 17)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFIFOPRELOAD (1u << 19)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDVERTICALTAPS (1u << 21)
+#define DSS_DISPC_VIDn_ATTRIBUTES_DOUBLESTRIDE (1u << 22)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDARBITRATION (1u << 23)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDSELFREFRESH (1u << 24)
+#define DSS_DISPC_VIDn_ATTRIBUTES_ZORDERENABLE (1u << 25)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(_b) ((_b) << 30)
+#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_PRIMARY_LCD \
+ DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(0u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_SECONDARY_LCD \
+ DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(1u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_WRITEBACK_MEM \
+ DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(3u)
+
+#define DSS_DISPC_CONTROL_LCDENABLE (1u << 0)
+#define DSS_DISPC_CONTROL_TVENABLE (1u << 1)
+#define DSS_DISPC_CONTROL_MONOCOLOR (1u << 2)
+#define DSS_DISPC_CONTROL_STNTFT (1u << 3)
+#define DSS_DISPC_CONTROL_M8B (1u << 4)
+#define DSS_DISPC_CONTROL_GOLCD (1u << 5)
+#define DSS_DISPC_CONTROL_GOTV (1u << 6)
+#define DSS_DISPC_CONTROL_STDITHERENABLE (1u << 7)
+
+#define DSS_DISPC_CONTROL_TFTDATALINES(_l) ((_l) << 8)
+#define DSS_DISPC_CONTROL_TFTDATALINES_12 \
+ DSS_DISPC_CONTROL_TFTDATALINES(0u)
+#define DSS_DISPC_CONTROL_TFTDATALINES_16 \
+ DSS_DISPC_CONTROL_TFTDATALINES(1u)
+#define DSS_DISPC_CONTROL_TFTDATALINES_18 \
+ DSS_DISPC_CONTROL_TFTDATALINES(2u)
+#define DSS_DISPC_CONTROL_TFTDATALINES_24 \
+ DSS_DISPC_CONTROL_TFTDATALINES(3u)
+
+#define DSS_DISPC_CONTROL_STALLMODE (1u << 11)
+#define DSS_DISPC_CONTROL_OVERLAYOPTIMIZATION (1u << 12)
+#define DSS_DISPC_CONTROL_GPIN0 (1u << 13) /* ro */
+#define DSS_DISPC_CONTROL_GPIN1 (1u << 14) /* ro */
+#define DSS_DISPC_CONTROL_GPOUT0 (1u << 15)
+#define DSS_DISPC_CONTROL_GPOUT1 (1u << 16)
+#define DSS_DISPC_CONTROL_HT(_ht) ((_ht) << 17)
+#define DSS_DISPC_CONTROL_TDMENABLE (1u << 20)
+#define DSS_DISPC_CONTROL_TDMPARALLELMODE(_pm) ((_pm) << 21)
+#define DSS_DISPC_CONTROL_TDMCYCLEFORMAT(_cf) ((_cf) << 23)
+#define DSS_DISPC_CONTROL_TDMUNUSEDBITS(_ub) ((_ub) << 25)
+#define DSS_DISPC_CONTROL_PCKFREEENABLE (1u << 27)
+#define DSS_DISPC_CONTROL_LCDENABLESIGNAL (1u << 28)
+#define DSS_DISPC_CONTROL_LCDENABLEPOL (1u << 29)
+#define DSS_DISPC_CONTROL_SPATIALTEMPD(_df) ((_df) << 30)
+
+#define DSS_DISPC_POL_FREQ_IVS (1u << 12)
+#define DSS_DISPC_POL_FREQ_IHS (1u << 13)
+#define DSS_DISPC_POL_FREQ_IPC (1u << 14)
+#define DSS_DISPC_POL_FREQ_IEO (1u << 15)
+#define DSS_DISPC_POL_FREQ_RF (1u << 16)
+#define DSS_DISPC_POL_FREQ_ONOFF (1u << 17)
+
+#define DSS_DISPC_TIMING_H_HSW(_hsw) ((_hsw) << 0)
+#define DSS_DISPC_TIMING_H_HFP(_hfp) ((_hfp) << 8)
+#define DSS_DISPC_TIMING_H_HBP(_hbp) ((_hbp) << 20)
+
+#define DSS_DISPC_TIMING_V_VSW(_vsw) ((_vsw) << 0)
+#define DSS_DISPC_TIMING_V_VFP(_vfp) ((_vfp) << 8)
+#define DSS_DISPC_TIMING_V_VBP(_vbp) ((_vbp) << 20)
+
+#define DSS_DISPC_DIVISOR_ENABLE (1u << 0)
+#define DSS_DISPC_DIVISOR_LCD(_lcd) ((_lcd) << 16)
+
+#define DSS_DISPC_DIVISOR2_PCD(_pcd) ((_pcd) << 0)
+#define DSS_DISPC_DIVISOR2_LCD(_lcd) ((_lcd) << 16)
+
+#define DSS_DISPC_IRQSTATUS_FRAMEDONE (1u << 0)
+#define DSS_DISPC_IRQSTATUS_FRAMEDONE2 (1u << 22)
+
+#define DSS_DSS_SYSSTATUS_RESETDONE (1u << 0)
+
+#endif /* H_BAREBOX_DRIVER_VIDEO_O4_REGS_H */
--
1.7.10.4
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v4] omap4-fb: add driver
2013-06-13 22:40 ` [PATCH v4] " Christoph Fritz
@ 2013-06-14 6:29 ` Alexander Aring
2013-06-14 7:23 ` Jan Weitzel
0 siblings, 1 reply; 24+ messages in thread
From: Alexander Aring @ 2013-06-14 6:29 UTC (permalink / raw)
To: Christoph Fritz; +Cc: barebox
Hi,
On Fri, Jun 14, 2013 at 12:40:39AM +0200, Christoph Fritz wrote:
> This patch adds omap4 display controller support.
>
> Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
> ---
> changes since v2:
> - use dev_request_mem_region_by_name()
> changes since v3:
> - remove register struct
> - use uncached screen_base
> ---
> arch/arm/mach-omap/Makefile | 1 +
> arch/arm/mach-omap/include/mach/omap4-fb.h | 46 +++
> arch/arm/mach-omap/omap4_fb.c | 27 ++
> drivers/video/Kconfig | 8 +
> drivers/video/Makefile | 1 +
> drivers/video/omap4.c | 505 ++++++++++++++++++++++++++++
> drivers/video/omap4.h | 179 ++++++++++
> 7 files changed, 767 insertions(+)
> create mode 100644 arch/arm/mach-omap/include/mach/omap4-fb.h
> create mode 100644 arch/arm/mach-omap/omap4_fb.c
> create mode 100644 drivers/video/omap4.c
> create mode 100644 drivers/video/omap4.h
>
> diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile
> index 94e42c6..e70ddbd 100644
> --- a/arch/arm/mach-omap/Makefile
> +++ b/arch/arm/mach-omap/Makefile
> @@ -28,6 +28,7 @@ obj-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
> pbl-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
> obj-$(CONFIG_OMAP_GPMC) += gpmc.o devices-gpmc-nand.o
> obj-$(CONFIG_SHELL_NONE) += xload.o
> +obj-$(CONFIG_DRIVER_VIDEO_OMAP4) += omap4_fb.o
> obj-$(CONFIG_I2C_TWL6030) += omap4_twl6030_mmc.o
> obj-$(CONFIG_OMAP4_USBBOOT) += omap4_rom_usb.o
> obj-y += gpio.o
> diff --git a/arch/arm/mach-omap/include/mach/omap4-fb.h b/arch/arm/mach-omap/include/mach/omap4-fb.h
> new file mode 100644
> index 0000000..5c0a54b
> --- /dev/null
> +++ b/arch/arm/mach-omap/include/mach/omap4-fb.h
> @@ -0,0 +1,46 @@
...
> + fb_write(1, fbi->dispc, O4_DISPC_VID1_PIXEL_INC);
> +
> + fb_write(0xfff, fbi->dispc, O4_DISPC_VID1_PRELOAD);
> +
> + fb_write(DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(fmt) |
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_8x128 |
> + DSS_DISPC_VIDn_ATTRIBUTES_ZORDERENABLE |
> + DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_SECONDARY_LCD,
> + fbi->dispc, O4_DISPC_VID1_ATTRIBUTES);
> +
> + while (fb_read(fbi->dispc, O4_DISPC_CONTROL2) & DSS_DISPC_CONTROL_GOLCD)
> + ; /* noop */
For busy waiting on statusbits I would prefer a mechanism like this:
start = get_time_ns();
while (condition) {
...
if (is_timeout(start, waiting_time)) {
dev_err(dev, "foo"
return -ETIMEOUT;
}
mdelay(interval);
...
}
I mean it avoid deadlocks in barebox and it's better to start linux
without a display instead of a deadlock in barebox.
On the other hand you need a waiting_time which works with all displays
together. Don't know if there any hardware dependency.
}
> +
> + fb_write(fb_read(fbi->dispc, O4_DISPC_CONTROL2) |
> + DSS_DISPC_CONTROL_GOLCD,
> + fbi->dispc, O4_DISPC_CONTROL2);
> +
> + fbi->cur_display = new_display;
> + info->xres = mode->xres;
> + info->yres = mode->yres;
> +
> + rc = 0;
> +
> +out:
> + return rc;
> +}
...
> +
> + omap4fb_reset(fbi);
> +
> + dev_add_param(fbi->dev, "bootargs", NULL, NULL, 0);
> +
Jean-Christophe PLAGNIOL-VILLARD said why we need this here in the last
mails. I don't saw any answer to this and asking myself... what do this
function?
Regards
Alex
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v4] omap4-fb: add driver
2013-06-14 6:29 ` Alexander Aring
@ 2013-06-14 7:23 ` Jan Weitzel
2013-06-14 8:15 ` [PATCH v5] " Christoph Fritz
0 siblings, 1 reply; 24+ messages in thread
From: Jan Weitzel @ 2013-06-14 7:23 UTC (permalink / raw)
To: barebox
Am Freitag, den 14.06.2013, 08:29 +0200 schrieb Alexander Aring:
> Hi,
>
> On Fri, Jun 14, 2013 at 12:40:39AM +0200, Christoph Fritz wrote:
> > This patch adds omap4 display controller support.
> >
> > Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
> > ---
> > changes since v2:
> > - use dev_request_mem_region_by_name()
> > changes since v3:
> > - remove register struct
> > - use uncached screen_base
> > ---
> > arch/arm/mach-omap/Makefile | 1 +
> > arch/arm/mach-omap/include/mach/omap4-fb.h | 46 +++
> > arch/arm/mach-omap/omap4_fb.c | 27 ++
> > drivers/video/Kconfig | 8 +
> > drivers/video/Makefile | 1 +
> > drivers/video/omap4.c | 505 ++++++++++++++++++++++++++++
> > drivers/video/omap4.h | 179 ++++++++++
> > 7 files changed, 767 insertions(+)
> > create mode 100644 arch/arm/mach-omap/include/mach/omap4-fb.h
> > create mode 100644 arch/arm/mach-omap/omap4_fb.c
> > create mode 100644 drivers/video/omap4.c
> > create mode 100644 drivers/video/omap4.h
> >
> > diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile
> > index 94e42c6..e70ddbd 100644
> > --- a/arch/arm/mach-omap/Makefile
> > +++ b/arch/arm/mach-omap/Makefile
> > @@ -28,6 +28,7 @@ obj-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
> > pbl-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
> > obj-$(CONFIG_OMAP_GPMC) += gpmc.o devices-gpmc-nand.o
> > obj-$(CONFIG_SHELL_NONE) += xload.o
> > +obj-$(CONFIG_DRIVER_VIDEO_OMAP4) += omap4_fb.o
> > obj-$(CONFIG_I2C_TWL6030) += omap4_twl6030_mmc.o
> > obj-$(CONFIG_OMAP4_USBBOOT) += omap4_rom_usb.o
> > obj-y += gpio.o
> > diff --git a/arch/arm/mach-omap/include/mach/omap4-fb.h b/arch/arm/mach-omap/include/mach/omap4-fb.h
> > new file mode 100644
> > index 0000000..5c0a54b
> > --- /dev/null
> > +++ b/arch/arm/mach-omap/include/mach/omap4-fb.h
> > @@ -0,0 +1,46 @@
>
> ...
>
> > + fb_write(1, fbi->dispc, O4_DISPC_VID1_PIXEL_INC);
> > +
> > + fb_write(0xfff, fbi->dispc, O4_DISPC_VID1_PRELOAD);
> > +
> > + fb_write(DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(fmt) |
> > + DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_8x128 |
> > + DSS_DISPC_VIDn_ATTRIBUTES_ZORDERENABLE |
> > + DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_SECONDARY_LCD,
> > + fbi->dispc, O4_DISPC_VID1_ATTRIBUTES);
> > +
> > + while (fb_read(fbi->dispc, O4_DISPC_CONTROL2) & DSS_DISPC_CONTROL_GOLCD)
> > + ; /* noop */
>
> For busy waiting on statusbits I would prefer a mechanism like this:
>
> start = get_time_ns();
> while (condition) {
> ...
> if (is_timeout(start, waiting_time)) {
> dev_err(dev, "foo"
> return -ETIMEOUT;
> }
> mdelay(interval);
> ...
> }
There is also a convenience wrapper: wait_on_timeout(timeout, condition)
Jan
>
> I mean it avoid deadlocks in barebox and it's better to start linux
> without a display instead of a deadlock in barebox.
> On the other hand you need a waiting_time which works with all displays
> together. Don't know if there any hardware dependency.
>
> }
> > +
> > + fb_write(fb_read(fbi->dispc, O4_DISPC_CONTROL2) |
> > + DSS_DISPC_CONTROL_GOLCD,
> > + fbi->dispc, O4_DISPC_CONTROL2);
> > +
> > + fbi->cur_display = new_display;
> > + info->xres = mode->xres;
> > + info->yres = mode->yres;
> > +
> > + rc = 0;
> > +
> > +out:
> > + return rc;
> > +}
>
> ...
>
> > +
> > + omap4fb_reset(fbi);
> > +
> > + dev_add_param(fbi->dev, "bootargs", NULL, NULL, 0);
> > +
> Jean-Christophe PLAGNIOL-VILLARD said why we need this here in the last
> mails. I don't saw any answer to this and asking myself... what do this
> function?
>
> Regards
> Alex
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v5] omap4-fb: add driver
2013-06-14 7:23 ` Jan Weitzel
@ 2013-06-14 8:15 ` Christoph Fritz
2013-06-14 11:43 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 1 reply; 24+ messages in thread
From: Christoph Fritz @ 2013-06-14 8:15 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD, Sascha Hauer; +Cc: barebox
This patch adds omap4 display controller support.
Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
---
changes since v2:
- use dev_request_mem_region_by_name()
changes since v3:
- remove register struct
- use uncached screen_base
changes since v4:
- remove useless dev_add_param()
- use wait_on_timeout() instead while-deadlock
---
arch/arm/mach-omap/Makefile | 1 +
arch/arm/mach-omap/include/mach/omap4-fb.h | 46 +++
arch/arm/mach-omap/omap4_fb.c | 27 ++
drivers/video/Kconfig | 8 +
drivers/video/Makefile | 1 +
drivers/video/omap4.c | 527 ++++++++++++++++++++++++++++
drivers/video/omap4.h | 181 ++++++++++
7 files changed, 791 insertions(+)
create mode 100644 arch/arm/mach-omap/include/mach/omap4-fb.h
create mode 100644 arch/arm/mach-omap/omap4_fb.c
create mode 100644 drivers/video/omap4.c
create mode 100644 drivers/video/omap4.h
diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile
index 94e42c6..e70ddbd 100644
--- a/arch/arm/mach-omap/Makefile
+++ b/arch/arm/mach-omap/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
pbl-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
obj-$(CONFIG_OMAP_GPMC) += gpmc.o devices-gpmc-nand.o
obj-$(CONFIG_SHELL_NONE) += xload.o
+obj-$(CONFIG_DRIVER_VIDEO_OMAP4) += omap4_fb.o
obj-$(CONFIG_I2C_TWL6030) += omap4_twl6030_mmc.o
obj-$(CONFIG_OMAP4_USBBOOT) += omap4_rom_usb.o
obj-y += gpio.o
diff --git a/arch/arm/mach-omap/include/mach/omap4-fb.h b/arch/arm/mach-omap/include/mach/omap4-fb.h
new file mode 100644
index 0000000..5c0a54b
--- /dev/null
+++ b/arch/arm/mach-omap/include/mach/omap4-fb.h
@@ -0,0 +1,46 @@
+#ifndef H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H
+#define H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H
+
+#include <fb.h>
+
+#define OMAP_DSS_LCD_TFT (1u << 0)
+#define OMAP_DSS_LCD_IVS (1u << 1)
+#define OMAP_DSS_LCD_IHS (1u << 2)
+#define OMAP_DSS_LCD_IPC (1u << 3)
+#define OMAP_DSS_LCD_IEO (1u << 4)
+#define OMAP_DSS_LCD_RF (1u << 5)
+#define OMAP_DSS_LCD_ONOFF (1u << 6)
+
+#define OMAP_DSS_LCD_DATALINES(_l) ((_l) << 10)
+#define OMAP_DSS_LCD_DATALINES_msk OMAP_DSS_LCD_DATALINES(3u)
+#define OMAP_DSS_LCD_DATALINES_12 OMAP_DSS_LCD_DATALINES(0u)
+#define OMAP_DSS_LCD_DATALINES_16 OMAP_DSS_LCD_DATALINES(1u)
+#define OMAP_DSS_LCD_DATALINES_18 OMAP_DSS_LCD_DATALINES(2u)
+#define OMAP_DSS_LCD_DATALINES_24 OMAP_DSS_LCD_DATALINES(3u)
+
+struct omap4fb_display {
+ struct fb_videomode mode;
+
+ unsigned long config;
+
+ unsigned int power_on_delay;
+ unsigned int power_off_delay;
+};
+
+struct omap4fb_platform_data {
+ struct omap4fb_display const *displays;
+ size_t num_displays;
+
+ unsigned int dss_clk_hz;
+
+ unsigned int bpp;
+
+ struct resource const *screen;
+
+ void (*enable)(int p);
+};
+
+struct device_d;
+struct device_d *omap4_add_display(void *pdata);
+
+#endif /* H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H */
diff --git a/arch/arm/mach-omap/omap4_fb.c b/arch/arm/mach-omap/omap4_fb.c
new file mode 100644
index 0000000..09a6af3
--- /dev/null
+++ b/arch/arm/mach-omap/omap4_fb.c
@@ -0,0 +1,27 @@
+#include <driver.h>
+#include <common.h>
+#include <linux/ioport.h>
+#include <mach/omap4-fb.h>
+
+static struct resource omap4_fb_resources[] = {
+ {
+ .name = "omap4_dss",
+ .start = 0x48040000,
+ .end = 0x48040000 + 512 - 1,
+ .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+ }, {
+ .name = "omap4_dispc",
+ .start = 0x48041000,
+ .end = 0x48041000 + 3072 - 1,
+ .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+ },
+};
+
+struct device_d *omap4_add_display(void *pdata)
+{
+ return add_generic_device_res("omap4_fb", -1,
+ omap4_fb_resources,
+ ARRAY_SIZE(omap4_fb_resources),
+ pdata);
+}
+EXPORT_SYMBOL(omap4_add_display);
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 6d6b08f..9dfa0cd 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -45,6 +45,14 @@ config DRIVER_VIDEO_S3C24XX
help
Add support for the S3C244x LCD controller.
+config DRIVER_VIDEO_OMAP4
+ bool "OMAP4 framebuffer driver"
+ depends on ARCH_OMAP4
+ help
+ Add support for the OMAP4 Display Controller.
+ DSI is unsupported, only DISPC parallel mode on LCD2
+ is supported.
+
if DRIVER_VIDEO_S3C24XX
config DRIVER_VIDEO_S3C_VERBOSE
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 7429141..83feebb 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_DRIVER_VIDEO_IMX_IPU) += imx-ipu-fb.o
obj-$(CONFIG_DRIVER_VIDEO_S3C24XX) += s3c24xx.o
obj-$(CONFIG_DRIVER_VIDEO_PXA) += pxa.o
obj-$(CONFIG_DRIVER_VIDEO_SDL) += sdl.o
+obj-$(CONFIG_DRIVER_VIDEO_OMAP4) += omap4.o
diff --git a/drivers/video/omap4.c b/drivers/video/omap4.c
new file mode 100644
index 0000000..a7c6253
--- /dev/null
+++ b/drivers/video/omap4.c
@@ -0,0 +1,527 @@
+/*
+ * TI Omap4 Frame Buffer device driver
+ *
+ * Copyright (C) 2013 Christoph Fritz <chf.fritz@googlemail.com>
+ * Based on work by Enrico Scholz, sponsored by Phytec
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <driver.h>
+#include <fb.h>
+#include <errno.h>
+#include <xfuncs.h>
+#include <init.h>
+#include <stdio.h>
+#include <io.h>
+#include <common.h>
+#include <malloc.h>
+#include <common.h>
+#include <clock.h>
+
+#include <mach/omap4-silicon.h>
+#include <mach/omap4-fb.h>
+
+#include <asm/mmu.h>
+
+#include "omap4.h"
+
+struct omap4fb_device {
+ struct fb_info info;
+ struct device_d *dev;
+
+ struct omap4fb_display const *cur_display;
+
+ struct omap4fb_display const *displays;
+ size_t num_displays;
+
+ void __iomem *dss;
+ void __iomem *dispc;
+
+ struct {
+ void __iomem *addr;
+ size_t size;
+ } prealloc_screen;
+
+ struct {
+ uint32_t dispc_control;
+ uint32_t dispc_pol_freq;
+ } shadow;
+
+ struct {
+ unsigned int dss_clk_hz;
+ unsigned int lckd;
+ unsigned int pckd;
+ } divisor;
+ size_t dma_size;
+ void (*enable_fn)(int);
+
+ struct fb_videomode video_modes[];
+};
+
+static void omap4fb_enable(struct fb_info *info)
+{
+ struct omap4fb_device *fbi =
+ container_of(info, struct omap4fb_device, info);
+
+ dev_info(fbi->dev, "%s\n", __func__);
+
+ if (!fbi->cur_display) {
+ dev_err(fbi->dev, "no valid mode set\n");
+ return;
+ }
+
+ if (fbi->enable_fn)
+ fbi->enable_fn(1);
+
+ udelay(fbi->cur_display->power_on_delay * 1000u);
+
+ fb_write(fb_read(fbi->dispc, O4_DISPC_CONTROL2) |
+ DSS_DISPC_CONTROL_LCDENABLE |
+ DSS_DISPC_CONTROL_LCDENABLESIGNAL,
+ fbi->dispc, O4_DISPC_CONTROL2);
+
+ fb_write(fb_read(fbi->dispc, O4_DISPC_VID1_ATTRIBUTES) |
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE,
+ fbi->dispc, O4_DISPC_VID1_ATTRIBUTES);
+
+ fb_write(fb_read(fbi->dispc, O4_DISPC_CONTROL2) |
+ DSS_DISPC_CONTROL_GOLCD,
+ fbi->dispc, O4_DISPC_CONTROL2);
+}
+
+static void omap4fb_disable(struct fb_info *info)
+{
+ struct omap4fb_device *fbi =
+ container_of(info, struct omap4fb_device, info);
+
+ dev_info(fbi->dev, "%s\n", __func__);
+
+ if (!fbi->cur_display) {
+ dev_err(fbi->dev, "no valid mode set\n");
+ return;
+ }
+
+ fb_write(fb_read(fbi->dispc, O4_DISPC_CONTROL2) &
+ ~(DSS_DISPC_CONTROL_LCDENABLE |
+ DSS_DISPC_CONTROL_LCDENABLESIGNAL),
+ fbi->dispc, O4_DISPC_CONTROL2);
+
+ fb_write(fb_read(fbi->dispc, O4_DISPC_VID1_ATTRIBUTES) &
+ ~(DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE),
+ fbi->dispc, O4_DISPC_VID1_ATTRIBUTES);
+
+ if (fbi->prealloc_screen.addr == NULL) {
+ /* free frame buffer; but only when screen is not
+ * preallocated */
+ if (info->screen_base)
+ dma_free_coherent(info->screen_base, fbi->dma_size);
+ }
+
+ info->screen_base = NULL;
+
+ udelay(fbi->cur_display->power_off_delay * 1000u);
+
+ if (fbi->enable_fn)
+ fbi->enable_fn(0);
+}
+
+static void omap4fb_calc_divisor(struct omap4fb_device *fbi,
+ struct fb_videomode const *mode)
+{
+ unsigned int l, k, t, b;
+
+ b = UINT_MAX;
+ for (l = 1; l < 256; l++) {
+ for (k = 1; k < 256; k++) {
+ t = abs(mode->pixclock * 100 -
+ (fbi->divisor.dss_clk_hz / l / k));
+ if (t <= b) {
+ b = t;
+ fbi->divisor.lckd = l;
+ fbi->divisor.pckd = k;
+ }
+ }
+ }
+}
+
+static unsigned int omap4fb_calc_format(struct fb_info const *info)
+{
+ switch (info->bits_per_pixel) {
+ case 24: return 9;
+ case 32: return 0x8; /* xRGB24-8888 (32-bit container) */
+ default:
+ printf("%s: unsupported bpp %d\n", __func__,
+ info->bits_per_pixel);
+ return 0;
+ }
+}
+
+struct omap4fb_colors {
+ struct fb_bitfield red;
+ struct fb_bitfield green;
+ struct fb_bitfield blue;
+ struct fb_bitfield transp;
+};
+
+static struct omap4fb_colors const omap4fb_col[] = {
+ [0] = {
+ .red = { .length = 0, .offset = 0 },
+ },
+ [1] = {
+ .blue = { .length = 8, .offset = 0 },
+ .green = { .length = 8, .offset = 8 },
+ .red = { .length = 8, .offset = 16 },
+ },
+ [2] = {
+ .blue = { .length = 8, .offset = 0 },
+ .green = { .length = 8, .offset = 8 },
+ .red = { .length = 8, .offset = 16 },
+ .transp = { .length = 8, .offset = 24 },
+ },
+};
+
+static void omap4fb_fill_shadow(struct omap4fb_device *fbi,
+ struct omap4fb_display const *display)
+{
+ fbi->shadow.dispc_control = 0;
+ fbi->shadow.dispc_pol_freq = 0;
+
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_STNTFT;
+
+ switch (display->config & OMAP_DSS_LCD_DATALINES_msk) {
+ case OMAP_DSS_LCD_DATALINES_12:
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_12;
+ break;
+ case OMAP_DSS_LCD_DATALINES_16:
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_16;
+ break;
+ case OMAP_DSS_LCD_DATALINES_18:
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_18;
+ break;
+ case OMAP_DSS_LCD_DATALINES_24:
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_24;
+ break;
+ }
+
+ if (display->config & OMAP_DSS_LCD_IPC)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IPC;
+
+ if (display->config & OMAP_DSS_LCD_IVS)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IVS;
+
+ if (display->config & OMAP_DSS_LCD_IHS)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IHS;
+
+ if (display->config & OMAP_DSS_LCD_IEO)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IEO;
+
+ if (display->config & OMAP_DSS_LCD_RF)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_RF;
+
+ if (display->config & OMAP_DSS_LCD_ONOFF)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_ONOFF;
+}
+
+static int omap4fb_activate_var(struct fb_info *info)
+{
+ struct omap4fb_device *fbi =
+ container_of(info, struct omap4fb_device, info);
+ struct fb_videomode const *mode = info->mode;
+ size_t size = mode->xres * mode->yres * (info->bits_per_pixel / 8);
+ int rc;
+ unsigned int fmt = omap4fb_calc_format(info);
+ struct omap4fb_colors const *cols;
+ size_t i;
+ struct omap4fb_display const *new_display = NULL;
+
+ for (i = 0; i < fbi->num_displays && new_display == NULL; ++i) {
+ if (strcmp(mode->name, fbi->displays[i].mode.name) == 0)
+ new_display = &fbi->displays[i];
+ }
+
+ if (WARN_ON(!new_display)) {
+ dev_err(fbi->dev, "no display found for this mode '%s'\n",
+ mode->name);
+ rc = -ENXIO;
+ goto out;
+ }
+
+ /*Free old screen buf*/
+ if (!fbi->prealloc_screen.addr && info->screen_base)
+ dma_free_coherent(info->screen_base, fbi->dma_size);
+
+ fbi->dma_size = PAGE_ALIGN(size);
+
+ if (fbi->prealloc_screen.addr == NULL) {
+ /* case 1: no preallocated screen */
+ info->screen_base = dma_alloc_coherent(size);
+ } else if (fbi->prealloc_screen.size < fbi->dma_size) {
+ /* case 2: preallocated screen, but too small */
+ dev_err(fbi->dev,
+ "allocated framebuffer too small (%zu < %zu)\n",
+ fbi->prealloc_screen.size, fbi->dma_size);
+ rc = -ENOMEM;
+ goto out;
+ } else {
+ /* case 3: preallocated screen */
+ info->screen_base = fbi->prealloc_screen.addr;
+ }
+
+ omap4fb_fill_shadow(fbi, new_display);
+
+ omap4fb_calc_divisor(fbi, mode);
+
+ switch (info->bits_per_pixel) {
+ case 24:
+ cols = &omap4fb_col[1];
+ break;
+ case 32:
+ cols = &omap4fb_col[2];
+ break;
+ default:
+ cols = &omap4fb_col[0];
+ }
+
+ info->red = cols->red;
+ info->green = cols->green;
+ info->blue = cols->blue;
+ info->transp = cols->transp;
+
+ fb_write(fbi->shadow.dispc_control,
+ fbi->dispc, O4_DISPC_CONTROL2);
+
+ fb_write(fbi->shadow.dispc_pol_freq,
+ fbi->dispc, O4_DISPC_POL_FREQ2);
+
+ fb_write(DSS_DISPC_TIMING_H_HSW(mode->hsync_len - 1) |
+ DSS_DISPC_TIMING_H_HFP(mode->right_margin - 1) |
+ DSS_DISPC_TIMING_H_HBP(mode->left_margin - 1),
+ fbi->dispc, O4_DISPC_TIMING_H2);
+
+ fb_write(DSS_DISPC_TIMING_V_VSW(mode->vsync_len - 1) |
+ DSS_DISPC_TIMING_V_VFP(mode->lower_margin) |
+ DSS_DISPC_TIMING_V_VBP(mode->upper_margin),
+ fbi->dispc, O4_DISPC_TIMING_V2);
+
+ fb_write(DSS_DISPC_DIVISOR_ENABLE | DSS_DISPC_DIVISOR_LCD(1),
+ fbi->dispc, O4_DISPC_DIVISOR);
+
+ fb_write(DSS_DISPC_DIVISOR2_LCD(fbi->divisor.lckd) |
+ DSS_DISPC_DIVISOR2_PCD(fbi->divisor.pckd),
+ fbi->dispc, O4_DISPC_DIVISOR2);
+
+ fb_write(DSS_DISPC_SIZE_LCD_PPL(mode->xres - 1) |
+ DSS_DISPC_SIZE_LCD_LPP(mode->yres - 1),
+ fbi->dispc, O4_DISPC_SIZE_LCD2);
+
+ fb_write(0x0000ff00, fbi->dispc, O4_DISPC_DEFAULT_COLOR2);
+
+ /* we use VID1 */
+ fb_write((uintptr_t)info->screen_base, fbi->dispc, O4_DISPC_VID1_BA0);
+ fb_write((uintptr_t)info->screen_base, fbi->dispc, O4_DISPC_VID1_BA1);
+
+ fb_write(DSS_DISPC_VIDn_POSITION_VIDPOSX(0) |
+ DSS_DISPC_VIDn_POSITION_VIDPOSY(0),
+ fbi->dispc, O4_DISPC_VID1_POSITION);
+ fb_write(DSS_DISPC_VIDn_SIZE_VIDSIZEX(mode->xres - 1) |
+ DSS_DISPC_VIDn_SIZE_VIDSIZEY(mode->yres - 1),
+ fbi->dispc, O4_DISPC_VID1_SIZE);
+ fb_write(DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEX(mode->xres - 1) |
+ DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEY(mode->yres - 1),
+ fbi->dispc, O4_DISPC_VID1_PICTURE_SIZE);
+ fb_write(1, fbi->dispc, O4_DISPC_VID1_ROW_INC);
+ fb_write(1, fbi->dispc, O4_DISPC_VID1_PIXEL_INC);
+
+ fb_write(0xfff, fbi->dispc, O4_DISPC_VID1_PRELOAD);
+
+ fb_write(DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(fmt) |
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_8x128 |
+ DSS_DISPC_VIDn_ATTRIBUTES_ZORDERENABLE |
+ DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_SECONDARY_LCD,
+ fbi->dispc, O4_DISPC_VID1_ATTRIBUTES);
+
+ rc = wait_on_timeout(O4_TIMEOUT,
+ !(fb_read(fbi->dispc, O4_DISPC_CONTROL2) &
+ DSS_DISPC_CONTROL_GOLCD));
+
+ if (rc) {
+ dev_err(fbi->dev, "timeout: dispc golcd\n");
+ goto out;
+ }
+
+ fb_write(fb_read(fbi->dispc, O4_DISPC_CONTROL2) |
+ DSS_DISPC_CONTROL_GOLCD,
+ fbi->dispc, O4_DISPC_CONTROL2);
+
+ fbi->cur_display = new_display;
+ info->xres = mode->xres;
+ info->yres = mode->yres;
+
+ rc = 0;
+
+out:
+ return rc;
+}
+
+static int omap4fb_reset(struct omap4fb_device const *fbi)
+{
+ uint32_t v = fb_read(fbi->dispc, O4_DISPC_CONTROL2);
+ int rc;
+
+ /* step 1: stop the LCD controller */
+ if (v & DSS_DISPC_CONTROL_LCDENABLE) {
+ fb_write(v & ~DSS_DISPC_CONTROL_LCDENABLE,
+ fbi->dispc, O4_DISPC_CONTROL2);
+
+ fb_write(DSS_DISPC_IRQSTATUS_FRAMEDONE2, fbi->dispc,
+ O4_DISPC_IRQSTATUS);
+
+
+ rc = wait_on_timeout(O4_TIMEOUT,
+ ((fb_read(fbi->dispc, O4_DISPC_IRQSTATUS) &
+ DSS_DISPC_IRQSTATUS_FRAMEDONE) != 0));
+
+ if (rc) {
+ dev_err(fbi->dev, "timeout: irqstatus framedone\n");
+ return -ETIMEDOUT;
+ }
+ }
+
+ /* step 2: wait for reset done status */
+ rc = wait_on_timeout(O4_TIMEOUT,
+ (fb_read(fbi->dss, O4_DSS_SYSSTATUS) &
+ DSS_DSS_SYSSTATUS_RESETDONE));
+
+ if (rc) {
+ dev_err(fbi->dev, "timeout: sysstatus resetdone\n");
+ return -ETIMEDOUT;
+ }
+
+ /* DSS_CTL: set to reset value */
+ fb_write(0, fbi->dss, O4_DSS_CTRL);
+
+ return 0;
+}
+
+static struct fb_ops omap4fb_ops = {
+ .fb_enable = omap4fb_enable,
+ .fb_disable = omap4fb_disable,
+ .fb_activate_var = omap4fb_activate_var,
+};
+
+static int omap4fb_probe(struct device_d *dev)
+{
+ struct omap4fb_platform_data const *pdata = dev->platform_data;
+ struct omap4fb_device *fbi;
+ struct fb_info *info;
+ int rc;
+ size_t i;
+
+ if (!pdata)
+ return -ENODEV;
+
+ fbi = xzalloc(sizeof *fbi +
+ pdata->num_displays * sizeof fbi->video_modes[0]);
+ info = &fbi->info;
+
+ fbi->dev = dev;
+
+ /* CM_DSS_CLKSTCTRL (TRM: 935) trigger SW_WKUP */
+ __raw_writel(0x2, 0x4a009100); /* TODO: move this to clockmanagement */
+
+ fbi->dss = dev_request_mem_region_by_name(dev, "omap4_dss");
+ fbi->dispc = dev_request_mem_region_by_name(dev, "omap4_dispc");
+
+ if (!fbi->dss || !fbi->dispc) {
+ dev_err(dev, "Insufficient register description\n");
+ rc = -EINVAL;
+ goto out;
+ }
+
+ dev_info(dev, "HW-Revision 0x%04x 0x%04x\n",
+ fb_read(fbi->dss, O4_DISPC_REVISION),
+ fb_read(fbi->dss, O4_DSS_REVISION));
+
+
+ if (!pdata->dss_clk_hz | !pdata->displays | !pdata->num_displays |
+ !pdata->bpp) {
+ dev_err(dev, "Insufficient omap4fb_platform_data\n");
+ rc = -EINVAL;
+ goto out;
+ }
+
+ fbi->enable_fn = pdata->enable;
+ fbi->displays = pdata->displays;
+ fbi->num_displays = pdata->num_displays;
+ fbi->divisor.dss_clk_hz = pdata->dss_clk_hz;
+
+ for (i = 0; i < pdata->num_displays; ++i)
+ fbi->video_modes[i] = pdata->displays[i].mode;
+
+ info->mode_list = fbi->video_modes;
+ info->num_modes = pdata->num_displays;
+
+ info->priv = fbi;
+ info->fbops = &omap4fb_ops;
+ info->bits_per_pixel = pdata->bpp;
+
+ if (pdata->screen) {
+ if (!IS_ALIGNED(pdata->screen->start, PAGE_SIZE) ||
+ !IS_ALIGNED(resource_size(pdata->screen), PAGE_SIZE)) {
+ dev_err(dev, "screen resource not aligned\n");
+ rc = -EINVAL;
+ goto out;
+ }
+ fbi->prealloc_screen.addr =
+ (void __iomem *)pdata->screen->start;
+ fbi->prealloc_screen.size = resource_size(pdata->screen);
+ remap_range(fbi->prealloc_screen.addr,
+ fbi->prealloc_screen.size,
+ mmu_get_pte_uncached_flags());
+ }
+
+ rc = omap4fb_reset(fbi);
+ if (rc < 0) {
+ dev_err(dev, "failed to reset: %d\n", rc);
+ goto out;
+ }
+
+ rc = register_framebuffer(info);
+ if (rc < 0) {
+ dev_err(dev, "failed to register framebuffer: %d\n", rc);
+ goto out;
+ }
+
+ rc = 0;
+ dev_info(dev, "registered\n");
+
+out:
+ if (rc < 0)
+ free(fbi);
+
+ return rc;
+}
+
+static struct driver_d omap4fb_driver = {
+ .name = "omap4_fb",
+ .probe = omap4fb_probe,
+};
+
+static int omap4fb_init(void)
+{
+ return platform_driver_register(&omap4fb_driver);
+}
+
+device_initcall(omap4fb_init);
diff --git a/drivers/video/omap4.h b/drivers/video/omap4.h
new file mode 100644
index 0000000..5704f7b
--- /dev/null
+++ b/drivers/video/omap4.h
@@ -0,0 +1,181 @@
+/*
+ * TI Omap4 Frame Buffer device driver
+ *
+ * Copyright (C) 2013 Christoph Fritz <chf.fritz@googlemail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef H_BAREBOX_DRIVER_VIDEO_OMAP4_REGS_H
+#define H_BAREBOX_DRIVER_VIDEO_OMAP4_REGS_H
+
+#include <types.h>
+#include <common.h>
+
+#define O4_TIMEOUT (128 * USECOND)
+
+#define fb_read(io, reg) __raw_readl((io)+(reg))
+#define fb_write(val, io, reg) __raw_writel((val), (io)+(reg))
+
+/* TRM: 10.1.3.2 DSS Registers */
+#define O4_DSS_REVISION 0x0
+#define O4_DSS_SYSSTATUS 0x14
+#define O4_DSS_CTRL 0x40
+#define O4_DSS_STATUS 0x5c
+
+/* TRM: 10.2.7.3 Display Controller Registers */
+#define O4_DISPC_REVISION 0x0
+#define O4_DISPC_IRQSTATUS 0x18
+#define O4_DISPC_CONTROL2 0x238
+#define O4_DISPC_VID1_ATTRIBUTES 0xcc
+#define O4_DISPC_TIMING_H2 0x400
+#define O4_DISPC_TIMING_V2 0x404
+#define O4_DISPC_POL_FREQ2 0x408
+#define O4_DISPC_DIVISOR2 0x40c
+#define O4_DISPC_DEFAULT_COLOR2 0x3ac
+#define O4_DISPC_SIZE_LCD2 0x3cc
+#define O4_DISPC_DIVISOR 0x804
+#define O4_DISPC_VID1_BA0 0xbc
+#define O4_DISPC_VID1_BA1 0xc0
+#define O4_DISPC_VID1_POSITION 0xc4
+#define O4_DISPC_VID1_SIZE 0xc8
+#define O4_DISPC_VID1_PICTURE_SIZE 0xe4
+#define O4_DISPC_VID1_ROW_INC 0xd8
+#define O4_DISPC_VID1_PIXEL_INC 0xdc
+#define O4_DISPC_VID1_PRELOAD 0x230
+
+#define DSS_DISPC_VIDn_POSITION_VIDPOSX(_x) ((_x) << 0)
+#define DSS_DISPC_VIDn_POSITION_VIDPOSY(_y) ((_y) << 16)
+
+#define DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEX(_x) ((_x) << 0)
+#define DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEY(_y) ((_y) << 16)
+
+#define DSS_DISPC_VIDn_SIZE_VIDSIZEX(_x) ((_x) << 0)
+#define DSS_DISPC_VIDn_SIZE_VIDSIZEY(_y) ((_y) << 16)
+
+#define DSS_DISPC_SIZE_LCD_PPL(_x) ((_x) << 0)
+#define DSS_DISPC_SIZE_LCD_LPP(_y) ((_y) << 16)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE (1u << 0)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(_fmt) ((_fmt) << 1)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB12 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(4u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB16 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(5u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB16 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(6u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB16o \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(7u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_xRGB24u \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(8u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB24p \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(9u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_YUV2 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(10u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_UYVY \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(11u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB32 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(12u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGBA32 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(13u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_xRGB32 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(14u)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(_b) ((_b) << 14)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_2x128 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(0u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_4x128 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(1u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_8x128 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(2u)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDCHANNELOUT (1u << 16)
+#define DSS_DISPC_VIDn_ATTRIBUTES_SELFREFRESHAUTO (1u << 17)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFIFOPRELOAD (1u << 19)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDVERTICALTAPS (1u << 21)
+#define DSS_DISPC_VIDn_ATTRIBUTES_DOUBLESTRIDE (1u << 22)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDARBITRATION (1u << 23)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDSELFREFRESH (1u << 24)
+#define DSS_DISPC_VIDn_ATTRIBUTES_ZORDERENABLE (1u << 25)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(_b) ((_b) << 30)
+#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_PRIMARY_LCD \
+ DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(0u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_SECONDARY_LCD \
+ DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(1u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_WRITEBACK_MEM \
+ DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(3u)
+
+#define DSS_DISPC_CONTROL_LCDENABLE (1u << 0)
+#define DSS_DISPC_CONTROL_TVENABLE (1u << 1)
+#define DSS_DISPC_CONTROL_MONOCOLOR (1u << 2)
+#define DSS_DISPC_CONTROL_STNTFT (1u << 3)
+#define DSS_DISPC_CONTROL_M8B (1u << 4)
+#define DSS_DISPC_CONTROL_GOLCD (1u << 5)
+#define DSS_DISPC_CONTROL_GOTV (1u << 6)
+#define DSS_DISPC_CONTROL_STDITHERENABLE (1u << 7)
+
+#define DSS_DISPC_CONTROL_TFTDATALINES(_l) ((_l) << 8)
+#define DSS_DISPC_CONTROL_TFTDATALINES_12 \
+ DSS_DISPC_CONTROL_TFTDATALINES(0u)
+#define DSS_DISPC_CONTROL_TFTDATALINES_16 \
+ DSS_DISPC_CONTROL_TFTDATALINES(1u)
+#define DSS_DISPC_CONTROL_TFTDATALINES_18 \
+ DSS_DISPC_CONTROL_TFTDATALINES(2u)
+#define DSS_DISPC_CONTROL_TFTDATALINES_24 \
+ DSS_DISPC_CONTROL_TFTDATALINES(3u)
+
+#define DSS_DISPC_CONTROL_STALLMODE (1u << 11)
+#define DSS_DISPC_CONTROL_OVERLAYOPTIMIZATION (1u << 12)
+#define DSS_DISPC_CONTROL_GPIN0 (1u << 13) /* ro */
+#define DSS_DISPC_CONTROL_GPIN1 (1u << 14) /* ro */
+#define DSS_DISPC_CONTROL_GPOUT0 (1u << 15)
+#define DSS_DISPC_CONTROL_GPOUT1 (1u << 16)
+#define DSS_DISPC_CONTROL_HT(_ht) ((_ht) << 17)
+#define DSS_DISPC_CONTROL_TDMENABLE (1u << 20)
+#define DSS_DISPC_CONTROL_TDMPARALLELMODE(_pm) ((_pm) << 21)
+#define DSS_DISPC_CONTROL_TDMCYCLEFORMAT(_cf) ((_cf) << 23)
+#define DSS_DISPC_CONTROL_TDMUNUSEDBITS(_ub) ((_ub) << 25)
+#define DSS_DISPC_CONTROL_PCKFREEENABLE (1u << 27)
+#define DSS_DISPC_CONTROL_LCDENABLESIGNAL (1u << 28)
+#define DSS_DISPC_CONTROL_LCDENABLEPOL (1u << 29)
+#define DSS_DISPC_CONTROL_SPATIALTEMPD(_df) ((_df) << 30)
+
+#define DSS_DISPC_POL_FREQ_IVS (1u << 12)
+#define DSS_DISPC_POL_FREQ_IHS (1u << 13)
+#define DSS_DISPC_POL_FREQ_IPC (1u << 14)
+#define DSS_DISPC_POL_FREQ_IEO (1u << 15)
+#define DSS_DISPC_POL_FREQ_RF (1u << 16)
+#define DSS_DISPC_POL_FREQ_ONOFF (1u << 17)
+
+#define DSS_DISPC_TIMING_H_HSW(_hsw) ((_hsw) << 0)
+#define DSS_DISPC_TIMING_H_HFP(_hfp) ((_hfp) << 8)
+#define DSS_DISPC_TIMING_H_HBP(_hbp) ((_hbp) << 20)
+
+#define DSS_DISPC_TIMING_V_VSW(_vsw) ((_vsw) << 0)
+#define DSS_DISPC_TIMING_V_VFP(_vfp) ((_vfp) << 8)
+#define DSS_DISPC_TIMING_V_VBP(_vbp) ((_vbp) << 20)
+
+#define DSS_DISPC_DIVISOR_ENABLE (1u << 0)
+#define DSS_DISPC_DIVISOR_LCD(_lcd) ((_lcd) << 16)
+
+#define DSS_DISPC_DIVISOR2_PCD(_pcd) ((_pcd) << 0)
+#define DSS_DISPC_DIVISOR2_LCD(_lcd) ((_lcd) << 16)
+
+#define DSS_DISPC_IRQSTATUS_FRAMEDONE (1u << 0)
+#define DSS_DISPC_IRQSTATUS_FRAMEDONE2 (1u << 22)
+
+#define DSS_DSS_SYSSTATUS_RESETDONE (1u << 0)
+
+#endif /* H_BAREBOX_DRIVER_VIDEO_O4_REGS_H */
--
1.7.10.4
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v5] omap4-fb: add driver
2013-06-14 8:15 ` [PATCH v5] " Christoph Fritz
@ 2013-06-14 11:43 ` Jean-Christophe PLAGNIOL-VILLARD
2013-06-14 15:11 ` [PATCH v6] " Christoph Fritz
2013-06-17 16:18 ` Christoph Fritz
0 siblings, 2 replies; 24+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2013-06-14 11:43 UTC (permalink / raw)
To: Christoph Fritz; +Cc: barebox
On 10:15 Fri 14 Jun , Christoph Fritz wrote:
> This patch adds omap4 display controller support.
>
> Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
> ---
> changes since v2:
> - use dev_request_mem_region_by_name()
> changes since v3:
> - remove register struct
> - use uncached screen_base
> changes since v4:
> - remove useless dev_add_param()
> - use wait_on_timeout() instead while-deadlock
> ---
> arch/arm/mach-omap/Makefile | 1 +
> arch/arm/mach-omap/include/mach/omap4-fb.h | 46 +++
> arch/arm/mach-omap/omap4_fb.c | 27 ++
Sasha will device but for me this is 2 patches
1 for the driver
1 for the mach-omap
> drivers/video/Kconfig | 8 +
> drivers/video/Makefile | 1 +
> drivers/video/omap4.c | 527 ++++++++++++++++++++++++++++
> drivers/video/omap4.h | 181 ++++++++++
> 7 files changed, 791 insertions(+)
> create mode 100644 arch/arm/mach-omap/include/mach/omap4-fb.h
> create mode 100644 arch/arm/mach-omap/omap4_fb.c
> create mode 100644 drivers/video/omap4.c
> create mode 100644 drivers/video/omap4.h
>
> diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile
> index 94e42c6..e70ddbd 100644
> --- a/arch/arm/mach-omap/Makefile
> +++ b/arch/arm/mach-omap/Makefile
> @@ -28,6 +28,7 @@ obj-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
> pbl-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
> obj-$(CONFIG_OMAP_GPMC) += gpmc.o devices-gpmc-nand.o
> obj-$(CONFIG_SHELL_NONE) += xload.o
> +obj-$(CONFIG_DRIVER_VIDEO_OMAP4) += omap4_fb.o
> obj-$(CONFIG_I2C_TWL6030) += omap4_twl6030_mmc.o
> obj-$(CONFIG_OMAP4_USBBOOT) += omap4_rom_usb.o
> obj-y += gpio.o
> diff --git a/arch/arm/mach-omap/include/mach/omap4-fb.h b/arch/arm/mach-omap/include/mach/omap4-fb.h
> new file mode 100644
> index 0000000..5c0a54b
> --- /dev/null
> +++ b/arch/arm/mach-omap/include/mach/omap4-fb.h
> @@ -0,0 +1,46 @@
> +#ifndef H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H
> +#define H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H
> +
> +#include <fb.h>
> +
> +#define OMAP_DSS_LCD_TFT (1u << 0)
> +#define OMAP_DSS_LCD_IVS (1u << 1)
> +#define OMAP_DSS_LCD_IHS (1u << 2)
> +#define OMAP_DSS_LCD_IPC (1u << 3)
> +#define OMAP_DSS_LCD_IEO (1u << 4)
> +#define OMAP_DSS_LCD_RF (1u << 5)
> +#define OMAP_DSS_LCD_ONOFF (1u << 6)
> +
> +#define OMAP_DSS_LCD_DATALINES(_l) ((_l) << 10)
> +#define OMAP_DSS_LCD_DATALINES_msk OMAP_DSS_LCD_DATALINES(3u)
> +#define OMAP_DSS_LCD_DATALINES_12 OMAP_DSS_LCD_DATALINES(0u)
> +#define OMAP_DSS_LCD_DATALINES_16 OMAP_DSS_LCD_DATALINES(1u)
> +#define OMAP_DSS_LCD_DATALINES_18 OMAP_DSS_LCD_DATALINES(2u)
> +#define OMAP_DSS_LCD_DATALINES_24 OMAP_DSS_LCD_DATALINES(3u)
> +
> +struct omap4fb_display {
> + struct fb_videomode mode;
> +
> + unsigned long config;
> +
> + unsigned int power_on_delay;
> + unsigned int power_off_delay;
> +};
> +
> +struct omap4fb_platform_data {
> + struct omap4fb_display const *displays;
> + size_t num_displays;
> +
> + unsigned int dss_clk_hz;
> +
> + unsigned int bpp;
> +
> + struct resource const *screen;
> +
> + void (*enable)(int p);
> +};
> +
> +struct device_d;
> +struct device_d *omap4_add_display(void *pdata);
> +
> +#endif /* H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H */
> diff --git a/arch/arm/mach-omap/omap4_fb.c b/arch/arm/mach-omap/omap4_fb.c
> new file mode 100644
> index 0000000..09a6af3
> --- /dev/null
> +++ b/arch/arm/mach-omap/omap4_fb.c
> @@ -0,0 +1,27 @@
> +#include <driver.h>
> +#include <common.h>
> +#include <linux/ioport.h>
> +#include <mach/omap4-fb.h>
> +
> +static struct resource omap4_fb_resources[] = {
> + {
> + .name = "omap4_dss",
> + .start = 0x48040000,
> + .end = 0x48040000 + 512 - 1,
> + .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
> + }, {
> + .name = "omap4_dispc",
> + .start = 0x48041000,
> + .end = 0x48041000 + 3072 - 1,
> + .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
> + },
> +};
> +
> +struct device_d *omap4_add_display(void *pdata)
> +{
> + return add_generic_device_res("omap4_fb", -1,
> + omap4_fb_resources,
> + ARRAY_SIZE(omap4_fb_resources),
> + pdata);
> +}
> +EXPORT_SYMBOL(omap4_add_display);
> diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
> index 6d6b08f..9dfa0cd 100644
> --- a/drivers/video/Kconfig
> +++ b/drivers/video/Kconfig
> @@ -45,6 +45,14 @@ config DRIVER_VIDEO_S3C24XX
> help
> Add support for the S3C244x LCD controller.
>
> +config DRIVER_VIDEO_OMAP4
> + bool "OMAP4 framebuffer driver"
> + depends on ARCH_OMAP4
> + help
> + Add support for the OMAP4 Display Controller.
> + DSI is unsupported, only DISPC parallel mode on LCD2
> + is supported.
> +
> if DRIVER_VIDEO_S3C24XX
>
> config DRIVER_VIDEO_S3C_VERBOSE
> diff --git a/drivers/video/Makefile b/drivers/video/Makefile
> index 7429141..83feebb 100644
> --- a/drivers/video/Makefile
> +++ b/drivers/video/Makefile
> @@ -8,3 +8,4 @@ obj-$(CONFIG_DRIVER_VIDEO_IMX_IPU) += imx-ipu-fb.o
> obj-$(CONFIG_DRIVER_VIDEO_S3C24XX) += s3c24xx.o
> obj-$(CONFIG_DRIVER_VIDEO_PXA) += pxa.o
> obj-$(CONFIG_DRIVER_VIDEO_SDL) += sdl.o
> +obj-$(CONFIG_DRIVER_VIDEO_OMAP4) += omap4.o
> diff --git a/drivers/video/omap4.c b/drivers/video/omap4.c
> new file mode 100644
> index 0000000..a7c6253
> --- /dev/null
> +++ b/drivers/video/omap4.c
> @@ -0,0 +1,527 @@
> +/*
> + * TI Omap4 Frame Buffer device driver
> + *
> + * Copyright (C) 2013 Christoph Fritz <chf.fritz@googlemail.com>
> + * Based on work by Enrico Scholz, sponsored by Phytec
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <driver.h>
> +#include <fb.h>
> +#include <errno.h>
> +#include <xfuncs.h>
> +#include <init.h>
> +#include <stdio.h>
> +#include <io.h>
> +#include <common.h>
> +#include <malloc.h>
> +#include <common.h>
> +#include <clock.h>
> +
> +#include <mach/omap4-silicon.h>
> +#include <mach/omap4-fb.h>
> +
> +#include <asm/mmu.h>
> +
> +#include "omap4.h"
> +
> +struct omap4fb_device {
> + struct fb_info info;
> + struct device_d *dev;
> +
> + struct omap4fb_display const *cur_display;
> +
> + struct omap4fb_display const *displays;
> + size_t num_displays;
> +
> + void __iomem *dss;
> + void __iomem *dispc;
> +
> + struct {
> + void __iomem *addr;
> + size_t size;
> + } prealloc_screen;
> +
> + struct {
> + uint32_t dispc_control;
> + uint32_t dispc_pol_freq;
> + } shadow;
> +
> + struct {
> + unsigned int dss_clk_hz;
> + unsigned int lckd;
> + unsigned int pckd;
> + } divisor;
> + size_t dma_size;
> + void (*enable_fn)(int);
> +
> + struct fb_videomode video_modes[];
> +};
> +
> +static void omap4fb_enable(struct fb_info *info)
> +{
> + struct omap4fb_device *fbi =
> + container_of(info, struct omap4fb_device, info);
> +
> + dev_info(fbi->dev, "%s\n", __func__);
dev_dbg
no need verbose for nornal operation
> +
> + if (!fbi->cur_display) {
> + dev_err(fbi->dev, "no valid mode set\n");
> + return;
> + }
> +
> + if (fbi->enable_fn)
> + fbi->enable_fn(1);
> +
> + udelay(fbi->cur_display->power_on_delay * 1000u);
> +
> + fb_write(fb_read(fbi->dispc, O4_DISPC_CONTROL2) |
> + DSS_DISPC_CONTROL_LCDENABLE |
> + DSS_DISPC_CONTROL_LCDENABLESIGNAL,
> + fbi->dispc, O4_DISPC_CONTROL2);
> +
> + fb_write(fb_read(fbi->dispc, O4_DISPC_VID1_ATTRIBUTES) |
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE,
> + fbi->dispc, O4_DISPC_VID1_ATTRIBUTES);
> +
> + fb_write(fb_read(fbi->dispc, O4_DISPC_CONTROL2) |
> + DSS_DISPC_CONTROL_GOLCD,
> + fbi->dispc, O4_DISPC_CONTROL2);
> +}
> +
> +static void omap4fb_disable(struct fb_info *info)
> +{
> + struct omap4fb_device *fbi =
> + container_of(info, struct omap4fb_device, info);
> +
> + dev_info(fbi->dev, "%s\n", __func__);
ditto
> +
> + if (!fbi->cur_display) {
> + dev_err(fbi->dev, "no valid mode set\n");
> + return;
> + }
> +
> + fb_write(fb_read(fbi->dispc, O4_DISPC_CONTROL2) &
> + ~(DSS_DISPC_CONTROL_LCDENABLE |
> + DSS_DISPC_CONTROL_LCDENABLESIGNAL),
> + fbi->dispc, O4_DISPC_CONTROL2);
> +
> + fb_write(fb_read(fbi->dispc, O4_DISPC_VID1_ATTRIBUTES) &
> + ~(DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE),
> + fbi->dispc, O4_DISPC_VID1_ATTRIBUTES);
> +
> + if (fbi->prealloc_screen.addr == NULL) {
> + /* free frame buffer; but only when screen is not
> + * preallocated */
> + if (info->screen_base)
> + dma_free_coherent(info->screen_base, fbi->dma_size);
> + }
> +
> + info->screen_base = NULL;
> +
> + udelay(fbi->cur_display->power_off_delay * 1000u);
> +
> + if (fbi->enable_fn)
> + fbi->enable_fn(0);
> +}
> +
> +static void omap4fb_calc_divisor(struct omap4fb_device *fbi,
> + struct fb_videomode const *mode)
> +{
> + unsigned int l, k, t, b;
> +
> + b = UINT_MAX;
> + for (l = 1; l < 256; l++) {
> + for (k = 1; k < 256; k++) {
> + t = abs(mode->pixclock * 100 -
> + (fbi->divisor.dss_clk_hz / l / k));
> + if (t <= b) {
> + b = t;
> + fbi->divisor.lckd = l;
> + fbi->divisor.pckd = k;
> + }
> + }
> + }
> +}
> +
> +static unsigned int omap4fb_calc_format(struct fb_info const *info)
> +{
> + switch (info->bits_per_pixel) {
> + case 24: return 9;
case x:
return
> + case 32: return 0x8; /* xRGB24-8888 (32-bit container) */
> + default:
> + printf("%s: unsupported bpp %d\n", __func__,
dev_err
> + info->bits_per_pixel);
> + return 0;
> + }
> +}
> +
> +struct omap4fb_colors {
> + struct fb_bitfield red;
> + struct fb_bitfield green;
> + struct fb_bitfield blue;
> + struct fb_bitfield transp;
> +};
> +
> +static struct omap4fb_colors const omap4fb_col[] = {
> + [0] = {
> + .red = { .length = 0, .offset = 0 },
> + },
> + [1] = {
> + .blue = { .length = 8, .offset = 0 },
> + .green = { .length = 8, .offset = 8 },
> + .red = { .length = 8, .offset = 16 },
> + },
> + [2] = {
> + .blue = { .length = 8, .offset = 0 },
> + .green = { .length = 8, .offset = 8 },
> + .red = { .length = 8, .offset = 16 },
> + .transp = { .length = 8, .offset = 24 },
> + },
> +};
> +
> +static void omap4fb_fill_shadow(struct omap4fb_device *fbi,
> + struct omap4fb_display const *display)
> +{
> + fbi->shadow.dispc_control = 0;
> + fbi->shadow.dispc_pol_freq = 0;
> +
> + fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_STNTFT;
> +
> + switch (display->config & OMAP_DSS_LCD_DATALINES_msk) {
> + case OMAP_DSS_LCD_DATALINES_12:
> + fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_12;
> + break;
> + case OMAP_DSS_LCD_DATALINES_16:
> + fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_16;
> + break;
> + case OMAP_DSS_LCD_DATALINES_18:
> + fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_18;
> + break;
> + case OMAP_DSS_LCD_DATALINES_24:
> + fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_24;
> + break;
> + }
> +
> + if (display->config & OMAP_DSS_LCD_IPC)
> + fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IPC;
> +
> + if (display->config & OMAP_DSS_LCD_IVS)
> + fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IVS;
> +
> + if (display->config & OMAP_DSS_LCD_IHS)
> + fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IHS;
> +
> + if (display->config & OMAP_DSS_LCD_IEO)
> + fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IEO;
> +
> + if (display->config & OMAP_DSS_LCD_RF)
> + fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_RF;
> +
> + if (display->config & OMAP_DSS_LCD_ONOFF)
> + fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_ONOFF;
> +}
> +
> +static int omap4fb_activate_var(struct fb_info *info)
> +{
> + struct omap4fb_device *fbi =
> + container_of(info, struct omap4fb_device, info);
> + struct fb_videomode const *mode = info->mode;
> + size_t size = mode->xres * mode->yres * (info->bits_per_pixel / 8);
> + int rc;
> + unsigned int fmt = omap4fb_calc_format(info);
> + struct omap4fb_colors const *cols;
> + size_t i;
> + struct omap4fb_display const *new_display = NULL;
> +
> + for (i = 0; i < fbi->num_displays && new_display == NULL; ++i) {
> + if (strcmp(mode->name, fbi->displays[i].mode.name) == 0)
> + new_display = &fbi->displays[i];
> + }
do this search in a function and return
> +
> + if (WARN_ON(!new_display)) {
> + dev_err(fbi->dev, "no display found for this mode '%s'\n",
> + mode->name);
> + rc = -ENXIO;
> + goto out;
> + }
> +
> + /*Free old screen buf*/
> + if (!fbi->prealloc_screen.addr && info->screen_base)
> + dma_free_coherent(info->screen_base, fbi->dma_size);
> +
> + fbi->dma_size = PAGE_ALIGN(size);
> +
> + if (fbi->prealloc_screen.addr == NULL) {
consistant !xxx
> + /* case 1: no preallocated screen */
> + info->screen_base = dma_alloc_coherent(size);
> + } else if (fbi->prealloc_screen.size < fbi->dma_size) {
> + /* case 2: preallocated screen, but too small */
> + dev_err(fbi->dev,
> + "allocated framebuffer too small (%zu < %zu)\n",
> + fbi->prealloc_screen.size, fbi->dma_size);
> + rc = -ENOMEM;
> + goto out;
> + } else {
> + /* case 3: preallocated screen */
> + info->screen_base = fbi->prealloc_screen.addr;
> + }
> +
> + omap4fb_fill_shadow(fbi, new_display);
> +
> + omap4fb_calc_divisor(fbi, mode);
> +
> + switch (info->bits_per_pixel) {
> + case 24:
> + cols = &omap4fb_col[1];
> + break;
> + case 32:
> + cols = &omap4fb_col[2];
> + break;
> + default:
> + cols = &omap4fb_col[0];
> + }
> +
> + info->red = cols->red;
> + info->green = cols->green;
> + info->blue = cols->blue;
> + info->transp = cols->transp;
> +
> + fb_write(fbi->shadow.dispc_control,
> + fbi->dispc, O4_DISPC_CONTROL2);
> +
> + fb_write(fbi->shadow.dispc_pol_freq,
> + fbi->dispc, O4_DISPC_POL_FREQ2);
> +
> + fb_write(DSS_DISPC_TIMING_H_HSW(mode->hsync_len - 1) |
> + DSS_DISPC_TIMING_H_HFP(mode->right_margin - 1) |
> + DSS_DISPC_TIMING_H_HBP(mode->left_margin - 1),
> + fbi->dispc, O4_DISPC_TIMING_H2);
> +
> + fb_write(DSS_DISPC_TIMING_V_VSW(mode->vsync_len - 1) |
> + DSS_DISPC_TIMING_V_VFP(mode->lower_margin) |
> + DSS_DISPC_TIMING_V_VBP(mode->upper_margin),
> + fbi->dispc, O4_DISPC_TIMING_V2);
> +
> + fb_write(DSS_DISPC_DIVISOR_ENABLE | DSS_DISPC_DIVISOR_LCD(1),
> + fbi->dispc, O4_DISPC_DIVISOR);
> +
> + fb_write(DSS_DISPC_DIVISOR2_LCD(fbi->divisor.lckd) |
> + DSS_DISPC_DIVISOR2_PCD(fbi->divisor.pckd),
> + fbi->dispc, O4_DISPC_DIVISOR2);
> +
> + fb_write(DSS_DISPC_SIZE_LCD_PPL(mode->xres - 1) |
> + DSS_DISPC_SIZE_LCD_LPP(mode->yres - 1),
> + fbi->dispc, O4_DISPC_SIZE_LCD2);
> +
> + fb_write(0x0000ff00, fbi->dispc, O4_DISPC_DEFAULT_COLOR2);
> +
> + /* we use VID1 */
> + fb_write((uintptr_t)info->screen_base, fbi->dispc, O4_DISPC_VID1_BA0);
> + fb_write((uintptr_t)info->screen_base, fbi->dispc, O4_DISPC_VID1_BA1);
> +
> + fb_write(DSS_DISPC_VIDn_POSITION_VIDPOSX(0) |
> + DSS_DISPC_VIDn_POSITION_VIDPOSY(0),
> + fbi->dispc, O4_DISPC_VID1_POSITION);
> + fb_write(DSS_DISPC_VIDn_SIZE_VIDSIZEX(mode->xres - 1) |
> + DSS_DISPC_VIDn_SIZE_VIDSIZEY(mode->yres - 1),
> + fbi->dispc, O4_DISPC_VID1_SIZE);
> + fb_write(DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEX(mode->xres - 1) |
> + DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEY(mode->yres - 1),
> + fbi->dispc, O4_DISPC_VID1_PICTURE_SIZE);
> + fb_write(1, fbi->dispc, O4_DISPC_VID1_ROW_INC);
> + fb_write(1, fbi->dispc, O4_DISPC_VID1_PIXEL_INC);
> +
> + fb_write(0xfff, fbi->dispc, O4_DISPC_VID1_PRELOAD);
> +
> + fb_write(DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(fmt) |
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_8x128 |
> + DSS_DISPC_VIDn_ATTRIBUTES_ZORDERENABLE |
> + DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_SECONDARY_LCD,
> + fbi->dispc, O4_DISPC_VID1_ATTRIBUTES);
> +
> + rc = wait_on_timeout(O4_TIMEOUT,
> + !(fb_read(fbi->dispc, O4_DISPC_CONTROL2) &
> + DSS_DISPC_CONTROL_GOLCD));
> +
> + if (rc) {
> + dev_err(fbi->dev, "timeout: dispc golcd\n");
> + goto out;
> + }
> +
> + fb_write(fb_read(fbi->dispc, O4_DISPC_CONTROL2) |
> + DSS_DISPC_CONTROL_GOLCD,
> + fbi->dispc, O4_DISPC_CONTROL2);
> +
> + fbi->cur_display = new_display;
> + info->xres = mode->xres;
> + info->yres = mode->yres;
> +
> + rc = 0;
> +
> +out:
> + return rc;
> +}
> +
> +static int omap4fb_reset(struct omap4fb_device const *fbi)
> +{
> + uint32_t v = fb_read(fbi->dispc, O4_DISPC_CONTROL2);
> + int rc;
> +
> + /* step 1: stop the LCD controller */
> + if (v & DSS_DISPC_CONTROL_LCDENABLE) {
> + fb_write(v & ~DSS_DISPC_CONTROL_LCDENABLE,
> + fbi->dispc, O4_DISPC_CONTROL2);
> +
> + fb_write(DSS_DISPC_IRQSTATUS_FRAMEDONE2, fbi->dispc,
> + O4_DISPC_IRQSTATUS);
> +
> +
> + rc = wait_on_timeout(O4_TIMEOUT,
> + ((fb_read(fbi->dispc, O4_DISPC_IRQSTATUS) &
> + DSS_DISPC_IRQSTATUS_FRAMEDONE) != 0));
> +
> + if (rc) {
> + dev_err(fbi->dev, "timeout: irqstatus framedone\n");
> + return -ETIMEDOUT;
> + }
> + }
> +
> + /* step 2: wait for reset done status */
> + rc = wait_on_timeout(O4_TIMEOUT,
> + (fb_read(fbi->dss, O4_DSS_SYSSTATUS) &
> + DSS_DSS_SYSSTATUS_RESETDONE));
> +
> + if (rc) {
> + dev_err(fbi->dev, "timeout: sysstatus resetdone\n");
> + return -ETIMEDOUT;
> + }
> +
> + /* DSS_CTL: set to reset value */
> + fb_write(0, fbi->dss, O4_DSS_CTRL);
> +
> + return 0;
> +}
> +
> +static struct fb_ops omap4fb_ops = {
> + .fb_enable = omap4fb_enable,
> + .fb_disable = omap4fb_disable,
> + .fb_activate_var = omap4fb_activate_var,
> +};
> +
> +static int omap4fb_probe(struct device_d *dev)
> +{
> + struct omap4fb_platform_data const *pdata = dev->platform_data;
> + struct omap4fb_device *fbi;
> + struct fb_info *info;
> + int rc;
> + size_t i;
> +
> + if (!pdata)
> + return -ENODEV;
> +
> + fbi = xzalloc(sizeof *fbi +
> + pdata->num_displays * sizeof fbi->video_modes[0]);
> + info = &fbi->info;
> +
> + fbi->dev = dev;
> +
> + /* CM_DSS_CLKSTCTRL (TRM: 935) trigger SW_WKUP */
> + __raw_writel(0x2, 0x4a009100); /* TODO: move this to clockmanagement */
> +
> + fbi->dss = dev_request_mem_region_by_name(dev, "omap4_dss");
> + fbi->dispc = dev_request_mem_region_by_name(dev, "omap4_dispc");
> +
> + if (!fbi->dss || !fbi->dispc) {
> + dev_err(dev, "Insufficient register description\n");
> + rc = -EINVAL;
> + goto out;
> + }
> +
> + dev_info(dev, "HW-Revision 0x%04x 0x%04x\n",
> + fb_read(fbi->dss, O4_DISPC_REVISION),
> + fb_read(fbi->dss, O4_DSS_REVISION));
> +
> +
drop one line
> + if (!pdata->dss_clk_hz | !pdata->displays | !pdata->num_displays |
> + !pdata->bpp) {
> + dev_err(dev, "Insufficient omap4fb_platform_data\n");
> + rc = -EINVAL;
> + goto out;
> + }
> +
> + fbi->enable_fn = pdata->enable;
> + fbi->displays = pdata->displays;
> + fbi->num_displays = pdata->num_displays;
> + fbi->divisor.dss_clk_hz = pdata->dss_clk_hz;
> +
> + for (i = 0; i < pdata->num_displays; ++i)
> + fbi->video_modes[i] = pdata->displays[i].mode;
> +
> + info->mode_list = fbi->video_modes;
> + info->num_modes = pdata->num_displays;
> +
> + info->priv = fbi;
> + info->fbops = &omap4fb_ops;
> + info->bits_per_pixel = pdata->bpp;
> +
> + if (pdata->screen) {
> + if (!IS_ALIGNED(pdata->screen->start, PAGE_SIZE) ||
> + !IS_ALIGNED(resource_size(pdata->screen), PAGE_SIZE)) {
> + dev_err(dev, "screen resource not aligned\n");
> + rc = -EINVAL;
> + goto out;
> + }
> + fbi->prealloc_screen.addr =
> + (void __iomem *)pdata->screen->start;
> + fbi->prealloc_screen.size = resource_size(pdata->screen);
> + remap_range(fbi->prealloc_screen.addr,
> + fbi->prealloc_screen.size,
> + mmu_get_pte_uncached_flags());
> + }
> +
> + rc = omap4fb_reset(fbi);
> + if (rc < 0) {
> + dev_err(dev, "failed to reset: %d\n", rc);
> + goto out;
> + }
> +
> + rc = register_framebuffer(info);
> + if (rc < 0) {
> + dev_err(dev, "failed to register framebuffer: %d\n", rc);
> + goto out;
> + }
> +
> + rc = 0;
> + dev_info(dev, "registered\n");
> +
> +out:
> + if (rc < 0)
> + free(fbi);
> +
> + return rc;
> +}
> +
> +static struct driver_d omap4fb_driver = {
> + .name = "omap4_fb",
> + .probe = omap4fb_probe,
> +};
> +
> +static int omap4fb_init(void)
> +{
> + return platform_driver_register(&omap4fb_driver);
> +}
> +
> +device_initcall(omap4fb_init);
> diff --git a/drivers/video/omap4.h b/drivers/video/omap4.h
> new file mode 100644
> index 0000000..5704f7b
> --- /dev/null
> +++ b/drivers/video/omap4.h
> @@ -0,0 +1,181 @@
> +/*
> + * TI Omap4 Frame Buffer device driver
> + *
> + * Copyright (C) 2013 Christoph Fritz <chf.fritz@googlemail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef H_BAREBOX_DRIVER_VIDEO_OMAP4_REGS_H
> +#define H_BAREBOX_DRIVER_VIDEO_OMAP4_REGS_H
> +
> +#include <types.h>
> +#include <common.h>
> +
> +#define O4_TIMEOUT (128 * USECOND)
> +
> +#define fb_read(io, reg) __raw_readl((io)+(reg))
> +#define fb_write(val, io, reg) __raw_writel((val), (io)+(reg))
fb_read is too much generic
better to use 2 macro for both resources and pass the fbi struct
> +
> +/* TRM: 10.1.3.2 DSS Registers */
> +#define O4_DSS_REVISION 0x0
> +#define O4_DSS_SYSSTATUS 0x14
> +#define O4_DSS_CTRL 0x40
> +#define O4_DSS_STATUS 0x5c
> +
> +/* TRM: 10.2.7.3 Display Controller Registers */
> +#define O4_DISPC_REVISION 0x0
> +#define O4_DISPC_IRQSTATUS 0x18
> +#define O4_DISPC_CONTROL2 0x238
> +#define O4_DISPC_VID1_ATTRIBUTES 0xcc
> +#define O4_DISPC_TIMING_H2 0x400
> +#define O4_DISPC_TIMING_V2 0x404
> +#define O4_DISPC_POL_FREQ2 0x408
> +#define O4_DISPC_DIVISOR2 0x40c
> +#define O4_DISPC_DEFAULT_COLOR2 0x3ac
> +#define O4_DISPC_SIZE_LCD2 0x3cc
> +#define O4_DISPC_DIVISOR 0x804
> +#define O4_DISPC_VID1_BA0 0xbc
> +#define O4_DISPC_VID1_BA1 0xc0
> +#define O4_DISPC_VID1_POSITION 0xc4
> +#define O4_DISPC_VID1_SIZE 0xc8
> +#define O4_DISPC_VID1_PICTURE_SIZE 0xe4
> +#define O4_DISPC_VID1_ROW_INC 0xd8
> +#define O4_DISPC_VID1_PIXEL_INC 0xdc
> +#define O4_DISPC_VID1_PRELOAD 0x230
> +
> +#define DSS_DISPC_VIDn_POSITION_VIDPOSX(_x) ((_x) << 0)
> +#define DSS_DISPC_VIDn_POSITION_VIDPOSY(_y) ((_y) << 16)
> +
> +#define DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEX(_x) ((_x) << 0)
> +#define DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEY(_y) ((_y) << 16)
> +
> +#define DSS_DISPC_VIDn_SIZE_VIDSIZEX(_x) ((_x) << 0)
> +#define DSS_DISPC_VIDn_SIZE_VIDSIZEY(_y) ((_y) << 16)
> +
> +#define DSS_DISPC_SIZE_LCD_PPL(_x) ((_x) << 0)
> +#define DSS_DISPC_SIZE_LCD_LPP(_y) ((_y) << 16)
> +
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE (1u << 0)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(_fmt) ((_fmt) << 1)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB12 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(4u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB16 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(5u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB16 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(6u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB16o \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(7u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_xRGB24u \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(8u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB24p \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(9u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_YUV2 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(10u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_UYVY \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(11u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB32 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(12u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGBA32 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(13u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_xRGB32 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(14u)
> +
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(_b) ((_b) << 14)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_2x128 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(0u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_4x128 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(1u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_8x128 \
> + DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(2u)
> +
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDCHANNELOUT (1u << 16)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_SELFREFRESHAUTO (1u << 17)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFIFOPRELOAD (1u << 19)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDVERTICALTAPS (1u << 21)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_DOUBLESTRIDE (1u << 22)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDARBITRATION (1u << 23)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_VIDSELFREFRESH (1u << 24)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_ZORDERENABLE (1u << 25)
> +
> +#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(_b) ((_b) << 30)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_PRIMARY_LCD \
> + DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(0u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_SECONDARY_LCD \
> + DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(1u)
> +#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_WRITEBACK_MEM \
> + DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(3u)
> +
> +#define DSS_DISPC_CONTROL_LCDENABLE (1u << 0)
> +#define DSS_DISPC_CONTROL_TVENABLE (1u << 1)
> +#define DSS_DISPC_CONTROL_MONOCOLOR (1u << 2)
> +#define DSS_DISPC_CONTROL_STNTFT (1u << 3)
> +#define DSS_DISPC_CONTROL_M8B (1u << 4)
> +#define DSS_DISPC_CONTROL_GOLCD (1u << 5)
> +#define DSS_DISPC_CONTROL_GOTV (1u << 6)
> +#define DSS_DISPC_CONTROL_STDITHERENABLE (1u << 7)
> +
> +#define DSS_DISPC_CONTROL_TFTDATALINES(_l) ((_l) << 8)
> +#define DSS_DISPC_CONTROL_TFTDATALINES_12 \
> + DSS_DISPC_CONTROL_TFTDATALINES(0u)
> +#define DSS_DISPC_CONTROL_TFTDATALINES_16 \
> + DSS_DISPC_CONTROL_TFTDATALINES(1u)
> +#define DSS_DISPC_CONTROL_TFTDATALINES_18 \
> + DSS_DISPC_CONTROL_TFTDATALINES(2u)
> +#define DSS_DISPC_CONTROL_TFTDATALINES_24 \
> + DSS_DISPC_CONTROL_TFTDATALINES(3u)
> +
> +#define DSS_DISPC_CONTROL_STALLMODE (1u << 11)
> +#define DSS_DISPC_CONTROL_OVERLAYOPTIMIZATION (1u << 12)
> +#define DSS_DISPC_CONTROL_GPIN0 (1u << 13) /* ro */
> +#define DSS_DISPC_CONTROL_GPIN1 (1u << 14) /* ro */
> +#define DSS_DISPC_CONTROL_GPOUT0 (1u << 15)
> +#define DSS_DISPC_CONTROL_GPOUT1 (1u << 16)
> +#define DSS_DISPC_CONTROL_HT(_ht) ((_ht) << 17)
> +#define DSS_DISPC_CONTROL_TDMENABLE (1u << 20)
> +#define DSS_DISPC_CONTROL_TDMPARALLELMODE(_pm) ((_pm) << 21)
> +#define DSS_DISPC_CONTROL_TDMCYCLEFORMAT(_cf) ((_cf) << 23)
> +#define DSS_DISPC_CONTROL_TDMUNUSEDBITS(_ub) ((_ub) << 25)
> +#define DSS_DISPC_CONTROL_PCKFREEENABLE (1u << 27)
> +#define DSS_DISPC_CONTROL_LCDENABLESIGNAL (1u << 28)
> +#define DSS_DISPC_CONTROL_LCDENABLEPOL (1u << 29)
> +#define DSS_DISPC_CONTROL_SPATIALTEMPD(_df) ((_df) << 30)
> +
> +#define DSS_DISPC_POL_FREQ_IVS (1u << 12)
> +#define DSS_DISPC_POL_FREQ_IHS (1u << 13)
> +#define DSS_DISPC_POL_FREQ_IPC (1u << 14)
> +#define DSS_DISPC_POL_FREQ_IEO (1u << 15)
> +#define DSS_DISPC_POL_FREQ_RF (1u << 16)
> +#define DSS_DISPC_POL_FREQ_ONOFF (1u << 17)
> +
> +#define DSS_DISPC_TIMING_H_HSW(_hsw) ((_hsw) << 0)
> +#define DSS_DISPC_TIMING_H_HFP(_hfp) ((_hfp) << 8)
> +#define DSS_DISPC_TIMING_H_HBP(_hbp) ((_hbp) << 20)
> +
> +#define DSS_DISPC_TIMING_V_VSW(_vsw) ((_vsw) << 0)
> +#define DSS_DISPC_TIMING_V_VFP(_vfp) ((_vfp) << 8)
> +#define DSS_DISPC_TIMING_V_VBP(_vbp) ((_vbp) << 20)
> +
> +#define DSS_DISPC_DIVISOR_ENABLE (1u << 0)
> +#define DSS_DISPC_DIVISOR_LCD(_lcd) ((_lcd) << 16)
> +
> +#define DSS_DISPC_DIVISOR2_PCD(_pcd) ((_pcd) << 0)
> +#define DSS_DISPC_DIVISOR2_LCD(_lcd) ((_lcd) << 16)
> +
> +#define DSS_DISPC_IRQSTATUS_FRAMEDONE (1u << 0)
> +#define DSS_DISPC_IRQSTATUS_FRAMEDONE2 (1u << 22)
> +
> +#define DSS_DSS_SYSSTATUS_RESETDONE (1u << 0)
> +
> +#endif /* H_BAREBOX_DRIVER_VIDEO_O4_REGS_H */
> --
> 1.7.10.4
>
>
>
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^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v6] omap4-fb: add driver
2013-06-14 11:43 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2013-06-14 15:11 ` Christoph Fritz
2013-06-17 7:36 ` Sascha Hauer
2013-06-17 18:45 ` [PATCH v6] " Alexander Aring
2013-06-17 16:18 ` Christoph Fritz
1 sibling, 2 replies; 24+ messages in thread
From: Christoph Fritz @ 2013-06-14 15:11 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD, Sascha Hauer; +Cc: barebox
This patch adds omap4 display controller support.
Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
---
changes since v2:
- use dev_request_mem_region_by_name()
changes since v3:
- remove register struct
- use uncached screen_base
changes since v4:
- remove useless dev_add_param()
- use wait_on_timeout() instead while-deadlock
changes since v5:
- use dev_dbg() and dev_err(), be less verbose
- fix coding-style issues
- add omap4fb_find_display_by_name()
- add additional read/write macros
---
arch/arm/mach-omap/Makefile | 1 +
arch/arm/mach-omap/include/mach/omap4-fb.h | 46 +++
arch/arm/mach-omap/omap4_fb.c | 27 ++
drivers/video/Kconfig | 8 +
drivers/video/Makefile | 1 +
drivers/video/omap4.c | 526 ++++++++++++++++++++++++++++
drivers/video/omap4.h | 187 ++++++++++
7 files changed, 796 insertions(+)
create mode 100644 arch/arm/mach-omap/include/mach/omap4-fb.h
create mode 100644 arch/arm/mach-omap/omap4_fb.c
create mode 100644 drivers/video/omap4.c
create mode 100644 drivers/video/omap4.h
diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile
index 94e42c6..e70ddbd 100644
--- a/arch/arm/mach-omap/Makefile
+++ b/arch/arm/mach-omap/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
pbl-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
obj-$(CONFIG_OMAP_GPMC) += gpmc.o devices-gpmc-nand.o
obj-$(CONFIG_SHELL_NONE) += xload.o
+obj-$(CONFIG_DRIVER_VIDEO_OMAP4) += omap4_fb.o
obj-$(CONFIG_I2C_TWL6030) += omap4_twl6030_mmc.o
obj-$(CONFIG_OMAP4_USBBOOT) += omap4_rom_usb.o
obj-y += gpio.o
diff --git a/arch/arm/mach-omap/include/mach/omap4-fb.h b/arch/arm/mach-omap/include/mach/omap4-fb.h
new file mode 100644
index 0000000..5c0a54b
--- /dev/null
+++ b/arch/arm/mach-omap/include/mach/omap4-fb.h
@@ -0,0 +1,46 @@
+#ifndef H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H
+#define H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H
+
+#include <fb.h>
+
+#define OMAP_DSS_LCD_TFT (1u << 0)
+#define OMAP_DSS_LCD_IVS (1u << 1)
+#define OMAP_DSS_LCD_IHS (1u << 2)
+#define OMAP_DSS_LCD_IPC (1u << 3)
+#define OMAP_DSS_LCD_IEO (1u << 4)
+#define OMAP_DSS_LCD_RF (1u << 5)
+#define OMAP_DSS_LCD_ONOFF (1u << 6)
+
+#define OMAP_DSS_LCD_DATALINES(_l) ((_l) << 10)
+#define OMAP_DSS_LCD_DATALINES_msk OMAP_DSS_LCD_DATALINES(3u)
+#define OMAP_DSS_LCD_DATALINES_12 OMAP_DSS_LCD_DATALINES(0u)
+#define OMAP_DSS_LCD_DATALINES_16 OMAP_DSS_LCD_DATALINES(1u)
+#define OMAP_DSS_LCD_DATALINES_18 OMAP_DSS_LCD_DATALINES(2u)
+#define OMAP_DSS_LCD_DATALINES_24 OMAP_DSS_LCD_DATALINES(3u)
+
+struct omap4fb_display {
+ struct fb_videomode mode;
+
+ unsigned long config;
+
+ unsigned int power_on_delay;
+ unsigned int power_off_delay;
+};
+
+struct omap4fb_platform_data {
+ struct omap4fb_display const *displays;
+ size_t num_displays;
+
+ unsigned int dss_clk_hz;
+
+ unsigned int bpp;
+
+ struct resource const *screen;
+
+ void (*enable)(int p);
+};
+
+struct device_d;
+struct device_d *omap4_add_display(void *pdata);
+
+#endif /* H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H */
diff --git a/arch/arm/mach-omap/omap4_fb.c b/arch/arm/mach-omap/omap4_fb.c
new file mode 100644
index 0000000..09a6af3
--- /dev/null
+++ b/arch/arm/mach-omap/omap4_fb.c
@@ -0,0 +1,27 @@
+#include <driver.h>
+#include <common.h>
+#include <linux/ioport.h>
+#include <mach/omap4-fb.h>
+
+static struct resource omap4_fb_resources[] = {
+ {
+ .name = "omap4_dss",
+ .start = 0x48040000,
+ .end = 0x48040000 + 512 - 1,
+ .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+ }, {
+ .name = "omap4_dispc",
+ .start = 0x48041000,
+ .end = 0x48041000 + 3072 - 1,
+ .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+ },
+};
+
+struct device_d *omap4_add_display(void *pdata)
+{
+ return add_generic_device_res("omap4_fb", -1,
+ omap4_fb_resources,
+ ARRAY_SIZE(omap4_fb_resources),
+ pdata);
+}
+EXPORT_SYMBOL(omap4_add_display);
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 6d6b08f..9dfa0cd 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -45,6 +45,14 @@ config DRIVER_VIDEO_S3C24XX
help
Add support for the S3C244x LCD controller.
+config DRIVER_VIDEO_OMAP4
+ bool "OMAP4 framebuffer driver"
+ depends on ARCH_OMAP4
+ help
+ Add support for the OMAP4 Display Controller.
+ DSI is unsupported, only DISPC parallel mode on LCD2
+ is supported.
+
if DRIVER_VIDEO_S3C24XX
config DRIVER_VIDEO_S3C_VERBOSE
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 7429141..83feebb 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_DRIVER_VIDEO_IMX_IPU) += imx-ipu-fb.o
obj-$(CONFIG_DRIVER_VIDEO_S3C24XX) += s3c24xx.o
obj-$(CONFIG_DRIVER_VIDEO_PXA) += pxa.o
obj-$(CONFIG_DRIVER_VIDEO_SDL) += sdl.o
+obj-$(CONFIG_DRIVER_VIDEO_OMAP4) += omap4.o
diff --git a/drivers/video/omap4.c b/drivers/video/omap4.c
new file mode 100644
index 0000000..afdee44
--- /dev/null
+++ b/drivers/video/omap4.c
@@ -0,0 +1,526 @@
+/*
+ * TI Omap4 Frame Buffer device driver
+ *
+ * Copyright (C) 2013 Christoph Fritz <chf.fritz@googlemail.com>
+ * Based on work by Enrico Scholz, sponsored by Phytec
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <driver.h>
+#include <fb.h>
+#include <errno.h>
+#include <xfuncs.h>
+#include <init.h>
+#include <stdio.h>
+#include <io.h>
+#include <common.h>
+#include <malloc.h>
+#include <common.h>
+#include <clock.h>
+
+#include <mach/omap4-silicon.h>
+#include <mach/omap4-fb.h>
+
+#include <asm/mmu.h>
+
+#include "omap4.h"
+
+struct omap4fb_device {
+ struct fb_info info;
+ struct device_d *dev;
+
+ struct omap4fb_display const *cur_display;
+
+ struct omap4fb_display const *displays;
+ size_t num_displays;
+
+ void __iomem *dss;
+ void __iomem *dispc;
+
+ struct {
+ void __iomem *addr;
+ size_t size;
+ } prealloc_screen;
+
+ struct {
+ uint32_t dispc_control;
+ uint32_t dispc_pol_freq;
+ } shadow;
+
+ struct {
+ unsigned int dss_clk_hz;
+ unsigned int lckd;
+ unsigned int pckd;
+ } divisor;
+ size_t dma_size;
+ void (*enable_fn)(int);
+
+ struct fb_videomode video_modes[];
+};
+
+static void omap4fb_enable(struct fb_info *info)
+{
+ struct omap4fb_device *fbi =
+ container_of(info, struct omap4fb_device, info);
+
+ dev_dbg(fbi->dev, "%s\n", __func__);
+
+ if (!fbi->cur_display) {
+ dev_err(fbi->dev, "no valid mode set\n");
+ return;
+ }
+
+ if (fbi->enable_fn)
+ fbi->enable_fn(1);
+
+ udelay(fbi->cur_display->power_on_delay * 1000u);
+
+ o4_dispc_write(o4_dispc_read(O4_DISPC_CONTROL2) |
+ DSS_DISPC_CONTROL_LCDENABLE |
+ DSS_DISPC_CONTROL_LCDENABLESIGNAL, O4_DISPC_CONTROL2);
+
+ o4_dispc_write(o4_dispc_read(O4_DISPC_VID1_ATTRIBUTES) |
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE, O4_DISPC_VID1_ATTRIBUTES);
+
+ o4_dispc_write(o4_dispc_read(O4_DISPC_CONTROL2) |
+ DSS_DISPC_CONTROL_GOLCD, O4_DISPC_CONTROL2);
+}
+
+static void omap4fb_disable(struct fb_info *info)
+{
+ struct omap4fb_device *fbi =
+ container_of(info, struct omap4fb_device, info);
+
+ dev_dbg(fbi->dev, "%s\n", __func__);
+
+ if (!fbi->cur_display) {
+ dev_err(fbi->dev, "no valid mode set\n");
+ return;
+ }
+
+ o4_dispc_write(o4_dispc_read(O4_DISPC_CONTROL2) &
+ ~(DSS_DISPC_CONTROL_LCDENABLE |
+ DSS_DISPC_CONTROL_LCDENABLESIGNAL), O4_DISPC_CONTROL2);
+
+ o4_dispc_write(o4_dispc_read(O4_DISPC_VID1_ATTRIBUTES) &
+ ~(DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE),
+ O4_DISPC_VID1_ATTRIBUTES);
+
+ if (fbi->prealloc_screen.addr == NULL) {
+ /* free frame buffer; but only when screen is not
+ * preallocated */
+ if (info->screen_base)
+ dma_free_coherent(info->screen_base, fbi->dma_size);
+ }
+
+ info->screen_base = NULL;
+
+ udelay(fbi->cur_display->power_off_delay * 1000u);
+
+ if (fbi->enable_fn)
+ fbi->enable_fn(0);
+}
+
+static void omap4fb_calc_divisor(struct omap4fb_device *fbi,
+ struct fb_videomode const *mode)
+{
+ unsigned int l, k, t, b;
+
+ b = UINT_MAX;
+ for (l = 1; l < 256; l++) {
+ for (k = 1; k < 256; k++) {
+ t = abs(mode->pixclock * 100 -
+ (fbi->divisor.dss_clk_hz / l / k));
+ if (t <= b) {
+ b = t;
+ fbi->divisor.lckd = l;
+ fbi->divisor.pckd = k;
+ }
+ }
+ }
+}
+
+static unsigned int omap4fb_calc_format(struct fb_info const *info)
+{
+ struct omap4fb_device *fbi =
+ container_of(info, struct omap4fb_device, info);
+
+ switch (info->bits_per_pixel) {
+ case 24:
+ return 9;
+ case 32:
+ return 0x8; /* xRGB24-8888 (32-bit container) */
+ default:
+ dev_err(fbi->dev, "%s: unsupported bpp %d\n", __func__,
+ info->bits_per_pixel);
+ return 0;
+ }
+}
+
+struct omap4fb_colors {
+ struct fb_bitfield red;
+ struct fb_bitfield green;
+ struct fb_bitfield blue;
+ struct fb_bitfield transp;
+};
+
+static struct omap4fb_colors const omap4fb_col[] = {
+ [0] = {
+ .red = { .length = 0, .offset = 0 },
+ },
+ [1] = {
+ .blue = { .length = 8, .offset = 0 },
+ .green = { .length = 8, .offset = 8 },
+ .red = { .length = 8, .offset = 16 },
+ },
+ [2] = {
+ .blue = { .length = 8, .offset = 0 },
+ .green = { .length = 8, .offset = 8 },
+ .red = { .length = 8, .offset = 16 },
+ .transp = { .length = 8, .offset = 24 },
+ },
+};
+
+static void omap4fb_fill_shadow(struct omap4fb_device *fbi,
+ struct omap4fb_display const *display)
+{
+ fbi->shadow.dispc_control = 0;
+ fbi->shadow.dispc_pol_freq = 0;
+
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_STNTFT;
+
+ switch (display->config & OMAP_DSS_LCD_DATALINES_msk) {
+ case OMAP_DSS_LCD_DATALINES_12:
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_12;
+ break;
+ case OMAP_DSS_LCD_DATALINES_16:
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_16;
+ break;
+ case OMAP_DSS_LCD_DATALINES_18:
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_18;
+ break;
+ case OMAP_DSS_LCD_DATALINES_24:
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_24;
+ break;
+ }
+
+ if (display->config & OMAP_DSS_LCD_IPC)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IPC;
+
+ if (display->config & OMAP_DSS_LCD_IVS)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IVS;
+
+ if (display->config & OMAP_DSS_LCD_IHS)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IHS;
+
+ if (display->config & OMAP_DSS_LCD_IEO)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IEO;
+
+ if (display->config & OMAP_DSS_LCD_RF)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_RF;
+
+ if (display->config & OMAP_DSS_LCD_ONOFF)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_ONOFF;
+}
+
+static int omap4fb_find_display_by_name(struct omap4fb_device *fbi,
+ const char *name)
+{
+ int i;
+
+ for (i = 0; i < fbi->num_displays; ++i) {
+ if (strcmp(name, fbi->displays[i].mode.name) == 0)
+ return i;
+ }
+ return -ENXIO;
+}
+
+static int omap4fb_activate_var(struct fb_info *info)
+{
+ struct omap4fb_device *fbi =
+ container_of(info, struct omap4fb_device, info);
+ struct fb_videomode const *mode = info->mode;
+ size_t size = mode->xres * mode->yres * (info->bits_per_pixel / 8);
+ int rc;
+ unsigned int fmt = omap4fb_calc_format(info);
+ struct omap4fb_colors const *cols;
+ struct omap4fb_display const *new_display = NULL;
+
+ rc = omap4fb_find_display_by_name(fbi, mode->name);
+ if (rc < 0) {
+ dev_err(fbi->dev, "no display found for this mode '%s'\n",
+ mode->name);
+ goto out;
+ }
+ new_display = &fbi->displays[rc];
+
+ /*Free old screen buf*/
+ if (!fbi->prealloc_screen.addr && info->screen_base)
+ dma_free_coherent(info->screen_base, fbi->dma_size);
+
+ fbi->dma_size = PAGE_ALIGN(size);
+
+ if (!fbi->prealloc_screen.addr) {
+ /* case 1: no preallocated screen */
+ info->screen_base = dma_alloc_coherent(size);
+ } else if (fbi->prealloc_screen.size < fbi->dma_size) {
+ /* case 2: preallocated screen, but too small */
+ dev_err(fbi->dev,
+ "allocated framebuffer too small (%zu < %zu)\n",
+ fbi->prealloc_screen.size, fbi->dma_size);
+ rc = -ENOMEM;
+ goto out;
+ } else {
+ /* case 3: preallocated screen */
+ info->screen_base = fbi->prealloc_screen.addr;
+ }
+
+ omap4fb_fill_shadow(fbi, new_display);
+
+ omap4fb_calc_divisor(fbi, mode);
+
+ switch (info->bits_per_pixel) {
+ case 24:
+ cols = &omap4fb_col[1];
+ break;
+ case 32:
+ cols = &omap4fb_col[2];
+ break;
+ default:
+ cols = &omap4fb_col[0];
+ }
+
+ info->red = cols->red;
+ info->green = cols->green;
+ info->blue = cols->blue;
+ info->transp = cols->transp;
+
+ o4_dispc_write(fbi->shadow.dispc_control, O4_DISPC_CONTROL2);
+
+ o4_dispc_write(fbi->shadow.dispc_pol_freq, O4_DISPC_POL_FREQ2);
+
+ o4_dispc_write(DSS_DISPC_TIMING_H_HSW(mode->hsync_len - 1) |
+ DSS_DISPC_TIMING_H_HFP(mode->right_margin - 1) |
+ DSS_DISPC_TIMING_H_HBP(mode->left_margin - 1),
+ O4_DISPC_TIMING_H2);
+
+ o4_dispc_write(DSS_DISPC_TIMING_V_VSW(mode->vsync_len - 1) |
+ DSS_DISPC_TIMING_V_VFP(mode->lower_margin) |
+ DSS_DISPC_TIMING_V_VBP(mode->upper_margin), O4_DISPC_TIMING_V2);
+
+ o4_dispc_write(DSS_DISPC_DIVISOR_ENABLE | DSS_DISPC_DIVISOR_LCD(1),
+ O4_DISPC_DIVISOR);
+
+ o4_dispc_write(DSS_DISPC_DIVISOR2_LCD(fbi->divisor.lckd) |
+ DSS_DISPC_DIVISOR2_PCD(fbi->divisor.pckd), O4_DISPC_DIVISOR2);
+
+ o4_dispc_write(DSS_DISPC_SIZE_LCD_PPL(mode->xres - 1) |
+ DSS_DISPC_SIZE_LCD_LPP(mode->yres - 1), O4_DISPC_SIZE_LCD2);
+
+ o4_dispc_write(0x0000ff00, O4_DISPC_DEFAULT_COLOR2);
+
+ /* we use VID1 */
+ o4_dispc_write((uintptr_t)info->screen_base, O4_DISPC_VID1_BA0);
+ o4_dispc_write((uintptr_t)info->screen_base, O4_DISPC_VID1_BA1);
+
+ o4_dispc_write(DSS_DISPC_VIDn_POSITION_VIDPOSX(0) |
+ DSS_DISPC_VIDn_POSITION_VIDPOSY(0), O4_DISPC_VID1_POSITION);
+ o4_dispc_write(DSS_DISPC_VIDn_SIZE_VIDSIZEX(mode->xres - 1) |
+ DSS_DISPC_VIDn_SIZE_VIDSIZEY(mode->yres - 1),
+ O4_DISPC_VID1_SIZE);
+ o4_dispc_write(DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEX(mode->xres - 1) |
+ DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEY(mode->yres - 1),
+ O4_DISPC_VID1_PICTURE_SIZE);
+ o4_dispc_write(1, O4_DISPC_VID1_ROW_INC);
+ o4_dispc_write(1, O4_DISPC_VID1_PIXEL_INC);
+
+ o4_dispc_write(0xfff, O4_DISPC_VID1_PRELOAD);
+
+ o4_dispc_write(DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(fmt) |
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_8x128 |
+ DSS_DISPC_VIDn_ATTRIBUTES_ZORDERENABLE |
+ DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_SECONDARY_LCD,
+ O4_DISPC_VID1_ATTRIBUTES);
+
+ rc = wait_on_timeout(O4_TIMEOUT,
+ !(o4_dispc_read(O4_DISPC_CONTROL2) &
+ DSS_DISPC_CONTROL_GOLCD));
+
+ if (rc) {
+ dev_err(fbi->dev, "timeout: dispc golcd\n");
+ goto out;
+ }
+
+ o4_dispc_write(o4_dispc_read(O4_DISPC_CONTROL2) |
+ DSS_DISPC_CONTROL_GOLCD, O4_DISPC_CONTROL2);
+
+ fbi->cur_display = new_display;
+ info->xres = mode->xres;
+ info->yres = mode->yres;
+
+ rc = 0;
+
+out:
+ return rc;
+}
+
+static int omap4fb_reset(struct omap4fb_device const *fbi)
+{
+ uint32_t v = o4_dispc_read(O4_DISPC_CONTROL2);
+ int rc;
+
+ /* step 1: stop the LCD controller */
+ if (v & DSS_DISPC_CONTROL_LCDENABLE) {
+ o4_dispc_write(v & ~DSS_DISPC_CONTROL_LCDENABLE,
+ O4_DISPC_CONTROL2);
+
+ o4_dispc_write(DSS_DISPC_IRQSTATUS_FRAMEDONE2,
+ O4_DISPC_IRQSTATUS);
+
+ rc = wait_on_timeout(O4_TIMEOUT,
+ ((o4_dispc_read(O4_DISPC_IRQSTATUS) &
+ DSS_DISPC_IRQSTATUS_FRAMEDONE) != 0));
+
+ if (rc) {
+ dev_err(fbi->dev, "timeout: irqstatus framedone\n");
+ return -ETIMEDOUT;
+ }
+ }
+
+ /* step 2: wait for reset done status */
+ rc = wait_on_timeout(O4_TIMEOUT,
+ (o4_dss_read(O4_DSS_SYSSTATUS) &
+ DSS_DSS_SYSSTATUS_RESETDONE));
+
+ if (rc) {
+ dev_err(fbi->dev, "timeout: sysstatus resetdone\n");
+ return -ETIMEDOUT;
+ }
+
+ /* DSS_CTL: set to reset value */
+ o4_dss_write(0, O4_DSS_CTRL);
+
+ return 0;
+}
+
+static struct fb_ops omap4fb_ops = {
+ .fb_enable = omap4fb_enable,
+ .fb_disable = omap4fb_disable,
+ .fb_activate_var = omap4fb_activate_var,
+};
+
+static int omap4fb_probe(struct device_d *dev)
+{
+ struct omap4fb_platform_data const *pdata = dev->platform_data;
+ struct omap4fb_device *fbi;
+ struct fb_info *info;
+ int rc;
+ size_t i;
+
+ if (!pdata)
+ return -ENODEV;
+
+ fbi = xzalloc(sizeof *fbi +
+ pdata->num_displays * sizeof fbi->video_modes[0]);
+ info = &fbi->info;
+
+ fbi->dev = dev;
+
+ /* CM_DSS_CLKSTCTRL (TRM: 935) trigger SW_WKUP */
+ __raw_writel(0x2, 0x4a009100); /* TODO: move this to clockmanagement */
+
+ fbi->dss = dev_request_mem_region_by_name(dev, "omap4_dss");
+ fbi->dispc = dev_request_mem_region_by_name(dev, "omap4_dispc");
+
+ if (!fbi->dss || !fbi->dispc) {
+ dev_err(dev, "Insufficient register description\n");
+ rc = -EINVAL;
+ goto out;
+ }
+
+ dev_info(dev, "HW-Revision 0x%04x 0x%04x\n",
+ o4_dss_read(O4_DISPC_REVISION),
+ o4_dss_read(O4_DSS_REVISION));
+
+ if (!pdata->dss_clk_hz | !pdata->displays | !pdata->num_displays |
+ !pdata->bpp) {
+ dev_err(dev, "Insufficient omap4fb_platform_data\n");
+ rc = -EINVAL;
+ goto out;
+ }
+
+ fbi->enable_fn = pdata->enable;
+ fbi->displays = pdata->displays;
+ fbi->num_displays = pdata->num_displays;
+ fbi->divisor.dss_clk_hz = pdata->dss_clk_hz;
+
+ for (i = 0; i < pdata->num_displays; ++i)
+ fbi->video_modes[i] = pdata->displays[i].mode;
+
+ info->mode_list = fbi->video_modes;
+ info->num_modes = pdata->num_displays;
+
+ info->priv = fbi;
+ info->fbops = &omap4fb_ops;
+ info->bits_per_pixel = pdata->bpp;
+
+ if (pdata->screen) {
+ if (!IS_ALIGNED(pdata->screen->start, PAGE_SIZE) ||
+ !IS_ALIGNED(resource_size(pdata->screen), PAGE_SIZE)) {
+ dev_err(dev, "screen resource not aligned\n");
+ rc = -EINVAL;
+ goto out;
+ }
+ fbi->prealloc_screen.addr =
+ (void __iomem *)pdata->screen->start;
+ fbi->prealloc_screen.size = resource_size(pdata->screen);
+ remap_range(fbi->prealloc_screen.addr,
+ fbi->prealloc_screen.size,
+ mmu_get_pte_uncached_flags());
+ }
+
+ rc = omap4fb_reset(fbi);
+ if (rc < 0) {
+ dev_err(dev, "failed to reset: %d\n", rc);
+ goto out;
+ }
+
+ rc = register_framebuffer(info);
+ if (rc < 0) {
+ dev_err(dev, "failed to register framebuffer: %d\n", rc);
+ goto out;
+ }
+
+ rc = 0;
+ dev_info(dev, "registered\n");
+
+out:
+ if (rc < 0)
+ free(fbi);
+
+ return rc;
+}
+
+static struct driver_d omap4fb_driver = {
+ .name = "omap4_fb",
+ .probe = omap4fb_probe,
+};
+
+static int omap4fb_init(void)
+{
+ return platform_driver_register(&omap4fb_driver);
+}
+
+device_initcall(omap4fb_init);
diff --git a/drivers/video/omap4.h b/drivers/video/omap4.h
new file mode 100644
index 0000000..4328a6c
--- /dev/null
+++ b/drivers/video/omap4.h
@@ -0,0 +1,187 @@
+/*
+ * TI Omap4 Frame Buffer device driver
+ *
+ * Copyright (C) 2013 Christoph Fritz <chf.fritz@googlemail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef H_BAREBOX_DRIVER_VIDEO_OMAP4_REGS_H
+#define H_BAREBOX_DRIVER_VIDEO_OMAP4_REGS_H
+
+#include <types.h>
+#include <common.h>
+
+#define O4_TIMEOUT (128 * USECOND)
+
+#define _o4fb_read(io, reg) __raw_readl((io)+(reg))
+#define _o4fb_write(val, io, reg) __raw_writel((val), (io)+(reg))
+
+/* TRM: 10.1.3.2 DSS Registers */
+#define O4_DSS_REVISION 0x0
+#define O4_DSS_SYSSTATUS 0x14
+#define O4_DSS_CTRL 0x40
+#define O4_DSS_STATUS 0x5c
+
+#define o4_dss_read(reg) _o4fb_read(fbi->dss, reg)
+#define o4_dss_write(val, reg) _o4fb_write(val, fbi->dss, reg)
+
+/* TRM: 10.2.7.3 Display Controller Registers */
+#define O4_DISPC_REVISION 0x0
+#define O4_DISPC_IRQSTATUS 0x18
+#define O4_DISPC_VID1_BA0 0xbc
+#define O4_DISPC_VID1_BA1 0xc0
+#define O4_DISPC_VID1_POSITION 0xc4
+#define O4_DISPC_VID1_SIZE 0xc8
+#define O4_DISPC_VID1_ATTRIBUTES 0xcc
+#define O4_DISPC_VID1_ROW_INC 0xd8
+#define O4_DISPC_VID1_PIXEL_INC 0xdc
+#define O4_DISPC_VID1_PICTURE_SIZE 0xe4
+#define O4_DISPC_VID1_PRELOAD 0x230
+#define O4_DISPC_CONTROL2 0x238
+#define O4_DISPC_DEFAULT_COLOR2 0x3ac
+#define O4_DISPC_SIZE_LCD2 0x3cc
+#define O4_DISPC_TIMING_H2 0x400
+#define O4_DISPC_TIMING_V2 0x404
+#define O4_DISPC_POL_FREQ2 0x408
+#define O4_DISPC_DIVISOR2 0x40c
+#define O4_DISPC_DIVISOR 0x804
+
+#define o4_dispc_read(reg) _o4fb_read(fbi->dispc, reg)
+#define o4_dispc_write(val, reg) _o4fb_write(val, fbi->dispc, reg)
+
+#define DSS_DISPC_VIDn_POSITION_VIDPOSX(_x) ((_x) << 0)
+#define DSS_DISPC_VIDn_POSITION_VIDPOSY(_y) ((_y) << 16)
+
+#define DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEX(_x) ((_x) << 0)
+#define DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEY(_y) ((_y) << 16)
+
+#define DSS_DISPC_VIDn_SIZE_VIDSIZEX(_x) ((_x) << 0)
+#define DSS_DISPC_VIDn_SIZE_VIDSIZEY(_y) ((_y) << 16)
+
+#define DSS_DISPC_SIZE_LCD_PPL(_x) ((_x) << 0)
+#define DSS_DISPC_SIZE_LCD_LPP(_y) ((_y) << 16)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE (1u << 0)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(_fmt) ((_fmt) << 1)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB12 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(4u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB16 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(5u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB16 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(6u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB16o \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(7u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_xRGB24u \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(8u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB24p \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(9u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_YUV2 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(10u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_UYVY \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(11u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB32 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(12u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGBA32 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(13u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_xRGB32 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(14u)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(_b) ((_b) << 14)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_2x128 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(0u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_4x128 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(1u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_8x128 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(2u)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDCHANNELOUT (1u << 16)
+#define DSS_DISPC_VIDn_ATTRIBUTES_SELFREFRESHAUTO (1u << 17)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFIFOPRELOAD (1u << 19)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDVERTICALTAPS (1u << 21)
+#define DSS_DISPC_VIDn_ATTRIBUTES_DOUBLESTRIDE (1u << 22)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDARBITRATION (1u << 23)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDSELFREFRESH (1u << 24)
+#define DSS_DISPC_VIDn_ATTRIBUTES_ZORDERENABLE (1u << 25)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(_b) ((_b) << 30)
+#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_PRIMARY_LCD \
+ DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(0u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_SECONDARY_LCD \
+ DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(1u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_WRITEBACK_MEM \
+ DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(3u)
+
+#define DSS_DISPC_CONTROL_LCDENABLE (1u << 0)
+#define DSS_DISPC_CONTROL_TVENABLE (1u << 1)
+#define DSS_DISPC_CONTROL_MONOCOLOR (1u << 2)
+#define DSS_DISPC_CONTROL_STNTFT (1u << 3)
+#define DSS_DISPC_CONTROL_M8B (1u << 4)
+#define DSS_DISPC_CONTROL_GOLCD (1u << 5)
+#define DSS_DISPC_CONTROL_GOTV (1u << 6)
+#define DSS_DISPC_CONTROL_STDITHERENABLE (1u << 7)
+
+#define DSS_DISPC_CONTROL_TFTDATALINES(_l) ((_l) << 8)
+#define DSS_DISPC_CONTROL_TFTDATALINES_12 \
+ DSS_DISPC_CONTROL_TFTDATALINES(0u)
+#define DSS_DISPC_CONTROL_TFTDATALINES_16 \
+ DSS_DISPC_CONTROL_TFTDATALINES(1u)
+#define DSS_DISPC_CONTROL_TFTDATALINES_18 \
+ DSS_DISPC_CONTROL_TFTDATALINES(2u)
+#define DSS_DISPC_CONTROL_TFTDATALINES_24 \
+ DSS_DISPC_CONTROL_TFTDATALINES(3u)
+
+#define DSS_DISPC_CONTROL_STALLMODE (1u << 11)
+#define DSS_DISPC_CONTROL_OVERLAYOPTIMIZATION (1u << 12)
+#define DSS_DISPC_CONTROL_GPIN0 (1u << 13) /* ro */
+#define DSS_DISPC_CONTROL_GPIN1 (1u << 14) /* ro */
+#define DSS_DISPC_CONTROL_GPOUT0 (1u << 15)
+#define DSS_DISPC_CONTROL_GPOUT1 (1u << 16)
+#define DSS_DISPC_CONTROL_HT(_ht) ((_ht) << 17)
+#define DSS_DISPC_CONTROL_TDMENABLE (1u << 20)
+#define DSS_DISPC_CONTROL_TDMPARALLELMODE(_pm) ((_pm) << 21)
+#define DSS_DISPC_CONTROL_TDMCYCLEFORMAT(_cf) ((_cf) << 23)
+#define DSS_DISPC_CONTROL_TDMUNUSEDBITS(_ub) ((_ub) << 25)
+#define DSS_DISPC_CONTROL_PCKFREEENABLE (1u << 27)
+#define DSS_DISPC_CONTROL_LCDENABLESIGNAL (1u << 28)
+#define DSS_DISPC_CONTROL_LCDENABLEPOL (1u << 29)
+#define DSS_DISPC_CONTROL_SPATIALTEMPD(_df) ((_df) << 30)
+
+#define DSS_DISPC_POL_FREQ_IVS (1u << 12)
+#define DSS_DISPC_POL_FREQ_IHS (1u << 13)
+#define DSS_DISPC_POL_FREQ_IPC (1u << 14)
+#define DSS_DISPC_POL_FREQ_IEO (1u << 15)
+#define DSS_DISPC_POL_FREQ_RF (1u << 16)
+#define DSS_DISPC_POL_FREQ_ONOFF (1u << 17)
+
+#define DSS_DISPC_TIMING_H_HSW(_hsw) ((_hsw) << 0)
+#define DSS_DISPC_TIMING_H_HFP(_hfp) ((_hfp) << 8)
+#define DSS_DISPC_TIMING_H_HBP(_hbp) ((_hbp) << 20)
+
+#define DSS_DISPC_TIMING_V_VSW(_vsw) ((_vsw) << 0)
+#define DSS_DISPC_TIMING_V_VFP(_vfp) ((_vfp) << 8)
+#define DSS_DISPC_TIMING_V_VBP(_vbp) ((_vbp) << 20)
+
+#define DSS_DISPC_DIVISOR_ENABLE (1u << 0)
+#define DSS_DISPC_DIVISOR_LCD(_lcd) ((_lcd) << 16)
+
+#define DSS_DISPC_DIVISOR2_PCD(_pcd) ((_pcd) << 0)
+#define DSS_DISPC_DIVISOR2_LCD(_lcd) ((_lcd) << 16)
+
+#define DSS_DISPC_IRQSTATUS_FRAMEDONE (1u << 0)
+#define DSS_DISPC_IRQSTATUS_FRAMEDONE2 (1u << 22)
+
+#define DSS_DSS_SYSSTATUS_RESETDONE (1u << 0)
+
+#endif /* H_BAREBOX_DRIVER_VIDEO_O4_REGS_H */
--
1.7.10.4
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v6] omap4-fb: add driver
2013-06-14 15:11 ` [PATCH v6] " Christoph Fritz
@ 2013-06-17 7:36 ` Sascha Hauer
2013-06-17 16:17 ` Jean-Christophe PLAGNIOL-VILLARD
2013-06-18 8:47 ` [PATCH v7] " Christoph Fritz
2013-06-17 18:45 ` [PATCH v6] " Alexander Aring
1 sibling, 2 replies; 24+ messages in thread
From: Sascha Hauer @ 2013-06-17 7:36 UTC (permalink / raw)
To: Christoph Fritz; +Cc: barebox
Hi Christoph,
Some small comments, then we shoulf be good to go.
On Fri, Jun 14, 2013 at 05:11:02PM +0200, Christoph Fritz wrote:
> This patch adds omap4 display controller support.
>
> index 94e42c6..e70ddbd 100644
> --- a/arch/arm/mach-omap/Makefile
> +++ b/arch/arm/mach-omap/Makefile
> @@ -28,6 +28,7 @@ obj-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
> pbl-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
> obj-$(CONFIG_OMAP_GPMC) += gpmc.o devices-gpmc-nand.o
> obj-$(CONFIG_SHELL_NONE) += xload.o
> +obj-$(CONFIG_DRIVER_VIDEO_OMAP4) += omap4_fb.o
Please compile this in unconditionally. Otherwise board using this have
to add a dependency on CONFIG_DRIVER_VIDEO_OMAP4 aswell.
> +struct device_d *omap4_add_display(void *pdata)
Let this function take a struct omap4fb_platform_data *. This makes it
more clear how to call it.
> +static void omap4fb_enable(struct fb_info *info)
> +{
> + struct omap4fb_device *fbi =
> + container_of(info, struct omap4fb_device, info);
You could add a static inline to_omap4fb function. It's less error prone
and the above would fit into a single line.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v6] omap4-fb: add driver
2013-06-17 7:36 ` Sascha Hauer
@ 2013-06-17 16:17 ` Jean-Christophe PLAGNIOL-VILLARD
2013-06-18 8:47 ` [PATCH v7] " Christoph Fritz
1 sibling, 0 replies; 24+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2013-06-17 16:17 UTC (permalink / raw)
To: Sascha Hauer, Tomi Valkeinen; +Cc: barebox
On 09:36 Mon 17 Jun , Sascha Hauer wrote:
> Hi Christoph,
>
> Some small comments, then we shoulf be good to go.
>
> On Fri, Jun 14, 2013 at 05:11:02PM +0200, Christoph Fritz wrote:
> > This patch adds omap4 display controller support.
> >
> > index 94e42c6..e70ddbd 100644
> > --- a/arch/arm/mach-omap/Makefile
> > +++ b/arch/arm/mach-omap/Makefile
> > @@ -28,6 +28,7 @@ obj-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
> > pbl-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
> > obj-$(CONFIG_OMAP_GPMC) += gpmc.o devices-gpmc-nand.o
> > obj-$(CONFIG_SHELL_NONE) += xload.o
> > +obj-$(CONFIG_DRIVER_VIDEO_OMAP4) += omap4_fb.o
>
> Please compile this in unconditionally. Otherwise board using this have
> to add a dependency on CONFIG_DRIVER_VIDEO_OMAP4 aswell.
if you have an inline for the fonction no need
as this will do the trick too
the mach-omap and the driver should be splittted and IIRC the omap fb is not
only for omap 4
I add Tomi to this patch from TI
>
> > +struct device_d *omap4_add_display(void *pdata)
>
> Let this function take a struct omap4fb_platform_data *. This makes it
> more clear how to call it.
and check the prototype by gcc
>
> > +static void omap4fb_enable(struct fb_info *info)
> > +{
> > + struct omap4fb_device *fbi =
> > + container_of(info, struct omap4fb_device, info);
>
> You could add a static inline to_omap4fb function. It's less error prone
> and the above would fit into a single line.
>
> Sascha
>
> --
> Pengutronix e.K. | |
> Industrial Linux Solutions | http://www.pengutronix.de/ |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v6] omap4-fb: add driver
2013-06-14 11:43 ` Jean-Christophe PLAGNIOL-VILLARD
2013-06-14 15:11 ` [PATCH v6] " Christoph Fritz
@ 2013-06-17 16:18 ` Christoph Fritz
2013-06-18 7:41 ` Tomi Valkeinen
1 sibling, 1 reply; 24+ messages in thread
From: Christoph Fritz @ 2013-06-17 16:18 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD, Sascha Hauer, Tomi Valkeinen; +Cc: barebox
This patch adds omap4 display controller support.
Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
---
changes since v2:
- use dev_request_mem_region_by_name()
changes since v3:
- remove register struct
- use uncached screen_base
changes since v4:
- remove useless dev_add_param()
- use wait_on_timeout() instead while-deadlock
changes since v5:
- use dev_dbg() and dev_err(), be less verbose
- fix coding-style issues
- add omap4fb_find_display_by_name()
- add additional read/write macros
---
arch/arm/mach-omap/Makefile | 1 +
arch/arm/mach-omap/include/mach/omap4-fb.h | 46 +++
arch/arm/mach-omap/omap4_fb.c | 27 ++
drivers/video/Kconfig | 8 +
drivers/video/Makefile | 1 +
drivers/video/omap4.c | 526 ++++++++++++++++++++++++++++
drivers/video/omap4.h | 187 ++++++++++
7 files changed, 796 insertions(+)
create mode 100644 arch/arm/mach-omap/include/mach/omap4-fb.h
create mode 100644 arch/arm/mach-omap/omap4_fb.c
create mode 100644 drivers/video/omap4.c
create mode 100644 drivers/video/omap4.h
diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile
index 94e42c6..e70ddbd 100644
--- a/arch/arm/mach-omap/Makefile
+++ b/arch/arm/mach-omap/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
pbl-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
obj-$(CONFIG_OMAP_GPMC) += gpmc.o devices-gpmc-nand.o
obj-$(CONFIG_SHELL_NONE) += xload.o
+obj-$(CONFIG_DRIVER_VIDEO_OMAP4) += omap4_fb.o
obj-$(CONFIG_I2C_TWL6030) += omap4_twl6030_mmc.o
obj-$(CONFIG_OMAP4_USBBOOT) += omap4_rom_usb.o
obj-y += gpio.o
diff --git a/arch/arm/mach-omap/include/mach/omap4-fb.h b/arch/arm/mach-omap/include/mach/omap4-fb.h
new file mode 100644
index 0000000..5c0a54b
--- /dev/null
+++ b/arch/arm/mach-omap/include/mach/omap4-fb.h
@@ -0,0 +1,46 @@
+#ifndef H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H
+#define H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H
+
+#include <fb.h>
+
+#define OMAP_DSS_LCD_TFT (1u << 0)
+#define OMAP_DSS_LCD_IVS (1u << 1)
+#define OMAP_DSS_LCD_IHS (1u << 2)
+#define OMAP_DSS_LCD_IPC (1u << 3)
+#define OMAP_DSS_LCD_IEO (1u << 4)
+#define OMAP_DSS_LCD_RF (1u << 5)
+#define OMAP_DSS_LCD_ONOFF (1u << 6)
+
+#define OMAP_DSS_LCD_DATALINES(_l) ((_l) << 10)
+#define OMAP_DSS_LCD_DATALINES_msk OMAP_DSS_LCD_DATALINES(3u)
+#define OMAP_DSS_LCD_DATALINES_12 OMAP_DSS_LCD_DATALINES(0u)
+#define OMAP_DSS_LCD_DATALINES_16 OMAP_DSS_LCD_DATALINES(1u)
+#define OMAP_DSS_LCD_DATALINES_18 OMAP_DSS_LCD_DATALINES(2u)
+#define OMAP_DSS_LCD_DATALINES_24 OMAP_DSS_LCD_DATALINES(3u)
+
+struct omap4fb_display {
+ struct fb_videomode mode;
+
+ unsigned long config;
+
+ unsigned int power_on_delay;
+ unsigned int power_off_delay;
+};
+
+struct omap4fb_platform_data {
+ struct omap4fb_display const *displays;
+ size_t num_displays;
+
+ unsigned int dss_clk_hz;
+
+ unsigned int bpp;
+
+ struct resource const *screen;
+
+ void (*enable)(int p);
+};
+
+struct device_d;
+struct device_d *omap4_add_display(void *pdata);
+
+#endif /* H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H */
diff --git a/arch/arm/mach-omap/omap4_fb.c b/arch/arm/mach-omap/omap4_fb.c
new file mode 100644
index 0000000..09a6af3
--- /dev/null
+++ b/arch/arm/mach-omap/omap4_fb.c
@@ -0,0 +1,27 @@
+#include <driver.h>
+#include <common.h>
+#include <linux/ioport.h>
+#include <mach/omap4-fb.h>
+
+static struct resource omap4_fb_resources[] = {
+ {
+ .name = "omap4_dss",
+ .start = 0x48040000,
+ .end = 0x48040000 + 512 - 1,
+ .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+ }, {
+ .name = "omap4_dispc",
+ .start = 0x48041000,
+ .end = 0x48041000 + 3072 - 1,
+ .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+ },
+};
+
+struct device_d *omap4_add_display(void *pdata)
+{
+ return add_generic_device_res("omap4_fb", -1,
+ omap4_fb_resources,
+ ARRAY_SIZE(omap4_fb_resources),
+ pdata);
+}
+EXPORT_SYMBOL(omap4_add_display);
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 6d6b08f..9dfa0cd 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -45,6 +45,14 @@ config DRIVER_VIDEO_S3C24XX
help
Add support for the S3C244x LCD controller.
+config DRIVER_VIDEO_OMAP4
+ bool "OMAP4 framebuffer driver"
+ depends on ARCH_OMAP4
+ help
+ Add support for the OMAP4 Display Controller.
+ DSI is unsupported, only DISPC parallel mode on LCD2
+ is supported.
+
if DRIVER_VIDEO_S3C24XX
config DRIVER_VIDEO_S3C_VERBOSE
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 7429141..83feebb 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_DRIVER_VIDEO_IMX_IPU) += imx-ipu-fb.o
obj-$(CONFIG_DRIVER_VIDEO_S3C24XX) += s3c24xx.o
obj-$(CONFIG_DRIVER_VIDEO_PXA) += pxa.o
obj-$(CONFIG_DRIVER_VIDEO_SDL) += sdl.o
+obj-$(CONFIG_DRIVER_VIDEO_OMAP4) += omap4.o
diff --git a/drivers/video/omap4.c b/drivers/video/omap4.c
new file mode 100644
index 0000000..afdee44
--- /dev/null
+++ b/drivers/video/omap4.c
@@ -0,0 +1,526 @@
+/*
+ * TI Omap4 Frame Buffer device driver
+ *
+ * Copyright (C) 2013 Christoph Fritz <chf.fritz@googlemail.com>
+ * Based on work by Enrico Scholz, sponsored by Phytec
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <driver.h>
+#include <fb.h>
+#include <errno.h>
+#include <xfuncs.h>
+#include <init.h>
+#include <stdio.h>
+#include <io.h>
+#include <common.h>
+#include <malloc.h>
+#include <common.h>
+#include <clock.h>
+
+#include <mach/omap4-silicon.h>
+#include <mach/omap4-fb.h>
+
+#include <asm/mmu.h>
+
+#include "omap4.h"
+
+struct omap4fb_device {
+ struct fb_info info;
+ struct device_d *dev;
+
+ struct omap4fb_display const *cur_display;
+
+ struct omap4fb_display const *displays;
+ size_t num_displays;
+
+ void __iomem *dss;
+ void __iomem *dispc;
+
+ struct {
+ void __iomem *addr;
+ size_t size;
+ } prealloc_screen;
+
+ struct {
+ uint32_t dispc_control;
+ uint32_t dispc_pol_freq;
+ } shadow;
+
+ struct {
+ unsigned int dss_clk_hz;
+ unsigned int lckd;
+ unsigned int pckd;
+ } divisor;
+ size_t dma_size;
+ void (*enable_fn)(int);
+
+ struct fb_videomode video_modes[];
+};
+
+static void omap4fb_enable(struct fb_info *info)
+{
+ struct omap4fb_device *fbi =
+ container_of(info, struct omap4fb_device, info);
+
+ dev_dbg(fbi->dev, "%s\n", __func__);
+
+ if (!fbi->cur_display) {
+ dev_err(fbi->dev, "no valid mode set\n");
+ return;
+ }
+
+ if (fbi->enable_fn)
+ fbi->enable_fn(1);
+
+ udelay(fbi->cur_display->power_on_delay * 1000u);
+
+ o4_dispc_write(o4_dispc_read(O4_DISPC_CONTROL2) |
+ DSS_DISPC_CONTROL_LCDENABLE |
+ DSS_DISPC_CONTROL_LCDENABLESIGNAL, O4_DISPC_CONTROL2);
+
+ o4_dispc_write(o4_dispc_read(O4_DISPC_VID1_ATTRIBUTES) |
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE, O4_DISPC_VID1_ATTRIBUTES);
+
+ o4_dispc_write(o4_dispc_read(O4_DISPC_CONTROL2) |
+ DSS_DISPC_CONTROL_GOLCD, O4_DISPC_CONTROL2);
+}
+
+static void omap4fb_disable(struct fb_info *info)
+{
+ struct omap4fb_device *fbi =
+ container_of(info, struct omap4fb_device, info);
+
+ dev_dbg(fbi->dev, "%s\n", __func__);
+
+ if (!fbi->cur_display) {
+ dev_err(fbi->dev, "no valid mode set\n");
+ return;
+ }
+
+ o4_dispc_write(o4_dispc_read(O4_DISPC_CONTROL2) &
+ ~(DSS_DISPC_CONTROL_LCDENABLE |
+ DSS_DISPC_CONTROL_LCDENABLESIGNAL), O4_DISPC_CONTROL2);
+
+ o4_dispc_write(o4_dispc_read(O4_DISPC_VID1_ATTRIBUTES) &
+ ~(DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE),
+ O4_DISPC_VID1_ATTRIBUTES);
+
+ if (fbi->prealloc_screen.addr == NULL) {
+ /* free frame buffer; but only when screen is not
+ * preallocated */
+ if (info->screen_base)
+ dma_free_coherent(info->screen_base, fbi->dma_size);
+ }
+
+ info->screen_base = NULL;
+
+ udelay(fbi->cur_display->power_off_delay * 1000u);
+
+ if (fbi->enable_fn)
+ fbi->enable_fn(0);
+}
+
+static void omap4fb_calc_divisor(struct omap4fb_device *fbi,
+ struct fb_videomode const *mode)
+{
+ unsigned int l, k, t, b;
+
+ b = UINT_MAX;
+ for (l = 1; l < 256; l++) {
+ for (k = 1; k < 256; k++) {
+ t = abs(mode->pixclock * 100 -
+ (fbi->divisor.dss_clk_hz / l / k));
+ if (t <= b) {
+ b = t;
+ fbi->divisor.lckd = l;
+ fbi->divisor.pckd = k;
+ }
+ }
+ }
+}
+
+static unsigned int omap4fb_calc_format(struct fb_info const *info)
+{
+ struct omap4fb_device *fbi =
+ container_of(info, struct omap4fb_device, info);
+
+ switch (info->bits_per_pixel) {
+ case 24:
+ return 9;
+ case 32:
+ return 0x8; /* xRGB24-8888 (32-bit container) */
+ default:
+ dev_err(fbi->dev, "%s: unsupported bpp %d\n", __func__,
+ info->bits_per_pixel);
+ return 0;
+ }
+}
+
+struct omap4fb_colors {
+ struct fb_bitfield red;
+ struct fb_bitfield green;
+ struct fb_bitfield blue;
+ struct fb_bitfield transp;
+};
+
+static struct omap4fb_colors const omap4fb_col[] = {
+ [0] = {
+ .red = { .length = 0, .offset = 0 },
+ },
+ [1] = {
+ .blue = { .length = 8, .offset = 0 },
+ .green = { .length = 8, .offset = 8 },
+ .red = { .length = 8, .offset = 16 },
+ },
+ [2] = {
+ .blue = { .length = 8, .offset = 0 },
+ .green = { .length = 8, .offset = 8 },
+ .red = { .length = 8, .offset = 16 },
+ .transp = { .length = 8, .offset = 24 },
+ },
+};
+
+static void omap4fb_fill_shadow(struct omap4fb_device *fbi,
+ struct omap4fb_display const *display)
+{
+ fbi->shadow.dispc_control = 0;
+ fbi->shadow.dispc_pol_freq = 0;
+
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_STNTFT;
+
+ switch (display->config & OMAP_DSS_LCD_DATALINES_msk) {
+ case OMAP_DSS_LCD_DATALINES_12:
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_12;
+ break;
+ case OMAP_DSS_LCD_DATALINES_16:
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_16;
+ break;
+ case OMAP_DSS_LCD_DATALINES_18:
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_18;
+ break;
+ case OMAP_DSS_LCD_DATALINES_24:
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_24;
+ break;
+ }
+
+ if (display->config & OMAP_DSS_LCD_IPC)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IPC;
+
+ if (display->config & OMAP_DSS_LCD_IVS)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IVS;
+
+ if (display->config & OMAP_DSS_LCD_IHS)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IHS;
+
+ if (display->config & OMAP_DSS_LCD_IEO)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IEO;
+
+ if (display->config & OMAP_DSS_LCD_RF)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_RF;
+
+ if (display->config & OMAP_DSS_LCD_ONOFF)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_ONOFF;
+}
+
+static int omap4fb_find_display_by_name(struct omap4fb_device *fbi,
+ const char *name)
+{
+ int i;
+
+ for (i = 0; i < fbi->num_displays; ++i) {
+ if (strcmp(name, fbi->displays[i].mode.name) == 0)
+ return i;
+ }
+ return -ENXIO;
+}
+
+static int omap4fb_activate_var(struct fb_info *info)
+{
+ struct omap4fb_device *fbi =
+ container_of(info, struct omap4fb_device, info);
+ struct fb_videomode const *mode = info->mode;
+ size_t size = mode->xres * mode->yres * (info->bits_per_pixel / 8);
+ int rc;
+ unsigned int fmt = omap4fb_calc_format(info);
+ struct omap4fb_colors const *cols;
+ struct omap4fb_display const *new_display = NULL;
+
+ rc = omap4fb_find_display_by_name(fbi, mode->name);
+ if (rc < 0) {
+ dev_err(fbi->dev, "no display found for this mode '%s'\n",
+ mode->name);
+ goto out;
+ }
+ new_display = &fbi->displays[rc];
+
+ /*Free old screen buf*/
+ if (!fbi->prealloc_screen.addr && info->screen_base)
+ dma_free_coherent(info->screen_base, fbi->dma_size);
+
+ fbi->dma_size = PAGE_ALIGN(size);
+
+ if (!fbi->prealloc_screen.addr) {
+ /* case 1: no preallocated screen */
+ info->screen_base = dma_alloc_coherent(size);
+ } else if (fbi->prealloc_screen.size < fbi->dma_size) {
+ /* case 2: preallocated screen, but too small */
+ dev_err(fbi->dev,
+ "allocated framebuffer too small (%zu < %zu)\n",
+ fbi->prealloc_screen.size, fbi->dma_size);
+ rc = -ENOMEM;
+ goto out;
+ } else {
+ /* case 3: preallocated screen */
+ info->screen_base = fbi->prealloc_screen.addr;
+ }
+
+ omap4fb_fill_shadow(fbi, new_display);
+
+ omap4fb_calc_divisor(fbi, mode);
+
+ switch (info->bits_per_pixel) {
+ case 24:
+ cols = &omap4fb_col[1];
+ break;
+ case 32:
+ cols = &omap4fb_col[2];
+ break;
+ default:
+ cols = &omap4fb_col[0];
+ }
+
+ info->red = cols->red;
+ info->green = cols->green;
+ info->blue = cols->blue;
+ info->transp = cols->transp;
+
+ o4_dispc_write(fbi->shadow.dispc_control, O4_DISPC_CONTROL2);
+
+ o4_dispc_write(fbi->shadow.dispc_pol_freq, O4_DISPC_POL_FREQ2);
+
+ o4_dispc_write(DSS_DISPC_TIMING_H_HSW(mode->hsync_len - 1) |
+ DSS_DISPC_TIMING_H_HFP(mode->right_margin - 1) |
+ DSS_DISPC_TIMING_H_HBP(mode->left_margin - 1),
+ O4_DISPC_TIMING_H2);
+
+ o4_dispc_write(DSS_DISPC_TIMING_V_VSW(mode->vsync_len - 1) |
+ DSS_DISPC_TIMING_V_VFP(mode->lower_margin) |
+ DSS_DISPC_TIMING_V_VBP(mode->upper_margin), O4_DISPC_TIMING_V2);
+
+ o4_dispc_write(DSS_DISPC_DIVISOR_ENABLE | DSS_DISPC_DIVISOR_LCD(1),
+ O4_DISPC_DIVISOR);
+
+ o4_dispc_write(DSS_DISPC_DIVISOR2_LCD(fbi->divisor.lckd) |
+ DSS_DISPC_DIVISOR2_PCD(fbi->divisor.pckd), O4_DISPC_DIVISOR2);
+
+ o4_dispc_write(DSS_DISPC_SIZE_LCD_PPL(mode->xres - 1) |
+ DSS_DISPC_SIZE_LCD_LPP(mode->yres - 1), O4_DISPC_SIZE_LCD2);
+
+ o4_dispc_write(0x0000ff00, O4_DISPC_DEFAULT_COLOR2);
+
+ /* we use VID1 */
+ o4_dispc_write((uintptr_t)info->screen_base, O4_DISPC_VID1_BA0);
+ o4_dispc_write((uintptr_t)info->screen_base, O4_DISPC_VID1_BA1);
+
+ o4_dispc_write(DSS_DISPC_VIDn_POSITION_VIDPOSX(0) |
+ DSS_DISPC_VIDn_POSITION_VIDPOSY(0), O4_DISPC_VID1_POSITION);
+ o4_dispc_write(DSS_DISPC_VIDn_SIZE_VIDSIZEX(mode->xres - 1) |
+ DSS_DISPC_VIDn_SIZE_VIDSIZEY(mode->yres - 1),
+ O4_DISPC_VID1_SIZE);
+ o4_dispc_write(DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEX(mode->xres - 1) |
+ DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEY(mode->yres - 1),
+ O4_DISPC_VID1_PICTURE_SIZE);
+ o4_dispc_write(1, O4_DISPC_VID1_ROW_INC);
+ o4_dispc_write(1, O4_DISPC_VID1_PIXEL_INC);
+
+ o4_dispc_write(0xfff, O4_DISPC_VID1_PRELOAD);
+
+ o4_dispc_write(DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(fmt) |
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_8x128 |
+ DSS_DISPC_VIDn_ATTRIBUTES_ZORDERENABLE |
+ DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_SECONDARY_LCD,
+ O4_DISPC_VID1_ATTRIBUTES);
+
+ rc = wait_on_timeout(O4_TIMEOUT,
+ !(o4_dispc_read(O4_DISPC_CONTROL2) &
+ DSS_DISPC_CONTROL_GOLCD));
+
+ if (rc) {
+ dev_err(fbi->dev, "timeout: dispc golcd\n");
+ goto out;
+ }
+
+ o4_dispc_write(o4_dispc_read(O4_DISPC_CONTROL2) |
+ DSS_DISPC_CONTROL_GOLCD, O4_DISPC_CONTROL2);
+
+ fbi->cur_display = new_display;
+ info->xres = mode->xres;
+ info->yres = mode->yres;
+
+ rc = 0;
+
+out:
+ return rc;
+}
+
+static int omap4fb_reset(struct omap4fb_device const *fbi)
+{
+ uint32_t v = o4_dispc_read(O4_DISPC_CONTROL2);
+ int rc;
+
+ /* step 1: stop the LCD controller */
+ if (v & DSS_DISPC_CONTROL_LCDENABLE) {
+ o4_dispc_write(v & ~DSS_DISPC_CONTROL_LCDENABLE,
+ O4_DISPC_CONTROL2);
+
+ o4_dispc_write(DSS_DISPC_IRQSTATUS_FRAMEDONE2,
+ O4_DISPC_IRQSTATUS);
+
+ rc = wait_on_timeout(O4_TIMEOUT,
+ ((o4_dispc_read(O4_DISPC_IRQSTATUS) &
+ DSS_DISPC_IRQSTATUS_FRAMEDONE) != 0));
+
+ if (rc) {
+ dev_err(fbi->dev, "timeout: irqstatus framedone\n");
+ return -ETIMEDOUT;
+ }
+ }
+
+ /* step 2: wait for reset done status */
+ rc = wait_on_timeout(O4_TIMEOUT,
+ (o4_dss_read(O4_DSS_SYSSTATUS) &
+ DSS_DSS_SYSSTATUS_RESETDONE));
+
+ if (rc) {
+ dev_err(fbi->dev, "timeout: sysstatus resetdone\n");
+ return -ETIMEDOUT;
+ }
+
+ /* DSS_CTL: set to reset value */
+ o4_dss_write(0, O4_DSS_CTRL);
+
+ return 0;
+}
+
+static struct fb_ops omap4fb_ops = {
+ .fb_enable = omap4fb_enable,
+ .fb_disable = omap4fb_disable,
+ .fb_activate_var = omap4fb_activate_var,
+};
+
+static int omap4fb_probe(struct device_d *dev)
+{
+ struct omap4fb_platform_data const *pdata = dev->platform_data;
+ struct omap4fb_device *fbi;
+ struct fb_info *info;
+ int rc;
+ size_t i;
+
+ if (!pdata)
+ return -ENODEV;
+
+ fbi = xzalloc(sizeof *fbi +
+ pdata->num_displays * sizeof fbi->video_modes[0]);
+ info = &fbi->info;
+
+ fbi->dev = dev;
+
+ /* CM_DSS_CLKSTCTRL (TRM: 935) trigger SW_WKUP */
+ __raw_writel(0x2, 0x4a009100); /* TODO: move this to clockmanagement */
+
+ fbi->dss = dev_request_mem_region_by_name(dev, "omap4_dss");
+ fbi->dispc = dev_request_mem_region_by_name(dev, "omap4_dispc");
+
+ if (!fbi->dss || !fbi->dispc) {
+ dev_err(dev, "Insufficient register description\n");
+ rc = -EINVAL;
+ goto out;
+ }
+
+ dev_info(dev, "HW-Revision 0x%04x 0x%04x\n",
+ o4_dss_read(O4_DISPC_REVISION),
+ o4_dss_read(O4_DSS_REVISION));
+
+ if (!pdata->dss_clk_hz | !pdata->displays | !pdata->num_displays |
+ !pdata->bpp) {
+ dev_err(dev, "Insufficient omap4fb_platform_data\n");
+ rc = -EINVAL;
+ goto out;
+ }
+
+ fbi->enable_fn = pdata->enable;
+ fbi->displays = pdata->displays;
+ fbi->num_displays = pdata->num_displays;
+ fbi->divisor.dss_clk_hz = pdata->dss_clk_hz;
+
+ for (i = 0; i < pdata->num_displays; ++i)
+ fbi->video_modes[i] = pdata->displays[i].mode;
+
+ info->mode_list = fbi->video_modes;
+ info->num_modes = pdata->num_displays;
+
+ info->priv = fbi;
+ info->fbops = &omap4fb_ops;
+ info->bits_per_pixel = pdata->bpp;
+
+ if (pdata->screen) {
+ if (!IS_ALIGNED(pdata->screen->start, PAGE_SIZE) ||
+ !IS_ALIGNED(resource_size(pdata->screen), PAGE_SIZE)) {
+ dev_err(dev, "screen resource not aligned\n");
+ rc = -EINVAL;
+ goto out;
+ }
+ fbi->prealloc_screen.addr =
+ (void __iomem *)pdata->screen->start;
+ fbi->prealloc_screen.size = resource_size(pdata->screen);
+ remap_range(fbi->prealloc_screen.addr,
+ fbi->prealloc_screen.size,
+ mmu_get_pte_uncached_flags());
+ }
+
+ rc = omap4fb_reset(fbi);
+ if (rc < 0) {
+ dev_err(dev, "failed to reset: %d\n", rc);
+ goto out;
+ }
+
+ rc = register_framebuffer(info);
+ if (rc < 0) {
+ dev_err(dev, "failed to register framebuffer: %d\n", rc);
+ goto out;
+ }
+
+ rc = 0;
+ dev_info(dev, "registered\n");
+
+out:
+ if (rc < 0)
+ free(fbi);
+
+ return rc;
+}
+
+static struct driver_d omap4fb_driver = {
+ .name = "omap4_fb",
+ .probe = omap4fb_probe,
+};
+
+static int omap4fb_init(void)
+{
+ return platform_driver_register(&omap4fb_driver);
+}
+
+device_initcall(omap4fb_init);
diff --git a/drivers/video/omap4.h b/drivers/video/omap4.h
new file mode 100644
index 0000000..4328a6c
--- /dev/null
+++ b/drivers/video/omap4.h
@@ -0,0 +1,187 @@
+/*
+ * TI Omap4 Frame Buffer device driver
+ *
+ * Copyright (C) 2013 Christoph Fritz <chf.fritz@googlemail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef H_BAREBOX_DRIVER_VIDEO_OMAP4_REGS_H
+#define H_BAREBOX_DRIVER_VIDEO_OMAP4_REGS_H
+
+#include <types.h>
+#include <common.h>
+
+#define O4_TIMEOUT (128 * USECOND)
+
+#define _o4fb_read(io, reg) __raw_readl((io)+(reg))
+#define _o4fb_write(val, io, reg) __raw_writel((val), (io)+(reg))
+
+/* TRM: 10.1.3.2 DSS Registers */
+#define O4_DSS_REVISION 0x0
+#define O4_DSS_SYSSTATUS 0x14
+#define O4_DSS_CTRL 0x40
+#define O4_DSS_STATUS 0x5c
+
+#define o4_dss_read(reg) _o4fb_read(fbi->dss, reg)
+#define o4_dss_write(val, reg) _o4fb_write(val, fbi->dss, reg)
+
+/* TRM: 10.2.7.3 Display Controller Registers */
+#define O4_DISPC_REVISION 0x0
+#define O4_DISPC_IRQSTATUS 0x18
+#define O4_DISPC_VID1_BA0 0xbc
+#define O4_DISPC_VID1_BA1 0xc0
+#define O4_DISPC_VID1_POSITION 0xc4
+#define O4_DISPC_VID1_SIZE 0xc8
+#define O4_DISPC_VID1_ATTRIBUTES 0xcc
+#define O4_DISPC_VID1_ROW_INC 0xd8
+#define O4_DISPC_VID1_PIXEL_INC 0xdc
+#define O4_DISPC_VID1_PICTURE_SIZE 0xe4
+#define O4_DISPC_VID1_PRELOAD 0x230
+#define O4_DISPC_CONTROL2 0x238
+#define O4_DISPC_DEFAULT_COLOR2 0x3ac
+#define O4_DISPC_SIZE_LCD2 0x3cc
+#define O4_DISPC_TIMING_H2 0x400
+#define O4_DISPC_TIMING_V2 0x404
+#define O4_DISPC_POL_FREQ2 0x408
+#define O4_DISPC_DIVISOR2 0x40c
+#define O4_DISPC_DIVISOR 0x804
+
+#define o4_dispc_read(reg) _o4fb_read(fbi->dispc, reg)
+#define o4_dispc_write(val, reg) _o4fb_write(val, fbi->dispc, reg)
+
+#define DSS_DISPC_VIDn_POSITION_VIDPOSX(_x) ((_x) << 0)
+#define DSS_DISPC_VIDn_POSITION_VIDPOSY(_y) ((_y) << 16)
+
+#define DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEX(_x) ((_x) << 0)
+#define DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEY(_y) ((_y) << 16)
+
+#define DSS_DISPC_VIDn_SIZE_VIDSIZEX(_x) ((_x) << 0)
+#define DSS_DISPC_VIDn_SIZE_VIDSIZEY(_y) ((_y) << 16)
+
+#define DSS_DISPC_SIZE_LCD_PPL(_x) ((_x) << 0)
+#define DSS_DISPC_SIZE_LCD_LPP(_y) ((_y) << 16)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE (1u << 0)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(_fmt) ((_fmt) << 1)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB12 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(4u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB16 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(5u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB16 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(6u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB16o \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(7u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_xRGB24u \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(8u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB24p \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(9u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_YUV2 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(10u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_UYVY \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(11u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB32 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(12u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGBA32 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(13u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_xRGB32 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(14u)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(_b) ((_b) << 14)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_2x128 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(0u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_4x128 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(1u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_8x128 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(2u)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDCHANNELOUT (1u << 16)
+#define DSS_DISPC_VIDn_ATTRIBUTES_SELFREFRESHAUTO (1u << 17)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFIFOPRELOAD (1u << 19)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDVERTICALTAPS (1u << 21)
+#define DSS_DISPC_VIDn_ATTRIBUTES_DOUBLESTRIDE (1u << 22)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDARBITRATION (1u << 23)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDSELFREFRESH (1u << 24)
+#define DSS_DISPC_VIDn_ATTRIBUTES_ZORDERENABLE (1u << 25)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(_b) ((_b) << 30)
+#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_PRIMARY_LCD \
+ DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(0u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_SECONDARY_LCD \
+ DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(1u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_WRITEBACK_MEM \
+ DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(3u)
+
+#define DSS_DISPC_CONTROL_LCDENABLE (1u << 0)
+#define DSS_DISPC_CONTROL_TVENABLE (1u << 1)
+#define DSS_DISPC_CONTROL_MONOCOLOR (1u << 2)
+#define DSS_DISPC_CONTROL_STNTFT (1u << 3)
+#define DSS_DISPC_CONTROL_M8B (1u << 4)
+#define DSS_DISPC_CONTROL_GOLCD (1u << 5)
+#define DSS_DISPC_CONTROL_GOTV (1u << 6)
+#define DSS_DISPC_CONTROL_STDITHERENABLE (1u << 7)
+
+#define DSS_DISPC_CONTROL_TFTDATALINES(_l) ((_l) << 8)
+#define DSS_DISPC_CONTROL_TFTDATALINES_12 \
+ DSS_DISPC_CONTROL_TFTDATALINES(0u)
+#define DSS_DISPC_CONTROL_TFTDATALINES_16 \
+ DSS_DISPC_CONTROL_TFTDATALINES(1u)
+#define DSS_DISPC_CONTROL_TFTDATALINES_18 \
+ DSS_DISPC_CONTROL_TFTDATALINES(2u)
+#define DSS_DISPC_CONTROL_TFTDATALINES_24 \
+ DSS_DISPC_CONTROL_TFTDATALINES(3u)
+
+#define DSS_DISPC_CONTROL_STALLMODE (1u << 11)
+#define DSS_DISPC_CONTROL_OVERLAYOPTIMIZATION (1u << 12)
+#define DSS_DISPC_CONTROL_GPIN0 (1u << 13) /* ro */
+#define DSS_DISPC_CONTROL_GPIN1 (1u << 14) /* ro */
+#define DSS_DISPC_CONTROL_GPOUT0 (1u << 15)
+#define DSS_DISPC_CONTROL_GPOUT1 (1u << 16)
+#define DSS_DISPC_CONTROL_HT(_ht) ((_ht) << 17)
+#define DSS_DISPC_CONTROL_TDMENABLE (1u << 20)
+#define DSS_DISPC_CONTROL_TDMPARALLELMODE(_pm) ((_pm) << 21)
+#define DSS_DISPC_CONTROL_TDMCYCLEFORMAT(_cf) ((_cf) << 23)
+#define DSS_DISPC_CONTROL_TDMUNUSEDBITS(_ub) ((_ub) << 25)
+#define DSS_DISPC_CONTROL_PCKFREEENABLE (1u << 27)
+#define DSS_DISPC_CONTROL_LCDENABLESIGNAL (1u << 28)
+#define DSS_DISPC_CONTROL_LCDENABLEPOL (1u << 29)
+#define DSS_DISPC_CONTROL_SPATIALTEMPD(_df) ((_df) << 30)
+
+#define DSS_DISPC_POL_FREQ_IVS (1u << 12)
+#define DSS_DISPC_POL_FREQ_IHS (1u << 13)
+#define DSS_DISPC_POL_FREQ_IPC (1u << 14)
+#define DSS_DISPC_POL_FREQ_IEO (1u << 15)
+#define DSS_DISPC_POL_FREQ_RF (1u << 16)
+#define DSS_DISPC_POL_FREQ_ONOFF (1u << 17)
+
+#define DSS_DISPC_TIMING_H_HSW(_hsw) ((_hsw) << 0)
+#define DSS_DISPC_TIMING_H_HFP(_hfp) ((_hfp) << 8)
+#define DSS_DISPC_TIMING_H_HBP(_hbp) ((_hbp) << 20)
+
+#define DSS_DISPC_TIMING_V_VSW(_vsw) ((_vsw) << 0)
+#define DSS_DISPC_TIMING_V_VFP(_vfp) ((_vfp) << 8)
+#define DSS_DISPC_TIMING_V_VBP(_vbp) ((_vbp) << 20)
+
+#define DSS_DISPC_DIVISOR_ENABLE (1u << 0)
+#define DSS_DISPC_DIVISOR_LCD(_lcd) ((_lcd) << 16)
+
+#define DSS_DISPC_DIVISOR2_PCD(_pcd) ((_pcd) << 0)
+#define DSS_DISPC_DIVISOR2_LCD(_lcd) ((_lcd) << 16)
+
+#define DSS_DISPC_IRQSTATUS_FRAMEDONE (1u << 0)
+#define DSS_DISPC_IRQSTATUS_FRAMEDONE2 (1u << 22)
+
+#define DSS_DSS_SYSSTATUS_RESETDONE (1u << 0)
+
+#endif /* H_BAREBOX_DRIVER_VIDEO_O4_REGS_H */
--
1.7.10.4
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v6] omap4-fb: add driver
2013-06-14 15:11 ` [PATCH v6] " Christoph Fritz
2013-06-17 7:36 ` Sascha Hauer
@ 2013-06-17 18:45 ` Alexander Aring
1 sibling, 0 replies; 24+ messages in thread
From: Alexander Aring @ 2013-06-17 18:45 UTC (permalink / raw)
To: Christoph Fritz; +Cc: barebox
Hi,
only a very small nitpick.
On Fri, Jun 14, 2013 at 05:11:02PM +0200, Christoph Fritz wrote:
> This patch adds omap4 display controller support.
>
> Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
> ---
> changes since v2:
> - use dev_request_mem_region_by_name()
> changes since v3:
> - remove register struct
> - use uncached screen_base
> changes since v4:
> - remove useless dev_add_param()
> - use wait_on_timeout() instead while-deadlock
> changes since v5:
> - use dev_dbg() and dev_err(), be less verbose
> - fix coding-style issues
> - add omap4fb_find_display_by_name()
> - add additional read/write macros
> ---
> arch/arm/mach-omap/Makefile | 1 +
> arch/arm/mach-omap/include/mach/omap4-fb.h | 46 +++
> arch/arm/mach-omap/omap4_fb.c | 27 ++
> drivers/video/Kconfig | 8 +
> drivers/video/Makefile | 1 +
> drivers/video/omap4.c | 526 ++++++++++++++++++++++++++++
> drivers/video/omap4.h | 187 ++++++++++
> 7 files changed, 796 insertions(+)
> create mode 100644 arch/arm/mach-omap/include/mach/omap4-fb.h
> create mode 100644 arch/arm/mach-omap/omap4_fb.c
> create mode 100644 drivers/video/omap4.c
> create mode 100644 drivers/video/omap4.h
>
> diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile
> index 94e42c6..e70ddbd 100644
> --- a/arch/arm/mach-omap/Makefile
> +++ b/arch/arm/mach-omap/Makefile
> @@ -28,6 +28,7 @@ obj-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
> pbl-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
> obj-$(CONFIG_OMAP_GPMC) += gpmc.o devices-gpmc-nand.o
> obj-$(CONFIG_SHELL_NONE) += xload.o
> +obj-$(CONFIG_DRIVER_VIDEO_OMAP4) += omap4_fb.o
> obj-$(CONFIG_I2C_TWL6030) += omap4_twl6030_mmc.o
> obj-$(CONFIG_OMAP4_USBBOOT) += omap4_rom_usb.o
> obj-y += gpio.o
> diff --git a/arch/arm/mach-omap/include/mach/omap4-fb.h b/arch/arm/mach-omap/include/mach/omap4-fb.h
> new file mode 100644
> index 0000000..5c0a54b
> --- /dev/null
> +++ b/arch/arm/mach-omap/include/mach/omap4-fb.h
> @@ -0,0 +1,46 @@
> +#ifndef H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H
> +#define H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H
> +
> +#include <fb.h>
> +
> +#define OMAP_DSS_LCD_TFT (1u << 0)
> +#define OMAP_DSS_LCD_IVS (1u << 1)
...
> +
> + if (!pdata)
> + return -ENODEV;
> +
In my opinion this is a false errno for this case. But better is to drop
this check completely. It's only a check that a programmer doesn't set a
pdata which is very unlikely.
I think there was another patches on this list to remove something like
this.
Regards
Alex
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v6] omap4-fb: add driver
2013-06-17 16:18 ` Christoph Fritz
@ 2013-06-18 7:41 ` Tomi Valkeinen
2013-06-18 8:09 ` Christoph Fritz
0 siblings, 1 reply; 24+ messages in thread
From: Tomi Valkeinen @ 2013-06-18 7:41 UTC (permalink / raw)
To: Christoph Fritz; +Cc: barebox
[-- Attachment #1.1: Type: text/plain, Size: 1036 bytes --]
Hi,
On 17/06/13 19:18, Christoph Fritz wrote:
> This patch adds omap4 display controller support.
I haven't been following the discussions about this patch, so maybe
these have been covered:
OMAP2/3/4/5 all have very similar DSS. Why did you go for omap_4_-fb
driver, not omap-fb driver?
> +config DRIVER_VIDEO_OMAP4
> + bool "OMAP4 framebuffer driver"
> + depends on ARCH_OMAP4
> + help
> + Add support for the OMAP4 Display Controller.
> + DSI is unsupported, only DISPC parallel mode on LCD2
> + is supported.
> +
Also HDMI, RFBI and VENC seem to be unsupported. The DISPC parallel mode
you mention is MIPI DPI.
Supporting only the DPI output is "easy", do you have plans to support
the other outputs and external encoders used in many boards? That may
require a more generic approach, with multiple display "entities" in the
pipeline. Not that the first version should support that, but I just
wanted to mention it so that you don't design the driver in too
non-generic manner.
Tomi
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v6] omap4-fb: add driver
2013-06-18 7:41 ` Tomi Valkeinen
@ 2013-06-18 8:09 ` Christoph Fritz
2013-06-18 9:59 ` Tomi Valkeinen
0 siblings, 1 reply; 24+ messages in thread
From: Christoph Fritz @ 2013-06-18 8:09 UTC (permalink / raw)
To: Tomi Valkeinen; +Cc: barebox
Hi Tomi
On Tue, 2013-06-18 at 10:41 +0300, Tomi Valkeinen wrote:
> On 17/06/13 19:18, Christoph Fritz wrote:
> > This patch adds omap4 display controller support.
>
> I haven't been following the discussions about this patch, so maybe
> these have been covered:
>
> OMAP2/3/4/5 all have very similar DSS. Why did you go for omap_4_-fb
> driver, not omap-fb driver?
I'm currently only having an omap4 board here. But I could rename the
driver to the more generic name "omap-fb" and explain in the KCONFIG
that it currently only covers omap4 devices.
So we could go from there up to all other OMAP devices. Okay?
> > +config DRIVER_VIDEO_OMAP4
> > + bool "OMAP4 framebuffer driver"
> > + depends on ARCH_OMAP4
> > + help
> > + Add support for the OMAP4 Display Controller.
> > + DSI is unsupported, only DISPC parallel mode on LCD2
> > + is supported.
> > +
>
> Also HDMI, RFBI and VENC seem to be unsupported. The DISPC parallel mode
> you mention is MIPI DPI.
>
> Supporting only the DPI output is "easy", do you have plans to support
> the other outputs and external encoders used in many boards?
No, at present I have no intention to do so.
> That may
> require a more generic approach, with multiple display "entities" in the
> pipeline. Not that the first version should support that, but I just
> wanted to mention it so that you don't design the driver in too
> non-generic manner.
Thanks
-- Christoph
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^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v7] omap4-fb: add driver
2013-06-17 7:36 ` Sascha Hauer
2013-06-17 16:17 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2013-06-18 8:47 ` Christoph Fritz
1 sibling, 0 replies; 24+ messages in thread
From: Christoph Fritz @ 2013-06-18 8:47 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
This patch adds omap4 display controller support.
Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
---
changes since v2:
- use dev_request_mem_region_by_name()
changes since v3:
- remove register struct
- use uncached screen_base
changes since v4:
- remove useless dev_add_param()
- use wait_on_timeout() instead while-deadlock
changes since v5:
- use dev_dbg() and dev_err(), be less verbose
- fix coding-style issues
- add omap4fb_find_display_by_name()
- add additional read/write macros
changes since v6:
- add inline function to_omap4fb()
- use 'struct omap4fb_platform_data *' as argument of omap4_add_display()
- remove platform data check from omap4fb_probe()
- compile omap4_fb.o unconditionally of CONFIG_DRIVER_VIDEO_OMAP4
---
arch/arm/mach-omap/Makefile | 1 +
arch/arm/mach-omap/include/mach/omap4-fb.h | 47 +++
arch/arm/mach-omap/omap4_fb.c | 27 ++
drivers/video/Kconfig | 8 +
drivers/video/Makefile | 1 +
drivers/video/omap4.c | 524 ++++++++++++++++++++++++++++
drivers/video/omap4.h | 187 ++++++++++
7 files changed, 795 insertions(+)
create mode 100644 arch/arm/mach-omap/include/mach/omap4-fb.h
create mode 100644 arch/arm/mach-omap/omap4_fb.c
create mode 100644 drivers/video/omap4.c
create mode 100644 drivers/video/omap4.h
diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile
index 94e42c6..965b16a 100644
--- a/arch/arm/mach-omap/Makefile
+++ b/arch/arm/mach-omap/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_ARCH_OMAP3) += omap3_core.o omap3_generic.o auxcr.o
pbl-$(CONFIG_ARCH_OMAP3) += omap3_core.o omap3_generic.o auxcr.o
obj-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o
pbl-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o
+obj-$(CONFIG_ARCH_OMAP4) += omap4_fb.o
obj-$(CONFIG_ARCH_AM33XX) += am33xx_generic.o am33xx_clock.o am33xx_mux.o
obj-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
pbl-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
diff --git a/arch/arm/mach-omap/include/mach/omap4-fb.h b/arch/arm/mach-omap/include/mach/omap4-fb.h
new file mode 100644
index 0000000..2db4ac6
--- /dev/null
+++ b/arch/arm/mach-omap/include/mach/omap4-fb.h
@@ -0,0 +1,47 @@
+#ifndef H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H
+#define H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H
+
+#include <fb.h>
+
+#define OMAP_DSS_LCD_TFT (1u << 0)
+#define OMAP_DSS_LCD_IVS (1u << 1)
+#define OMAP_DSS_LCD_IHS (1u << 2)
+#define OMAP_DSS_LCD_IPC (1u << 3)
+#define OMAP_DSS_LCD_IEO (1u << 4)
+#define OMAP_DSS_LCD_RF (1u << 5)
+#define OMAP_DSS_LCD_ONOFF (1u << 6)
+
+#define OMAP_DSS_LCD_DATALINES(_l) ((_l) << 10)
+#define OMAP_DSS_LCD_DATALINES_msk OMAP_DSS_LCD_DATALINES(3u)
+#define OMAP_DSS_LCD_DATALINES_12 OMAP_DSS_LCD_DATALINES(0u)
+#define OMAP_DSS_LCD_DATALINES_16 OMAP_DSS_LCD_DATALINES(1u)
+#define OMAP_DSS_LCD_DATALINES_18 OMAP_DSS_LCD_DATALINES(2u)
+#define OMAP_DSS_LCD_DATALINES_24 OMAP_DSS_LCD_DATALINES(3u)
+
+struct omap4fb_display {
+ struct fb_videomode mode;
+
+ unsigned long config;
+
+ unsigned int power_on_delay;
+ unsigned int power_off_delay;
+};
+
+struct omap4fb_platform_data {
+ struct omap4fb_display const *displays;
+ size_t num_displays;
+
+ unsigned int dss_clk_hz;
+
+ unsigned int bpp;
+
+ struct resource const *screen;
+
+ void (*enable)(int p);
+};
+
+struct device_d;
+struct device_d *omap4_add_display(struct omap4fb_platform_data *o4_pdata);
+
+
+#endif /* H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H */
diff --git a/arch/arm/mach-omap/omap4_fb.c b/arch/arm/mach-omap/omap4_fb.c
new file mode 100644
index 0000000..a6bc898
--- /dev/null
+++ b/arch/arm/mach-omap/omap4_fb.c
@@ -0,0 +1,27 @@
+#include <driver.h>
+#include <common.h>
+#include <linux/ioport.h>
+#include <mach/omap4-fb.h>
+
+static struct resource omap4_fb_resources[] = {
+ {
+ .name = "omap4_dss",
+ .start = 0x48040000,
+ .end = 0x48040000 + 512 - 1,
+ .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+ }, {
+ .name = "omap4_dispc",
+ .start = 0x48041000,
+ .end = 0x48041000 + 3072 - 1,
+ .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+ },
+};
+
+struct device_d *omap4_add_display(struct omap4fb_platform_data *o4_pdata)
+{
+ return add_generic_device_res("omap4_fb", -1,
+ omap4_fb_resources,
+ ARRAY_SIZE(omap4_fb_resources),
+ o4_pdata);
+}
+EXPORT_SYMBOL(omap4_add_display);
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 6d6b08f..9dfa0cd 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -45,6 +45,14 @@ config DRIVER_VIDEO_S3C24XX
help
Add support for the S3C244x LCD controller.
+config DRIVER_VIDEO_OMAP4
+ bool "OMAP4 framebuffer driver"
+ depends on ARCH_OMAP4
+ help
+ Add support for the OMAP4 Display Controller.
+ DSI is unsupported, only DISPC parallel mode on LCD2
+ is supported.
+
if DRIVER_VIDEO_S3C24XX
config DRIVER_VIDEO_S3C_VERBOSE
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 7429141..83feebb 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_DRIVER_VIDEO_IMX_IPU) += imx-ipu-fb.o
obj-$(CONFIG_DRIVER_VIDEO_S3C24XX) += s3c24xx.o
obj-$(CONFIG_DRIVER_VIDEO_PXA) += pxa.o
obj-$(CONFIG_DRIVER_VIDEO_SDL) += sdl.o
+obj-$(CONFIG_DRIVER_VIDEO_OMAP4) += omap4.o
diff --git a/drivers/video/omap4.c b/drivers/video/omap4.c
new file mode 100644
index 0000000..389edce
--- /dev/null
+++ b/drivers/video/omap4.c
@@ -0,0 +1,524 @@
+/*
+ * TI Omap4 Frame Buffer device driver
+ *
+ * Copyright (C) 2013 Christoph Fritz <chf.fritz@googlemail.com>
+ * Based on work by Enrico Scholz, sponsored by Phytec
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <driver.h>
+#include <fb.h>
+#include <errno.h>
+#include <xfuncs.h>
+#include <init.h>
+#include <stdio.h>
+#include <io.h>
+#include <common.h>
+#include <malloc.h>
+#include <common.h>
+#include <clock.h>
+
+#include <mach/omap4-silicon.h>
+#include <mach/omap4-fb.h>
+
+#include <asm/mmu.h>
+
+#include "omap4.h"
+
+struct omap4fb_device {
+ struct fb_info info;
+ struct device_d *dev;
+
+ struct omap4fb_display const *cur_display;
+
+ struct omap4fb_display const *displays;
+ size_t num_displays;
+
+ void __iomem *dss;
+ void __iomem *dispc;
+
+ struct {
+ void __iomem *addr;
+ size_t size;
+ } prealloc_screen;
+
+ struct {
+ uint32_t dispc_control;
+ uint32_t dispc_pol_freq;
+ } shadow;
+
+ struct {
+ unsigned int dss_clk_hz;
+ unsigned int lckd;
+ unsigned int pckd;
+ } divisor;
+ size_t dma_size;
+ void (*enable_fn)(int);
+
+ struct fb_videomode video_modes[];
+};
+
+static inline struct omap4fb_device *to_omap4fb(const struct fb_info *info)
+{
+ return container_of(info, struct omap4fb_device, info);
+}
+
+static void omap4fb_enable(struct fb_info *info)
+{
+ struct omap4fb_device *fbi = to_omap4fb(info);
+
+ dev_dbg(fbi->dev, "%s\n", __func__);
+
+ if (!fbi->cur_display) {
+ dev_err(fbi->dev, "no valid mode set\n");
+ return;
+ }
+
+ if (fbi->enable_fn)
+ fbi->enable_fn(1);
+
+ udelay(fbi->cur_display->power_on_delay * 1000u);
+
+ o4_dispc_write(o4_dispc_read(O4_DISPC_CONTROL2) |
+ DSS_DISPC_CONTROL_LCDENABLE |
+ DSS_DISPC_CONTROL_LCDENABLESIGNAL, O4_DISPC_CONTROL2);
+
+ o4_dispc_write(o4_dispc_read(O4_DISPC_VID1_ATTRIBUTES) |
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE, O4_DISPC_VID1_ATTRIBUTES);
+
+ o4_dispc_write(o4_dispc_read(O4_DISPC_CONTROL2) |
+ DSS_DISPC_CONTROL_GOLCD, O4_DISPC_CONTROL2);
+}
+
+static void omap4fb_disable(struct fb_info *info)
+{
+ struct omap4fb_device *fbi = to_omap4fb(info);
+
+ dev_dbg(fbi->dev, "%s\n", __func__);
+
+ if (!fbi->cur_display) {
+ dev_err(fbi->dev, "no valid mode set\n");
+ return;
+ }
+
+ o4_dispc_write(o4_dispc_read(O4_DISPC_CONTROL2) &
+ ~(DSS_DISPC_CONTROL_LCDENABLE |
+ DSS_DISPC_CONTROL_LCDENABLESIGNAL), O4_DISPC_CONTROL2);
+
+ o4_dispc_write(o4_dispc_read(O4_DISPC_VID1_ATTRIBUTES) &
+ ~(DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE),
+ O4_DISPC_VID1_ATTRIBUTES);
+
+ if (fbi->prealloc_screen.addr == NULL) {
+ /* free frame buffer; but only when screen is not
+ * preallocated */
+ if (info->screen_base)
+ dma_free_coherent(info->screen_base, fbi->dma_size);
+ }
+
+ info->screen_base = NULL;
+
+ udelay(fbi->cur_display->power_off_delay * 1000u);
+
+ if (fbi->enable_fn)
+ fbi->enable_fn(0);
+}
+
+static void omap4fb_calc_divisor(struct omap4fb_device *fbi,
+ struct fb_videomode const *mode)
+{
+ unsigned int l, k, t, b;
+
+ b = UINT_MAX;
+ for (l = 1; l < 256; l++) {
+ for (k = 1; k < 256; k++) {
+ t = abs(mode->pixclock * 100 -
+ (fbi->divisor.dss_clk_hz / l / k));
+ if (t <= b) {
+ b = t;
+ fbi->divisor.lckd = l;
+ fbi->divisor.pckd = k;
+ }
+ }
+ }
+}
+
+static unsigned int omap4fb_calc_format(struct fb_info const *info)
+{
+ struct omap4fb_device *fbi = to_omap4fb(info);
+
+ switch (info->bits_per_pixel) {
+ case 24:
+ return 9;
+ case 32:
+ return 0x8; /* xRGB24-8888 (32-bit container) */
+ default:
+ dev_err(fbi->dev, "%s: unsupported bpp %d\n", __func__,
+ info->bits_per_pixel);
+ return 0;
+ }
+}
+
+struct omap4fb_colors {
+ struct fb_bitfield red;
+ struct fb_bitfield green;
+ struct fb_bitfield blue;
+ struct fb_bitfield transp;
+};
+
+static struct omap4fb_colors const omap4fb_col[] = {
+ [0] = {
+ .red = { .length = 0, .offset = 0 },
+ },
+ [1] = {
+ .blue = { .length = 8, .offset = 0 },
+ .green = { .length = 8, .offset = 8 },
+ .red = { .length = 8, .offset = 16 },
+ },
+ [2] = {
+ .blue = { .length = 8, .offset = 0 },
+ .green = { .length = 8, .offset = 8 },
+ .red = { .length = 8, .offset = 16 },
+ .transp = { .length = 8, .offset = 24 },
+ },
+};
+
+static void omap4fb_fill_shadow(struct omap4fb_device *fbi,
+ struct omap4fb_display const *display)
+{
+ fbi->shadow.dispc_control = 0;
+ fbi->shadow.dispc_pol_freq = 0;
+
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_STNTFT;
+
+ switch (display->config & OMAP_DSS_LCD_DATALINES_msk) {
+ case OMAP_DSS_LCD_DATALINES_12:
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_12;
+ break;
+ case OMAP_DSS_LCD_DATALINES_16:
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_16;
+ break;
+ case OMAP_DSS_LCD_DATALINES_18:
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_18;
+ break;
+ case OMAP_DSS_LCD_DATALINES_24:
+ fbi->shadow.dispc_control |= DSS_DISPC_CONTROL_TFTDATALINES_24;
+ break;
+ }
+
+ if (display->config & OMAP_DSS_LCD_IPC)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IPC;
+
+ if (display->config & OMAP_DSS_LCD_IVS)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IVS;
+
+ if (display->config & OMAP_DSS_LCD_IHS)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IHS;
+
+ if (display->config & OMAP_DSS_LCD_IEO)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_IEO;
+
+ if (display->config & OMAP_DSS_LCD_RF)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_RF;
+
+ if (display->config & OMAP_DSS_LCD_ONOFF)
+ fbi->shadow.dispc_pol_freq |= DSS_DISPC_POL_FREQ_ONOFF;
+}
+
+static int omap4fb_find_display_by_name(struct omap4fb_device *fbi,
+ const char *name)
+{
+ int i;
+
+ for (i = 0; i < fbi->num_displays; ++i) {
+ if (strcmp(name, fbi->displays[i].mode.name) == 0)
+ return i;
+ }
+ return -ENXIO;
+}
+
+static int omap4fb_activate_var(struct fb_info *info)
+{
+ struct omap4fb_device *fbi = to_omap4fb(info);
+ struct fb_videomode const *mode = info->mode;
+ size_t size = mode->xres * mode->yres * (info->bits_per_pixel / 8);
+ int rc;
+ unsigned int fmt = omap4fb_calc_format(info);
+ struct omap4fb_colors const *cols;
+ struct omap4fb_display const *new_display = NULL;
+
+ rc = omap4fb_find_display_by_name(fbi, mode->name);
+ if (rc < 0) {
+ dev_err(fbi->dev, "no display found for this mode '%s'\n",
+ mode->name);
+ goto out;
+ }
+ new_display = &fbi->displays[rc];
+
+ /*Free old screen buf*/
+ if (!fbi->prealloc_screen.addr && info->screen_base)
+ dma_free_coherent(info->screen_base, fbi->dma_size);
+
+ fbi->dma_size = PAGE_ALIGN(size);
+
+ if (!fbi->prealloc_screen.addr) {
+ /* case 1: no preallocated screen */
+ info->screen_base = dma_alloc_coherent(size);
+ } else if (fbi->prealloc_screen.size < fbi->dma_size) {
+ /* case 2: preallocated screen, but too small */
+ dev_err(fbi->dev,
+ "allocated framebuffer too small (%zu < %zu)\n",
+ fbi->prealloc_screen.size, fbi->dma_size);
+ rc = -ENOMEM;
+ goto out;
+ } else {
+ /* case 3: preallocated screen */
+ info->screen_base = fbi->prealloc_screen.addr;
+ }
+
+ omap4fb_fill_shadow(fbi, new_display);
+
+ omap4fb_calc_divisor(fbi, mode);
+
+ switch (info->bits_per_pixel) {
+ case 24:
+ cols = &omap4fb_col[1];
+ break;
+ case 32:
+ cols = &omap4fb_col[2];
+ break;
+ default:
+ cols = &omap4fb_col[0];
+ }
+
+ info->red = cols->red;
+ info->green = cols->green;
+ info->blue = cols->blue;
+ info->transp = cols->transp;
+
+ o4_dispc_write(fbi->shadow.dispc_control, O4_DISPC_CONTROL2);
+
+ o4_dispc_write(fbi->shadow.dispc_pol_freq, O4_DISPC_POL_FREQ2);
+
+ o4_dispc_write(DSS_DISPC_TIMING_H_HSW(mode->hsync_len - 1) |
+ DSS_DISPC_TIMING_H_HFP(mode->right_margin - 1) |
+ DSS_DISPC_TIMING_H_HBP(mode->left_margin - 1),
+ O4_DISPC_TIMING_H2);
+
+ o4_dispc_write(DSS_DISPC_TIMING_V_VSW(mode->vsync_len - 1) |
+ DSS_DISPC_TIMING_V_VFP(mode->lower_margin) |
+ DSS_DISPC_TIMING_V_VBP(mode->upper_margin), O4_DISPC_TIMING_V2);
+
+ o4_dispc_write(DSS_DISPC_DIVISOR_ENABLE | DSS_DISPC_DIVISOR_LCD(1),
+ O4_DISPC_DIVISOR);
+
+ o4_dispc_write(DSS_DISPC_DIVISOR2_LCD(fbi->divisor.lckd) |
+ DSS_DISPC_DIVISOR2_PCD(fbi->divisor.pckd), O4_DISPC_DIVISOR2);
+
+ o4_dispc_write(DSS_DISPC_SIZE_LCD_PPL(mode->xres - 1) |
+ DSS_DISPC_SIZE_LCD_LPP(mode->yres - 1), O4_DISPC_SIZE_LCD2);
+
+ o4_dispc_write(0x0000ff00, O4_DISPC_DEFAULT_COLOR2);
+
+ /* we use VID1 */
+ o4_dispc_write((uintptr_t)info->screen_base, O4_DISPC_VID1_BA0);
+ o4_dispc_write((uintptr_t)info->screen_base, O4_DISPC_VID1_BA1);
+
+ o4_dispc_write(DSS_DISPC_VIDn_POSITION_VIDPOSX(0) |
+ DSS_DISPC_VIDn_POSITION_VIDPOSY(0), O4_DISPC_VID1_POSITION);
+ o4_dispc_write(DSS_DISPC_VIDn_SIZE_VIDSIZEX(mode->xres - 1) |
+ DSS_DISPC_VIDn_SIZE_VIDSIZEY(mode->yres - 1),
+ O4_DISPC_VID1_SIZE);
+ o4_dispc_write(DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEX(mode->xres - 1) |
+ DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEY(mode->yres - 1),
+ O4_DISPC_VID1_PICTURE_SIZE);
+ o4_dispc_write(1, O4_DISPC_VID1_ROW_INC);
+ o4_dispc_write(1, O4_DISPC_VID1_PIXEL_INC);
+
+ o4_dispc_write(0xfff, O4_DISPC_VID1_PRELOAD);
+
+ o4_dispc_write(DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(fmt) |
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_8x128 |
+ DSS_DISPC_VIDn_ATTRIBUTES_ZORDERENABLE |
+ DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_SECONDARY_LCD,
+ O4_DISPC_VID1_ATTRIBUTES);
+
+ rc = wait_on_timeout(O4_TIMEOUT,
+ !(o4_dispc_read(O4_DISPC_CONTROL2) &
+ DSS_DISPC_CONTROL_GOLCD));
+
+ if (rc) {
+ dev_err(fbi->dev, "timeout: dispc golcd\n");
+ goto out;
+ }
+
+ o4_dispc_write(o4_dispc_read(O4_DISPC_CONTROL2) |
+ DSS_DISPC_CONTROL_GOLCD, O4_DISPC_CONTROL2);
+
+ fbi->cur_display = new_display;
+ info->xres = mode->xres;
+ info->yres = mode->yres;
+
+ rc = 0;
+
+out:
+ return rc;
+}
+
+static int omap4fb_reset(struct omap4fb_device const *fbi)
+{
+ uint32_t v = o4_dispc_read(O4_DISPC_CONTROL2);
+ int rc;
+
+ /* step 1: stop the LCD controller */
+ if (v & DSS_DISPC_CONTROL_LCDENABLE) {
+ o4_dispc_write(v & ~DSS_DISPC_CONTROL_LCDENABLE,
+ O4_DISPC_CONTROL2);
+
+ o4_dispc_write(DSS_DISPC_IRQSTATUS_FRAMEDONE2,
+ O4_DISPC_IRQSTATUS);
+
+ rc = wait_on_timeout(O4_TIMEOUT,
+ ((o4_dispc_read(O4_DISPC_IRQSTATUS) &
+ DSS_DISPC_IRQSTATUS_FRAMEDONE) != 0));
+
+ if (rc) {
+ dev_err(fbi->dev, "timeout: irqstatus framedone\n");
+ return -ETIMEDOUT;
+ }
+ }
+
+ /* step 2: wait for reset done status */
+ rc = wait_on_timeout(O4_TIMEOUT,
+ (o4_dss_read(O4_DSS_SYSSTATUS) &
+ DSS_DSS_SYSSTATUS_RESETDONE));
+
+ if (rc) {
+ dev_err(fbi->dev, "timeout: sysstatus resetdone\n");
+ return -ETIMEDOUT;
+ }
+
+ /* DSS_CTL: set to reset value */
+ o4_dss_write(0, O4_DSS_CTRL);
+
+ return 0;
+}
+
+static struct fb_ops omap4fb_ops = {
+ .fb_enable = omap4fb_enable,
+ .fb_disable = omap4fb_disable,
+ .fb_activate_var = omap4fb_activate_var,
+};
+
+static int omap4fb_probe(struct device_d *dev)
+{
+ struct omap4fb_platform_data const *pdata = dev->platform_data;
+ struct omap4fb_device *fbi;
+ struct fb_info *info;
+ int rc;
+ size_t i;
+
+ fbi = xzalloc(sizeof *fbi +
+ pdata->num_displays * sizeof fbi->video_modes[0]);
+ info = &fbi->info;
+
+ fbi->dev = dev;
+
+ /* CM_DSS_CLKSTCTRL (TRM: 935) trigger SW_WKUP */
+ __raw_writel(0x2, 0x4a009100); /* TODO: move this to clockmanagement */
+
+ fbi->dss = dev_request_mem_region_by_name(dev, "omap4_dss");
+ fbi->dispc = dev_request_mem_region_by_name(dev, "omap4_dispc");
+
+ if (!fbi->dss || !fbi->dispc) {
+ dev_err(dev, "Insufficient register description\n");
+ rc = -EINVAL;
+ goto out;
+ }
+
+ dev_info(dev, "HW-Revision 0x%04x 0x%04x\n",
+ o4_dss_read(O4_DISPC_REVISION),
+ o4_dss_read(O4_DSS_REVISION));
+
+ if (!pdata->dss_clk_hz | !pdata->displays | !pdata->num_displays |
+ !pdata->bpp) {
+ dev_err(dev, "Insufficient omap4fb_platform_data\n");
+ rc = -EINVAL;
+ goto out;
+ }
+
+ fbi->enable_fn = pdata->enable;
+ fbi->displays = pdata->displays;
+ fbi->num_displays = pdata->num_displays;
+ fbi->divisor.dss_clk_hz = pdata->dss_clk_hz;
+
+ for (i = 0; i < pdata->num_displays; ++i)
+ fbi->video_modes[i] = pdata->displays[i].mode;
+
+ info->mode_list = fbi->video_modes;
+ info->num_modes = pdata->num_displays;
+
+ info->priv = fbi;
+ info->fbops = &omap4fb_ops;
+ info->bits_per_pixel = pdata->bpp;
+
+ if (pdata->screen) {
+ if (!IS_ALIGNED(pdata->screen->start, PAGE_SIZE) ||
+ !IS_ALIGNED(resource_size(pdata->screen), PAGE_SIZE)) {
+ dev_err(dev, "screen resource not aligned\n");
+ rc = -EINVAL;
+ goto out;
+ }
+ fbi->prealloc_screen.addr =
+ (void __iomem *)pdata->screen->start;
+ fbi->prealloc_screen.size = resource_size(pdata->screen);
+ remap_range(fbi->prealloc_screen.addr,
+ fbi->prealloc_screen.size,
+ mmu_get_pte_uncached_flags());
+ }
+
+ rc = omap4fb_reset(fbi);
+ if (rc < 0) {
+ dev_err(dev, "failed to reset: %d\n", rc);
+ goto out;
+ }
+
+ rc = register_framebuffer(info);
+ if (rc < 0) {
+ dev_err(dev, "failed to register framebuffer: %d\n", rc);
+ goto out;
+ }
+
+ rc = 0;
+ dev_info(dev, "registered\n");
+
+out:
+ if (rc < 0)
+ free(fbi);
+
+ return rc;
+}
+
+static struct driver_d omap4fb_driver = {
+ .name = "omap4_fb",
+ .probe = omap4fb_probe,
+};
+
+static int omap4fb_init(void)
+{
+ return platform_driver_register(&omap4fb_driver);
+}
+
+device_initcall(omap4fb_init);
diff --git a/drivers/video/omap4.h b/drivers/video/omap4.h
new file mode 100644
index 0000000..4328a6c
--- /dev/null
+++ b/drivers/video/omap4.h
@@ -0,0 +1,187 @@
+/*
+ * TI Omap4 Frame Buffer device driver
+ *
+ * Copyright (C) 2013 Christoph Fritz <chf.fritz@googlemail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef H_BAREBOX_DRIVER_VIDEO_OMAP4_REGS_H
+#define H_BAREBOX_DRIVER_VIDEO_OMAP4_REGS_H
+
+#include <types.h>
+#include <common.h>
+
+#define O4_TIMEOUT (128 * USECOND)
+
+#define _o4fb_read(io, reg) __raw_readl((io)+(reg))
+#define _o4fb_write(val, io, reg) __raw_writel((val), (io)+(reg))
+
+/* TRM: 10.1.3.2 DSS Registers */
+#define O4_DSS_REVISION 0x0
+#define O4_DSS_SYSSTATUS 0x14
+#define O4_DSS_CTRL 0x40
+#define O4_DSS_STATUS 0x5c
+
+#define o4_dss_read(reg) _o4fb_read(fbi->dss, reg)
+#define o4_dss_write(val, reg) _o4fb_write(val, fbi->dss, reg)
+
+/* TRM: 10.2.7.3 Display Controller Registers */
+#define O4_DISPC_REVISION 0x0
+#define O4_DISPC_IRQSTATUS 0x18
+#define O4_DISPC_VID1_BA0 0xbc
+#define O4_DISPC_VID1_BA1 0xc0
+#define O4_DISPC_VID1_POSITION 0xc4
+#define O4_DISPC_VID1_SIZE 0xc8
+#define O4_DISPC_VID1_ATTRIBUTES 0xcc
+#define O4_DISPC_VID1_ROW_INC 0xd8
+#define O4_DISPC_VID1_PIXEL_INC 0xdc
+#define O4_DISPC_VID1_PICTURE_SIZE 0xe4
+#define O4_DISPC_VID1_PRELOAD 0x230
+#define O4_DISPC_CONTROL2 0x238
+#define O4_DISPC_DEFAULT_COLOR2 0x3ac
+#define O4_DISPC_SIZE_LCD2 0x3cc
+#define O4_DISPC_TIMING_H2 0x400
+#define O4_DISPC_TIMING_V2 0x404
+#define O4_DISPC_POL_FREQ2 0x408
+#define O4_DISPC_DIVISOR2 0x40c
+#define O4_DISPC_DIVISOR 0x804
+
+#define o4_dispc_read(reg) _o4fb_read(fbi->dispc, reg)
+#define o4_dispc_write(val, reg) _o4fb_write(val, fbi->dispc, reg)
+
+#define DSS_DISPC_VIDn_POSITION_VIDPOSX(_x) ((_x) << 0)
+#define DSS_DISPC_VIDn_POSITION_VIDPOSY(_y) ((_y) << 16)
+
+#define DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEX(_x) ((_x) << 0)
+#define DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEY(_y) ((_y) << 16)
+
+#define DSS_DISPC_VIDn_SIZE_VIDSIZEX(_x) ((_x) << 0)
+#define DSS_DISPC_VIDn_SIZE_VIDSIZEY(_y) ((_y) << 16)
+
+#define DSS_DISPC_SIZE_LCD_PPL(_x) ((_x) << 0)
+#define DSS_DISPC_SIZE_LCD_LPP(_y) ((_y) << 16)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE (1u << 0)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(_fmt) ((_fmt) << 1)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB12 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(4u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB16 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(5u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB16 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(6u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB16o \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(7u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_xRGB24u \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(8u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB24p \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(9u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_YUV2 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(10u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_UYVY \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(11u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB32 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(12u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGBA32 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(13u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_xRGB32 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(14u)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(_b) ((_b) << 14)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_2x128 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(0u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_4x128 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(1u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_8x128 \
+ DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(2u)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDCHANNELOUT (1u << 16)
+#define DSS_DISPC_VIDn_ATTRIBUTES_SELFREFRESHAUTO (1u << 17)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFIFOPRELOAD (1u << 19)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDVERTICALTAPS (1u << 21)
+#define DSS_DISPC_VIDn_ATTRIBUTES_DOUBLESTRIDE (1u << 22)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDARBITRATION (1u << 23)
+#define DSS_DISPC_VIDn_ATTRIBUTES_VIDSELFREFRESH (1u << 24)
+#define DSS_DISPC_VIDn_ATTRIBUTES_ZORDERENABLE (1u << 25)
+
+#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(_b) ((_b) << 30)
+#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_PRIMARY_LCD \
+ DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(0u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_SECONDARY_LCD \
+ DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(1u)
+#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_WRITEBACK_MEM \
+ DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(3u)
+
+#define DSS_DISPC_CONTROL_LCDENABLE (1u << 0)
+#define DSS_DISPC_CONTROL_TVENABLE (1u << 1)
+#define DSS_DISPC_CONTROL_MONOCOLOR (1u << 2)
+#define DSS_DISPC_CONTROL_STNTFT (1u << 3)
+#define DSS_DISPC_CONTROL_M8B (1u << 4)
+#define DSS_DISPC_CONTROL_GOLCD (1u << 5)
+#define DSS_DISPC_CONTROL_GOTV (1u << 6)
+#define DSS_DISPC_CONTROL_STDITHERENABLE (1u << 7)
+
+#define DSS_DISPC_CONTROL_TFTDATALINES(_l) ((_l) << 8)
+#define DSS_DISPC_CONTROL_TFTDATALINES_12 \
+ DSS_DISPC_CONTROL_TFTDATALINES(0u)
+#define DSS_DISPC_CONTROL_TFTDATALINES_16 \
+ DSS_DISPC_CONTROL_TFTDATALINES(1u)
+#define DSS_DISPC_CONTROL_TFTDATALINES_18 \
+ DSS_DISPC_CONTROL_TFTDATALINES(2u)
+#define DSS_DISPC_CONTROL_TFTDATALINES_24 \
+ DSS_DISPC_CONTROL_TFTDATALINES(3u)
+
+#define DSS_DISPC_CONTROL_STALLMODE (1u << 11)
+#define DSS_DISPC_CONTROL_OVERLAYOPTIMIZATION (1u << 12)
+#define DSS_DISPC_CONTROL_GPIN0 (1u << 13) /* ro */
+#define DSS_DISPC_CONTROL_GPIN1 (1u << 14) /* ro */
+#define DSS_DISPC_CONTROL_GPOUT0 (1u << 15)
+#define DSS_DISPC_CONTROL_GPOUT1 (1u << 16)
+#define DSS_DISPC_CONTROL_HT(_ht) ((_ht) << 17)
+#define DSS_DISPC_CONTROL_TDMENABLE (1u << 20)
+#define DSS_DISPC_CONTROL_TDMPARALLELMODE(_pm) ((_pm) << 21)
+#define DSS_DISPC_CONTROL_TDMCYCLEFORMAT(_cf) ((_cf) << 23)
+#define DSS_DISPC_CONTROL_TDMUNUSEDBITS(_ub) ((_ub) << 25)
+#define DSS_DISPC_CONTROL_PCKFREEENABLE (1u << 27)
+#define DSS_DISPC_CONTROL_LCDENABLESIGNAL (1u << 28)
+#define DSS_DISPC_CONTROL_LCDENABLEPOL (1u << 29)
+#define DSS_DISPC_CONTROL_SPATIALTEMPD(_df) ((_df) << 30)
+
+#define DSS_DISPC_POL_FREQ_IVS (1u << 12)
+#define DSS_DISPC_POL_FREQ_IHS (1u << 13)
+#define DSS_DISPC_POL_FREQ_IPC (1u << 14)
+#define DSS_DISPC_POL_FREQ_IEO (1u << 15)
+#define DSS_DISPC_POL_FREQ_RF (1u << 16)
+#define DSS_DISPC_POL_FREQ_ONOFF (1u << 17)
+
+#define DSS_DISPC_TIMING_H_HSW(_hsw) ((_hsw) << 0)
+#define DSS_DISPC_TIMING_H_HFP(_hfp) ((_hfp) << 8)
+#define DSS_DISPC_TIMING_H_HBP(_hbp) ((_hbp) << 20)
+
+#define DSS_DISPC_TIMING_V_VSW(_vsw) ((_vsw) << 0)
+#define DSS_DISPC_TIMING_V_VFP(_vfp) ((_vfp) << 8)
+#define DSS_DISPC_TIMING_V_VBP(_vbp) ((_vbp) << 20)
+
+#define DSS_DISPC_DIVISOR_ENABLE (1u << 0)
+#define DSS_DISPC_DIVISOR_LCD(_lcd) ((_lcd) << 16)
+
+#define DSS_DISPC_DIVISOR2_PCD(_pcd) ((_pcd) << 0)
+#define DSS_DISPC_DIVISOR2_LCD(_lcd) ((_lcd) << 16)
+
+#define DSS_DISPC_IRQSTATUS_FRAMEDONE (1u << 0)
+#define DSS_DISPC_IRQSTATUS_FRAMEDONE2 (1u << 22)
+
+#define DSS_DSS_SYSSTATUS_RESETDONE (1u << 0)
+
+#endif /* H_BAREBOX_DRIVER_VIDEO_O4_REGS_H */
--
1.7.10.4
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v6] omap4-fb: add driver
2013-06-18 8:09 ` Christoph Fritz
@ 2013-06-18 9:59 ` Tomi Valkeinen
0 siblings, 0 replies; 24+ messages in thread
From: Tomi Valkeinen @ 2013-06-18 9:59 UTC (permalink / raw)
To: Christoph Fritz; +Cc: barebox
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On 18/06/13 11:09, Christoph Fritz wrote:
> Hi Tomi
>
> On Tue, 2013-06-18 at 10:41 +0300, Tomi Valkeinen wrote:
>> On 17/06/13 19:18, Christoph Fritz wrote:
>>> This patch adds omap4 display controller support.
>>
>> I haven't been following the discussions about this patch, so maybe
>> these have been covered:
>>
>> OMAP2/3/4/5 all have very similar DSS. Why did you go for omap_4_-fb
>> driver, not omap-fb driver?
>
> I'm currently only having an omap4 board here. But I could rename the
> driver to the more generic name "omap-fb" and explain in the KCONFIG
> that it currently only covers omap4 devices.
>
> So we could go from there up to all other OMAP devices. Okay?
That sounds good to me.
Tomi
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^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2013-06-18 9:59 UTC | newest]
Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-04-04 6:42 [PATCH] omap4-fb: add driver Christoph Fritz
2013-04-05 8:59 ` Sascha Hauer
2013-04-07 22:15 ` [PATCH v2] " Christoph Fritz
2013-04-08 7:17 ` Jean-Christophe PLAGNIOL-VILLARD
2013-04-09 7:16 ` Sascha Hauer
2013-04-09 13:29 ` Jean-Christophe PLAGNIOL-VILLARD
2013-04-11 19:01 ` Christoph Fritz
2013-06-02 21:07 ` Christoph Fritz
2013-06-12 20:45 ` [PATCH v3] " Christoph Fritz
2013-06-13 10:10 ` Jean-Christophe PLAGNIOL-VILLARD
2013-06-13 22:40 ` [PATCH v4] " Christoph Fritz
2013-06-14 6:29 ` Alexander Aring
2013-06-14 7:23 ` Jan Weitzel
2013-06-14 8:15 ` [PATCH v5] " Christoph Fritz
2013-06-14 11:43 ` Jean-Christophe PLAGNIOL-VILLARD
2013-06-14 15:11 ` [PATCH v6] " Christoph Fritz
2013-06-17 7:36 ` Sascha Hauer
2013-06-17 16:17 ` Jean-Christophe PLAGNIOL-VILLARD
2013-06-18 8:47 ` [PATCH v7] " Christoph Fritz
2013-06-17 18:45 ` [PATCH v6] " Alexander Aring
2013-06-17 16:18 ` Christoph Fritz
2013-06-18 7:41 ` Tomi Valkeinen
2013-06-18 8:09 ` Christoph Fritz
2013-06-18 9:59 ` Tomi Valkeinen
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