Re: [PATCH 11/23] ARM: i.MX8M: esdctl: drop ddrc base from imx8m_ddrc_sdram_size

[Ahmad Fatoum <a.fatoum@pengutronix.de>]

Hi Marco,

On 11/10/25 9:34 PM, Marco Felsch wrote:
> All i.MX8M use the same DDRC MMIO address. Therefore drop the ddrc param
> from imx8m_ddrc_sdram_size() and set it locally.
> 
> While on it drop the param from _imx8m_ddrc_add_mem() as well since it
> is no longer needed to be passed to imx8m_ddrc_sdram_size().
> 
> Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

Acked-by: Ahmad Fatoum <a.fatoum@pengutronix.de>

Cheers,
Ahmad

> ---
>  arch/arm/mach-imx/esdctl.c | 13 +++++++------
>  1 file changed, 7 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
> index 4c4c3528e1a6e68c508edc48ad38c9e2e6324c1c..0a1e042792bd90b40ffc8084efbdc5a25ba0dd02 100644
> --- a/arch/arm/mach-imx/esdctl.c
> +++ b/arch/arm/mach-imx/esdctl.c
> @@ -467,8 +467,9 @@ static void imx_ddrc_set_mstr_device_config(u32 *mstr, unsigned bits)
>  	*mstr |= FIELD_PREP(DDRC_MSTR_DEVICE_CONFIG, fls(bits / 8));
>  }
>  
> -static resource_size_t imx8m_ddrc_sdram_size(void __iomem *ddrc, unsigned buswidth)
> +static resource_size_t imx8m_ddrc_sdram_size(unsigned buswidth)
>  {
> +	void __iomem *ddrc = IOMEM(MX8M_DDRC_CTL_BASE_ADDR);
>  	const u32 addrmap[DDRC_ADDRMAP_LENGTH] = {
>  		readl(ddrc + DDRC_ADDRMAP(0)),
>  		readl(ddrc + DDRC_ADDRMAP(1)),
> @@ -518,10 +519,10 @@ static resource_size_t imx8m_ddrc_sdram_size(void __iomem *ddrc, unsigned buswid
>  				   reduced_adress_space, mstr);
>  }
>  
> -static int _imx8m_ddrc_add_mem(void *mmdcbase, const struct imx_esdctl_data *data,
> +static int _imx8m_ddrc_add_mem(const struct imx_esdctl_data *data,
>  			       unsigned int buswidth)
>  {
> -	resource_size_t size = imx8m_ddrc_sdram_size(mmdcbase, buswidth);
> +	resource_size_t size = imx8m_ddrc_sdram_size(buswidth);
>  	resource_size_t size0, size1;
>  	int ret;
>  
> @@ -555,12 +556,12 @@ static int _imx8m_ddrc_add_mem(void *mmdcbase, const struct imx_esdctl_data *dat
>  
>  static int imx8m_ddrc_add_mem(void *mmdcbase, const struct imx_esdctl_data *data)
>  {
> -	return _imx8m_ddrc_add_mem(mmdcbase, data, 32);
> +	return _imx8m_ddrc_add_mem(data, 32);
>  }
>  
>  static int imx8mn_ddrc_add_mem(void *mmdcbase, const struct imx_esdctl_data *data)
>  {
> -	return _imx8m_ddrc_add_mem(mmdcbase, data, 16);
> +	return _imx8m_ddrc_add_mem(data, 16);
>  }
>  
>  #define IMX9_DDRC_CS_CONFIG(n)	(0x80 + (n) * 4)
> @@ -1001,7 +1002,7 @@ resource_size_t imx8m_barebox_earlymem_size(unsigned buswidth)
>  {
>  	resource_size_t size;
>  
> -	size = imx8m_ddrc_sdram_size(IOMEM(MX8M_DDRC_CTL_BASE_ADDR), buswidth);
> +	size = imx8m_ddrc_sdram_size(buswidth);
>  	/*
>  	 * We artificially limit detected memory size to force malloc
>  	 * pool placement to be within 4GiB address space, so as to
> 

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