Re: [PATCH] Arm: i.MX5: Do not disable L2 cache

[Lucas Stach <l.stach@pengutronix.de>]

Am Donnerstag, den 18.06.2020, 14:12 +0200 schrieb Sascha Hauer:
> Disabling the L2 cache is not working in imx5_init_lowlevel() because
> the necessary cache maintenance operations are missing. This often
> results in cache corruption in a chainloaded barebox.
> Disabling the cache is unnecessary: when we come from the ROM the L2
> cache is disabled anyway, so disabling it is a no-op. When we get here
> in a chainloaded barebox the L2 cache is already enabled and correctly
> configured. So instead of initializing it again we can take an enabled
> L2 cache as a sign to skip initialization and just return from the
> function.

While this won't hurt much, shouldn't we also disable the L2 cache on
Barebox shutdown, like we do on other SoCs?

Regards,
Lucas

> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  arch/arm/mach-imx/imx5.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/imx5.c b/arch/arm/mach-imx/imx5.c
> index 96288f99e0..dd6c079fe3 100644
> --- a/arch/arm/mach-imx/imx5.c
> +++ b/arch/arm/mach-imx/imx5.c
> @@ -37,10 +37,13 @@ void imx5_init_lowlevel(void)
>  {
>  	u32 r;
>  
> -	/* ARM errata ID #468414 */
>  	__asm__ __volatile__("mrc 15, 0, %0, c1, c0, 1":"=r"(r));
> +
> +	if (r & (1 << 1))
> +		return;
> +
> +	/* ARM errata ID #468414 */
>  	r |= (1 << 5);    /* enable L1NEON bit */
> -	r &= ~(1 << 1);   /* explicitly disable L2 cache */
>  	__asm__ __volatile__("mcr 15, 0, %0, c1, c0, 1" : : "r"(r));
>  
>          /* reconfigure L2 cache aux control reg */


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